From 715fd8deade82c0fc9707e91b097e9915cb3fe0d Mon Sep 17 00:00:00 2001
From: qinfan <qinfan.wang@terapines.com>
Date: Tue, 26 Dec 2023 16:38:50 +0800
Subject: [PATCH] [VENTUS][fix] Add phi-node instruction to divergence for
 non-kernel function

Add phi-node instruction to divergence for non-kernel function.
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |  5 ++++
 .../RISCV/VentusGPGPU/non_kernel_branch.ll    | 25 +++++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/VentusGPGPU/non_kernel_branch.ll

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index ffe3685909f8..ec61d406a8c5 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -401,5 +401,10 @@ bool RISCVTTIImpl::isSourceOfDivergence(const Value *V) const {
   if (isa<InvokeInst>(V))
     return true;
 
+  if (dyn_cast<PHINode>(V) && 
+      dyn_cast<Instruction>(V)->getParent()->getParent()->getCallingConv() !=
+      CallingConv::VENTUS_KERNEL) 
+    return true;
+
   return false;
 }
diff --git a/llvm/test/CodeGen/RISCV/VentusGPGPU/non_kernel_branch.ll b/llvm/test/CodeGen/RISCV/VentusGPGPU/non_kernel_branch.ll
new file mode 100644
index 000000000000..b482cce8d6ce
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/VentusGPGPU/non_kernel_branch.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=VENTUS %s
+
+; Function Attrs: nofree norecurse nosync nounwind memory(none) vscale_range(1,2048)
+define dso_local i32 @loop(i32 noundef %x) local_unnamed_addr {
+; VENTUS:    vbeq	v1, v0, .LBB0_4
+; VENTUS:    vadd.vi	v0, v0, 2
+; VENTUS:    vbne	v0, v2, .LBB0_1
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.inc
+  %i.05 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
+  %cmp1 = icmp eq i32 %i.05, %x
+  br i1 %cmp1, label %cleanup, label %for.inc
+
+for.inc:                                          ; preds = %for.body
+  %add = add nuw nsw i32 %i.05, 2
+  %cmp.not = icmp eq i32 %add, 64
+  br i1 %cmp.not, label %cleanup, label %for.body
+
+cleanup:                                          ; preds = %for.body, %for.inc
+  %spec.select = phi i32 [ %i.05, %for.body ], [ 0, %for.inc ]
+  ret i32 %spec.select
+}
\ No newline at end of file