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[BOLT][NFC] Fix MCPlusBuilder::getAliases caching behavior 

Caching behavior of `getAliases` causes a failure in unit tests where two
MCPlusBuilder objects are created corresponding to AArch64 and X86:
the alias cache is created for AArch64 but then used for X86.

https://lab.llvm.org/staging/#/builders/211/builds/126

The issue only affects unit tests as we only construct one MCPlusBuilder
for ELF binary.

Resolve the issue by moving alias bitvectors to MCPlusBuilder object.

Reviewed By: yota9

Differential Revision: https://reviews.llvm.org/D124942
This commit is contained in:
Amir Ayupov 2022-05-04 11:42:14 -07:00 committed by Amir Ayupov
parent 2966f0fa50
commit 68c7299f16
2 changed files with 16 additions and 14 deletions
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10
bolt/include/bolt/Core/MCPlusBuilder.h
View File

@ -282,6 +282,8 @@ public:
// Initialize the default annotation allocator with id 0 // Initialize the default annotation allocator with id 0
AnnotationAllocators.emplace(0, AnnotationAllocator()); AnnotationAllocators.emplace(0, AnnotationAllocator());
MaxAllocatorId++; MaxAllocatorId++;
// Build alias map
initAliases();
} }
/// Initialize a new annotation allocator and return its id /// Initialize a new annotation allocator and return its id
@ -1135,6 +1137,9 @@ public:
virtual const BitVector &getAliases(MCPhysReg Reg, virtual const BitVector &getAliases(MCPhysReg Reg,
bool OnlySmaller = false) const; bool OnlySmaller = false) const;
/// Initialize aliases tables.
virtual void initAliases();
/// Change \p Regs setting all registers used to pass parameters according /// Change \p Regs setting all registers used to pass parameters according
/// to the host abi. Do nothing if not implemented. /// to the host abi. Do nothing if not implemented.
virtual BitVector getRegsUsedAsParams() const { virtual BitVector getRegsUsedAsParams() const {
@ -1904,6 +1909,11 @@ public:
llvm_unreachable("not implemented"); llvm_unreachable("not implemented");
return BlocksVectorTy(); return BlocksVectorTy();
} }
// AliasMap caches a mapping of registers to the set of registers that
// alias (are sub or superregs of itself, including itself).
std::vector<BitVector> AliasMap;
std::vector<BitVector> SmallerAliasMap;
}; };
MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *, MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *,

20
bolt/lib/Core/MCPlusBuilder.cpp
View File

@ -441,17 +441,13 @@ bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg, const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
bool OnlySmaller) const { bool OnlySmaller) const {
// AliasMap caches a mapping of registers to the set of registers that if (OnlySmaller)
// alias (are sub or superregs of itself, including itself). return SmallerAliasMap[Reg];
static std::vector<BitVector> AliasMap; return AliasMap[Reg];
static std::vector<BitVector> SmallerAliasMap; }
if (AliasMap.size() > 0) {
if (OnlySmaller)
return SmallerAliasMap[Reg];
return AliasMap[Reg];
}
void MCPlusBuilder::initAliases() {
assert(AliasMap.size() == 0 && SmallerAliasMap.size() == 0);
// Build alias map // Build alias map
for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) { for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
BitVector BV(RegInfo->getNumRegs(), false); BitVector BV(RegInfo->getNumRegs(), false);
@ -492,10 +488,6 @@ const BitVector &MCPlusBuilder::getAliases(MCPhysReg Reg,
dbgs() << "\n"; dbgs() << "\n";
} }
}); });
if (OnlySmaller)
return SmallerAliasMap[Reg];
return AliasMap[Reg];
} }
uint8_t MCPlusBuilder::getRegSize(MCPhysReg Reg) const { uint8_t MCPlusBuilder::getRegSize(MCPhysReg Reg) const {