[ARM] Enable and/cmp0 folding
The `CodeGenPrepare` pass can sink bitwise `and` used by compare to zero into the basic blocks where the users are. This operation is guarded by lowering hook, which is disabled for ARM. In the ARM architecture versions from v7-M up these two operations can be folded into `tst rN, #imm` instruction. Sinking of `and` can also enable the cmov-to-bfi DAG combiner. This patch fixes some benchmark regressions caused by https://reviews.llvm.org/D129370 as well scoring slightly better overall. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D134360
This commit is contained in:
Momchil Velikov
parent
a412e9cd40
commit
6602110152
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@ -21191,6 +21191,21 @@ bool ARMTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
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return Subtarget->hasV6T2Ops();
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}
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bool ARMTargetLowering::isMaskAndCmp0FoldingBeneficial(
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const Instruction &AndI) const {
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if (!Subtarget->hasV7Ops())
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return false;
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// Sink the `and` instruction only if the mask would fit into a modified
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// immediate operand.
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ConstantInt *Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
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if (!Mask || Mask->getValue().getBitWidth() > 32u)
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return false;
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auto MaskVal = unsigned(Mask->getValue().getZExtValue());
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return (Subtarget->isThumb2() ? ARM_AM::getT2SOImmVal(MaskVal)
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: ARM_AM::getSOImmVal(MaskVal)) != -1;
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}
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bool ARMTargetLowering::shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
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return !Subtarget->hasMinSize() || Subtarget->isTargetWindows();
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}
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@ -584,6 +584,8 @@ class VectorType;
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bool preferZeroCompareBranch() const override { return true; }
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bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
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bool
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isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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@ -11,86 +11,99 @@ define void @f(i32 %v, ptr noalias %outp) {
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; V7M-LABEL: f:
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; V7M: @ %bb.0: @ %entry
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; V7M-NEXT: movs r2, #0
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; V7M-NEXT: and r12, r0, #14
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; V7M-NEXT: str r2, [r1]
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; V7M-NEXT: and r3, r0, #4
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; V7M-NEXT: and r2, r0, #2
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; V7M-NEXT: lsls r0, r0, #31
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; V7M-NEXT: bne .LBB0_2
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; V7M-NEXT: lsls r2, r0, #31
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; V7M-NEXT: bne .LBB0_3
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; V7M-NEXT: @ %bb.1: @ %if.then
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; V7M-NEXT: cmp r2, #0
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; V7M-NEXT: it ne
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; V7M-NEXT: movne.w r2, #33024
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; V7M-NEXT: cmp r3, #0
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; V7M-NEXT: it ne
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; V7M-NEXT: addne.w r2, r2, #16512
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; V7M-NEXT: b .LBB0_3
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; V7M-NEXT: .LBB0_2: @ %if.else
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; V7M-NEXT: cmp r2, #0
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; V7M-NEXT: it ne
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; V7M-NEXT: movne.w r2, #8256
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; V7M-NEXT: cmp r3, #0
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; V7M-NEXT: it ne
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; V7M-NEXT: addne.w r2, r2, #4128
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; V7M-NEXT: tst.w r0, #14
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; V7M-NEXT: beq .LBB0_6
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; V7M-NEXT: @ %bb.2:
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; V7M-NEXT: lsls r2, r0, #30
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; V7M-NEXT: mov.w r3, #33024
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; V7M-NEXT: and.w r2, r3, r2, asr #31
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; V7M-NEXT: lsrs r0, r0, #2
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; V7M-NEXT: bfi r2, r0, #7, #1
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; V7M-NEXT: bfi r2, r0, #14, #1
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; V7M-NEXT: b .LBB0_5
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; V7M-NEXT: .LBB0_3: @ %if.else
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; V7M-NEXT: cmp.w r12, #0
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; V7M-NEXT: it ne
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; V7M-NEXT: strne r2, [r1]
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; V7M-NEXT: tst.w r0, #14
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; V7M-NEXT: it eq
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; V7M-NEXT: bxeq lr
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; V7M-NEXT: .LBB0_4:
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; V7M-NEXT: lsls r2, r0, #30
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; V7M-NEXT: mov.w r3, #8256
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; V7M-NEXT: and.w r2, r3, r2, asr #31
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; V7M-NEXT: lsrs r0, r0, #2
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; V7M-NEXT: bfi r2, r0, #5, #1
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; V7M-NEXT: bfi r2, r0, #12, #1
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; V7M-NEXT: .LBB0_5: @ %if.end
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; V7M-NEXT: str r2, [r1]
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; V7M-NEXT: .LBB0_6: @ %exit
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; V7M-NEXT: bx lr
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;
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; V7A-LABEL: f:
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; V7A: @ %bb.0: @ %entry
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; V7A-NEXT: mov r2, #0
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; V7A-NEXT: and r12, r0, #14
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; V7A-NEXT: str r2, [r1]
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; V7A-NEXT: and r3, r0, #4
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; V7A-NEXT: and r2, r0, #2
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; V7A-NEXT: tst r0, #1
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; V7A-NEXT: bne .LBB0_2
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; V7A-NEXT: str r2, [r1]
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; V7A-NEXT: bne .LBB0_3
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; V7A-NEXT: @ %bb.1: @ %if.then
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; V7A-NEXT: cmp r2, #0
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; V7A-NEXT: movw r0, #16512
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; V7A-NEXT: movwne r2, #33024
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; V7A-NEXT: b .LBB0_3
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; V7A-NEXT: .LBB0_2: @ %if.else
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; V7A-NEXT: cmp r2, #0
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; V7A-NEXT: movw r0, #4128
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; V7A-NEXT: movwne r2, #8256
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; V7A-NEXT: tst r0, #14
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; V7A-NEXT: beq .LBB0_6
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; V7A-NEXT: @ %bb.2:
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; V7A-NEXT: lsl r2, r0, #30
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; V7A-NEXT: mov r3, #33024
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; V7A-NEXT: and r2, r3, r2, asr #31
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; V7A-NEXT: lsr r0, r0, #2
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; V7A-NEXT: bfi r2, r0, #7, #1
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; V7A-NEXT: bfi r2, r0, #14, #1
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; V7A-NEXT: b .LBB0_5
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; V7A-NEXT: .LBB0_3: @ %if.else
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; V7A-NEXT: cmp r3, #0
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; V7A-NEXT: orrne r2, r2, r0
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; V7A-NEXT: cmp r12, #0
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; V7A-NEXT: strne r2, [r1]
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; V7A-NEXT: tst r0, #14
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; V7A-NEXT: bxeq lr
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; V7A-NEXT: .LBB0_4:
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; V7A-NEXT: lsl r2, r0, #30
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; V7A-NEXT: mov r3, #8256
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; V7A-NEXT: and r2, r3, r2, asr #31
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; V7A-NEXT: lsr r0, r0, #2
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; V7A-NEXT: bfi r2, r0, #5, #1
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; V7A-NEXT: bfi r2, r0, #12, #1
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; V7A-NEXT: .LBB0_5: @ %if.end
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; V7A-NEXT: str r2, [r1]
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; V7A-NEXT: .LBB0_6: @ %exit
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; V7A-NEXT: bx lr
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;
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; V7A-T-LABEL: f:
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; V7A-T: @ %bb.0: @ %entry
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; V7A-T-NEXT: movs r2, #0
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; V7A-T-NEXT: and r12, r0, #14
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; V7A-T-NEXT: str r2, [r1]
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; V7A-T-NEXT: and r3, r0, #4
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; V7A-T-NEXT: and r2, r0, #2
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; V7A-T-NEXT: lsls r0, r0, #31
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; V7A-T-NEXT: bne .LBB0_2
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; V7A-T-NEXT: lsls r2, r0, #31
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; V7A-T-NEXT: bne .LBB0_3
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; V7A-T-NEXT: @ %bb.1: @ %if.then
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; V7A-T-NEXT: cmp r2, #0
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; V7A-T-NEXT: it ne
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; V7A-T-NEXT: movne.w r2, #33024
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; V7A-T-NEXT: cmp r3, #0
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; V7A-T-NEXT: it ne
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; V7A-T-NEXT: addne.w r2, r2, #16512
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; V7A-T-NEXT: b .LBB0_3
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; V7A-T-NEXT: .LBB0_2: @ %if.else
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; V7A-T-NEXT: cmp r2, #0
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; V7A-T-NEXT: it ne
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; V7A-T-NEXT: movne.w r2, #8256
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; V7A-T-NEXT: cmp r3, #0
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; V7A-T-NEXT: it ne
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; V7A-T-NEXT: addne.w r2, r2, #4128
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; V7A-T-NEXT: tst.w r0, #14
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; V7A-T-NEXT: beq .LBB0_6
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; V7A-T-NEXT: @ %bb.2:
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; V7A-T-NEXT: lsls r2, r0, #30
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; V7A-T-NEXT: mov.w r3, #33024
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; V7A-T-NEXT: and.w r2, r3, r2, asr #31
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; V7A-T-NEXT: lsrs r0, r0, #2
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; V7A-T-NEXT: bfi r2, r0, #7, #1
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; V7A-T-NEXT: bfi r2, r0, #14, #1
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; V7A-T-NEXT: b .LBB0_5
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; V7A-T-NEXT: .LBB0_3: @ %if.else
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; V7A-T-NEXT: cmp.w r12, #0
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; V7A-T-NEXT: it ne
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; V7A-T-NEXT: strne r2, [r1]
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; V7A-T-NEXT: tst.w r0, #14
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; V7A-T-NEXT: it eq
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; V7A-T-NEXT: bxeq lr
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; V7A-T-NEXT: .LBB0_4:
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; V7A-T-NEXT: lsls r2, r0, #30
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; V7A-T-NEXT: mov.w r3, #8256
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; V7A-T-NEXT: and.w r2, r3, r2, asr #31
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; V7A-T-NEXT: lsrs r0, r0, #2
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; V7A-T-NEXT: bfi r2, r0, #5, #1
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; V7A-T-NEXT: bfi r2, r0, #12, #1
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; V7A-T-NEXT: .LBB0_5: @ %if.end
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; V7A-T-NEXT: str r2, [r1]
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; V7A-T-NEXT: .LBB0_6: @ %exit
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; V7A-T-NEXT: bx lr
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;
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; V6M-LABEL: f:
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@ -176,17 +189,16 @@ exit:
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define i32 @f0(i1 %c0, i32 %v) {
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; V7M-LABEL: f0:
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; V7M: @ %bb.0: @ %E
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; V7M-NEXT: bic r1, r1, #-16843010
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; V7M-NEXT: lsls r0, r0, #31
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; V7M-NEXT: beq .LBB1_2
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; V7M-NEXT: @ %bb.1: @ %A
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; V7M-NEXT: cmp r1, #0
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; V7M-NEXT: tst.w r1, #16843009
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; V7M-NEXT: itt eq
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; V7M-NEXT: moveq r0, #0
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; V7M-NEXT: bxeq lr
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; V7M-NEXT: b .LBB1_3
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; V7M-NEXT: .LBB1_2: @ %B
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; V7M-NEXT: cmp r1, #0
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; V7M-NEXT: tst.w r1, #16843009
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; V7M-NEXT: itt ne
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; V7M-NEXT: movne r0, #0
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; V7M-NEXT: bxne lr
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@ -216,17 +228,16 @@ define i32 @f0(i1 %c0, i32 %v) {
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;
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; V7A-T-LABEL: f0:
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; V7A-T: @ %bb.0: @ %E
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; V7A-T-NEXT: bic r1, r1, #-16843010
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; V7A-T-NEXT: lsls r0, r0, #31
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; V7A-T-NEXT: beq .LBB1_2
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; V7A-T-NEXT: @ %bb.1: @ %A
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; V7A-T-NEXT: cmp r1, #0
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; V7A-T-NEXT: tst.w r1, #16843009
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; V7A-T-NEXT: itt eq
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; V7A-T-NEXT: moveq r0, #0
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; V7A-T-NEXT: bxeq lr
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; V7A-T-NEXT: b .LBB1_3
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; V7A-T-NEXT: .LBB1_2: @ %B
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; V7A-T-NEXT: cmp r1, #0
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; V7A-T-NEXT: tst.w r1, #16843009
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; V7A-T-NEXT: itt ne
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; V7A-T-NEXT: movne r0, #0
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; V7A-T-NEXT: bxne lr
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@ -286,17 +297,16 @@ X:
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define i32 @f1(i1 %c0, i32 %v) {
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; V7M-LABEL: f1:
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; V7M: @ %bb.0: @ %E
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; V7M-NEXT: and r1, r1, #100663296
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; V7M-NEXT: lsls r0, r0, #31
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; V7M-NEXT: beq .LBB2_2
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; V7M-NEXT: @ %bb.1: @ %A
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; V7M-NEXT: cmp r1, #0
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; V7M-NEXT: tst.w r1, #100663296
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; V7M-NEXT: itt eq
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; V7M-NEXT: moveq r0, #0
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; V7M-NEXT: bxeq lr
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; V7M-NEXT: b .LBB2_3
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; V7M-NEXT: .LBB2_2: @ %B
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; V7M-NEXT: cmp r1, #0
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; V7M-NEXT: tst.w r1, #100663296
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; V7M-NEXT: itt ne
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; V7M-NEXT: movne r0, #0
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; V7M-NEXT: bxne lr
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@ -306,11 +316,10 @@ define i32 @f1(i1 %c0, i32 %v) {
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;
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; V7A-LABEL: f1:
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; V7A: @ %bb.0: @ %E
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; V7A-NEXT: and r1, r1, #100663296
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; V7A-NEXT: tst r0, #1
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; V7A-NEXT: beq .LBB2_3
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; V7A-NEXT: @ %bb.1: @ %A
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; V7A-NEXT: cmp r1, #0
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; V7A-NEXT: tst r1, #100663296
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; V7A-NEXT: moveq r0, #0
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; V7A-NEXT: bxeq lr
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; V7A-NEXT: .LBB2_2: @ %D
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@ -318,23 +327,22 @@ define i32 @f1(i1 %c0, i32 %v) {
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; V7A-NEXT: bx lr
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; V7A-NEXT: .LBB2_3: @ %B
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; V7A-NEXT: mov r0, #0
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; V7A-NEXT: cmp r1, #0
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; V7A-NEXT: tst r1, #100663296
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; V7A-NEXT: moveq r0, #1
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; V7A-NEXT: bx lr
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;
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; V7A-T-LABEL: f1:
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; V7A-T: @ %bb.0: @ %E
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; V7A-T-NEXT: and r1, r1, #100663296
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; V7A-T-NEXT: lsls r0, r0, #31
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; V7A-T-NEXT: beq .LBB2_2
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; V7A-T-NEXT: @ %bb.1: @ %A
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; V7A-T-NEXT: cmp r1, #0
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; V7A-T-NEXT: tst.w r1, #100663296
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; V7A-T-NEXT: itt eq
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; V7A-T-NEXT: moveq r0, #0
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; V7A-T-NEXT: bxeq lr
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; V7A-T-NEXT: b .LBB2_3
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; V7A-T-NEXT: .LBB2_2: @ %B
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; V7A-T-NEXT: cmp r1, #0
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; V7A-T-NEXT: tst.w r1, #100663296
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; V7A-T-NEXT: itt ne
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; V7A-T-NEXT: movne r0, #0
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; V7A-T-NEXT: bxne lr
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@ -1426,12 +1426,11 @@ define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instanc
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: ldrd r12, r6, [r0, #4]
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: ldrb r0, [r0]
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; CHECK-NEXT: and r8, r3, #1
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; CHECK-NEXT: ldrd r12, r6, [r0, #4]
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; CHECK-NEXT: ldrb.w r9, [r0]
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; CHECK-NEXT: vldr.16 s0, .LCPI17_0
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; CHECK-NEXT: lsr.w r9, r3, #1
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; CHECK-NEXT: lsr.w r8, r3, #1
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; CHECK-NEXT: b .LBB17_3
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; CHECK-NEXT: .LBB17_1: @ %if.else
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; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
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@ -1441,7 +1440,7 @@ define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instanc
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; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
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; CHECK-NEXT: vstr.16 s5, [r12, #2]
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; CHECK-NEXT: adds r6, #10
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; CHECK-NEXT: subs r0, #1
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; CHECK-NEXT: subs.w r9, r9, #1
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; CHECK-NEXT: add.w r12, r12, #4
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; CHECK-NEXT: mov r1, r2
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; CHECK-NEXT: beq .LBB17_8
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@ -1458,7 +1457,7 @@ define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instanc
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; CHECK-NEXT: vldrh.u16 q1, [r12]
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; CHECK-NEXT: vmov.f32 s5, s1
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; CHECK-NEXT: mov r5, r2
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||||
; CHECK-NEXT: wls lr, r9, .LBB17_6
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||||
; CHECK-NEXT: wls lr, r8, .LBB17_6
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||||
; CHECK-NEXT: @ %bb.4: @ %while.body.preheader
|
||||
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
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||||
; CHECK-NEXT: mov r5, r2
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||||
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|
@ -1466,7 +1465,7 @@ define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instanc
|
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; CHECK-NEXT: @ Parent Loop BB17_3 Depth=1
|
||||
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
|
||||
; CHECK-NEXT: ldrh r7, [r1], #4
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vfma.f16 q1, q2, r7
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||||
; CHECK-NEXT: ldrh r4, [r1, #-2]
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||||
; CHECK-NEXT: vmov.u16 r7, q1[0]
|
||||
|
|
@ -1478,19 +1477,19 @@ define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instanc
|
|||
; CHECK-NEXT: strh r4, [r5, #2]
|
||||
; CHECK-NEXT: vmov.f32 s4, s5
|
||||
; CHECK-NEXT: strh r7, [r5], #4
|
||||
; CHECK-NEXT: vmov.16 q1[2], r3
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: le lr, .LBB17_5
|
||||
; CHECK-NEXT: .LBB17_6: @ %while.end
|
||||
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
|
||||
; CHECK-NEXT: cmp.w r8, #0
|
||||
; CHECK-NEXT: lsls r0, r3, #31
|
||||
; CHECK-NEXT: beq .LBB17_1
|
||||
; CHECK-NEXT: @ %bb.7: @ %if.then
|
||||
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
|
||||
; CHECK-NEXT: ldrh r1, [r1]
|
||||
; CHECK-NEXT: vfma.f16 q1, q2, r1
|
||||
; CHECK-NEXT: vmov.u16 r1, q1[0]
|
||||
; CHECK-NEXT: vfma.f16 q1, q3, r1
|
||||
; CHECK-NEXT: strh r1, [r5]
|
||||
; CHECK-NEXT: ldrh r0, [r1]
|
||||
; CHECK-NEXT: vfma.f16 q1, q2, r0
|
||||
; CHECK-NEXT: vmov.u16 r0, q1[0]
|
||||
; CHECK-NEXT: vfma.f16 q1, q3, r0
|
||||
; CHECK-NEXT: strh r0, [r5]
|
||||
; CHECK-NEXT: vmovx.f16 s2, s4
|
||||
; CHECK-NEXT: vstr.16 s2, [r12]
|
||||
; CHECK-NEXT: b .LBB17_2
|
||||
|
|
|
|||
|
|
@ -2015,9 +2015,8 @@ define void @arm_biquad_cascade_df2T_f32(%struct.arm_biquad_cascade_df2T_instanc
|
|||
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: ldrd r12, r6, [r0, #4]
|
||||
; CHECK-NEXT: and r8, r3, #1
|
||||
; CHECK-NEXT: lsr.w r8, r3, #1
|
||||
; CHECK-NEXT: ldrb r0, [r0]
|
||||
; CHECK-NEXT: lsrs r3, r3, #1
|
||||
; CHECK-NEXT: vldr s0, .LCPI20_0
|
||||
; CHECK-NEXT: b .LBB20_3
|
||||
; CHECK-NEXT: .LBB20_1: @ %if.else
|
||||
|
|
@ -2046,7 +2045,7 @@ define void @arm_biquad_cascade_df2T_f32(%struct.arm_biquad_cascade_df2T_instanc
|
|||
; CHECK-NEXT: vmov.f32 s6, s0
|
||||
; CHECK-NEXT: mov r5, r2
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: wls lr, r3, .LBB20_6
|
||||
; CHECK-NEXT: wls lr, r8, .LBB20_6
|
||||
; CHECK-NEXT: @ %bb.4: @ %while.body.preheader
|
||||
; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1
|
||||
; CHECK-NEXT: vmov q6, q1
|
||||
|
|
@ -2073,7 +2072,7 @@ define void @arm_biquad_cascade_df2T_f32(%struct.arm_biquad_cascade_df2T_instanc
|
|||
; CHECK-NEXT: le lr, .LBB20_5
|
||||
; CHECK-NEXT: .LBB20_6: @ %while.end
|
||||
; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1
|
||||
; CHECK-NEXT: cmp.w r8, #0
|
||||
; CHECK-NEXT: lsls r7, r3, #31
|
||||
; CHECK-NEXT: beq .LBB20_1
|
||||
; CHECK-NEXT: @ %bb.7: @ %if.then
|
||||
; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1
|
||||
|
|
|
|||
Loading…
Reference in New Issue