Revert "[ISel] Match all bits when merge undef(s) for DAG combine"

This reverts commit 5fe5aa284e.
This commit is contained in:
Xiang1 Zhang 2022-07-01 08:59:04 +08:00
parent 5fe5aa284e
commit 64f44a90ef
5 changed files with 10 additions and 44 deletions

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@ -2239,16 +2239,12 @@ Optional<unsigned> GetMostSignificantDifferentBit(const APInt &A,
/// Splat/Merge neighboring bits to widen/narrow the bitmask represented /// Splat/Merge neighboring bits to widen/narrow the bitmask represented
/// by \param A to \param NewBitWidth bits. /// by \param A to \param NewBitWidth bits.
/// ///
/// MatchAnyBits: (Default)
/// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011 /// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011
/// e.g. ScaleBitMask(0b00011011, 4) -> 0b0111 /// e.g. ScaleBitMask(0b00011011, 4) -> 0b0111
///
/// MatchAllBits:
/// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011
/// e.g. ScaleBitMask(0b00011011, 4) -> 0b0001
/// A.getBitwidth() or NewBitWidth must be a whole multiples of the other. /// A.getBitwidth() or NewBitWidth must be a whole multiples of the other.
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, ///
bool MatchAllBits = false); /// TODO: Do we need a mode where all bits must be set when merging down?
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth);
} // namespace APIntOps } // namespace APIntOps
// See friend declaration above. This additional declaration is required in // See friend declaration above. This additional declaration is required in

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@ -2712,16 +2712,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
SubDemandedElts &= ScaledDemandedElts; SubDemandedElts &= ScaledDemandedElts;
if (!isSplatValue(Src, SubDemandedElts, SubUndefElts, Depth + 1)) if (!isSplatValue(Src, SubDemandedElts, SubUndefElts, Depth + 1))
return false; return false;
UndefElts |= APIntOps::ScaleBitMask(SubUndefElts, NumElts);
// Here we can't do "MatchAnyBits" operation merge for undef bits.
// Because some operation only use part value of the source.
// Take llvm.fshl.* for example:
// t1: v4i32 = Constant:i32<12>, undef:i32, Constant:i32<12>, undef:i32
// t2: v2i64 = bitcast t1
// t5: v2i64 = fshl t3, t4, t2
// We can not convert t2 to {i64 undef, i64 undef}
UndefElts |= APIntOps::ScaleBitMask(SubUndefElts, NumElts,
/*MatchAllBits=*/true);
} }
return true; return true;
} }

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@ -2968,8 +2968,7 @@ llvm::APIntOps::GetMostSignificantDifferentBit(const APInt &A, const APInt &B) {
return A.getBitWidth() - ((A ^ B).countLeadingZeros() + 1); return A.getBitWidth() - ((A ^ B).countLeadingZeros() + 1);
} }
APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth, APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth) {
bool MatchAllBits) {
unsigned OldBitWidth = A.getBitWidth(); unsigned OldBitWidth = A.getBitWidth();
assert((((OldBitWidth % NewBitWidth) == 0) || assert((((OldBitWidth % NewBitWidth) == 0) ||
((NewBitWidth % OldBitWidth) == 0)) && ((NewBitWidth % OldBitWidth) == 0)) &&
@ -2993,16 +2992,11 @@ APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth,
if (A[i]) if (A[i])
NewA.setBits(i * Scale, (i + 1) * Scale); NewA.setBits(i * Scale, (i + 1) * Scale);
} else { } else {
// Merge bits - if any old bit is set, then set scale equivalent new bit.
unsigned Scale = OldBitWidth / NewBitWidth; unsigned Scale = OldBitWidth / NewBitWidth;
for (unsigned i = 0; i != NewBitWidth; ++i) { for (unsigned i = 0; i != NewBitWidth; ++i)
if (MatchAllBits) { if (!A.extractBits(Scale, i * Scale).isZero())
if (A.extractBits(Scale, i * Scale).isAllOnes()) NewA.setBit(i);
NewA.setBit(i);
} else {
if (!A.extractBits(Scale, i * Scale).isZero())
NewA.setBit(i);
}
}
} }
return NewA; return NewA;

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@ -20,14 +20,8 @@
define void @test_fshl(<8 x i64> %lo, <8 x i64> %hi, <8 x i64>* %arr) { define void @test_fshl(<8 x i64> %lo, <8 x i64> %hi, <8 x i64>* %arr) {
; CHECK-LABEL: test_fshl: ; CHECK-LABEL: test_fshl:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $63, %eax
; CHECK-NEXT: vmovd %eax, %xmm2
; CHECK-NEXT: movl $12, %eax
; CHECK-NEXT: vmovd %eax, %xmm3
; CHECK-NEXT: vpand %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vpsllq %xmm2, %zmm1, %zmm1
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: vpsrlq $52, %zmm0, %zmm0 ; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
; CHECK-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0 ; CHECK-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; CHECK-NEXT: vmovdqa64 %zmm0, (%eax) ; CHECK-NEXT: vmovdqa64 %zmm0, (%eax)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper

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@ -3115,15 +3115,6 @@ TEST(APIntTest, ScaleBitMask) {
APInt::getAllOnes(256)); APInt::getAllOnes(256));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt::getOneBitSet(4096, 32), 256), EXPECT_EQ(APIntOps::ScaleBitMask(APInt::getOneBitSet(4096, 32), 256),
APInt::getOneBitSet(256, 2)); APInt::getOneBitSet(256, 2));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x00), 8, true), APInt(8, 0x00));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x01), 8, true), APInt(8, 0x0F));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x02), 8, true), APInt(8, 0xF0));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x03), 8, true), APInt(8, 0xFF));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0x00), 4, true), APInt(4, 0x00));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0xFF), 4, true), APInt(4, 0x0F));
EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0xE4), 4, true), APInt(4, 0x08));
} }
} // end anonymous namespace } // end anonymous namespace