Revert "[ISel] Match all bits when merge undef(s) for DAG combine"
This reverts commit 5fe5aa284e
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5fe5aa284e
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64f44a90ef
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@ -2239,16 +2239,12 @@ Optional<unsigned> GetMostSignificantDifferentBit(const APInt &A,
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/// Splat/Merge neighboring bits to widen/narrow the bitmask represented
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/// by \param A to \param NewBitWidth bits.
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///
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/// MatchAnyBits: (Default)
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/// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011
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/// e.g. ScaleBitMask(0b00011011, 4) -> 0b0111
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///
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/// MatchAllBits:
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/// e.g. ScaleBitMask(0b0101, 8) -> 0b00110011
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/// e.g. ScaleBitMask(0b00011011, 4) -> 0b0001
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/// A.getBitwidth() or NewBitWidth must be a whole multiples of the other.
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APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth,
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bool MatchAllBits = false);
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///
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/// TODO: Do we need a mode where all bits must be set when merging down?
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APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth);
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} // namespace APIntOps
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// See friend declaration above. This additional declaration is required in
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@ -2712,16 +2712,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
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SubDemandedElts &= ScaledDemandedElts;
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if (!isSplatValue(Src, SubDemandedElts, SubUndefElts, Depth + 1))
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return false;
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// Here we can't do "MatchAnyBits" operation merge for undef bits.
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// Because some operation only use part value of the source.
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// Take llvm.fshl.* for example:
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// t1: v4i32 = Constant:i32<12>, undef:i32, Constant:i32<12>, undef:i32
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// t2: v2i64 = bitcast t1
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// t5: v2i64 = fshl t3, t4, t2
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// We can not convert t2 to {i64 undef, i64 undef}
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UndefElts |= APIntOps::ScaleBitMask(SubUndefElts, NumElts,
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/*MatchAllBits=*/true);
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UndefElts |= APIntOps::ScaleBitMask(SubUndefElts, NumElts);
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}
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return true;
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}
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@ -2968,8 +2968,7 @@ llvm::APIntOps::GetMostSignificantDifferentBit(const APInt &A, const APInt &B) {
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return A.getBitWidth() - ((A ^ B).countLeadingZeros() + 1);
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}
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APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth,
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bool MatchAllBits) {
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APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth) {
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unsigned OldBitWidth = A.getBitWidth();
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assert((((OldBitWidth % NewBitWidth) == 0) ||
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((NewBitWidth % OldBitWidth) == 0)) &&
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@ -2993,16 +2992,11 @@ APInt llvm::APIntOps::ScaleBitMask(const APInt &A, unsigned NewBitWidth,
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if (A[i])
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NewA.setBits(i * Scale, (i + 1) * Scale);
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} else {
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// Merge bits - if any old bit is set, then set scale equivalent new bit.
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unsigned Scale = OldBitWidth / NewBitWidth;
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for (unsigned i = 0; i != NewBitWidth; ++i) {
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if (MatchAllBits) {
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if (A.extractBits(Scale, i * Scale).isAllOnes())
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NewA.setBit(i);
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} else {
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if (!A.extractBits(Scale, i * Scale).isZero())
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NewA.setBit(i);
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}
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}
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for (unsigned i = 0; i != NewBitWidth; ++i)
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if (!A.extractBits(Scale, i * Scale).isZero())
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NewA.setBit(i);
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}
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return NewA;
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@ -20,14 +20,8 @@
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define void @test_fshl(<8 x i64> %lo, <8 x i64> %hi, <8 x i64>* %arr) {
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; CHECK-LABEL: test_fshl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $63, %eax
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; CHECK-NEXT: vmovd %eax, %xmm2
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; CHECK-NEXT: movl $12, %eax
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; CHECK-NEXT: vmovd %eax, %xmm3
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; CHECK-NEXT: vpand %xmm2, %xmm3, %xmm2
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; CHECK-NEXT: vpsllq %xmm2, %zmm1, %zmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: vpsrlq $52, %zmm0, %zmm0
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; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
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; CHECK-NEXT: vpternlogq $168, {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
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; CHECK-NEXT: vmovdqa64 %zmm0, (%eax)
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; CHECK-NEXT: vzeroupper
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@ -3115,15 +3115,6 @@ TEST(APIntTest, ScaleBitMask) {
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APInt::getAllOnes(256));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt::getOneBitSet(4096, 32), 256),
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APInt::getOneBitSet(256, 2));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x00), 8, true), APInt(8, 0x00));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x01), 8, true), APInt(8, 0x0F));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x02), 8, true), APInt(8, 0xF0));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(2, 0x03), 8, true), APInt(8, 0xFF));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0x00), 4, true), APInt(4, 0x00));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0xFF), 4, true), APInt(4, 0x0F));
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EXPECT_EQ(APIntOps::ScaleBitMask(APInt(8, 0xE4), 4, true), APInt(4, 0x08));
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}
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} // end anonymous namespace
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