diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 47eb1582773b..4e13d2c18230 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -185,7 +185,6 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (RISCV::GPRF32RegClass.contains(SrcReg) &&
       RISCV::VGPRRegClass.contains(DstReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::VFMV_S_F), DstReg)
-        .addReg(DstReg, RegState::Undef)
         .addReg(SrcReg, getKillRegState(KillSrc));
     return;
   }
@@ -240,6 +239,10 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     Opcode = RISCV::FSW;
   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSD;
+  } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FSW;
+  } else if (RISCV::GPRF64RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FSW;
   } else if (RISCV::VGPRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VSW;
   } else
@@ -283,6 +286,10 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     Opcode = RISCV::FLW;
   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FLD;
+  } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FLW;
+  } else if (RISCV::GPRF64RegClass.hasSubClassEq(RC)) {
+    Opcode = RISCV::FLW;
   } else if (RISCV::VGPRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VLW;
   } else
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index a7338d94919d..5e3b64f3f0cb 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -216,6 +216,8 @@ RISCVRegisterInfo::getPhysRegClass(MCRegister Reg) const {
     */
     &RISCV::VGPRRegClass,
     &RISCV::GPRRegClass,
+    &RISCV::GPRF32RegClass,
+    &RISCV::GPRF64RegClass,
   };
 
   for (const TargetRegisterClass *BaseClass : BaseClasses) {
diff --git a/llvm/lib/Target/RISCV/VentusRegisterInfo.td b/llvm/lib/Target/RISCV/VentusRegisterInfo.td
index d0f3d18aaa1f..4b5050b5385d 100644
--- a/llvm/lib/Target/RISCV/VentusRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/VentusRegisterInfo.td
@@ -32,9 +32,11 @@ class RVRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
   // vALU and sALU registers
   field bit IsVGPR = 0;
   field bit IsSGPR = 0;
+  field bit IsFGPR = 0;
 
   let TSFlags{0} = IsVGPR;
   let TSFlags{1} = IsSGPR;
+  let TSFlags{2} = IsFGPR;
 }
 
 class RISCVReg<bits<8> Enc, string n, list<string> alt = []> : Register<n> {
@@ -240,6 +242,30 @@ let RegAltNameIndices = [ABIRegAltName] in {
   }
 }
 
+// Float registers
+
+let RegAltNameIndices = [ABIRegAltName] in {
+  let CostPerUse = [0, 1] in {
+    foreach Index = {5, 6, 7, 16...63} in {
+      defvar Reg = !cast<Register>("X"#Index);
+      def F#Index : RISCVRegWithSubRegs<Index, Reg.AsmName,
+                                            [!cast<Register>("X"#Index)],
+                                            Reg.AltNames> {
+        let SubRegIndices = [lo32];
+      }
+    }
+  }
+
+  foreach Index = [8, 9, 11, 12, 13, 14, 15] in {
+    defvar Reg = !cast<Register>("X"#Index);
+    def F#Index : RISCVRegWithSubRegs<Index, Reg.AsmName,
+                                          [!cast<Register>("X"#Index)],
+                                          Reg.AltNames> {
+      let SubRegIndices = [lo32];
+    }
+  }
+}
+
 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
                                [i32,  i64]>;
 def XLenRI : RegInfoByHwMode<
@@ -256,6 +282,14 @@ def GPR : RVRegisterClass<"RISCV", [XLenVT], 32, (add
   let IsSGPR = 1;
 }
 
+def FPR : RVRegisterClass<"RISCV", [f32], 32, (add
+    (sequence "F%u", 5, 9),
+    (sequence "F%u", 11, 63)
+  )> {
+  let RegInfos = XLenRI;
+  let IsFGPR = 1;
+}
+
 def GPRX0 : RVRegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
   let RegInfos = XLenRI;
   let IsSGPR = 1;
@@ -416,9 +450,9 @@ def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
 }
 
 let RegInfos = XLenRI in {
-def GPRF16  : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
-def GPRF32  : RegisterClass<"RISCV", [f32], 32, (add GPR)>;
-def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRF16  : RegisterClass<"RISCV", [f16], 16, (add FPR)>;
+def GPRF32  : RegisterClass<"RISCV", [f32], 32, (add FPR)>;
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add FPR)>;
 } // RegInfos = XLenRI
 
 let RegAltNameIndices = [ABIRegAltName] in {
diff --git a/llvm/test/CodeGen/RISCV/VentusGPGPU/load-store.ll b/llvm/test/CodeGen/RISCV/VentusGPGPU/load-store.ll
new file mode 100644
index 000000000000..90d1dd0e9044
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/VentusGPGPU/load-store.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=VENTUS %s
+
+; Function Attrs: convergent norecurse nounwind
+define dso_local ventus_kernel void @loadstore(float noundef %a, float noundef %b, float noundef %c, ptr addrspace(1) %ADDR, ptr addrspace(1) %ADDR1, ptr addrspace(1) %ADDR2) {
+; VENTUS-LABEL: loadstore:
+; VENTUS:       # %bb.0: # %entry
+; VENTUS-NEXT:    lw t0, 20(a0)
+; VENTUS-NEXT:    flw t1, 8(a0)
+; VENTUS-NEXT:    lw t2, 16(a0)
+; VENTUS-NEXT:    lw s0, 12(a0)
+; VENTUS-NEXT:    flw s1, 0(a0)
+; VENTUS-NEXT:    flw a1, 4(a0)
+; VENTUS-NEXT:    fsw s1, 0(s0)
+; VENTUS-NEXT:    fsw a1, 0(t2)
+; VENTUS-NEXT:    fsw t1, 0(t0)
+; VENTUS-NEXT:    ret
+entry:
+  store float %a, ptr addrspace(1) %ADDR
+  store float %b, ptr addrspace(1) %ADDR1
+  store float %c, ptr addrspace(1) %ADDR2
+  ret void
+}