[ARM] CSINC/CSINV patterns from CMOV
We sometimes end up generating CMOV with constant operands that can be simplified to CSINC or CSINV under Arm-8.1m. This adds some simple patterns for them. Differential Revision: https://reviews.llvm.org/D114349
This commit is contained in:
David Green
parent
ff649e0802
commit
5c64d8ef8c
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@ -5603,6 +5603,15 @@ let Predicates = [HasV8_1MMainline] in {
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defm : CSPats<ARMcsinv, t2CSINV>;
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defm : CSPats<ARMcsneg, t2CSNEG>;
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def : T2Pat<(ARMcmov (i32 1), (i32 0), cmovpred:$imm),
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(t2CSINC ZR, ZR, imm0_31:$imm)>;
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def : T2Pat<(ARMcmov (i32 -1), (i32 0), cmovpred:$imm),
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(t2CSINV ZR, ZR, imm0_31:$imm)>;
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def : T2Pat<(ARMcmov (i32 0), (i32 1), cmovpred:$imm),
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(t2CSINC ZR, ZR, (inv_cond_XFORM imm:$imm))>;
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def : T2Pat<(ARMcmov (i32 0), (i32 -1), cmovpred:$imm),
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(t2CSINV ZR, ZR, (inv_cond_XFORM imm:$imm))>;
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multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {
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def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm),
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(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
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@ -4,47 +4,42 @@
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define <2 x i64> @v2i64(i32 %index, i32 %TC, <2 x i64> %V1, <2 x i64> %V2) {
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; CHECK-LABEL: v2i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: vmov q0[2], q0[0], r0, r0
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; CHECK-NEXT: vmov.i64 q1, #0xffffffff
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: vmov q2[2], q2[0], r1, r1
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; CHECK-NEXT: vmov r0, r12, d1
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; CHECK-NEXT: movs r7, #0
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; CHECK-NEXT: adds.w r8, r0, #1
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; CHECK-NEXT: adc lr, r12, #0
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; CHECK-NEXT: vmov r12, s0
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; CHECK-NEXT: vmov q0[2], q0[0], r12, r8
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; CHECK-NEXT: vmov lr, s0
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; CHECK-NEXT: adds r0, #1
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; CHECK-NEXT: vmov q0[2], q0[0], lr, r0
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; CHECK-NEXT: adc r12, r12, #0
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: vand q1, q2, q1
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; CHECK-NEXT: vmov r4, r5, d1
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; CHECK-NEXT: vmov.i32 q2, #0x1
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; CHECK-NEXT: vmov r1, r6, d3
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; CHECK-NEXT: eors r0, r4
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; CHECK-NEXT: subs r1, r4, r1
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; CHECK-NEXT: sbcs.w r1, r5, r6
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; CHECK-NEXT: vmov r5, r6, d0
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; CHECK-NEXT: mov.w r1, #0
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo r1, #1
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; CHECK-NEXT: cset r1, lo
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: vmov r0, r1, d2
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; CHECK-NEXT: csetm r9, ne
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; CHECK-NEXT: subs r0, r5, r0
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; CHECK-NEXT: sbcs.w r0, r6, r1
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo r7, #1
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; CHECK-NEXT: cmp r7, #0
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; CHECK-NEXT: vmov r7, r1, d2
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; CHECK-NEXT: csetm r8, ne
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; CHECK-NEXT: subs r7, r5, r7
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; CHECK-NEXT: sbcs.w r1, r6, r1
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; CHECK-NEXT: cset r1, lo
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: orrs.w r0, r0, r12
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
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; CHECK-NEXT: eor.w r0, r4, r8
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; CHECK-NEXT: orrs.w r0, r0, lr
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: teq.w r5, r12
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; CHECK-NEXT: teq.w r5, lr
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r8
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
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; CHECK-NEXT: veor q1, q1, q2
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; CHECK-NEXT: vldr d5, [sp, #32]
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; CHECK-NEXT: vldr d5, [sp, #24]
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; CHECK-NEXT: vand q0, q1, q0
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; CHECK-NEXT: vmov d4, r2, r3
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; CHECK-NEXT: vmov r0, s2
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@ -55,15 +50,14 @@ define <2 x i64> @v2i64(i32 %index, i32 %TC, <2 x i64> %V1, <2 x i64> %V2) {
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
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; CHECK-NEXT: add r0, sp, #40
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; CHECK-NEXT: add r0, sp, #32
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vbic q1, q1, q0
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; CHECK-NEXT: vand q0, q2, q0
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; CHECK-NEXT: vorr q0, q0, q1
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
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%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
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%select = select <2 x i1> %active.lane.mask, <2 x i64> %V1, <2 x i64> %V2
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ret <2 x i64> %select
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@ -467,43 +461,39 @@ define void @test_width2(i32* nocapture readnone %x, i32* nocapture %y, i8 zeroe
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; CHECK-NEXT: vmov.i64 q0, #0xffffffff
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; CHECK-NEXT: vldrw.u32 q2, [r2]
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; CHECK-NEXT: add.w lr, r3, r0, lsr #1
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: mov.w r8, #0
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; CHECK-NEXT: vand q1, q1, q0
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; CHECK-NEXT: .LBB5_2: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vmov q3[2], q3[0], r12, r12
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; CHECK-NEXT: vmov q3[2], q3[0], r8, r8
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; CHECK-NEXT: vmov r6, r7, d3
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; CHECK-NEXT: vand q3, q3, q0
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; CHECK-NEXT: add.w r12, r12, #2
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; CHECK-NEXT: add.w r8, r8, #2
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; CHECK-NEXT: vmov r2, r3, d7
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; CHECK-NEXT: vmov r9, s12
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; CHECK-NEXT: adds r0, r2, #1
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; CHECK-NEXT: vmov q3[2], q3[0], r9, r0
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; CHECK-NEXT: adc r8, r3, #0
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; CHECK-NEXT: adds r2, #1
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; CHECK-NEXT: vmov q3[2], q3[0], r9, r2
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; CHECK-NEXT: adc r12, r3, #0
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; CHECK-NEXT: vand q3, q3, q0
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; CHECK-NEXT: vmov r3, r2, d2
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; CHECK-NEXT: vmov r0, r3, d2
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; CHECK-NEXT: vmov r4, r5, d7
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; CHECK-NEXT: subs r6, r4, r6
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; CHECK-NEXT: eor.w r0, r0, r4
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; CHECK-NEXT: sbcs r5, r7
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; CHECK-NEXT: vmov r6, r7, d6
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; CHECK-NEXT: mov.w r5, #0
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo r5, #1
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; CHECK-NEXT: cset r5, lo
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; CHECK-NEXT: cmp r5, #0
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; CHECK-NEXT: csetm r5, ne
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; CHECK-NEXT: subs r3, r6, r3
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; CHECK-NEXT: sbcs.w r2, r7, r2
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; CHECK-NEXT: mov.w r2, #0
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: csetm r2, ne
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; CHECK-NEXT: orrs.w r0, r0, r8
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; CHECK-NEXT: vmov q3[2], q3[0], r2, r5
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; CHECK-NEXT: subs r0, r6, r0
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; CHECK-NEXT: sbcs.w r0, r7, r3
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; CHECK-NEXT: cset r0, lo
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: vmov q3[2], q3[0], r0, r5
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; CHECK-NEXT: vmov q3[3], q3[1], r0, r5
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; CHECK-NEXT: eor.w r0, r4, r2
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; CHECK-NEXT: orrs.w r0, r0, r12
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: teq.w r6, r9
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; CHECK-NEXT: vmov q3[3], q3[1], r2, r5
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; CHECK-NEXT: csetm r2, ne
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; CHECK-NEXT: vmov q4[2], q4[0], r2, r0
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; CHECK-NEXT: vmov q4[3], q4[1], r2, r0
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@ -404,87 +404,71 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
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; CHECK-MVE-NEXT: vmovx.f16 s13, s0
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; CHECK-MVE-NEXT: vcmp.f16 s14, #0
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; CHECK-MVE-NEXT: vmovx.f16 s12, s8
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; CHECK-MVE-NEXT: vmov.f32 s15, s13
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmov.f32 s15, s13
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; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vcmp.f16 s4, #0
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; CHECK-MVE-NEXT: vmov.f32 s14, s0
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; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s5
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; CHECK-MVE-NEXT: vmovx.f16 s4, s9
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vcmp.f16 s8, #0
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
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; CHECK-MVE-NEXT: vmovx.f16 s8, s5
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: vins.f16 s0, s12
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; CHECK-MVE-NEXT: vmovx.f16 s12, s1
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; CHECK-MVE-NEXT: vcmp.f16 s8, #0
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; CHECK-MVE-NEXT: vmovx.f16 s4, s9
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; CHECK-MVE-NEXT: vmov.f32 s14, s12
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vcmp.f16 s5, #0
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; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
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; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
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; CHECK-MVE-NEXT: vmov.f32 s8, s1
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: vmovx.f16 s12, s2
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; CHECK-MVE-NEXT: vmov.f32 s14, s12
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s6
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; CHECK-MVE-NEXT: vmovx.f16 s12, s2
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; CHECK-MVE-NEXT: vcmp.f16 s8, #0
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; CHECK-MVE-NEXT: vins.f16 s1, s4
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmovx.f16 s4, s10
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; CHECK-MVE-NEXT: vmov.f32 s14, s12
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vcmp.f16 s6, #0
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; CHECK-MVE-NEXT: vmov.f32 s8, s2
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; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
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; CHECK-MVE-NEXT: vmovx.f16 s6, s7
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vmovx.f16 s6, s7
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; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s3
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; CHECK-MVE-NEXT: vcmp.f16 s6, #0
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; CHECK-MVE-NEXT: vins.f16 s2, s4
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmovx.f16 s8, s3
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; CHECK-MVE-NEXT: vins.f16 s2, s4
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; CHECK-MVE-NEXT: vmovx.f16 s4, s11
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; CHECK-MVE-NEXT: vmov.f32 s10, s8
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vcmp.f16 s7, #0
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; CHECK-MVE-NEXT: vmov.f32 s6, s3
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; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
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; CHECK-MVE-NEXT: movs r0, #0
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r0, #1
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; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
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; CHECK-MVE-NEXT: vins.f16 s3, s4
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@ -517,87 +501,71 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
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; CHECK-MVE-NEXT: vmovx.f16 s13, s0
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; CHECK-MVE-NEXT: vcmp.f16 s14, #0
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; CHECK-MVE-NEXT: vmovx.f16 s12, s8
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; CHECK-MVE-NEXT: vmov.f32 s15, s13
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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; CHECK-MVE-NEXT: vmov.f32 s15, s13
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; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
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; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-NEXT: movmi r1, #1
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; CHECK-MVE-NEXT: cmp r1, #0
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; CHECK-MVE-NEXT: vcmp.f16 s4, #0
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; CHECK-MVE-NEXT: vmov.f32 s14, s0
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; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s5
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; CHECK-MVE-NEXT: vmovx.f16 s4, s9
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; CHECK-MVE-NEXT: cset r0, mi
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; CHECK-MVE-NEXT: cmp r0, #0
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; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
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; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-MVE-NEXT: mov.w r1, #0
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||||
; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vins.f16 s0, s12
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s1
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
|
||||
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s6
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s1, s4
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s2
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s2, s4
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
|
||||
; CHECK-MVE-NEXT: vins.f16 s2, s4
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s6, s3
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
|
||||
; CHECK-MVE-NEXT: vins.f16 s3, s4
|
||||
|
|
@ -630,87 +598,71 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
|
|||
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s15, s13
|
||||
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vins.f16 s0, s12
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s1
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
|
||||
; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s8, s5, s9
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s6
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s1, s4
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s2
|
||||
; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s2, s4
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
|
||||
; CHECK-MVE-NEXT: vins.f16 s2, s4
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmls.f16 s10, s6, s4
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s6, s3
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: vmls.f16 s6, s7, s11
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
|
||||
; CHECK-MVE-NEXT: vins.f16 s3, s4
|
||||
|
|
@ -748,44 +700,35 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
|||
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s10, #0
|
||||
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vins.f16 s0, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s10, s1
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s10
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s1
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s5, s8
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s10, s2
|
||||
; CHECK-MVE-NEXT: vins.f16 s1, s4
|
||||
|
|
@ -793,39 +736,32 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
|
|||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s10
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s2
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s2
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s6
|
||||
; CHECK-MVE-NEXT: vins.f16 s2, s4
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s6
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s6, s3
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s6, s3
|
||||
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s8
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
|
||||
; CHECK-MVE-NEXT: vins.f16 s3, s4
|
||||
|
|
@ -865,83 +801,67 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
|
|||
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s10, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s14, s12, s10
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s0, s10
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vins.f16 s0, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s10, s1
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s5, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s1, s5
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s8
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s10, s2
|
||||
; CHECK-MVE-NEXT: vins.f16 s1, s4
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s2, s6
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: vins.f16 s2, s4
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
|
||||
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: mov.w r1, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: vcmp.f16 s7, #0
|
||||
; CHECK-MVE-NEXT: vmla.f16 s8, s3, s7
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s8
|
||||
; CHECK-MVE-NEXT: vins.f16 s3, s4
|
||||
|
|
@ -973,41 +893,33 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
|
|||
;
|
||||
; CHECK-MVE-LABEL: vfma32_v1_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r2, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-MVE-NEXT: mov.w r0, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
|
||||
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11
|
||||
; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: cset r1, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r2, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: cset r3, mi
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -1034,41 +946,33 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
|
|||
;
|
||||
; CHECK-MVE-LABEL: vfma32_v2_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r2, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-MVE-NEXT: mov.w r0, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
|
||||
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11
|
||||
; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: cset r1, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r2, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: cset r3, mi
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -1095,41 +999,33 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
|
|||
;
|
||||
; CHECK-MVE-LABEL: vfms32_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r2, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s1
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-MVE-NEXT: mov.w r0, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s8, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9
|
||||
; CHECK-MVE-NEXT: vmls.f32 s4, s7, s11
|
||||
; CHECK-MVE-NEXT: vmls.f32 s8, s6, s10
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: cset r1, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: cset r2, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: cset r3, mi
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -1159,41 +1055,33 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
|
|||
;
|
||||
; CHECK-MVE-LABEL: vfmar32_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r2, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s14, s2
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s1
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s8
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
|
||||
; CHECK-MVE-NEXT: cset r1, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: movs r0, #0
|
||||
; CHECK-MVE-NEXT: cset r2, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s8
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
|
||||
; CHECK-MVE-NEXT: cset r3, mi
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -1224,40 +1112,32 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
|
|||
;
|
||||
; CHECK-MVE-LABEL: vfmas32_pred:
|
||||
; CHECK-MVE: @ %bb.0: @ %entry
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s8
|
||||
; CHECK-MVE-NEXT: movs r1, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-MVE-NEXT: movs r2, #0
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s12, s8
|
||||
; CHECK-MVE-NEXT: vmov.f32 s10, s8
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r1, #1
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s8
|
||||
; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
|
||||
; CHECK-MVE-NEXT: vmla.f32 s4, s3, s7
|
||||
; CHECK-MVE-NEXT: cset r0, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r2, #1
|
||||
; CHECK-MVE-NEXT: cset r1, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
|
||||
; CHECK-MVE-NEXT: mov.w r3, #0
|
||||
; CHECK-MVE-NEXT: vmov.f32 s4, s8
|
||||
; CHECK-MVE-NEXT: mov.w r0, #0
|
||||
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r3, #1
|
||||
; CHECK-MVE-NEXT: cset r2, mi
|
||||
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-MVE-NEXT: it mi
|
||||
; CHECK-MVE-NEXT: movmi r0, #1
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
|
||||
; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
|
||||
; CHECK-MVE-NEXT: vmla.f32 s4, s3, s7
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
|
||||
; CHECK-MVE-NEXT: cset r3, mi
|
||||
; CHECK-MVE-NEXT: cmp r2, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
|
||||
; CHECK-MVE-NEXT: cmp r3, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
|
||||
; CHECK-MVE-NEXT: cmp r0, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
|
||||
; CHECK-MVE-NEXT: cmp r1, #0
|
||||
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
|
||||
; CHECK-MVE-NEXT: bx lr
|
||||
entry:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -93,61 +93,55 @@ define void @foo_sext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32>
|
|||
; CHECK-LE-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: ldrd lr, r5, [r1]
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: @ implicit-def: $q0
|
||||
; CHECK-LE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r4, r5, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: ldrd lr, r1, [r1]
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r12, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
|
||||
; CHECK-LE-NEXT: cset r3, lt
|
||||
; CHECK-LE-NEXT: @ implicit-def: $q1
|
||||
; CHECK-LE-NEXT: vmov q0[2], q0[0], lr, r1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: vmov r4, s4
|
||||
; CHECK-LE-NEXT: rsbs.w r4, lr, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
|
||||
; CHECK-LE-NEXT: mov.w lr, #0
|
||||
; CHECK-LE-NEXT: cset r4, lt
|
||||
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
|
||||
; CHECK-LE-NEXT: and r12, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r1, r3, #31
|
||||
; CHECK-LE-NEXT: lsls r3, r3, #31
|
||||
; CHECK-LE-NEXT: itt ne
|
||||
; CHECK-LE-NEXT: ldrne r1, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r1
|
||||
; CHECK-LE-NEXT: ldrne r3, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q1[0], r3
|
||||
; CHECK-LE-NEXT: lsls.w r1, r12, #30
|
||||
; CHECK-LE-NEXT: itt mi
|
||||
; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
|
||||
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
|
||||
; CHECK-LE-NEXT: vmov r3, s0
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmov r1, s2
|
||||
; CHECK-LE-NEXT: vmov q0[2], q0[0], r3, r1
|
||||
; CHECK-LE-NEXT: rsbs r5, r4, #0
|
||||
; CHECK-LE-NEXT: asr.w lr, r3, #31
|
||||
; CHECK-LE-NEXT: vmov r3, s6
|
||||
; CHECK-LE-NEXT: vmovmi.32 q1[2], r1
|
||||
; CHECK-LE-NEXT: vmov r1, s6
|
||||
; CHECK-LE-NEXT: vmov r2, s2
|
||||
; CHECK-LE-NEXT: vmov r3, s4
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], r3, r1
|
||||
; CHECK-LE-NEXT: rsbs r5, r2, #0
|
||||
; CHECK-LE-NEXT: asr.w r12, r1, #31
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r2, r4, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: vmov q0[3], q0[1], lr, r12
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r5, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r2, #1
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r2, asr #31
|
||||
; CHECK-LE-NEXT: vmov r1, s0
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: asr.w r4, r3, #31
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: vmov q1[3], q1[1], r4, r12
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r1, asr #31
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: vstrne d0, [r0]
|
||||
; CHECK-LE-NEXT: vstrne d2, [r0]
|
||||
; CHECK-LE-NEXT: lsls r1, r1, #30
|
||||
; CHECK-LE-NEXT: it mi
|
||||
; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
|
||||
; CHECK-LE-NEXT: vstrmi d3, [r0, #8]
|
||||
; CHECK-LE-NEXT: add sp, #4
|
||||
; CHECK-LE-NEXT: pop {r4, r5, r7, pc}
|
||||
;
|
||||
|
|
@ -157,23 +151,20 @@ define void @foo_sext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32>
|
|||
; CHECK-BE-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: ldrd r12, lr, [r1]
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt.w lr, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: ldrd r3, lr, [r1]
|
||||
; CHECK-BE-NEXT: mov.w r12, #0
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q2
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: vmov q0[3], q0[1], r3, lr
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-BE-NEXT: cset r3, lt
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, lr, #0, #1
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q2
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r3, r3, #30
|
||||
; CHECK-BE-NEXT: bpl .LBB5_2
|
||||
|
|
@ -193,31 +184,28 @@ define void @foo_sext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32>
|
|||
; CHECK-BE-NEXT: .LBB5_4: @ %else2
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q2
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q1
|
||||
; CHECK-BE-NEXT: vmov r2, s11
|
||||
; CHECK-BE-NEXT: movs r4, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s3
|
||||
; CHECK-BE-NEXT: movs r4, #0
|
||||
; CHECK-BE-NEXT: vmov r3, s1
|
||||
; CHECK-BE-NEXT: rsbs r5, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
|
||||
; CHECK-BE-NEXT: vmov r2, s9
|
||||
; CHECK-BE-NEXT: asr.w r12, r1, #31
|
||||
; CHECK-BE-NEXT: asr.w lr, r3, #31
|
||||
; CHECK-BE-NEXT: rsbs r5, r2, #0
|
||||
; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12
|
||||
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r1, #1
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: rsbs r3, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r4, #1
|
||||
; CHECK-BE-NEXT: cmp r4, #0
|
||||
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1
|
||||
; CHECK-BE-NEXT: vmov r1, s11
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r4, #1
|
||||
; CHECK-BE-NEXT: bfi r4, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r4, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r4, #30
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r4, r1, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: it mi
|
||||
; CHECK-BE-NEXT: vstrmi d0, [r0]
|
||||
; CHECK-BE-NEXT: lsls r1, r1, #31
|
||||
|
|
@ -241,53 +229,47 @@ define void @foo_sext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask,
|
|||
; CHECK-LE-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: ldrd lr, r5, [r1]
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: ldrd lr, r1, [r1]
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r12, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
|
||||
; CHECK-LE-NEXT: cset r3, lt
|
||||
; CHECK-LE-NEXT: @ implicit-def: $q0
|
||||
; CHECK-LE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r4, r5, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: vmov r4, s4
|
||||
; CHECK-LE-NEXT: rsbs.w r4, lr, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
|
||||
; CHECK-LE-NEXT: mov.w lr, #0
|
||||
; CHECK-LE-NEXT: cset r4, lt
|
||||
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
|
||||
; CHECK-LE-NEXT: and r12, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r1, r3, #31
|
||||
; CHECK-LE-NEXT: lsls r3, r3, #31
|
||||
; CHECK-LE-NEXT: itt ne
|
||||
; CHECK-LE-NEXT: ldrne r1, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r1
|
||||
; CHECK-LE-NEXT: ldrne r3, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r3
|
||||
; CHECK-LE-NEXT: lsls.w r1, r12, #30
|
||||
; CHECK-LE-NEXT: itt mi
|
||||
; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
|
||||
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
|
||||
; CHECK-LE-NEXT: vmov r3, s0
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmov r1, s2
|
||||
; CHECK-LE-NEXT: vmov r2, s6
|
||||
; CHECK-LE-NEXT: vmov r3, s0
|
||||
; CHECK-LE-NEXT: vmov q0[2], q0[0], r3, r1
|
||||
; CHECK-LE-NEXT: rsbs r5, r4, #0
|
||||
; CHECK-LE-NEXT: asr.w lr, r3, #31
|
||||
; CHECK-LE-NEXT: vmov r3, s6
|
||||
; CHECK-LE-NEXT: rsbs r5, r2, #0
|
||||
; CHECK-LE-NEXT: asr.w r12, r1, #31
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r2, r4, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: vmov q0[3], q0[1], lr, r12
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r5, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r2, #1
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r2, asr #31
|
||||
; CHECK-LE-NEXT: vmov r1, s4
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: asr.w r4, r3, #31
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: vmov q0[3], q0[1], r4, r12
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r1, asr #31
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
|
|
@ -307,23 +289,20 @@ define void @foo_sext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask,
|
|||
; CHECK-BE-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: ldrd r12, lr, [r1]
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt.w lr, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: ldrd r3, lr, [r1]
|
||||
; CHECK-BE-NEXT: mov.w r12, #0
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q2
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: vmov q0[3], q0[1], r3, lr
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-BE-NEXT: cset r3, lt
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, lr, #0, #1
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q2
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r3, r3, #30
|
||||
; CHECK-BE-NEXT: bpl .LBB6_2
|
||||
|
|
@ -343,31 +322,28 @@ define void @foo_sext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask,
|
|||
; CHECK-BE-NEXT: .LBB6_4: @ %else2
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q2
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q1
|
||||
; CHECK-BE-NEXT: vmov r2, s11
|
||||
; CHECK-BE-NEXT: movs r4, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s3
|
||||
; CHECK-BE-NEXT: movs r4, #0
|
||||
; CHECK-BE-NEXT: vmov r3, s1
|
||||
; CHECK-BE-NEXT: rsbs r5, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
|
||||
; CHECK-BE-NEXT: vmov r2, s9
|
||||
; CHECK-BE-NEXT: asr.w r12, r1, #31
|
||||
; CHECK-BE-NEXT: asr.w lr, r3, #31
|
||||
; CHECK-BE-NEXT: rsbs r5, r2, #0
|
||||
; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12
|
||||
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r1, #1
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: rsbs r3, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r4, #1
|
||||
; CHECK-BE-NEXT: cmp r4, #0
|
||||
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1
|
||||
; CHECK-BE-NEXT: vmov r1, s11
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r4, #1
|
||||
; CHECK-BE-NEXT: bfi r4, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r4, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r4, #30
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r4, r1, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: itt mi
|
||||
; CHECK-BE-NEXT: vmovmi r2, r3, d0
|
||||
; CHECK-BE-NEXT: strdmi r3, r2, [r0]
|
||||
|
|
@ -389,53 +365,47 @@ entry:
|
|||
define void @foo_zext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) {
|
||||
; CHECK-LE-LABEL: foo_zext_v2i64_v2i32:
|
||||
; CHECK-LE: @ %bb.0: @ %entry
|
||||
; CHECK-LE-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-LE-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-LE-NEXT: .save {r4, lr}
|
||||
; CHECK-LE-NEXT: push {r4, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: ldrd lr, r5, [r1]
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: ldrd lr, r1, [r1]
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r12, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
|
||||
; CHECK-LE-NEXT: cset r3, lt
|
||||
; CHECK-LE-NEXT: @ implicit-def: $q0
|
||||
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-LE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r4, r5, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: rsbs.w r4, lr, #0
|
||||
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
|
||||
; CHECK-LE-NEXT: cset r4, lt
|
||||
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
|
||||
; CHECK-LE-NEXT: and r12, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r1, r3, #31
|
||||
; CHECK-LE-NEXT: lsls r3, r3, #31
|
||||
; CHECK-LE-NEXT: itt ne
|
||||
; CHECK-LE-NEXT: ldrne r1, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r1
|
||||
; CHECK-LE-NEXT: ldrne r3, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r3
|
||||
; CHECK-LE-NEXT: lsls.w r1, r12, #30
|
||||
; CHECK-LE-NEXT: itt mi
|
||||
; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
|
||||
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
|
||||
; CHECK-LE-NEXT: vmov r1, s4
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmov r2, s6
|
||||
; CHECK-LE-NEXT: movs r1, #0
|
||||
; CHECK-LE-NEXT: vand q0, q0, q2
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: vmov r3, s6
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r2, r1, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r5, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r3, r2, #0
|
||||
; CHECK-LE-NEXT: vmov r3, s4
|
||||
; CHECK-LE-NEXT: sbcs.w r2, r1, r2, asr #31
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r4, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r1, r3, asr #31
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
|
|
@ -445,7 +415,7 @@ define void @foo_zext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32>
|
|||
; CHECK-LE-NEXT: it mi
|
||||
; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
|
||||
; CHECK-LE-NEXT: add sp, #4
|
||||
; CHECK-LE-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-LE-NEXT: pop {r4, pc}
|
||||
;
|
||||
; CHECK-BE-LABEL: foo_zext_v2i64_v2i32:
|
||||
; CHECK-BE: @ %bb.0: @ %entry
|
||||
|
|
@ -453,59 +423,53 @@ define void @foo_zext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32>
|
|||
; CHECK-BE-NEXT: push {r7, lr}
|
||||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: ldrd r12, lr, [r1]
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt.w lr, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: ldrd r3, lr, [r1]
|
||||
; CHECK-BE-NEXT: mov.w r12, #0
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q0
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, lr
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-BE-NEXT: cset r3, lt
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, lr, #0, #1
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q1
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r3, r3, #30
|
||||
; CHECK-BE-NEXT: bpl .LBB7_2
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
|
||||
; CHECK-BE-NEXT: ldr r3, [r2]
|
||||
; CHECK-BE-NEXT: vmov.32 q2[1], r3
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q2
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q2
|
||||
; CHECK-BE-NEXT: .LBB7_2: @ %else
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q0
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q1
|
||||
; CHECK-BE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-BE-NEXT: beq .LBB7_4
|
||||
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
|
||||
; CHECK-BE-NEXT: ldr r1, [r2, #4]
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: vmov.32 q1[3], r1
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: .LBB7_4: @ %else2
|
||||
; CHECK-BE-NEXT: vrev64.32 q3, q2
|
||||
; CHECK-BE-NEXT: movs r2, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s15
|
||||
; CHECK-BE-NEXT: mov.w r12, #0
|
||||
; CHECK-BE-NEXT: vmov.i64 q0, #0xffffffff
|
||||
; CHECK-BE-NEXT: vand q0, q1, q0
|
||||
; CHECK-BE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-BE-NEXT: vmov r3, s13
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r2, r1, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt.w r12, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r2, r3, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r2, #1
|
||||
; CHECK-BE-NEXT: vmov r2, s13
|
||||
; CHECK-BE-NEXT: vmov.i64 q1, #0xffffffff
|
||||
; CHECK-BE-NEXT: vand q0, q0, q1
|
||||
; CHECK-BE-NEXT: rsbs r3, r2, #0
|
||||
; CHECK-BE-NEXT: vmov r3, s15
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r12, r2, asr #31
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: bfi r2, r12, #0, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: it mi
|
||||
|
|
@ -527,53 +491,47 @@ entry:
|
|||
define void @foo_zext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) {
|
||||
; CHECK-LE-LABEL: foo_zext_v2i64_v2i32_unaligned:
|
||||
; CHECK-LE: @ %bb.0: @ %entry
|
||||
; CHECK-LE-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-LE-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-LE-NEXT: .save {r4, lr}
|
||||
; CHECK-LE-NEXT: push {r4, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: ldrd lr, r5, [r1]
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: ldrd lr, r1, [r1]
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r12, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
|
||||
; CHECK-LE-NEXT: cset r3, lt
|
||||
; CHECK-LE-NEXT: @ implicit-def: $q0
|
||||
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-LE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r4, r5, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: rsbs.w r4, lr, #0
|
||||
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
|
||||
; CHECK-LE-NEXT: cset r4, lt
|
||||
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
|
||||
; CHECK-LE-NEXT: and r12, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r1, r3, #31
|
||||
; CHECK-LE-NEXT: lsls r3, r3, #31
|
||||
; CHECK-LE-NEXT: itt ne
|
||||
; CHECK-LE-NEXT: ldrne r1, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r1
|
||||
; CHECK-LE-NEXT: ldrne r3, [r2]
|
||||
; CHECK-LE-NEXT: vmovne.32 q0[0], r3
|
||||
; CHECK-LE-NEXT: lsls.w r1, r12, #30
|
||||
; CHECK-LE-NEXT: itt mi
|
||||
; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
|
||||
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
|
||||
; CHECK-LE-NEXT: vmov r1, s4
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmov r2, s6
|
||||
; CHECK-LE-NEXT: movs r1, #0
|
||||
; CHECK-LE-NEXT: vand q0, q0, q2
|
||||
; CHECK-LE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-LE-NEXT: vmov r3, s6
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r2, r1, asr #31
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs r5, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r3, r2, #0
|
||||
; CHECK-LE-NEXT: vmov r3, s4
|
||||
; CHECK-LE-NEXT: sbcs.w r2, r1, r2, asr #31
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r4, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r1, r3, asr #31
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
|
|
@ -585,7 +543,7 @@ define void @foo_zext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask,
|
|||
; CHECK-LE-NEXT: vmovmi r1, r2, d1
|
||||
; CHECK-LE-NEXT: strdmi r1, r2, [r0, #8]
|
||||
; CHECK-LE-NEXT: add sp, #4
|
||||
; CHECK-LE-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-LE-NEXT: pop {r4, pc}
|
||||
;
|
||||
; CHECK-BE-LABEL: foo_zext_v2i64_v2i32_unaligned:
|
||||
; CHECK-BE: @ %bb.0: @ %entry
|
||||
|
|
@ -593,59 +551,53 @@ define void @foo_zext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask,
|
|||
; CHECK-BE-NEXT: push {r7, lr}
|
||||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: ldrd r12, lr, [r1]
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31
|
||||
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt.w lr, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: ldrd r3, lr, [r1]
|
||||
; CHECK-BE-NEXT: mov.w r12, #0
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q0
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, lr
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-BE-NEXT: cset r3, lt
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, lr, #0, #1
|
||||
; CHECK-BE-NEXT: @ implicit-def: $q1
|
||||
; CHECK-BE-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r3, r3, #30
|
||||
; CHECK-BE-NEXT: bpl .LBB8_2
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
|
||||
; CHECK-BE-NEXT: ldr r3, [r2]
|
||||
; CHECK-BE-NEXT: vmov.32 q2[1], r3
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q2
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q2
|
||||
; CHECK-BE-NEXT: .LBB8_2: @ %else
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q0
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q1
|
||||
; CHECK-BE-NEXT: lsls r1, r1, #31
|
||||
; CHECK-BE-NEXT: beq .LBB8_4
|
||||
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
|
||||
; CHECK-BE-NEXT: ldr r1, [r2, #4]
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: vmov.32 q1[3], r1
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: .LBB8_4: @ %else2
|
||||
; CHECK-BE-NEXT: vrev64.32 q3, q2
|
||||
; CHECK-BE-NEXT: movs r2, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s15
|
||||
; CHECK-BE-NEXT: mov.w r12, #0
|
||||
; CHECK-BE-NEXT: vmov.i64 q0, #0xffffffff
|
||||
; CHECK-BE-NEXT: vand q0, q1, q0
|
||||
; CHECK-BE-NEXT: rsbs r3, r1, #0
|
||||
; CHECK-BE-NEXT: vmov r3, s13
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r2, r1, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt.w r12, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r2, r3, asr #31
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r2, #1
|
||||
; CHECK-BE-NEXT: vmov r2, s13
|
||||
; CHECK-BE-NEXT: vmov.i64 q1, #0xffffffff
|
||||
; CHECK-BE-NEXT: vand q0, q0, q1
|
||||
; CHECK-BE-NEXT: rsbs r3, r2, #0
|
||||
; CHECK-BE-NEXT: vmov r3, s15
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r12, r2, asr #31
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: bfi r2, r12, #0, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: itt mi
|
||||
|
|
|
|||
|
|
@ -1754,24 +1754,21 @@ define arm_aapcs_vfpcc <2 x i64> @masked_v2i64_align4_zero(<2 x i64> *%dest, <2
|
|||
; CHECK-LE-NEXT: push {r7, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d0
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: vmov lr, r12, d1
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d1
|
||||
; CHECK-LE-NEXT: mov.w lr, #0
|
||||
; CHECK-LE-NEXT: vmov r3, r12, d0
|
||||
; CHECK-LE-NEXT: rsbs r1, r1, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, r2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r2
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r3, #31
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
; CHECK-LE-NEXT: beq .LBB49_2
|
||||
; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
|
||||
; CHECK-LE-NEXT: vldr d1, .LCPI49_0
|
||||
|
|
@ -1798,24 +1795,21 @@ define arm_aapcs_vfpcc <2 x i64> @masked_v2i64_align4_zero(<2 x i64> *%dest, <2
|
|||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r3, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d3
|
||||
; CHECK-BE-NEXT: vmov r12, lr, d2
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d2
|
||||
; CHECK-BE-NEXT: vmov r12, r3, d3
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r1
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r1, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r1
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r3, #30
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: bpl .LBB49_2
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
|
||||
; CHECK-BE-NEXT: vldr d1, .LCPI49_0
|
||||
|
|
@ -1847,24 +1841,21 @@ define arm_aapcs_vfpcc <2 x double> @masked_v2f64_align4_zero(<2 x double> *%des
|
|||
; CHECK-LE-NEXT: push {r7, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d2
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: vmov lr, r12, d3
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d3
|
||||
; CHECK-LE-NEXT: mov.w lr, #0
|
||||
; CHECK-LE-NEXT: vmov r3, r12, d2
|
||||
; CHECK-LE-NEXT: rsbs r1, r1, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, r2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r2
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r3, #31
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
; CHECK-LE-NEXT: beq .LBB50_2
|
||||
; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
|
||||
; CHECK-LE-NEXT: vldr d1, .LCPI50_0
|
||||
|
|
@ -1891,24 +1882,21 @@ define arm_aapcs_vfpcc <2 x double> @masked_v2f64_align4_zero(<2 x double> *%des
|
|||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q0, q1
|
||||
; CHECK-BE-NEXT: movs r3, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d1
|
||||
; CHECK-BE-NEXT: vmov r12, lr, d0
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d0
|
||||
; CHECK-BE-NEXT: vmov r12, r3, d1
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r1
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r1, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r1
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r3, #30
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: bpl .LBB50_2
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
|
||||
; CHECK-BE-NEXT: vldr d1, .LCPI50_0
|
||||
|
|
|
|||
|
|
@ -939,24 +939,21 @@ define arm_aapcs_vfpcc void @masked_v2i64(<2 x i64> *%dest, <2 x i64> %a) {
|
|||
; CHECK-LE-NEXT: push {r7, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d0
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: vmov lr, r12, d1
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d1
|
||||
; CHECK-LE-NEXT: mov.w lr, #0
|
||||
; CHECK-LE-NEXT: vmov r3, r12, d0
|
||||
; CHECK-LE-NEXT: rsbs r1, r1, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, r2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r2
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r3, #31
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: vstrne d0, [r0]
|
||||
; CHECK-LE-NEXT: lsls r1, r1, #30
|
||||
|
|
@ -972,24 +969,21 @@ define arm_aapcs_vfpcc void @masked_v2i64(<2 x i64> *%dest, <2 x i64> %a) {
|
|||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r3, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d3
|
||||
; CHECK-BE-NEXT: vmov r12, lr, d2
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d2
|
||||
; CHECK-BE-NEXT: vmov r12, r3, d3
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r1
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r1, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r1
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r3, #30
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: it mi
|
||||
; CHECK-BE-NEXT: vstrmi d0, [r0]
|
||||
; CHECK-BE-NEXT: lsls r1, r1, #31
|
||||
|
|
@ -1010,24 +1004,21 @@ define arm_aapcs_vfpcc void @masked_v2f64(<2 x double> *%dest, <2 x double> %a,
|
|||
; CHECK-LE-NEXT: push {r7, lr}
|
||||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d2
|
||||
; CHECK-LE-NEXT: movs r3, #0
|
||||
; CHECK-LE-NEXT: vmov lr, r12, d3
|
||||
; CHECK-LE-NEXT: vmov r1, r2, d3
|
||||
; CHECK-LE-NEXT: mov.w lr, #0
|
||||
; CHECK-LE-NEXT: vmov r3, r12, d2
|
||||
; CHECK-LE-NEXT: rsbs r1, r1, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, r3, r2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r1, #1
|
||||
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-LE-NEXT: it lt
|
||||
; CHECK-LE-NEXT: movlt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r2
|
||||
; CHECK-LE-NEXT: cset r2, lt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: mvnne r3, #1
|
||||
; CHECK-LE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r3, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r3, #31
|
||||
; CHECK-LE-NEXT: mvnne r2, #1
|
||||
; CHECK-LE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-LE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-LE-NEXT: cset r1, lt
|
||||
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-LE-NEXT: and r1, r2, #3
|
||||
; CHECK-LE-NEXT: lsls r2, r2, #31
|
||||
; CHECK-LE-NEXT: it ne
|
||||
; CHECK-LE-NEXT: vstrne d0, [r0]
|
||||
; CHECK-LE-NEXT: lsls r1, r1, #30
|
||||
|
|
@ -1043,24 +1034,21 @@ define arm_aapcs_vfpcc void @masked_v2f64(<2 x double> *%dest, <2 x double> %a,
|
|||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q2, q1
|
||||
; CHECK-BE-NEXT: movs r3, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d5
|
||||
; CHECK-BE-NEXT: vmov r12, lr, d4
|
||||
; CHECK-BE-NEXT: mov.w lr, #0
|
||||
; CHECK-BE-NEXT: vmov r1, r2, d4
|
||||
; CHECK-BE-NEXT: vmov r12, r3, d5
|
||||
; CHECK-BE-NEXT: rsbs r2, r2, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, r3, r1
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r1, #1
|
||||
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
|
||||
; CHECK-BE-NEXT: it lt
|
||||
; CHECK-BE-NEXT: movlt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r1
|
||||
; CHECK-BE-NEXT: cset r2, lt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: it ne
|
||||
; CHECK-BE-NEXT: mvnne r3, #1
|
||||
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r3, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r3, #30
|
||||
; CHECK-BE-NEXT: mvnne r2, #1
|
||||
; CHECK-BE-NEXT: rsbs r1, r3, #0
|
||||
; CHECK-BE-NEXT: sbcs.w r1, lr, r12
|
||||
; CHECK-BE-NEXT: cset r1, lt
|
||||
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
|
||||
; CHECK-BE-NEXT: and r1, r2, #3
|
||||
; CHECK-BE-NEXT: lsls r2, r2, #30
|
||||
; CHECK-BE-NEXT: it mi
|
||||
; CHECK-BE-NEXT: vstrmi d0, [r0]
|
||||
; CHECK-BE-NEXT: lsls r1, r1, #31
|
||||
|
|
@ -1224,42 +1212,34 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
|||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vcmp.f32 s0, #0
|
||||
; CHECK-LE-NEXT: movs r1, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-LE-NEXT: cset r1, gt
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #0, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #1, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #2, #1
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-LE-NEXT: lsls r2, r1, #31
|
||||
; CHECK-LE-NEXT: bne .LBB25_5
|
||||
; CHECK-LE-NEXT: @ %bb.1: @ %else
|
||||
|
|
@ -1298,43 +1278,35 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
|||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r1, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-BE-NEXT: movs r2, #0
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
|
||||
; CHECK-BE-NEXT: cset r1, gt
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #0, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #1, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #2, #1
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-BE-NEXT: lsls r2, r1, #28
|
||||
; CHECK-BE-NEXT: bmi .LBB25_5
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %else
|
||||
|
|
@ -1380,42 +1352,34 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
|||
; CHECK-LE-NEXT: .pad #4
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vcmp.f32 s0, #0
|
||||
; CHECK-LE-NEXT: movs r1, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-LE-NEXT: cset r1, gt
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #0, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #1, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #2, #1
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-LE-NEXT: lsls r2, r1, #31
|
||||
; CHECK-LE-NEXT: bne .LBB26_5
|
||||
; CHECK-LE-NEXT: @ %bb.1: @ %else
|
||||
|
|
@ -1454,43 +1418,35 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
|||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r1, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-BE-NEXT: movs r2, #0
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
|
||||
; CHECK-BE-NEXT: cset r1, gt
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #0, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #1, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #2, #1
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-BE-NEXT: lsls r2, r1, #28
|
||||
; CHECK-BE-NEXT: bmi .LBB26_5
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %else
|
||||
|
|
@ -1536,42 +1492,34 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
|||
; CHECK-LE-NEXT: .pad #20
|
||||
; CHECK-LE-NEXT: sub sp, #20
|
||||
; CHECK-LE-NEXT: vcmp.f32 s0, #0
|
||||
; CHECK-LE-NEXT: movs r1, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-LE-NEXT: mov.w r3, #0
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r3, #1
|
||||
; CHECK-LE-NEXT: cmp r3, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: csetm r3, ne
|
||||
; CHECK-LE-NEXT: movs r2, #0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r2, #1
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-LE-NEXT: cset r1, gt
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #0, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s2, #0
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #1, #1
|
||||
; CHECK-LE-NEXT: vcmp.f32 s3, #0
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #2, #1
|
||||
; CHECK-LE-NEXT: cset r2, gt
|
||||
; CHECK-LE-NEXT: cmp r2, #0
|
||||
; CHECK-LE-NEXT: csetm r2, ne
|
||||
; CHECK-LE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-LE-NEXT: lsls r2, r1, #31
|
||||
; CHECK-LE-NEXT: bne .LBB27_5
|
||||
; CHECK-LE-NEXT: @ %bb.1: @ %else
|
||||
|
|
@ -1618,43 +1566,35 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
|||
; CHECK-BE-NEXT: .pad #20
|
||||
; CHECK-BE-NEXT: sub sp, #20
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r1, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-BE-NEXT: movs r2, #0
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r3, #1
|
||||
; CHECK-BE-NEXT: cmp r3, #0
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: csetm r3, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r2, #1
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: vcmp.f32 s6, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
|
||||
; CHECK-BE-NEXT: cset r1, gt
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #0, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #1, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #2, #1
|
||||
; CHECK-BE-NEXT: cset r2, gt
|
||||
; CHECK-BE-NEXT: cmp r2, #0
|
||||
; CHECK-BE-NEXT: csetm r2, ne
|
||||
; CHECK-BE-NEXT: bfi r1, r2, #3, #1
|
||||
; CHECK-BE-NEXT: lsls r2, r1, #28
|
||||
; CHECK-BE-NEXT: bmi .LBB27_5
|
||||
; CHECK-BE-NEXT: @ %bb.1: @ %else
|
||||
|
|
|
|||
|
|
@ -38,32 +38,28 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @smin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
|
||||
; CHECK-LABEL: smin_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vmov r0, r1, d3
|
||||
; CHECK-NEXT: movs r6, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d1
|
||||
; CHECK-NEXT: vmov r12, lr, d2
|
||||
; CHECK-NEXT: vmov r4, r5, d0
|
||||
; CHECK-NEXT: subs r0, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r1, r4, r12
|
||||
; CHECK-NEXT: sbcs.w r1, r5, lr
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r6, #1
|
||||
; CHECK-NEXT: cmp r6, #0
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%0 = icmp slt <2 x i64> %s1, %s2
|
||||
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
|
||||
|
|
@ -106,32 +102,28 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @umin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
|
||||
; CHECK-LABEL: umin_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vmov r0, r1, d3
|
||||
; CHECK-NEXT: movs r6, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d1
|
||||
; CHECK-NEXT: vmov r12, lr, d2
|
||||
; CHECK-NEXT: vmov r4, r5, d0
|
||||
; CHECK-NEXT: subs r0, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r1, r4, r12
|
||||
; CHECK-NEXT: sbcs.w r1, r5, lr
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r6, #1
|
||||
; CHECK-NEXT: cmp r6, #0
|
||||
; CHECK-NEXT: cset r1, lo
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%0 = icmp ult <2 x i64> %s1, %s2
|
||||
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
|
||||
|
|
@ -175,32 +167,28 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @smax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
|
||||
; CHECK-LABEL: smax_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r6, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d3
|
||||
; CHECK-NEXT: vmov r12, lr, d0
|
||||
; CHECK-NEXT: vmov r4, r5, d2
|
||||
; CHECK-NEXT: subs r0, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r1, r4, r12
|
||||
; CHECK-NEXT: sbcs.w r1, r5, lr
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r6, #1
|
||||
; CHECK-NEXT: cmp r6, #0
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%0 = icmp sgt <2 x i64> %s1, %s2
|
||||
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
|
||||
|
|
@ -243,32 +231,28 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @umax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
|
||||
; CHECK-LABEL: umax_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r6, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d3
|
||||
; CHECK-NEXT: vmov r12, lr, d0
|
||||
; CHECK-NEXT: vmov r4, r5, d2
|
||||
; CHECK-NEXT: subs r0, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r1, r4, r12
|
||||
; CHECK-NEXT: sbcs.w r1, r5, lr
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r6, #1
|
||||
; CHECK-NEXT: cmp r6, #0
|
||||
; CHECK-NEXT: cset r1, lo
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
entry:
|
||||
%0 = icmp ugt <2 x i64> %s1, %s2
|
||||
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
|
||||
|
|
|
|||
|
|
@ -75,20 +75,17 @@ define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) {
|
|||
; CHECK-LABEL: sext_v2i1_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: vmov r2, r12, d0
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: sbcs.w r0, r12, r1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: rsbs r1, r2, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r3, r12
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r3
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
|
|
@ -216,22 +213,19 @@ define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) {
|
|||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: vmov lr, r12, d0
|
||||
; CHECK-NEXT: adr r2, .LCPI12_0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r2]
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r2, lr, d0
|
||||
; CHECK-NEXT: adr r3, .LCPI12_0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r3]
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: sbcs.w r0, r12, r1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r3, r12
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: rsbs r1, r2, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r12, lr
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vand q0, q1, q0
|
||||
|
|
@ -483,22 +477,19 @@ define arm_aapcs_vfpcc <2 x double> @uitofp_v2i1_v2f64(<2 x i64> %src) {
|
|||
; CHECK-NEXT: .vsave {d8, d9}
|
||||
; CHECK-NEXT: vpush {d8, d9}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: vmov lr, r12, d0
|
||||
; CHECK-NEXT: adr r2, .LCPI26_0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r2]
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r2, lr, d0
|
||||
; CHECK-NEXT: adr r3, .LCPI26_0
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r3]
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: sbcs.w r0, r12, r1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: rsbs.w r1, lr, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r3, r12
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: rsbs r1, r2, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r12, lr
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vand q4, q1, q0
|
||||
|
|
@ -534,18 +525,15 @@ define arm_aapcs_vfpcc <2 x double> @sitofp_v2i1_v2f64(<2 x i64> %src) {
|
|||
; CHECK-NEXT: .vsave {d8, d9}
|
||||
; CHECK-NEXT: vpush {d8, d9}
|
||||
; CHECK-NEXT: vmov r0, r1, d0
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: vmov r2, r12, d1
|
||||
; CHECK-NEXT: movs r4, #0
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d1
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: sbcs.w r0, r12, r1
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: rsbs r0, r2, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r12
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r12, r3
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: mov r1, r0
|
||||
; CHECK-NEXT: bl __aeabi_l2d
|
||||
|
|
|
|||
|
|
@ -46,21 +46,17 @@ define arm_aapcs_vfpcc void @ssatmul_s_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: smull r6, r5, r8, r5
|
||||
; CHECK-NEXT: rsbs.w r9, r4, #-2147483648
|
||||
; CHECK-NEXT: sbcs r3, r7
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: asrl r6, r5, #31
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r6, r4
|
||||
; CHECK-NEXT: csetm r9, ne
|
||||
; CHECK-NEXT: rsbs.w r3, r6, #-2147483648
|
||||
; CHECK-NEXT: mov.w r3, #-1
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r6, r4
|
||||
; CHECK-NEXT: sbcs r3, r5
|
||||
; CHECK-NEXT: vmov q4[3], q4[1], r5, r7
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: sbcs r3, r5
|
||||
; CHECK-NEXT: mvn r6, #-2147483648
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r3, r9
|
||||
|
|
@ -72,17 +68,13 @@ define arm_aapcs_vfpcc void @ssatmul_s_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs r3, r3, r6
|
||||
; CHECK-NEXT: sbcs r3, r4, #0
|
||||
; CHECK-NEXT: vmov r4, r5, d5
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov.32 q3[1], r3
|
||||
; CHECK-NEXT: subs r4, r4, r6
|
||||
; CHECK-NEXT: sbcs r4, r5, #0
|
||||
; CHECK-NEXT: mov.w r4, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csetm r4, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r3, r4
|
||||
|
|
@ -110,9 +102,7 @@ define arm_aapcs_vfpcc void @ssatmul_s_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: asrl r4, r3, #31
|
||||
; CHECK-NEXT: subs r5, r1, r4
|
||||
; CHECK-NEXT: sbcs.w r5, r0, r3
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r5, #1
|
||||
; CHECK-NEXT: cset r5, lt
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csel r4, r4, r1, ne
|
||||
; CHECK-NEXT: csel r3, r3, r0, ne
|
||||
|
|
@ -223,10 +213,10 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: beq.w .LBB1_8
|
||||
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
|
||||
; CHECK-NEXT: movs r7, #0
|
||||
; CHECK-NEXT: cmp r3, #3
|
||||
; CHECK-NEXT: bhi .LBB1_3
|
||||
; CHECK-NEXT: @ %bb.2:
|
||||
; CHECK-NEXT: movs r7, #0
|
||||
; CHECK-NEXT: mov r12, r0
|
||||
; CHECK-NEXT: mov r9, r1
|
||||
; CHECK-NEXT: mov r11, r2
|
||||
|
|
@ -263,20 +253,16 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: vmov r6, s12
|
||||
; CHECK-NEXT: rsbs.w r5, r4, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r5, r2, r7
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r5, #1
|
||||
; CHECK-NEXT: cset r5, lt
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: vmov r10, r5, d12
|
||||
; CHECK-NEXT: csetm r8, ne
|
||||
; CHECK-NEXT: asrl r10, r5, #31
|
||||
; CHECK-NEXT: csetm r8, ne
|
||||
; CHECK-NEXT: rsbs.w r3, r10, #-2147483648
|
||||
; CHECK-NEXT: vmov q6[2], q6[0], r10, r4
|
||||
; CHECK-NEXT: sbcs.w r3, r2, r5
|
||||
; CHECK-NEXT: vmov q6[3], q6[1], r5, r7
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q4[2], q4[0], r3, r8
|
||||
|
|
@ -289,18 +275,14 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs.w r3, r3, r8
|
||||
; CHECK-NEXT: sbcs r3, r4, #0
|
||||
; CHECK-NEXT: vmov r4, r5, d9
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov.32 q5[1], r3
|
||||
; CHECK-NEXT: subs.w r4, r4, r8
|
||||
; CHECK-NEXT: sbcs r4, r5, #0
|
||||
; CHECK-NEXT: vmov r5, s8
|
||||
; CHECK-NEXT: mov.w r4, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csetm r4, ne
|
||||
; CHECK-NEXT: vmov q5[2], q5[0], r3, r4
|
||||
|
|
@ -318,16 +300,12 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: vmov q5[2], q5[0], r6, r4
|
||||
; CHECK-NEXT: sbcs.w r3, r2, r7
|
||||
; CHECK-NEXT: vmov q5[3], q5[1], r5, r7
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: rsbs.w r1, r6, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r1, r2, r5
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r1, r3
|
||||
|
|
@ -339,18 +317,14 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: vmov r4, r3, d4
|
||||
; CHECK-NEXT: subs.w r4, r4, r8
|
||||
; CHECK-NEXT: sbcs r3, r3, #0
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: vmov r3, r4, d5
|
||||
; CHECK-NEXT: csetm r5, ne
|
||||
; CHECK-NEXT: vmov.32 q3[1], r5
|
||||
; CHECK-NEXT: subs.w r3, r3, r8
|
||||
; CHECK-NEXT: sbcs r3, r4, #0
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r5, r3
|
||||
|
|
@ -379,9 +353,7 @@ define arm_aapcs_vfpcc void @ssatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: asrl r4, r1, #31
|
||||
; CHECK-NEXT: subs r5, r3, r4
|
||||
; CHECK-NEXT: sbcs.w r5, r0, r1
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r5, #1
|
||||
; CHECK-NEXT: cset r5, lt
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csel r4, r4, r3, ne
|
||||
; CHECK-NEXT: csel r1, r1, r0, ne
|
||||
|
|
@ -532,21 +504,17 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: asrl r6, r5, #31
|
||||
; CHECK-NEXT: rsbs.w r7, r6, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r7, r12, r5
|
||||
; CHECK-NEXT: mov.w r7, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r7, #1
|
||||
; CHECK-NEXT: cset r7, lt
|
||||
; CHECK-NEXT: cmp r7, #0
|
||||
; CHECK-NEXT: vmov r4, r7, d0
|
||||
; CHECK-NEXT: csetm r10, ne
|
||||
; CHECK-NEXT: asrl r4, r7, #31
|
||||
; CHECK-NEXT: csetm r10, ne
|
||||
; CHECK-NEXT: rsbs.w r3, r4, #-2147483648
|
||||
; CHECK-NEXT: vmov q7[2], q7[0], r4, r6
|
||||
; CHECK-NEXT: sbcs.w r3, r12, r7
|
||||
; CHECK-NEXT: vmov q7[3], q7[1], r7, r5
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: vmov r7, s20
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r10
|
||||
|
|
@ -558,17 +526,13 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs.w r3, r3, r8
|
||||
; CHECK-NEXT: sbcs r3, r4, #0
|
||||
; CHECK-NEXT: vmov r4, r5, d13
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: subs.w r4, r4, r8
|
||||
; CHECK-NEXT: sbcs r4, r5, #0
|
||||
; CHECK-NEXT: mov.w r4, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csetm r4, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r4
|
||||
|
|
@ -584,9 +548,7 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: asrl r6, r5, #31
|
||||
; CHECK-NEXT: rsbs.w r3, r6, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r3, r12, r5
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r10, ne
|
||||
; CHECK-NEXT: smull r4, r7, r7, r4
|
||||
|
|
@ -595,9 +557,7 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: vmov q5[2], q5[0], r4, r6
|
||||
; CHECK-NEXT: sbcs.w r3, r12, r7
|
||||
; CHECK-NEXT: vmov q5[3], q5[1], r7, r5
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r10
|
||||
|
|
@ -609,17 +569,13 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs.w r3, r3, r8
|
||||
; CHECK-NEXT: sbcs r3, r4, #0
|
||||
; CHECK-NEXT: vmov r4, r5, d9
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: subs.w r4, r4, r8
|
||||
; CHECK-NEXT: sbcs r4, r5, #0
|
||||
; CHECK-NEXT: mov.w r4, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csetm r4, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r3, r4
|
||||
|
|
@ -733,9 +689,7 @@ define arm_aapcs_vfpcc void @usatmul_2_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs.w r6, r4, #-1
|
||||
; CHECK-NEXT: umull r6, r7, r10, r7
|
||||
; CHECK-NEXT: sbcs r5, r5, #0
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r5, #1
|
||||
; CHECK-NEXT: cset r5, lo
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: lsrl r6, r7, #31
|
||||
; CHECK-NEXT: csetm r9, ne
|
||||
|
|
@ -743,9 +697,7 @@ define arm_aapcs_vfpcc void @usatmul_2_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: vmov.32 q0[1], r9
|
||||
; CHECK-NEXT: sbcs r5, r7, #0
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r4, r6
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r5, #1
|
||||
; CHECK-NEXT: cset r5, lo
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csetm r5, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r9, r5
|
||||
|
|
@ -860,10 +812,10 @@ define arm_aapcs_vfpcc void @usatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: beq.w .LBB4_8
|
||||
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
|
||||
; CHECK-NEXT: mov.w r8, #0
|
||||
; CHECK-NEXT: cmp r3, #3
|
||||
; CHECK-NEXT: bhi .LBB4_3
|
||||
; CHECK-NEXT: @ %bb.2:
|
||||
; CHECK-NEXT: mov.w r8, #0
|
||||
; CHECK-NEXT: mov r12, r0
|
||||
; CHECK-NEXT: mov r9, r1
|
||||
; CHECK-NEXT: mov r10, r2
|
||||
|
|
@ -892,19 +844,15 @@ define arm_aapcs_vfpcc void @usatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs.w r6, r4, #-1
|
||||
; CHECK-NEXT: sbcs r5, r5, #0
|
||||
; CHECK-NEXT: vmov r6, r7, d9
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: cset r5, lo
|
||||
; CHECK-NEXT: lsrl r6, r7, #31
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r5, #1
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r4, r6
|
||||
; CHECK-NEXT: csetm r11, ne
|
||||
; CHECK-NEXT: subs.w r5, r6, #-1
|
||||
; CHECK-NEXT: sbcs r5, r7, #0
|
||||
; CHECK-NEXT: vmov.32 q1[1], r11
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r4, r6
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r5, #1
|
||||
; CHECK-NEXT: cset r5, lo
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csetm r5, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r11, r5
|
||||
|
|
@ -916,19 +864,15 @@ define arm_aapcs_vfpcc void @usatmul_4_q31(i32* nocapture readonly %pSrcA, i32*
|
|||
; CHECK-NEXT: subs.w r6, r4, #-1
|
||||
; CHECK-NEXT: sbcs r5, r5, #0
|
||||
; CHECK-NEXT: vmov r6, r7, d7
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: cset r5, lo
|
||||
; CHECK-NEXT: lsrl r6, r7, #31
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r5, #1
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r4, r6
|
||||
; CHECK-NEXT: csetm r11, ne
|
||||
; CHECK-NEXT: subs.w r5, r6, #-1
|
||||
; CHECK-NEXT: sbcs r5, r7, #0
|
||||
; CHECK-NEXT: vmov.32 q0[1], r11
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r4, r6
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r5, #1
|
||||
; CHECK-NEXT: cset r5, lo
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csetm r5, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r11, r5
|
||||
|
|
|
|||
|
|
@ -394,24 +394,18 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vcmp_slt_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) {
|
||||
; CHECK-LABEL: vcmp_slt_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: vmov r0, r12, d3
|
||||
; CHECK-NEXT: movs r1, #0
|
||||
; CHECK-NEXT: vmov r0, r1, d3
|
||||
; CHECK-NEXT: vmov r2, r3, d1
|
||||
; CHECK-NEXT: subs r0, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r12
|
||||
; CHECK-NEXT: vmov lr, r12, d2
|
||||
; CHECK-NEXT: sbcs.w r0, r3, r1
|
||||
; CHECK-NEXT: vmov r1, r12, d2
|
||||
; CHECK-NEXT: vmov r3, r2, d0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r3, r3, lr
|
||||
; CHECK-NEXT: sbcs.w r2, r2, r12
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: subs r1, r3, r1
|
||||
; CHECK-NEXT: sbcs.w r1, r2, r12
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
|
|
@ -419,7 +413,7 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_slt_v2i64(<2 x i64> %src, <2 x i64> %srcb
|
|||
; CHECK-NEXT: vbic q1, q3, q0
|
||||
; CHECK-NEXT: vand q0, q2, q0
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%c = icmp slt <2 x i64> %src, %srcb
|
||||
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
|
||||
|
|
@ -456,12 +450,11 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
|
||||
; CHECK-LABEL: vcmp_multi_v2i32:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9}
|
||||
; CHECK-NEXT: vpush {d8, d9}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, r2, d0
|
||||
; CHECK-NEXT: csetm r0, eq
|
||||
|
|
@ -472,22 +465,19 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
|||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
; CHECK-NEXT: vbic q0, q2, q0
|
||||
; CHECK-NEXT: vmov r0, s2
|
||||
; CHECK-NEXT: subs r1, r0, r2
|
||||
; CHECK-NEXT: asr.w r12, r0, #31
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: subs r3, r0, r2
|
||||
; CHECK-NEXT: asr.w r1, r0, #31
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: sbcs.w r1, r1, r2, asr #31
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: csetm lr, ne
|
||||
; CHECK-NEXT: subs r1, r2, r3
|
||||
; CHECK-NEXT: asr.w r12, r2, #31
|
||||
; CHECK-NEXT: subs r4, r2, r1
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r1, asr #31
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
|
||||
|
|
@ -511,7 +501,7 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
|||
; CHECK-NEXT: vand q1, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q1, q0
|
||||
; CHECK-NEXT: vpop {d8, d9}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
%a4 = icmp eq <2 x i64> %a, zeroinitializer
|
||||
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
|
||||
%a6 = icmp ne <2 x i32> %b, zeroinitializer
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -487,12 +487,11 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
|
||||
; CHECK-LABEL: vcmp_multi_v2i32:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9}
|
||||
; CHECK-NEXT: vpush {d8, d9}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, r2, d0
|
||||
; CHECK-NEXT: csetm r0, eq
|
||||
|
|
@ -503,22 +502,19 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
|||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
; CHECK-NEXT: vbic q0, q2, q0
|
||||
; CHECK-NEXT: vmov r0, s2
|
||||
; CHECK-NEXT: subs r1, r0, r2
|
||||
; CHECK-NEXT: asr.w r12, r0, #31
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: subs r3, r0, r2
|
||||
; CHECK-NEXT: asr.w r1, r0, #31
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: sbcs.w r1, r1, r2, asr #31
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: csetm lr, ne
|
||||
; CHECK-NEXT: subs r1, r2, r3
|
||||
; CHECK-NEXT: asr.w r12, r2, #31
|
||||
; CHECK-NEXT: subs r4, r2, r1
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r1, asr #31
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
|
||||
|
|
@ -542,7 +538,7 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
|
|||
; CHECK-NEXT: vand q1, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q1, q0
|
||||
; CHECK-NEXT: vpop {d8, d9}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
%a4 = icmp eq <2 x i64> %a, zeroinitializer
|
||||
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
|
||||
%a6 = icmp ne <2 x i32> %b, zeroinitializer
|
||||
|
|
@ -1042,12 +1038,11 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
|
||||
; CHECK-LABEL: vcmp_r_multi_v2i32:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9}
|
||||
; CHECK-NEXT: vpush {d8, d9}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: vmov r1, r2, d0
|
||||
; CHECK-NEXT: csetm r0, eq
|
||||
|
|
@ -1058,22 +1053,19 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
|
|||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
; CHECK-NEXT: vbic q0, q2, q0
|
||||
; CHECK-NEXT: vmov r0, s2
|
||||
; CHECK-NEXT: subs r1, r0, r2
|
||||
; CHECK-NEXT: asr.w r12, r0, #31
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: subs r3, r0, r2
|
||||
; CHECK-NEXT: asr.w r1, r0, #31
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: sbcs.w r1, r1, r2, asr #31
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: csetm lr, ne
|
||||
; CHECK-NEXT: subs r1, r2, r3
|
||||
; CHECK-NEXT: asr.w r12, r2, #31
|
||||
; CHECK-NEXT: subs r4, r2, r1
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r1, asr #31
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r3, asr #31
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
|
||||
|
|
@ -1097,7 +1089,7 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b,
|
|||
; CHECK-NEXT: vand q1, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q1, q0
|
||||
; CHECK-NEXT: vpop {d8, d9}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
%a4 = icmp eq <2 x i64> %a, zeroinitializer
|
||||
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
|
||||
%a6 = icmp ne <2 x i32> %b, zeroinitializer
|
||||
|
|
|
|||
|
|
@ -178,16 +178,13 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_ult_v2i64(i64 %n, <2 x i64> %a, <2 x i64>
|
|||
; CHECK-NEXT: rsbs.w r3, r0, #1
|
||||
; CHECK-NEXT: mov.w r2, #0
|
||||
; CHECK-NEXT: sbcs.w r3, r2, r1
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r3, #1
|
||||
; CHECK-NEXT: cset r3, lo
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csetm r3, ne
|
||||
; CHECK-NEXT: rsbs r0, r0, #0
|
||||
; CHECK-NEXT: sbcs.w r0, r2, r1
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r0, r3
|
||||
|
|
@ -207,15 +204,13 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_uge_v2i64(i64 %n, <2 x i64> %a, <2 x i64>
|
|||
; CHECK-LABEL: vcmp_uge_v2i64:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: subs r0, #1
|
||||
; CHECK-NEXT: mov.w r2, #0
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: it hs
|
||||
; CHECK-NEXT: movhs r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: vldr s8, .LCPI11_0
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: cset r0, hs
|
||||
; CHECK-NEXT: vmov.f32 s9, s8
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov s10, r0
|
||||
; CHECK-NEXT: vmov.f32 s9, s8
|
||||
; CHECK-NEXT: vmov.f32 s11, s10
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
|
|
|
|||
|
|
@ -493,8 +493,8 @@ define arm_aapcs_vfpcc signext i16 @trunc_and_zext(<8 x i16> %vec, i32 %max) #1
|
|||
define arm_aapcs_vfpcc i64 @uminv2i64(<2 x i64> %vec, i64 %min) {
|
||||
; CHECK-LABEL: uminv2i64:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: vmov r2, r12, d1
|
||||
; CHECK-NEXT: vmov r3, lr, d0
|
||||
; CHECK-NEXT: cmp r3, r2
|
||||
|
|
@ -502,16 +502,14 @@ define arm_aapcs_vfpcc i64 @uminv2i64(<2 x i64> %vec, i64 %min) {
|
|||
; CHECK-NEXT: cmp lr, r12
|
||||
; CHECK-NEXT: csel r2, r3, r2, lo
|
||||
; CHECK-NEXT: csel r3, lr, r12, lo
|
||||
; CHECK-NEXT: csel r5, r4, r2, eq
|
||||
; CHECK-NEXT: movs r4, #0
|
||||
; CHECK-NEXT: subs r2, r5, r0
|
||||
; CHECK-NEXT: sbcs.w r2, r3, r1
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r4, #1
|
||||
; CHECK-NEXT: csel r2, r4, r2, eq
|
||||
; CHECK-NEXT: subs r4, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r4, r3, r1
|
||||
; CHECK-NEXT: cset r4, lo
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csel r0, r5, r0, ne
|
||||
; CHECK-NEXT: csel r0, r2, r0, ne
|
||||
; CHECK-NEXT: csel r1, r3, r1, ne
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
%x = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec)
|
||||
%cmp = icmp ult i64 %x, %min
|
||||
%1 = select i1 %cmp, i64 %x, i64 %min
|
||||
|
|
@ -521,8 +519,8 @@ define arm_aapcs_vfpcc i64 @uminv2i64(<2 x i64> %vec, i64 %min) {
|
|||
define arm_aapcs_vfpcc i64 @sminv2i64(<2 x i64> %vec, i64 %min) {
|
||||
; CHECK-LABEL: sminv2i64:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: vmov r2, r12, d1
|
||||
; CHECK-NEXT: vmov r3, lr, d0
|
||||
; CHECK-NEXT: cmp r3, r2
|
||||
|
|
@ -530,16 +528,14 @@ define arm_aapcs_vfpcc i64 @sminv2i64(<2 x i64> %vec, i64 %min) {
|
|||
; CHECK-NEXT: cmp lr, r12
|
||||
; CHECK-NEXT: csel r2, r3, r2, lt
|
||||
; CHECK-NEXT: csel r3, lr, r12, lt
|
||||
; CHECK-NEXT: csel r5, r4, r2, eq
|
||||
; CHECK-NEXT: movs r4, #0
|
||||
; CHECK-NEXT: subs r2, r5, r0
|
||||
; CHECK-NEXT: sbcs.w r2, r3, r1
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: csel r2, r4, r2, eq
|
||||
; CHECK-NEXT: subs r4, r2, r0
|
||||
; CHECK-NEXT: sbcs.w r4, r3, r1
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csel r0, r5, r0, ne
|
||||
; CHECK-NEXT: csel r0, r2, r0, ne
|
||||
; CHECK-NEXT: csel r1, r3, r1, ne
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
%x = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec)
|
||||
%cmp = icmp slt i64 %x, %min
|
||||
%1 = select i1 %cmp, i64 %x, i64 %min
|
||||
|
|
@ -549,8 +545,8 @@ define arm_aapcs_vfpcc i64 @sminv2i64(<2 x i64> %vec, i64 %min) {
|
|||
define arm_aapcs_vfpcc i64 @umaxv2i64(<2 x i64> %vec, i64 %max) {
|
||||
; CHECK-LABEL: umaxv2i64:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: vmov r2, r12, d1
|
||||
; CHECK-NEXT: vmov r3, lr, d0
|
||||
; CHECK-NEXT: cmp r3, r2
|
||||
|
|
@ -558,16 +554,14 @@ define arm_aapcs_vfpcc i64 @umaxv2i64(<2 x i64> %vec, i64 %max) {
|
|||
; CHECK-NEXT: cmp lr, r12
|
||||
; CHECK-NEXT: csel r2, r3, r2, hi
|
||||
; CHECK-NEXT: csel r3, lr, r12, hi
|
||||
; CHECK-NEXT: csel r5, r4, r2, eq
|
||||
; CHECK-NEXT: movs r4, #0
|
||||
; CHECK-NEXT: subs r2, r0, r5
|
||||
; CHECK-NEXT: sbcs.w r2, r1, r3
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r4, #1
|
||||
; CHECK-NEXT: csel r2, r4, r2, eq
|
||||
; CHECK-NEXT: subs r4, r0, r2
|
||||
; CHECK-NEXT: sbcs.w r4, r1, r3
|
||||
; CHECK-NEXT: cset r4, lo
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csel r0, r5, r0, ne
|
||||
; CHECK-NEXT: csel r0, r2, r0, ne
|
||||
; CHECK-NEXT: csel r1, r3, r1, ne
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
%x = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec)
|
||||
%cmp = icmp ugt i64 %x, %max
|
||||
%1 = select i1 %cmp, i64 %x, i64 %max
|
||||
|
|
@ -577,8 +571,8 @@ define arm_aapcs_vfpcc i64 @umaxv2i64(<2 x i64> %vec, i64 %max) {
|
|||
define arm_aapcs_vfpcc i64 @smaxv2i64(<2 x i64> %vec, i64 %max) {
|
||||
; CHECK-LABEL: smaxv2i64:
|
||||
; CHECK: @ %bb.0:
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: vmov r2, r12, d1
|
||||
; CHECK-NEXT: vmov r3, lr, d0
|
||||
; CHECK-NEXT: cmp r3, r2
|
||||
|
|
@ -586,16 +580,14 @@ define arm_aapcs_vfpcc i64 @smaxv2i64(<2 x i64> %vec, i64 %max) {
|
|||
; CHECK-NEXT: cmp lr, r12
|
||||
; CHECK-NEXT: csel r2, r3, r2, gt
|
||||
; CHECK-NEXT: csel r3, lr, r12, gt
|
||||
; CHECK-NEXT: csel r5, r4, r2, eq
|
||||
; CHECK-NEXT: movs r4, #0
|
||||
; CHECK-NEXT: subs r2, r0, r5
|
||||
; CHECK-NEXT: sbcs.w r2, r1, r3
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: csel r2, r4, r2, eq
|
||||
; CHECK-NEXT: subs r4, r0, r2
|
||||
; CHECK-NEXT: sbcs.w r4, r1, r3
|
||||
; CHECK-NEXT: cset r4, lt
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csel r0, r5, r0, ne
|
||||
; CHECK-NEXT: csel r0, r2, r0, ne
|
||||
; CHECK-NEXT: csel r1, r3, r1, ne
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
%x = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec)
|
||||
%cmp = icmp sgt i64 %x, %max
|
||||
%1 = select i1 %cmp, i64 %x, i64 %max
|
||||
|
|
|
|||
|
|
@ -513,9 +513,7 @@ define <2 x i64> @large_i128(<2 x double> %x) {
|
|||
; CHECK-NEXT: mov.w r9, #1
|
||||
; CHECK-NEXT: sbcs r7, r3, #0
|
||||
; CHECK-NEXT: mov.w r4, #0
|
||||
; CHECK-NEXT: mov.w r7, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r7, #1
|
||||
; CHECK-NEXT: cset r7, lt
|
||||
; CHECK-NEXT: cmp r7, #0
|
||||
; CHECK-NEXT: csel r0, r0, r7, ne
|
||||
; CHECK-NEXT: csel r3, r3, r7, ne
|
||||
|
|
@ -525,9 +523,7 @@ define <2 x i64> @large_i128(<2 x double> %x) {
|
|||
; CHECK-NEXT: sbcs.w r7, r4, r1
|
||||
; CHECK-NEXT: sbcs.w r2, r4, r2
|
||||
; CHECK-NEXT: sbcs.w r2, r4, r3
|
||||
; CHECK-NEXT: mov.w r2, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r2, #1
|
||||
; CHECK-NEXT: cset r2, lt
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csel r6, r0, r2, ne
|
||||
; CHECK-NEXT: csel r7, r1, r2, ne
|
||||
|
|
@ -536,9 +532,7 @@ define <2 x i64> @large_i128(<2 x double> %x) {
|
|||
; CHECK-NEXT: bl __fixdfti
|
||||
; CHECK-NEXT: subs r5, r2, #1
|
||||
; CHECK-NEXT: sbcs r5, r3, #0
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r5, #1
|
||||
; CHECK-NEXT: cset r5, lt
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csel r0, r0, r5, ne
|
||||
; CHECK-NEXT: csel r3, r3, r5, ne
|
||||
|
|
@ -548,11 +542,10 @@ define <2 x i64> @large_i128(<2 x double> %x) {
|
|||
; CHECK-NEXT: sbcs.w r5, r4, r1
|
||||
; CHECK-NEXT: sbcs.w r2, r4, r2
|
||||
; CHECK-NEXT: sbcs.w r2, r4, r3
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r4, #1
|
||||
; CHECK-NEXT: cmp r4, #0
|
||||
; CHECK-NEXT: csel r2, r0, r4, ne
|
||||
; CHECK-NEXT: csel r3, r1, r4, ne
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: csel r2, r0, r3, ne
|
||||
; CHECK-NEXT: csel r3, r1, r3, ne
|
||||
; CHECK-NEXT: mov r0, r6
|
||||
; CHECK-NEXT: mov r1, r7
|
||||
; CHECK-NEXT: add sp, #4
|
||||
|
|
|
|||
|
|
@ -164,49 +164,41 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vqmovni64_smaxmin(<2 x i64> %s0) {
|
||||
; CHECK-LABEL: vqmovni64_smaxmin:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r1, r2, d1
|
||||
; CHECK-NEXT: mvn r12, #-2147483648
|
||||
; CHECK-NEXT: movs r0, #0
|
||||
; CHECK-NEXT: subs.w r1, r1, r12
|
||||
; CHECK-NEXT: sbcs r1, r2, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: mvn r2, #-2147483648
|
||||
; CHECK-NEXT: subs r0, r0, r2
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs r1, r1, r2
|
||||
; CHECK-NEXT: mov.w r2, #-1
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: subs.w r2, r2, r12
|
||||
; CHECK-NEXT: mov.w r12, #-1
|
||||
; CHECK-NEXT: sbcs r2, r3, #0
|
||||
; CHECK-NEXT: mov.w r2, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r2, r1
|
||||
; CHECK-NEXT: adr r1, .LCPI12_0
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r1]
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
; CHECK-NEXT: adr r0, .LCPI12_0
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: vbic q2, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q0, q2
|
||||
; CHECK-NEXT: vmov r1, r2, d1
|
||||
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r2
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: rsbs.w r2, r2, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r2, r12, r3
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r0, r2, r1
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r0, r1
|
||||
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r1, r2, r3
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
; CHECK-NEXT: adr r0, .LCPI12_1
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
|
|
@ -236,49 +228,41 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vqmovni64_sminmax(<2 x i64> %s0) {
|
||||
; CHECK-LABEL: vqmovni64_sminmax:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r1, r2, d1
|
||||
; CHECK-NEXT: mov.w r12, #-1
|
||||
; CHECK-NEXT: movs r0, #0
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: mov.w r2, #-1
|
||||
; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r0, r2, r1
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r1, r12, r2
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: sbcs.w r1, r2, r3
|
||||
; CHECK-NEXT: mvn r2, #-2147483648
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: rsbs.w r2, r2, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r2, r12, r3
|
||||
; CHECK-NEXT: mvn r12, #-2147483648
|
||||
; CHECK-NEXT: mov.w r2, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r2, r1
|
||||
; CHECK-NEXT: adr r1, .LCPI13_0
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r1]
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
; CHECK-NEXT: adr r0, .LCPI13_0
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: vbic q2, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q0, q2
|
||||
; CHECK-NEXT: vmov r1, r2, d1
|
||||
; CHECK-NEXT: subs.w r1, r1, r12
|
||||
; CHECK-NEXT: sbcs r1, r2, #0
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: subs.w r2, r2, r12
|
||||
; CHECK-NEXT: sbcs r2, r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: subs r0, r0, r2
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r0, r1
|
||||
; CHECK-NEXT: subs r1, r1, r2
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
; CHECK-NEXT: adr r0, .LCPI13_1
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
|
|
@ -309,21 +293,17 @@ define arm_aapcs_vfpcc <2 x i64> @vqmovni64_umaxmin(<2 x i64> %s0) {
|
|||
; CHECK-LABEL: vqmovni64_umaxmin:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r2, #0
|
||||
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-NEXT: subs.w r0, r0, #-1
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: vmov r1, r2, d0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r1, r1, #-1
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: sbcs r1, r2, #0
|
||||
; CHECK-NEXT: cset r1, lo
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
|
@ -341,21 +321,17 @@ define arm_aapcs_vfpcc <2 x i64> @vqmovni64_uminmax(<2 x i64> %s0) {
|
|||
; CHECK-LABEL: vqmovni64_uminmax:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: movs r2, #0
|
||||
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-NEXT: subs.w r0, r0, #-1
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: vmov r1, r2, d0
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r1, r1, #-1
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: sbcs r1, r2, #0
|
||||
; CHECK-NEXT: cset r1, lo
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
|
|
|||
|
|
@ -180,52 +180,42 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_smaxmin(<2 x i64> %so) {
|
||||
; CHECK-LABEL: vqshrni64_smaxmin:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: vmov r2, r3, d1
|
||||
; CHECK-NEXT: mvn lr, #-2147483648
|
||||
; CHECK-NEXT: vmov r0, r1, d0
|
||||
; CHECK-NEXT: asrl r2, r3, #3
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: mvn r12, #-2147483648
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: asrl r0, r1, #3
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
|
||||
; CHECK-NEXT: subs.w r2, r2, lr
|
||||
; CHECK-NEXT: sbcs r2, r3, #0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
|
||||
; CHECK-NEXT: mov.w r2, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r2, #1
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: subs.w r0, r0, lr
|
||||
; CHECK-NEXT: asrl r2, r3, #3
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
|
||||
; CHECK-NEXT: subs.w r0, r0, r12
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r0, r2
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r0, r2
|
||||
; CHECK-NEXT: subs.w r1, r2, r12
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: mov.w r2, #-1
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
; CHECK-NEXT: adr r0, .LCPI12_0
|
||||
; CHECK-NEXT: vldrw.u32 q2, [r0]
|
||||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: mov.w r2, #-1
|
||||
; CHECK-NEXT: vbic q1, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r0, r2, r1
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r1, r2, r3
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt.w r12, #1
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
|
@ -234,7 +224,7 @@ define arm_aapcs_vfpcc <2 x i64> @vqshrni64_smaxmin(<2 x i64> %so) {
|
|||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: vbic q2, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q0, q2
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
; CHECK-NEXT: bx lr
|
||||
; CHECK-NEXT: .p2align 4
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI12_0:
|
||||
|
|
@ -259,35 +249,30 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) {
|
||||
; CHECK-LABEL: vqshrni64_sminmax:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r7, lr}
|
||||
; CHECK-NEXT: vmov r2, r1, d1
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: mov.w r12, #-1
|
||||
; CHECK-NEXT: asrl r2, r1, #3
|
||||
; CHECK-NEXT: mov.w lr, #0
|
||||
; CHECK-NEXT: rsbs.w r3, r2, #-2147483648
|
||||
; CHECK-NEXT: asrl r0, r1, #3
|
||||
; CHECK-NEXT: rsbs.w r3, r0, #-2147483648
|
||||
; CHECK-NEXT: sbcs.w r3, r12, r1
|
||||
; CHECK-NEXT: mov.w r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r3, #1
|
||||
; CHECK-NEXT: cset r3, lt
|
||||
; CHECK-NEXT: cmp r3, #0
|
||||
; CHECK-NEXT: vmov r4, r3, d0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: asrl r4, r3, #3
|
||||
; CHECK-NEXT: rsbs.w r5, r4, #-2147483648
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r4, r2
|
||||
; CHECK-NEXT: sbcs.w r5, r12, r3
|
||||
; CHECK-NEXT: csetm lr, ne
|
||||
; CHECK-NEXT: rsbs.w r2, r4, #-2147483648
|
||||
; CHECK-NEXT: vmov q2[2], q2[0], r4, r0
|
||||
; CHECK-NEXT: sbcs.w r2, r12, r3
|
||||
; CHECK-NEXT: vmov q2[3], q2[1], r3, r1
|
||||
; CHECK-NEXT: mov.w r5, #0
|
||||
; CHECK-NEXT: cset r2, lt
|
||||
; CHECK-NEXT: cmp r2, #0
|
||||
; CHECK-NEXT: csetm r2, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r2, lr
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r2, lr
|
||||
; CHECK-NEXT: adr r2, .LCPI13_0
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r2]
|
||||
; CHECK-NEXT: mvn r2, #-2147483648
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r5, #1
|
||||
; CHECK-NEXT: cmp r5, #0
|
||||
; CHECK-NEXT: csetm r5, ne
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r5, r0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r5, r0
|
||||
; CHECK-NEXT: adr r0, .LCPI13_0
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r0]
|
||||
; CHECK-NEXT: vbic q1, q1, q0
|
||||
; CHECK-NEXT: vand q0, q2, q0
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
|
|
@ -295,16 +280,13 @@ define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) {
|
|||
; CHECK-NEXT: subs r0, r0, r2
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov r1, r3, d0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt r0, #1
|
||||
; CHECK-NEXT: cset r0, lt
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs r1, r1, r2
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: it lt
|
||||
; CHECK-NEXT: movlt.w lr, #1
|
||||
; CHECK-NEXT: cmp.w lr, #0
|
||||
; CHECK-NEXT: cset r1, lt
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
|
@ -313,7 +295,7 @@ define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) {
|
|||
; CHECK-NEXT: vand q0, q0, q1
|
||||
; CHECK-NEXT: vbic q2, q2, q1
|
||||
; CHECK-NEXT: vorr q0, q0, q2
|
||||
; CHECK-NEXT: pop {r4, r5, r7, pc}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: .p2align 4
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI13_0:
|
||||
|
|
@ -338,26 +320,22 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_umaxmin(<2 x i64> %so) {
|
||||
; CHECK-LABEL: vqshrni64_umaxmin:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r0, r3, d1
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r2, r1, d0
|
||||
; CHECK-NEXT: lsrl r0, r3, #3
|
||||
; CHECK-NEXT: lsrl r2, r1, #3
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: lsrl r0, r1, #3
|
||||
; CHECK-NEXT: lsrl r2, r3, #3
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
|
||||
; CHECK-NEXT: subs.w r0, r0, #-1
|
||||
; CHECK-NEXT: sbcs r0, r3, #0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r2, r2, #-1
|
||||
; CHECK-NEXT: sbcs r1, r1, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo.w r12, #1
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: subs.w r1, r2, #-1
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: cset r1, lo
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
|
@ -375,26 +353,22 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_uminmax(<2 x i64> %so) {
|
||||
; CHECK-LABEL: vqshrni64_uminmax:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r0, r3, d1
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r2, r1, d0
|
||||
; CHECK-NEXT: lsrl r0, r3, #3
|
||||
; CHECK-NEXT: lsrl r2, r1, #3
|
||||
; CHECK-NEXT: vmov r0, r1, d1
|
||||
; CHECK-NEXT: vmov.i64 q2, #0xffffffff
|
||||
; CHECK-NEXT: vmov r2, r3, d0
|
||||
; CHECK-NEXT: lsrl r0, r1, #3
|
||||
; CHECK-NEXT: lsrl r2, r3, #3
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
|
||||
; CHECK-NEXT: subs.w r0, r0, #-1
|
||||
; CHECK-NEXT: sbcs r0, r3, #0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: sbcs r0, r1, #0
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
|
||||
; CHECK-NEXT: cset r0, lo
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: subs.w r2, r2, #-1
|
||||
; CHECK-NEXT: sbcs r1, r1, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo.w r12, #1
|
||||
; CHECK-NEXT: cmp.w r12, #0
|
||||
; CHECK-NEXT: subs.w r1, r2, #-1
|
||||
; CHECK-NEXT: sbcs r1, r3, #0
|
||||
; CHECK-NEXT: cset r1, lo
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
|
||||
|
|
|
|||
Loading…
Reference in New Issue