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[RISCV] Simplify some code in RISCVInstrInfo::verifyInstruction. NFCI 

This code was written as if it lived in the MC layer instead of
the CodeGen layer. We get the MCInstrDesc directly from MachineInstr.
And we can use RISCVSubtarget::is64Bit instead of going to the
Triple.

Differential Revision: https://reviews.llvm.org/D133905
This commit is contained in:
Craig Topper 2022-09-14 15:53:18 -07:00
parent 8273ca1421
commit 5888c157a7
1 changed files with 4 additions and 8 deletions
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12
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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@ -1127,8 +1127,7 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
const MCInstrInfo *MCII = STI.getInstrInfo();
MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
MCInstrDesc const &Desc = MI.getDesc();
for (auto &OI : enumerate(Desc.operands())) {
unsigned OpType = OI.value().OperandType;
@ -1195,17 +1194,14 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
Ok = isShiftedInt<7, 5>(Imm);
break;
case RISCVOp::OPERAND_UIMMLOG2XLEN:
Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
: isUInt<5>(Imm);
Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm);
break;
case RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO:
Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<6>(Imm)
: isUInt<5>(Imm);
Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm);
Ok = Ok && Imm != 0;
break;
case RISCVOp::OPERAND_UIMM_SHFL:
Ok = STI.getTargetTriple().isArch64Bit() ? isUInt<5>(Imm)
: isUInt<4>(Imm);
Ok = STI.is64Bit() ? isUInt<5>(Imm) : isUInt<4>(Imm);
break;
case RISCVOp::OPERAND_RVKRNUM:
Ok = Imm >= 0 && Imm <= 10;