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[RISCV] Prevent crashes when bitcasting between fixed vectors and scalars. 

Not all scalar element types are allowed in vectors so we may not
be able to bitcast to a 1 element vector to use insert/extract.

This will become a bigger issue when the Zve extensions are commited.
For now, I'm using the ELEN limit to limit the element types.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D113219
This commit is contained in:
Craig Topper 2021-11-10 08:56:00 -08:00
parent 48bb5f4cbe
commit 57bc7b1089
2 changed files with 273 additions and 3 deletions
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10
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -2410,7 +2410,9 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// into a one-element vector of the result type, and perform a vector
// bitcast.
if (!Op0VT.isVector()) {
auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1);
EVT BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1);
if (!isTypeLegal(BVT))
return SDValue();
return DAG.getBitcast(VT, DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, BVT,
DAG.getUNDEF(BVT), Op0,
DAG.getConstant(0, DL, XLenVT)));
@ -2421,8 +2423,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// thus: bitcast the vector to a one-element vector type whose element type
// is the same as the result type, and extract the first element.
if (!VT.isVector() && Op0VT.isFixedLengthVector()) {
LLVMContext &Context = *DAG.getContext();
SDValue BVec = DAG.getBitcast(EVT::getVectorVT(Context, VT, 1), Op0);
EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1);
if (!isTypeLegal(BVT))
return SDValue();
SDValue BVec = DAG.getBitcast(BVT, Op0);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec,
DAG.getConstant(0, DL, XLenVT));
}

266
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
View File

@ -5,6 +5,14 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: -riscv-v-vector-bits-min=128 \
; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < %s \
; RUN: | FileCheck %s --check-prefixes=ELEN32,RV32ELEN32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: -riscv-v-vector-bits-min=128 \
; RUN: -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < %s \
; RUN: | FileCheck %s --check-prefixes=ELEN32,RV64ELEN32
define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
; CHECK-LABEL: bitcast_v4i8_v32i1:
@ -13,6 +21,13 @@ define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmxor.mm v0, v0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v4i8_v32i1:
; ELEN32: # %bb.0:
; ELEN32-NEXT: addi a0, zero, 32
; ELEN32-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; ELEN32-NEXT: vmxor.mm v0, v0, v8
; ELEN32-NEXT: ret
%c = bitcast <4 x i8> %a to <32 x i1>
%d = xor <32 x i1> %b, %c
ret <32 x i1> %d
@ -24,6 +39,12 @@ define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
; CHECK-NEXT: vsetivli zero, 0, e8, mf8, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i8_i8:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e8, mf4, ta, mu
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i8> %a to i8
ret i8 %b
}
@ -34,6 +55,12 @@ define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v2i8_i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e16, mf2, ta, mu
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <2 x i8> %a to i16
ret i16 %b
}
@ -44,6 +71,12 @@ define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i16_i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e16, mf2, ta, mu
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i16> %a to i16
ret i16 %b
}
@ -54,6 +87,12 @@ define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v4i8_i32:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <4 x i8> %a to i32
ret i32 %b
}
@ -64,6 +103,12 @@ define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v2i16_i32:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <2 x i16> %a to i32
ret i32 %b
}
@ -74,6 +119,12 @@ define i32 @bitcast_v1i32_i32(<1 x i32> %a) {
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i32_i32:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; ELEN32-NEXT: vmv.x.s a0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i32> %a to i32
ret i32 %b
}
@ -93,6 +144,25 @@ define i64 @bitcast_v8i8_i64(<8 x i8> %a) {
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_v8i8_i64:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32ELEN32-NEXT: vslidedown.vi v9, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_v8i8_i64:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vse8.v v8, (a0)
; RV64ELEN32-NEXT: ld a0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret
%b = bitcast <8 x i8> %a to i64
ret i64 %b
}
@ -112,6 +182,25 @@ define i64 @bitcast_v4i16_i64(<4 x i16> %a) {
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_v4i16_i64:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32ELEN32-NEXT: vslidedown.vi v9, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_v4i16_i64:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vse16.v v8, (a0)
; RV64ELEN32-NEXT: ld a0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret
%b = bitcast <4 x i16> %a to i64
ret i64 %b
}
@ -131,6 +220,25 @@ define i64 @bitcast_v2i32_i64(<2 x i32> %a) {
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_v2i32_i64:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32ELEN32-NEXT: vslidedown.vi v9, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_v2i32_i64:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vse32.v v8, (a0)
; RV64ELEN32-NEXT: ld a0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret
%b = bitcast <2 x i32> %a to i64
ret i64 %b
}
@ -150,6 +258,10 @@ define i64 @bitcast_v1i64_i64(<1 x i64> %a) {
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i64_i64:
; ELEN32: # %bb.0:
; ELEN32-NEXT: ret
%b = bitcast <1 x i64> %a to i64
ret i64 %b
}
@ -160,6 +272,12 @@ define half @bitcast_v2i8_f16(<2 x i8> %a) {
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v2i8_f16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e16, mf2, ta, mu
; ELEN32-NEXT: vfmv.f.s fa0, v8
; ELEN32-NEXT: ret
%b = bitcast <2 x i8> %a to half
ret half %b
}
@ -170,6 +288,12 @@ define half @bitcast_v1i16_f16(<1 x i16> %a) {
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i16_f16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e16, mf2, ta, mu
; ELEN32-NEXT: vfmv.f.s fa0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i16> %a to half
ret half %b
}
@ -180,6 +304,12 @@ define float @bitcast_v4i8_f32(<4 x i8> %a) {
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v4i8_f32:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; ELEN32-NEXT: vfmv.f.s fa0, v8
; ELEN32-NEXT: ret
%b = bitcast <4 x i8> %a to float
ret float %b
}
@ -190,6 +320,12 @@ define float @bitcast_v2i16_f32(<2 x i16> %a) {
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v2i16_f32:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; ELEN32-NEXT: vfmv.f.s fa0, v8
; ELEN32-NEXT: ret
%b = bitcast <2 x i16> %a to float
ret float %b
}
@ -200,6 +336,12 @@ define float @bitcast_v1i32_f32(<1 x i32> %a) {
; CHECK-NEXT: vsetivli zero, 0, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v1i32_f32:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; ELEN32-NEXT: vfmv.f.s fa0, v8
; ELEN32-NEXT: ret
%b = bitcast <1 x i32> %a to float
ret float %b
}
@ -210,6 +352,17 @@ define double @bitcast_v8i8_f64(<8 x i8> %a) {
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v8i8_f64:
; ELEN32: # %bb.0:
; ELEN32-NEXT: addi sp, sp, -16
; ELEN32-NEXT: .cfi_def_cfa_offset 16
; ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ELEN32-NEXT: addi a0, sp, 8
; ELEN32-NEXT: vse8.v v8, (a0)
; ELEN32-NEXT: fld fa0, 8(sp)
; ELEN32-NEXT: addi sp, sp, 16
; ELEN32-NEXT: ret
%b = bitcast <8 x i8> %a to double
ret double %b
}
@ -220,6 +373,17 @@ define double @bitcast_v4i16_f64(<4 x i16> %a) {
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v4i16_f64:
; ELEN32: # %bb.0:
; ELEN32-NEXT: addi sp, sp, -16
; ELEN32-NEXT: .cfi_def_cfa_offset 16
; ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ELEN32-NEXT: addi a0, sp, 8
; ELEN32-NEXT: vse16.v v8, (a0)
; ELEN32-NEXT: fld fa0, 8(sp)
; ELEN32-NEXT: addi sp, sp, 16
; ELEN32-NEXT: ret
%b = bitcast <4 x i16> %a to double
ret double %b
}
@ -230,6 +394,17 @@ define double @bitcast_v2i32_f64(<2 x i32> %a) {
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_v2i32_f64:
; ELEN32: # %bb.0:
; ELEN32-NEXT: addi sp, sp, -16
; ELEN32-NEXT: .cfi_def_cfa_offset 16
; ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; ELEN32-NEXT: addi a0, sp, 8
; ELEN32-NEXT: vse32.v v8, (a0)
; ELEN32-NEXT: fld fa0, 8(sp)
; ELEN32-NEXT: addi sp, sp, 16
; ELEN32-NEXT: ret
%b = bitcast <2 x i32> %a to double
ret double %b
}
@ -240,6 +415,25 @@ define double @bitcast_v1i64_f64(<1 x i64> %a) {
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, mu
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_v1i64_f64:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: addi sp, sp, -16
; RV32ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32ELEN32-NEXT: sw a1, 12(sp)
; RV32ELEN32-NEXT: sw a0, 8(sp)
; RV32ELEN32-NEXT: fld fa0, 8(sp)
; RV32ELEN32-NEXT: addi sp, sp, 16
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_v1i64_f64:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: sd a0, 8(sp)
; RV64ELEN32-NEXT: fld fa0, 8(sp)
; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret
%b = bitcast <1 x i64> %a to double
ret double %b
}
@ -250,6 +444,12 @@ define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: ret
;
; ELEN32-LABEL: bitcast_i16_v1i16:
; ELEN32: # %bb.0:
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; ELEN32-NEXT: vmv.v.x v8, a0
; ELEN32-NEXT: ret
%b = bitcast i16 %a to <1 x i16>
ret <1 x i16> %b
}
@ -266,6 +466,18 @@ define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_i32_v2i16:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32ELEN32-NEXT: vmv.s.x v8, a0
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_i32_v2i16:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64ELEN32-NEXT: vmv.v.x v8, a0
; RV64ELEN32-NEXT: ret
%b = bitcast i32 %a to <2 x i16>
ret <2 x i16> %b
}
@ -282,6 +494,18 @@ define <1 x i32> @bitcast_i32_v1i32(i32 %a) {
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_i32_v1i32:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32ELEN32-NEXT: vmv.s.x v8, a0
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_i32_v1i32:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64ELEN32-NEXT: vmv.v.x v8, a0
; RV64ELEN32-NEXT: ret
%b = bitcast i32 %a to <1 x i32>
ret <1 x i32> %b
}
@ -302,6 +526,25 @@ define <4 x i16> @bitcast_i64_v4i16(i64 %a) {
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_i64_v4i16:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32ELEN32-NEXT: vmv.v.x v8, a1
; RV32ELEN32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32ELEN32-NEXT: vmv.s.x v8, a0
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_i64_v4i16:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: sd a0, 8(sp)
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vle16.v v8, (a0)
; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret
%b = bitcast i64 %a to <4 x i16>
ret <4 x i16> %b
}
@ -322,6 +565,25 @@ define <2 x i32> @bitcast_i64_v2i32(i64 %a) {
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: ret
;
; RV32ELEN32-LABEL: bitcast_i64_v2i32:
; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32ELEN32-NEXT: vmv.v.x v8, a1
; RV32ELEN32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32ELEN32-NEXT: vmv.s.x v8, a0
; RV32ELEN32-NEXT: ret
;
; RV64ELEN32-LABEL: bitcast_i64_v2i32:
; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: sd a0, 8(sp)
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vle32.v v8, (a0)
; RV64ELEN32-NEXT: addi sp, sp, 16
; RV64ELEN32-NEXT: ret
%b = bitcast i64 %a to <2 x i32>
ret <2 x i32> %b
}
@ -342,6 +604,10 @@ define <1 x i64> @bitcast_i64_v1i64(i64 %a) {
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: ret
;
; ELEN32-LABEL: bitcast_i64_v1i64:
; ELEN32: # %bb.0:
; ELEN32-NEXT: ret
%b = bitcast i64 %a to <1 x i64>
ret <1 x i64> %b
}