[RISCV] Simplify interface to combineMUL_VLToVWMUL. NFC
Instead of passing the both the SDNode* and 2 of the operands in two different orders, just pass the SDNode * and a bool to indicate which operand order to test. While there rename to combineMUL_VLToVWMUL_VL.
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@ -7242,9 +7242,14 @@ static SDValue performANY_EXTENDCombine(SDNode *N,
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// Try to form VWMUL or VWMULU.
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// Try to form VWMUL or VWMULU.
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// FIXME: Support VWMULSU.
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// FIXME: Support VWMULSU.
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static SDValue combineMUL_VLToVWMUL(SDNode *N, SDValue Op0, SDValue Op1,
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static SDValue combineMUL_VLToVWMUL_VL(SDNode *N, SelectionDAG &DAG,
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SelectionDAG &DAG) {
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bool Commute) {
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assert(N->getOpcode() == RISCVISD::MUL_VL && "Unexpected opcode");
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assert(N->getOpcode() == RISCVISD::MUL_VL && "Unexpected opcode");
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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if (Commute)
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std::swap(Op0, Op1);
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bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL;
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bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL;
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bool IsZeroExt = Op0.getOpcode() == RISCVISD::VZEXT_VL;
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bool IsZeroExt = Op0.getOpcode() == RISCVISD::VZEXT_VL;
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if ((!IsSignExt && !IsZeroExt) || !Op0.hasOneUse())
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if ((!IsSignExt && !IsZeroExt) || !Op0.hasOneUse())
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@ -7887,15 +7892,11 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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}
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}
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break;
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break;
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}
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}
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case RISCVISD::MUL_VL: {
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case RISCVISD::MUL_VL:
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SDValue Op0 = N->getOperand(0);
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if (SDValue V = combineMUL_VLToVWMUL_VL(N, DAG, /*Commute*/ false))
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SDValue Op1 = N->getOperand(1);
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if (SDValue V = combineMUL_VLToVWMUL(N, Op0, Op1, DAG))
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return V;
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return V;
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if (SDValue V = combineMUL_VLToVWMUL(N, Op1, Op0, DAG))
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// Mul is commutative.
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return V;
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return combineMUL_VLToVWMUL_VL(N, DAG, /*Commute*/ true);
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return SDValue();
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}
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case ISD::STORE: {
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case ISD::STORE: {
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auto *Store = cast<StoreSDNode>(N);
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auto *Store = cast<StoreSDNode>(N);
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SDValue Val = Store->getValue();
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SDValue Val = Store->getValue();
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