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[RISCV] Simplify interface to combineMUL_VLToVWMUL. NFC 

Instead of passing the both the SDNode* and 2 of the operands
in two different orders, just pass the SDNode * and a bool to
indicate which operand order to test.

While there rename to combineMUL_VLToVWMUL_VL.
This commit is contained in:
Craig Topper 2022-01-21 11:30:49 -08:00
parent 3c90ae5d0b
commit 48132bb1e4
1 changed files with 11 additions and 10 deletions
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21
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -7242,9 +7242,14 @@ static SDValue performANY_EXTENDCombine(SDNode *N,
// Try to form VWMUL or VWMULU.
// FIXME: Support VWMULSU.
static SDValue combineMUL_VLToVWMUL(SDNode *N, SDValue Op0, SDValue Op1,
SelectionDAG &DAG) {
static SDValue combineMUL_VLToVWMUL_VL(SDNode *N, SelectionDAG &DAG,
bool Commute) {
assert(N->getOpcode() == RISCVISD::MUL_VL && "Unexpected opcode");
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
if (Commute)
std::swap(Op0, Op1);
bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL;
bool IsZeroExt = Op0.getOpcode() == RISCVISD::VZEXT_VL;
if ((!IsSignExt && !IsZeroExt) || !Op0.hasOneUse())
@ -7887,15 +7892,11 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
}
break;
}
case RISCVISD::MUL_VL: {
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
if (SDValue V = combineMUL_VLToVWMUL(N, Op0, Op1, DAG))
case RISCVISD::MUL_VL:
if (SDValue V = combineMUL_VLToVWMUL_VL(N, DAG, /*Commute*/ false))
return V;
if (SDValue V = combineMUL_VLToVWMUL(N, Op1, Op0, DAG))
return V;
return SDValue();
}
// Mul is commutative.
return combineMUL_VLToVWMUL_VL(N, DAG, /*Commute*/ true);
case ISD::STORE: {
auto *Store = cast<StoreSDNode>(N);
SDValue Val = Store->getValue();