[mips] Fix the definitions of the EVA instructions
Correct their availability to their respective ISAs. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D44209 llvm-svn: 327403
This commit is contained in:
Simon Dardis
parent
d9a8b6a745
commit
476ed8f26e
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@ -777,32 +777,50 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
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LW_FM_MM<0x3e>;
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}
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}
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let DecoderNamespace = "MicroMips" in {
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let DecoderMethod = "DecodeMemMMImm9" in {
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def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
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def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
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def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9,
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null_frag, II_LHE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
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def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9,
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null_frag, II_LHUE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
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def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9,
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null_frag, II_LWE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
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def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9,
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null_frag, II_SBE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
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def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9,
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null_frag, II_SHE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
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def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9,
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null_frag, II_SWE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
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def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,
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II_LHE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;
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def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,
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II_LHUE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;
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def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,
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II_LWE>,
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POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;
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def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,
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II_SBE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;
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def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,
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II_SHE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;
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def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
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II_SWE>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;
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def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
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II_LWLE>,
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POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,
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ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
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def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
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II_LWRE>,
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POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,
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ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
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def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
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II_SWLE>,
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POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,
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ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
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def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
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II_SWRE>,
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POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
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ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
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}
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}
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
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/// Load and Store Instructions - unaligned
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@ -814,18 +832,6 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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LWL_FM_MM<0x8>;
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def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>,
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LWL_FM_MM<0x9>;
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let DecoderMethod = "DecodeMemMMImm9" in {
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def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
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II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
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def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
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II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
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def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
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II_SWLE>,
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POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
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def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
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II_SWRE>,
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POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
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}
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/// Load and Store Instructions - multiple
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def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
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@ -978,23 +984,30 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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/// Load-linked, Store-conditional
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def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
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def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
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def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
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def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
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}
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let DecoderNamespace = "MicroMips" in {
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def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
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ISA_MICROMIPS, ASE_EVA;
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def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
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ISA_MICROMIPS, ASE_EVA;
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}
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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let DecoderMethod = "DecodeCacheOpMM" in {
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def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
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CACHE_PREF_FM_MM<0x08, 0x6>;
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def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
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CACHE_PREF_FM_MM<0x18, 0x2>;
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}
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}
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let DecoderNamespace = "MicroMips" in {
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let DecoderMethod = "DecodePrefeOpMM" in {
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def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
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CACHE_PREFE_FM_MM<0x18, 0x2>;
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CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
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def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
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CACHE_PREFE_FM_MM<0x18, 0x3>;
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CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
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}
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}
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
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def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
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def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
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@ -95,6 +95,7 @@ class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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string BaseOpcode = instr_asm;
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string Constraints = "$src = $rt";
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bit canFoldAsLoad = 1;
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InstrItinClass Itinerary = itin;
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@ -110,6 +111,7 @@ class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeMemEVA";
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string BaseOpcode = instr_asm;
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InstrItinClass Itinerary = itin;
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}
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@ -177,38 +179,32 @@ class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>;
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//
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//===----------------------------------------------------------------------===//
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/// Load and Store EVA Instructions
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def LBE : MMRel, LBE_ENC, LBE_DESC, ASE_EVA;
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def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA;
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def LHE : MMRel, LHE_ENC, LHE_DESC, ASE_EVA;
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def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA;
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let AdditionalPredicates = [NotInMicroMips] in {
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def LWE : MMRel, LWE_ENC, LWE_DESC, ASE_EVA;
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}
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def SBE : MMRel, SBE_ENC, SBE_DESC, ASE_EVA;
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def SHE : MMRel, SHE_ENC, SHE_DESC, ASE_EVA;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SWE : MMRel, SWE_ENC, SWE_DESC, ASE_EVA;
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}
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/// Load and Store EVA Instructions
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def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA;
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def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA;
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/// load/store left/right EVA
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let AdditionalPredicates = [NotInMicroMips] in {
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def LWLE : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def LWRE : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def SWLE : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def SWRE : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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}
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/// load/store left/right EVA
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def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
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/// Load-linked EVA, Store-conditional EVA
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let AdditionalPredicates = [NotInMicroMips] in {
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def LLE : MMRel, LLE_ENC, LLE_DESC, ASE_EVA;
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def SCE : MMRel, SCE_ENC, SCE_DESC, ASE_EVA;
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}
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/// Load-linked EVA, Store-conditional EVA
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def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA;
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def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA;
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let AdditionalPredicates = [NotInMicroMips] in {
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def TLBINV : TLBINV_ENC, TLBINV_DESC, ASE_EVA;
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def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA;
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}
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/// TLB invalidate instructions
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def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA;
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def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA;
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def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA;
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def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA;
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/// EVA versions of cache and pref
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def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA;
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def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA;
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}
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@ -235,7 +235,7 @@ def IsBE : Predicate<"!Subtarget->isLittle()">;
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def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
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def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
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def HasEVA : Predicate<"Subtarget->hasEVA()">,
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AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
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AssemblerPredicate<"FeatureEVA">;
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def HasMSA : Predicate<"Subtarget->hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
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@ -1,5 +1,5 @@
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# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips -start-after=expand-isel-pseudos \
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# RUN: -filetype obj %s -o - | llvm-objdump -d - | FileCheck %s
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# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
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# RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
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--- |
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips \
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# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips,eva \
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# RUN: | FileCheck %s
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0xf9 0x4f # CHECK: addiusp -16
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips \
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips,eva \
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# RUN: | FileCheck %s
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0x4f 0xf9 # CHECK: addiusp -16
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@ -1,4 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips | FileCheck %s
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# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips,eva | FileCheck %s
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0x6f 0x83 # CHECK: addiur1sp $7, 4
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0x6f 0x7e # CHECK: addiur2 $6, $7, -1
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@ -39,15 +39,7 @@
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# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
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# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
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# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
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# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
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# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
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# CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
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# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
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# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
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# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
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# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
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# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c]
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# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac]
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#------------------------------------------------------------------------------
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# Big endian
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#------------------------------------------------------------------------------
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@ -81,15 +73,7 @@
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# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c]
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# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
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# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
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# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
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# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
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# CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
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# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
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# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
|
||||
# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
|
||||
# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
|
||||
# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08]
|
||||
# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08]
|
||||
|
||||
sdbbp
|
||||
sdbbp 34
|
||||
|
|
@ -118,12 +102,5 @@
|
|||
tlbr
|
||||
tlbwi
|
||||
tlbwr
|
||||
prefe 1, 8($5)
|
||||
cachee 1, 8($5)
|
||||
prefx 1, $3($5)
|
||||
swre $24, 5($3)
|
||||
swle $24, 5($3)
|
||||
lwre $24, 5($3)
|
||||
lwle $24, 2($4)
|
||||
lle $2, 8($4)
|
||||
sce $2, 8($4)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,96 @@
|
|||
# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r2 \
|
||||
# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s
|
||||
# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r2 \
|
||||
# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s
|
||||
# Check that the assembler can handle the documented syntax
|
||||
# for EVA instructions.
|
||||
#------------------------------------------------------------------------------
|
||||
# microMIPS EVA Instructions
|
||||
#------------------------------------------------------------------------------
|
||||
# Little endian
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
|
||||
# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
|
||||
# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
|
||||
# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
|
||||
# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWRE_MM
|
||||
# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWLE_MM
|
||||
# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWRE_MM
|
||||
# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWLE_MM
|
||||
# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHuE_M
|
||||
# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
|
||||
# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
|
||||
# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
|
||||
# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
|
||||
# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
|
||||
# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
|
||||
# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
|
||||
#------------------------------------------------------------------------------
|
||||
# Big endian
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
|
||||
# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
|
||||
# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
|
||||
# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
|
||||
# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWRE_MM
|
||||
# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWLE_MM
|
||||
# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWRE_MM
|
||||
# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWLE_MM
|
||||
# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHuE_MM
|
||||
# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
|
||||
# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
|
||||
# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
|
||||
# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
|
||||
# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
|
||||
# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
|
||||
# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
|
||||
|
||||
prefe 1, 8($5)
|
||||
cachee 1, 8($5)
|
||||
lle $2, 8($4)
|
||||
sce $2, 8($4)
|
||||
swre $24, 5($3)
|
||||
swle $24, 5($3)
|
||||
lwre $24, 5($3)
|
||||
lwle $24, 2($4)
|
||||
lhue $4, 8($2)
|
||||
lbe $4, 8($2)
|
||||
lbue $4, 8($2)
|
||||
lhe $4, 8($2)
|
||||
lwe $4, 8($2)
|
||||
sbe $5, 8($4)
|
||||
she $5, 8($4)
|
||||
swe $5, 8($4)
|
||||
|
||||
|
|
@ -44,14 +44,6 @@
|
|||
# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0]
|
||||
# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
|
||||
# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
|
||||
# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
|
||||
# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
|
||||
# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
|
||||
# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
|
||||
# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
|
||||
# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
|
||||
# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
|
||||
# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
|
||||
#------------------------------------------------------------------------------
|
||||
# Big endian
|
||||
#------------------------------------------------------------------------------
|
||||
|
|
@ -90,14 +82,6 @@
|
|||
# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
|
||||
# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
|
||||
# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
|
||||
# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
|
||||
# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
|
||||
# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
|
||||
# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
|
||||
# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
|
||||
# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
|
||||
# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
|
||||
# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
|
||||
lb $5, 8($4)
|
||||
lbu $6, 8($4)
|
||||
lh $2, 8($4)
|
||||
|
|
@ -133,11 +117,4 @@
|
|||
swm $16, $17, 8($sp)
|
||||
swp $16, 8($4)
|
||||
lwp $16, 8($4)
|
||||
lhue $4, 8($2)
|
||||
lbe $4, 8($2)
|
||||
lbue $4, 8($2)
|
||||
lhe $4, 8($2)
|
||||
lwe $4, 8($2)
|
||||
sbe $5, 8($4)
|
||||
she $5, 8($4)
|
||||
swe $5, 8($4)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
|
||||
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips,eva 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips | FileCheck %s
|
||||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips,eva | FileCheck %s
|
||||
|
||||
.set noat
|
||||
addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,76 @@
|
|||
# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r6 \
|
||||
# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s
|
||||
# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r6 \
|
||||
# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s
|
||||
# Check that the assembler can handle the documented syntax
|
||||
# for EVA instructions.
|
||||
#------------------------------------------------------------------------------
|
||||
# microMIPS EVA Instructions
|
||||
#------------------------------------------------------------------------------
|
||||
# Little endian
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
|
||||
# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
|
||||
# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
|
||||
# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
|
||||
# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHuE_M
|
||||
# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
|
||||
# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
|
||||
# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
|
||||
# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
|
||||
# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
|
||||
# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
|
||||
# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
|
||||
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
|
||||
#------------------------------------------------------------------------------
|
||||
# Big endian
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
|
||||
# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
|
||||
# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
|
||||
# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
|
||||
# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHuE_MM
|
||||
# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
|
||||
# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
|
||||
# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
|
||||
# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
|
||||
# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
|
||||
# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
|
||||
# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
|
||||
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
|
||||
|
||||
prefe 1, 8($5)
|
||||
cachee 1, 8($5)
|
||||
lle $2, 8($4)
|
||||
sce $2, 8($4)
|
||||
lhue $4, 8($2)
|
||||
lbe $4, 8($2)
|
||||
lbue $4, 8($2)
|
||||
lhe $4, 8($2)
|
||||
lwe $4, 8($2)
|
||||
sbe $5, 8($4)
|
||||
she $5, 8($4)
|
||||
swe $5, 8($4)
|
||||
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
|
||||
# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=+micromips,+eva 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
|
||||
|
|
|
|||
|
|
@ -68,9 +68,7 @@
|
|||
lapc $7, 1048572 # CHECK: lapc $7, 1048572 # encoding: [0x78,0xe3,0xff,0xff]
|
||||
lapc $7, -1048576 # CHECK: lapc $7, -1048576 # encoding: [0x78,0xe4,0x00,0x00]
|
||||
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
|
||||
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
|
||||
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
|
||||
lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
|
||||
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
|
||||
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
|
||||
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
|
||||
|
|
@ -148,7 +146,6 @@
|
|||
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
|
||||
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
|
||||
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
|
||||
swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
|
||||
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
|
||||
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM
|
||||
|
|
@ -260,12 +257,7 @@
|
|||
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
|
||||
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
|
||||
sb $4, 6($5) # CHECK: sb $4, 6($5) # encoding: [0x18,0x85,0x00,0x06]
|
||||
sbe $4, 6($5) # CHECK: sbe $4, 6($5) # encoding: [0x60,0x85,0xa8,0x06]
|
||||
sce $4, 6($5) # CHECK: sce $4, 6($5) # encoding: [0x60,0x85,0xac,0x06]
|
||||
sh $4, 6($5) # CHECK: sh $4, 6($5) # encoding: [0x38,0x85,0x00,0x06]
|
||||
she $4, 6($5) # CHECK: she $4, 6($5) # encoding: [0x60,0x85,0xaa,0x06]
|
||||
lle $4, 6($5) # CHECK: lle $4, 6($5) # encoding: [0x60,0x85,0x6c,0x06]
|
||||
lwe $4, 6($5) # CHECK: lwe $4, 6($5) # encoding: [0x60,0x85,0x6e,0x06]
|
||||
lw $4, 6($5) # CHECK: lw $4, 6($5) # encoding: [0xfc,0x85,0x00,0x06]
|
||||
lui $6, 17767 # CHECK: lui $6, 17767 # encoding: [0x10,0xc0,0x45,0x67]
|
||||
addu16 $6, $17, $4 # CHECK: addu16 $6, $17, $4 # encoding: [0x04,0xcc]
|
||||
|
|
@ -275,8 +267,6 @@
|
|||
or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
|
||||
sll16 $3, $6, 8 # CHECK: sll16 $3, $6, 8 # encoding: [0x25,0xe0]
|
||||
srl16 $3, $6, 8 # CHECK: srl16 $3, $6, 8 # encoding: [0x25,0xe1]
|
||||
prefe 1, 8($5) # CHECK: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
|
||||
cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
|
||||
teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
|
||||
teq $5, $7, 15 # CHECK: teq $5, $7, 15 # encoding: [0x00,0xe5,0xf0,0x3c]
|
||||
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x01,0x47,0x02,0x3c]
|
||||
|
|
@ -297,8 +287,6 @@
|
|||
xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8]
|
||||
lb $4, 8($5) # CHECK: lb $4, 8($5) # encoding: [0x1c,0x85,0x00,0x08]
|
||||
lbu $4, 8($5) # CHECK: lbu $4, 8($5) # encoding: [0x14,0x85,0x00,0x08]
|
||||
lbe $4, 8($5) # CHECK: lbe $4, 8($5) # encoding: [0x60,0x85,0x68,0x08]
|
||||
lbue $4, 8($5) # CHECK: lbue $4, 8($5) # encoding: [0x60,0x85,0x60,0x08]
|
||||
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
|
||||
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
|
||||
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
|
||||
|
|
|
|||
Loading…
Reference in New Issue