diff --git a/llvm/lib/Target/RISCV/VentusInstrInfoF.td b/llvm/lib/Target/RISCV/VentusInstrInfoF.td
index fbb59ea30c2c..312f2c7b211b 100644
--- a/llvm/lib/Target/RISCV/VentusInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/VentusInstrInfoF.td
@@ -340,29 +340,7 @@ class PseudoVFROUND<RegisterClass Ty>
 // Instructions
 //===----------------------------------------------------------------------===//
 
-// FIXME: Ventus doesn't have FLW/FSW,it is same opcode with LW/SW
-// but for GPRF32.
-let Predicates = [HasStdExtZfinx] in {
-/// Loads
-def FLW  : RVInstI<0b010, OPC_LOAD, (outs GPRF32:$rd),
-                   (ins GPRMem:$rs1, simm12:$imm12),
-                   "flw", "$rd, ${imm12}(${rs1})">,
-                   Sched<[WriteLDW, ReadMemBase]>;
 
-def : Pat<(f32 (UniformLoadFrag<load>
-          (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
-          (FLW GPR:$rs1, simm12:$imm12)>;
-
-/// Stores
-def FSW : RVInstS<0b010, OPC_STORE, (outs),
-              (ins GPRF32:$rs2, GPRMem:$rs1, simm12:$imm12),
-              "fsw", "$rs2, ${imm12}(${rs1})">,
-              Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
-
-def : Pat<(UniformStoreFrag<store> (f32 GPRF32:$rs2),
-          (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
-          (FSW GPRF32:$rs2, GPR:$rs1, simm12:$imm12)>;
-} // Predicates = [HasStdExtZfinx]
 
 let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
 defm FMADD_S  : FPFMA_rrr_frm_m<OPC_MADD,  0b00, "fmadd.s",  FINX>;
@@ -466,8 +444,12 @@ defm           : FPUnaryOpDynFrmAlias_m<FCVT_S_LU, "fcvt.s.lu", FXIN64X>;
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfinx] in {
-// def : InstAlias<"flw $rd, (${rs1})",  (FLW GPRF32:$rd,  GPR:$rs1, 0), 0>;
-// def : InstAlias<"fsw $rs2, (${rs1})", (FSW GPRF32:$rs2, GPR:$rs1, 0), 0>;
+
+def : InstAlias<"flw $rd, ${imm12}(${rs1})",
+                (LW  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+
+def : InstAlias<"fsw $rs2, ${imm12}(${rs1})",
+                (SW  GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
 
 def : InstAlias<"fmv.s $rd, $rs",  (FSGNJ_S  GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>;
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S GPRF32:$rd, GPRF32:$rs, GPRF32:$rs)>;
@@ -510,8 +492,26 @@ def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, SysRegFFLAGS.Encoding, ui
 def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
 def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
 
-def PseudoFLW  : PseudoFloatLoad<"flw", GPRF32>;
-def PseudoFSW  : PseudoStore<"fsw", GPRF32>;
+def PseudoFLW : Pseudo<(outs GPRF32:$rd), (ins GPRMem:$rs1, simm12:$imm12), [],
+                       "flw", "$rd, ${imm12}(${rs1})">,
+                PseudoInstExpansion<(LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)> {
+  let hasSideEffects = 0;
+  let mayLoad = 1;
+  let mayStore = 0;
+  let isCodeGenOnly = 0;
+  let isAsmParserOnly = 1;
+}
+
+def PseudoFSW : Pseudo<(outs), (ins  GPRF32:$rs2, GPRMem:$rs1, simm12:$imm12),
+                       [], "fsw", "$rs2, ${imm12}(${rs1})">,
+                PseudoInstExpansion<(SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)> {
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 1;
+  let isCodeGenOnly = 0;
+  let isAsmParserOnly = 1;
+}
+
 let usesCustomInserter = 1 in {
 def PseudoQuietFLE_S : PseudoQuietFCMP<GPRF32>;
 def PseudoQuietFLT_S : PseudoQuietFCMP<GPRF32>;
@@ -654,11 +654,11 @@ def PseudoFROUND_S : PseudoFROUND<GPRF32>;
 
 // /// Loads
 
-// defm : UniformLdPat<load, FLW, f32>;
+defm : UniformLdPat<load, PseudoFLW, f32>;
 
 // /// Stores
 
-// defm : UniformStPat<store, FSW, GPRF32, f32>;
+defm : UniformStPat<store, PseudoFSW, GPRF32, f32>;
 
 } // Predicates = [HasStdExtZfinx]