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[RISCV] Limit transformAddImmMulImm to prevent an infinite loop. 

This fixes an issue reported in D108607.
This commit is contained in:
Craig Topper 2021-09-23 15:52:49 -07:00
parent e9d1a679a1
commit 40b230f685
2 changed files with 31 additions and 0 deletions
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3
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -6416,6 +6416,9 @@ static SDValue transformAddImmMulImm(SDNode *N, SelectionDAG &DAG,
if (C0 == -1 || C0 == 0 || C0 == 1 || (C1 / C0) == 0 || isInt<12>(C1) ||
!isInt<12>(C1 % C0) || !isInt<12>(C1 / C0))
return SDValue();
// If C0 * (C1 / C0) is a 12-bit integer, this transform will be reversed.
if (isInt<12>(C0 * (C1 / C0)))
return SDValue();
// Build new nodes (add (mul (add x, c1/c0), c0), c1%c0).
SDLoc DL(N);
SDValue New0 = DAG.getNode(ISD::ADD, DL, VT, N0->getOperand(0),

28
llvm/test/CodeGen/RISCV/addimm-mulimm.ll
View File

@ -540,3 +540,31 @@ define i64 @add_mul_combine_reject_g3(i64 %x) {
%tmp1 = add i64 %tmp0, 7310
ret i64 %tmp1
}
; This test previously infinite looped in DAG combine.
define i64 @add_mul_combine_infinite_loop(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_infinite_loop:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 24
; RV32IMB-NEXT: mulhu a2, a0, a2
; RV32IMB-NEXT: sh1add a1, a1, a1
; RV32IMB-NEXT: sh3add a1, a1, a2
; RV32IMB-NEXT: sh1add a0, a0, a0
; RV32IMB-NEXT: slli a2, a0, 3
; RV32IMB-NEXT: addi a0, a2, 1024
; RV32IMB-NEXT: addi a0, a0, 1024
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_infinite_loop:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: sh1add a0, a0, a0
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -2048
; RV64IMB-NEXT: sh3add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 24
%tmp1 = add i64 %tmp0, 2048
ret i64 %tmp1
}