Update TODOs and add inst 'endprg' to end warp execution.

README.md

@@ -38,6 +38,7 @@ clang -cl-std=CL2.0 -target riscv32 -mcpu=ventus-gpgpu -O1 -S vector_add.cl -o v
 
 ### TODOs
 
+* Emit `barrier` instruction for all stores to local/global memory except sGPR spill.
 * Stacks for sGPR spilling and per-thread usage is supported by using RISCV::X2 as warp level stack, RISCV::X4 as per-thread level stack. But the 2 stack size calculation are not yet splitted out, so a lot of stack slots are wasted.
 * VentusRegextInsertion pass may generate incorrect register ordering for next instruction, see FIXME in that pass. To avoid breaking def-use chain, we could keep the extended instruction unmodified by removing `Op.setRegIgnoreDUChain()` from the pass, the elf generation pass should ignore the higher bit(>2^5) of the register encoding automatically.
 * Pattern match VV and VX optimization. There is only type information in the DAG pattern matching, we can't specify whether to match a DAG to a vop.vv or vop.vx MIR in a tblgen pattern, so a fix pass should be ran after codegen pass.

compiler-rt/lib/ventus/crt0.S

@@ -42,4 +42,8 @@ _start:
 
   # call exit routine
   # tail    exit
+
+  # End of warp execution
+  endprg
+
 .size  _start, .-_start