[LoopSimplifyCFG] Forget loop and block dispos after merging blocks.
This fixes another case where block and loop dispositions weren't properly invalidate after changing the CFG. Fixes #58489.
This commit is contained in:
Florian Hahn
parent
bed31153b7
commit
3a4aa24fd1
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@ -660,7 +660,8 @@ static bool constantFoldTerminators(Loop &L, DominatorTree &DT, LoopInfo &LI,
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}
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static bool mergeBlocksIntoPredecessors(Loop &L, DominatorTree &DT,
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LoopInfo &LI, MemorySSAUpdater *MSSAU) {
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LoopInfo &LI, MemorySSAUpdater *MSSAU,
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ScalarEvolution &SE) {
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bool Changed = false;
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DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager);
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// Copy blocks into a temporary array to avoid iterator invalidation issues
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@ -687,6 +688,9 @@ static bool mergeBlocksIntoPredecessors(Loop &L, DominatorTree &DT,
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Changed = true;
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}
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if (Changed)
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SE.forgetBlockAndLoopDispositions();
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return Changed;
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}
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@ -702,7 +706,7 @@ static bool simplifyLoopCFG(Loop &L, DominatorTree &DT, LoopInfo &LI,
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return true;
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// Eliminate unconditional branches by merging blocks into their predecessors.
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Changed |= mergeBlocksIntoPredecessors(L, DT, LI, MSSAU);
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Changed |= mergeBlocksIntoPredecessors(L, DT, LI, MSSAU, SE);
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if (Changed)
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SE.forgetTopmostLoop(&L);
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@ -1,5 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -verify-scev -passes='loop(require<iv-users>),loop-mssa(loop-simplifycfg)' -S %s | FileCheck %s
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; RUN: opt -verify-scev -passes='loop(require<iv-users>),loop-mssa(loop-simplifycfg)' -S %s | FileCheck --check-prefixes=CHECK,IVUSERS %s
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; RUN: opt -verify-scev -passes="indvars,loop-simplifycfg" -S %s | FileCheck --check-prefixes=CHECK,INDVARS %s
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target datalayout = "p:16:16-n16:32"
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@ -27,30 +28,55 @@ inner:
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}
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define void @test_remove_instrs_in_exit_block() {
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; CHECK-LABEL: @test_remove_instrs_in_exit_block(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A:%.*]] = alloca [10 x i64], align 1
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; CHECK-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [
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; CHECK-NEXT: i32 1, label [[OUTER_LATCH]]
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; CHECK-NEXT: ]
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; CHECK: outer.header.split:
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; CHECK-NEXT: br label [[INNER:%.*]]
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; CHECK: inner:
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; CHECK-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]
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; CHECK-NEXT: store i64 0, ptr [[GEP]], align 4
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; CHECK-NEXT: [[L:%.*]] = call i16 @get()
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; CHECK-NEXT: [[IV_NEXT]] = add nsw i16 [[IV]], 1
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; CHECK-NEXT: br label [[INNER]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i16 [[OUTER_IV]], 1
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; CHECK-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]
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; CHECK-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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; IVUSERS-LABEL: @test_remove_instrs_in_exit_block(
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; IVUSERS-NEXT: entry:
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; IVUSERS-NEXT: [[A:%.*]] = alloca [10 x i64], align 1
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; IVUSERS-NEXT: br label [[OUTER_HEADER:%.*]]
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; IVUSERS: outer.header:
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; IVUSERS-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; IVUSERS-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [
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; IVUSERS-NEXT: i32 1, label [[OUTER_LATCH]]
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; IVUSERS-NEXT: ]
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; IVUSERS: outer.header.split:
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; IVUSERS-NEXT: br label [[INNER:%.*]]
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; IVUSERS: inner:
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; IVUSERS-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]
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; IVUSERS-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]
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; IVUSERS-NEXT: store i64 0, ptr [[GEP]], align 4
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; IVUSERS-NEXT: [[L:%.*]] = call i16 @get()
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; IVUSERS-NEXT: [[IV_NEXT]] = add nsw i16 [[IV]], 1
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; IVUSERS-NEXT: br label [[INNER]]
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; IVUSERS: outer.latch:
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; IVUSERS-NEXT: [[OUTER_IV_NEXT]] = add nsw i16 [[OUTER_IV]], 1
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; IVUSERS-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]
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; IVUSERS-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
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; IVUSERS: exit:
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; IVUSERS-NEXT: ret void
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;
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; INDVARS-LABEL: @test_remove_instrs_in_exit_block(
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; INDVARS-NEXT: entry:
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; INDVARS-NEXT: [[A:%.*]] = alloca [10 x i64], align 1
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; INDVARS-NEXT: br label [[OUTER_HEADER:%.*]]
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; INDVARS: outer.header:
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; INDVARS-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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; INDVARS-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [
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; INDVARS-NEXT: i32 1, label [[OUTER_LATCH]]
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; INDVARS-NEXT: ]
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; INDVARS: outer.header.split:
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; INDVARS-NEXT: br label [[INNER:%.*]]
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; INDVARS: inner:
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; INDVARS-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]
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; INDVARS-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]
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; INDVARS-NEXT: store i64 0, ptr [[GEP]], align 4
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; INDVARS-NEXT: [[L:%.*]] = call i16 @get()
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; INDVARS-NEXT: [[IV_NEXT]] = add nuw nsw i16 [[IV]], 1
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; INDVARS-NEXT: br label [[INNER]]
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; INDVARS: outer.latch:
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; INDVARS-NEXT: [[OUTER_IV_NEXT]] = add nuw nsw i16 [[OUTER_IV]], 1
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; INDVARS-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]
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; INDVARS-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
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; INDVARS: exit:
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; INDVARS-NEXT: ret void
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;
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entry:
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%a = alloca [10 x i64], align 1
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@ -79,3 +105,50 @@ exit:
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}
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declare i16 @get()
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define i32 @test_pr58489(i32 %a) {
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; CHECK-LABEL: @test_pr58489(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[A:%.*]], -23
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; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])
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; CHECK-NEXT: switch i32 0, label [[ENTRY_SPLIT:%.*]] [
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; CHECK-NEXT: i32 1, label [[EXIT:%.*]]
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; CHECK-NEXT: ]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT]] ], [ [[SHIFT:%.*]], [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[C_2:%.*]] = icmp ne i32 [[P]], 0
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; CHECK-NEXT: [[C_2_EXT:%.*]] = zext i1 [[C_2]] to i16
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; CHECK-NEXT: call void @use(i16 [[C_2_EXT]])
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; CHECK-NEXT: [[SHIFT]] = ashr exact i32 [[A]], 16
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; CHECK-NEXT: br label [[LOOP_HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 poison
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;
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entry:
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%c.1 = icmp slt i32 %a, -23
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call void @llvm.assume(i1 %c.1)
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br label %loop.header
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loop.header:
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%p = phi i32 [ 0, %entry ], [ %shift, %loop.latch ]
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br label %loop.latch
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loop.latch:
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%c.2 = icmp ne i32 %p, 0
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%c.2.ext = zext i1 %c.2 to i16
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call void @use(i16 %c.2.ext)
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%shift = ashr exact i32 %a, 16
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switch i32 50, label %exit [
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i32 50, label %loop.header
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]
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exit:
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%shift.lcssa = phi i32 [ %shift, %loop.latch ]
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ret i32 %shift.lcssa
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}
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declare void @llvm.assume(i1 noundef) #0
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declare void @use(i16)
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