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[LoopSimplifyCFG] Forget loop and block dispos after merging blocks. 

This fixes another case where block and loop dispositions weren't
properly invalidate after changing the CFG.

Fixes #58489.
This commit is contained in:
Florian Hahn 2022-10-20 11:23:29 +01:00
parent bed31153b7
commit 3a4aa24fd1
No known key found for this signature in database
GPG Key ID: EEF712BB5E80EBBA
2 changed files with 104 additions and 27 deletions
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8
llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp
View File

@ -660,7 +660,8 @@ static bool constantFoldTerminators(Loop &L, DominatorTree &DT, LoopInfo &LI,
} }
static bool mergeBlocksIntoPredecessors(Loop &L, DominatorTree &DT, static bool mergeBlocksIntoPredecessors(Loop &L, DominatorTree &DT,
LoopInfo &LI, MemorySSAUpdater *MSSAU) { LoopInfo &LI, MemorySSAUpdater *MSSAU,
ScalarEvolution &SE) {
bool Changed = false; bool Changed = false;
DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager); DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager);
// Copy blocks into a temporary array to avoid iterator invalidation issues // Copy blocks into a temporary array to avoid iterator invalidation issues
@ -687,6 +688,9 @@ static bool mergeBlocksIntoPredecessors(Loop &L, DominatorTree &DT,
Changed = true; Changed = true;
} }
if (Changed)
SE.forgetBlockAndLoopDispositions();
return Changed; return Changed;
} }
@ -702,7 +706,7 @@ static bool simplifyLoopCFG(Loop &L, DominatorTree &DT, LoopInfo &LI,
return true; return true;
// Eliminate unconditional branches by merging blocks into their predecessors. // Eliminate unconditional branches by merging blocks into their predecessors.
Changed |= mergeBlocksIntoPredecessors(L, DT, LI, MSSAU); Changed |= mergeBlocksIntoPredecessors(L, DT, LI, MSSAU, SE);
if (Changed) if (Changed)
SE.forgetTopmostLoop(&L); SE.forgetTopmostLoop(&L);

123
llvm/test/Transforms/LoopSimplifyCFG/invalidate-scev-dispositions.ll
View File

@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -verify-scev -passes='loop(require<iv-users>),loop-mssa(loop-simplifycfg)' -S %s | FileCheck %s ; RUN: opt -verify-scev -passes='loop(require<iv-users>),loop-mssa(loop-simplifycfg)' -S %s | FileCheck --check-prefixes=CHECK,IVUSERS %s
; RUN: opt -verify-scev -passes="indvars,loop-simplifycfg" -S %s | FileCheck --check-prefixes=CHECK,INDVARS %s
target datalayout = "p:16:16-n16:32" target datalayout = "p:16:16-n16:32"
@ -27,30 +28,55 @@ inner:
} }
define void @test_remove_instrs_in_exit_block() { define void @test_remove_instrs_in_exit_block() {
; CHECK-LABEL: @test_remove_instrs_in_exit_block( ; IVUSERS-LABEL: @test_remove_instrs_in_exit_block(
; CHECK-NEXT: entry: ; IVUSERS-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = alloca [10 x i64], align 1 ; IVUSERS-NEXT: [[A:%.*]] = alloca [10 x i64], align 1
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] ; IVUSERS-NEXT: br label [[OUTER_HEADER:%.*]]
; CHECK: outer.header: ; IVUSERS: outer.header:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ] ; IVUSERS-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
; CHECK-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [ ; IVUSERS-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [
; CHECK-NEXT: i32 1, label [[OUTER_LATCH]] ; IVUSERS-NEXT: i32 1, label [[OUTER_LATCH]]
; CHECK-NEXT: ] ; IVUSERS-NEXT: ]
; CHECK: outer.header.split: ; IVUSERS: outer.header.split:
; CHECK-NEXT: br label [[INNER:%.*]] ; IVUSERS-NEXT: br label [[INNER:%.*]]
; CHECK: inner: ; IVUSERS: inner:
; CHECK-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ] ; IVUSERS-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]] ; IVUSERS-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]
; CHECK-NEXT: store i64 0, ptr [[GEP]], align 4 ; IVUSERS-NEXT: store i64 0, ptr [[GEP]], align 4
; CHECK-NEXT: [[L:%.*]] = call i16 @get() ; IVUSERS-NEXT: [[L:%.*]] = call i16 @get()
; CHECK-NEXT: [[IV_NEXT]] = add nsw i16 [[IV]], 1 ; IVUSERS-NEXT: [[IV_NEXT]] = add nsw i16 [[IV]], 1
; CHECK-NEXT: br label [[INNER]] ; IVUSERS-NEXT: br label [[INNER]]
; CHECK: outer.latch: ; IVUSERS: outer.latch:
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i16 [[OUTER_IV]], 1 ; IVUSERS-NEXT: [[OUTER_IV_NEXT]] = add nsw i16 [[OUTER_IV]], 1
; CHECK-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]] ; IVUSERS-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]
; CHECK-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]] ; IVUSERS-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
; CHECK: exit: ; IVUSERS: exit:
; CHECK-NEXT: ret void ; IVUSERS-NEXT: ret void
;
; INDVARS-LABEL: @test_remove_instrs_in_exit_block(
; INDVARS-NEXT: entry:
; INDVARS-NEXT: [[A:%.*]] = alloca [10 x i64], align 1
; INDVARS-NEXT: br label [[OUTER_HEADER:%.*]]
; INDVARS: outer.header:
; INDVARS-NEXT: [[OUTER_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
; INDVARS-NEXT: switch i32 0, label [[OUTER_HEADER_SPLIT:%.*]] [
; INDVARS-NEXT: i32 1, label [[OUTER_LATCH]]
; INDVARS-NEXT: ]
; INDVARS: outer.header.split:
; INDVARS-NEXT: br label [[INNER:%.*]]
; INDVARS: inner:
; INDVARS-NEXT: [[IV:%.*]] = phi i16 [ 0, [[OUTER_HEADER_SPLIT]] ], [ [[IV_NEXT:%.*]], [[INNER]] ]
; INDVARS-NEXT: [[GEP:%.*]] = getelementptr inbounds [10 x i64], ptr [[A]], i32 0, i16 [[IV]]
; INDVARS-NEXT: store i64 0, ptr [[GEP]], align 4
; INDVARS-NEXT: [[L:%.*]] = call i16 @get()
; INDVARS-NEXT: [[IV_NEXT]] = add nuw nsw i16 [[IV]], 1
; INDVARS-NEXT: br label [[INNER]]
; INDVARS: outer.latch:
; INDVARS-NEXT: [[OUTER_IV_NEXT]] = add nuw nsw i16 [[OUTER_IV]], 1
; INDVARS-NEXT: [[CMP_2:%.*]] = icmp eq i16 poison, [[OUTER_IV]]
; INDVARS-NEXT: br i1 [[CMP_2]], label [[OUTER_HEADER]], label [[EXIT:%.*]]
; INDVARS: exit:
; INDVARS-NEXT: ret void
; ;
entry: entry:
%a = alloca [10 x i64], align 1 %a = alloca [10 x i64], align 1
@ -79,3 +105,50 @@ exit:
} }
declare i16 @get() declare i16 @get()
define i32 @test_pr58489(i32 %a) {
; CHECK-LABEL: @test_pr58489(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[A:%.*]], -23
; CHECK-NEXT: call void @llvm.assume(i1 [[C_1]])
; CHECK-NEXT: switch i32 0, label [[ENTRY_SPLIT:%.*]] [
; CHECK-NEXT: i32 1, label [[EXIT:%.*]]
; CHECK-NEXT: ]
; CHECK: entry.split:
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
; CHECK: loop.header:
; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT]] ], [ [[SHIFT:%.*]], [[LOOP_HEADER]] ]
; CHECK-NEXT: [[C_2:%.*]] = icmp ne i32 [[P]], 0
; CHECK-NEXT: [[C_2_EXT:%.*]] = zext i1 [[C_2]] to i16
; CHECK-NEXT: call void @use(i16 [[C_2_EXT]])
; CHECK-NEXT: [[SHIFT]] = ashr exact i32 [[A]], 16
; CHECK-NEXT: br label [[LOOP_HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret i32 poison
;
entry:
%c.1 = icmp slt i32 %a, -23
call void @llvm.assume(i1 %c.1)
br label %loop.header
loop.header:
%p = phi i32 [ 0, %entry ], [ %shift, %loop.latch ]
br label %loop.latch
loop.latch:
%c.2 = icmp ne i32 %p, 0
%c.2.ext = zext i1 %c.2 to i16
call void @use(i16 %c.2.ext)
%shift = ashr exact i32 %a, 16
switch i32 50, label %exit [
i32 50, label %loop.header
]
exit:
%shift.lcssa = phi i32 [ %shift, %loop.latch ]
ret i32 %shift.lcssa
}
declare void @llvm.assume(i1 noundef) #0
declare void @use(i16)