PEI should be able to use backward walk in replaceFrameIndicesBackward.
The backward register scavenger has correct register liveness information. PEI should leverage the backward register scavenger. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D137574
This commit is contained in:
Alexander Timofeev
parent
244105f791
commit
32bd75716c
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@ -1028,6 +1028,12 @@ public:
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return false;
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}
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/// Process frame indices in reverse block order. This changes the behavior of
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/// the RegScavenger passed to eliminateFrameIndex. If this is true targets
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/// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
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/// should prefer reverse scavenging behavior.
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virtual bool supportsBackwardScavenger() const { return false; }
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/// This method must be overriden to eliminate abstract frame indices from
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/// instructions which may use them. The instruction referenced by the
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/// iterator contains an MO_FrameIndex operand which must be eliminated by
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@ -1035,7 +1041,9 @@ public:
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/// as long as it keeps the iterator pointing at the finished product.
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/// SPAdj is the SP adjustment due to call frame setup instruction.
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/// FIOperandNum is the FI operand number.
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virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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/// Returns true if the current instruction was removed and the iterator
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/// is not longer valid
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virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const = 0;
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@ -128,8 +128,16 @@ private:
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void replaceFrameIndices(MachineFunction &MF);
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void replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
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int &SPAdj);
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// Frame indices in debug values are encoded in a target independent
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// way with simply the frame index and offset rather than any
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// target-specific addressing mode.
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bool replaceFrameIndexDebugInstr(MachineFunction &MF, MachineInstr &MI,
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unsigned OpIdx, int SPAdj = 0);
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// Does same as replaceFrameIndices but using the backward MIR walk and
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// backward register scavenger walk. Does not yet support call sequence
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// processing.
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void replaceFrameIndicesBackward(MachineBasicBlock *BB, MachineFunction &MF,
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int &SPAdj);
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void insertPrologEpilogCode(MachineFunction &MF);
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void insertZeroCallUsedRegs(MachineFunction &MF);
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@ -1438,6 +1446,72 @@ bool PEI::replaceFrameIndexDebugInstr(MachineFunction &MF, MachineInstr &MI,
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return false;
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}
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void PEI::replaceFrameIndicesBackward(MachineBasicBlock *BB,
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MachineFunction &MF, int &SPAdj) {
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assert(MF.getSubtarget().getRegisterInfo() &&
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"getRegisterInfo() must be implemented!");
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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RS->enterBasicBlockEnd(*BB);
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for (MachineInstr &MI : make_early_inc_range(reverse(*BB))) {
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// Register scavenger backward step
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MachineBasicBlock::iterator Step(MI);
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for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
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if (!MI.getOperand(i).isFI())
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continue;
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if (replaceFrameIndexDebugInstr(MF, MI, i, SPAdj))
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continue;
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// If this instruction has a FrameIndex operand, we need to
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// use that target machine register info object to eliminate
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// it.
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// TRI.eliminateFrameIndex may lower the frame index to a sequence of
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// instructions. It also can remove/change instructions passed by the
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// iterator and invalidate the iterator. We have to take care of this. For
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// that we support two iterators: *Step* - points to the position up to
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// which the scavenger should scan by the next iteration to have liveness
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// information up to date. *Curr* - keeps track of the correct RS->MBBI -
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// the scan start point. It points to the currently processed instruction
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// right before the frame lowering.
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//
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// ITERATORS WORK AS FOLLOWS:
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// *Step* is shifted one step back right before the frame lowering and
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// one step forward right after it. No matter how many instructions were
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// inserted, *Step* will be right after the position which is going to be
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// processed in the next iteration, thus, in the correct position for the
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// scavenger to go up to.
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// *Curr* is shifted one step forward right before calling
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// TRI.eliminateFrameIndex and one step backward after. Thus, we make sure
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// it points right to the position that is the correct starting point for
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// the scavenger to scan.
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MachineBasicBlock::iterator Curr = ++RS->getCurrentPosition();
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// Shift back
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--Step;
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bool Removed = TRI.eliminateFrameIndex(MI, SPAdj, i, RS);
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// Restore to unify logic with a shift back that happens in the end of
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// the outer loop.
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++Step;
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RS->skipTo(--Curr);
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if (Removed)
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break;
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}
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// Shift it to make RS collect reg info up to the current instruction.
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if (Step != BB->begin())
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Step--;
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// Update register states.
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RS->backward(Step);
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}
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}
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void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
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int &SPAdj) {
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assert(MF.getSubtarget().getRegisterInfo() &&
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@ -1446,6 +1520,9 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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if (RS && TRI.supportsBackwardScavenger())
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return replaceFrameIndicesBackward(BB, MF, SPAdj);
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if (RS && FrameIndexEliminationScavenging)
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RS->enterBasicBlock(*BB);
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@ -1466,9 +1543,6 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
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if (!MI.getOperand(i).isFI())
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continue;
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// Frame indices in debug values are encoded in a target independent
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// way with simply the frame index and offset rather than any
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// target-specific addressing mode.
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if (replaceFrameIndexDebugInstr(MF, MI, i, SPAdj))
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continue;
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@ -817,7 +817,7 @@ void AArch64RegisterInfo::getOffsetOpcodes(
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}
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}
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void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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bool AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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@ -845,7 +845,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
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return;
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return false;
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}
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if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) {
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@ -854,7 +854,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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assert(!Offset.getScalable() &&
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"Frame offsets with a scalable component are not supported");
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FI.ChangeToImmediate(Offset.getFixed());
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return;
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return false;
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}
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StackOffset Offset;
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@ -884,7 +884,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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.addImm(0);
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MI.getOperand(FIOperandNum)
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.ChangeToRegister(ScratchReg, false, false, true);
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return;
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return false;
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}
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FrameReg = AArch64::SP;
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Offset = StackOffset::getFixed(MFI.getObjectOffset(FrameIndex) +
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@ -896,7 +896,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// Modify MI as necessary to handle as much of 'Offset' as possible
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if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
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return;
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return true;
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assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
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"Emergency spill slot is out of reach");
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@ -907,6 +907,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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Register ScratchReg =
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createScratchRegisterForInstruction(MI, FIOperandNum, TII);
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emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
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return false;
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}
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unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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@ -116,7 +116,7 @@ public:
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
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int64_t Offset) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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bool cannotEliminateFrame(const MachineFunction &MF) const;
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@ -103,7 +103,7 @@ bool R600RegisterInfo::isPhysRegLiveAcrossClauses(Register Reg) const {
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}
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}
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void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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bool R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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@ -47,7 +47,7 @@ struct R600RegisterInfo final : public R600GenRegisterInfo {
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// another.
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bool isPhysRegLiveAcrossClauses(Register Reg) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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@ -1364,7 +1364,7 @@ void SIRegisterInfo::buildSpillLoadStore(
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// TODO: Clobbering SCC is not necessary for scratch instructions in the
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// entry.
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if (RS) {
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SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);
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SOffset = RS->scavengeRegisterBackwards(AMDGPU::SGPR_32RegClass, MI, false, 0, false);
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// Piggy back on the liveness scan we just did see if SCC is dead.
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CanClobberSCC = !RS->isRegUsed(AMDGPU::SCC);
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@ -1385,7 +1385,7 @@ void SIRegisterInfo::buildSpillLoadStore(
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UseVGPROffset = true;
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if (RS) {
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TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
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TmpOffsetVGPR = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, false, 0);
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} else {
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assert(LiveRegs);
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for (MCRegister Reg : AMDGPU::VGPR_32RegClass) {
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@ -1961,7 +1961,7 @@ bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex(
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}
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}
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void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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MachineFunction *MF = MI->getParent()->getParent();
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@ -1992,8 +1992,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_S96_SAVE:
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S32_SAVE: {
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spillSGPR(MI, Index, RS);
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break;
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return spillSGPR(MI, Index, RS);
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}
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// SGPR register restore
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@ -2007,8 +2006,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_S96_RESTORE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_S32_RESTORE: {
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restoreSGPR(MI, Index, RS);
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break;
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return restoreSGPR(MI, Index, RS);
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}
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// VGPR register spill
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@ -2056,7 +2054,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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*MI->memoperands_begin(), RS);
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MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
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MI->eraseFromParent();
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break;
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return true;
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}
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case AMDGPU::SI_SPILL_V32_RESTORE:
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case AMDGPU::SI_SPILL_V64_RESTORE:
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@ -2101,7 +2099,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
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*MI->memoperands_begin(), RS);
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MI->eraseFromParent();
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break;
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return true;
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}
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default: {
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@ -2120,7 +2118,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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FIOp.ChangeToRegister(FrameReg, false);
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if (!Offset)
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return;
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return false;
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MachineOperand *OffsetOp =
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TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
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@ -2129,7 +2127,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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SIInstrFlags::FlatScratch)) {
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OffsetOp->setImm(NewOffset);
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if (FrameReg)
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return;
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return false;
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Offset = 0;
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}
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@ -2167,7 +2165,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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MI->tieOperands(NewVDst, NewVDstIn);
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}
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MI->setDesc(TII->get(NewOpc));
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return;
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return false;
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}
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}
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}
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@ -2175,7 +2173,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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if (!FrameReg) {
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FIOp.ChangeToImmediate(Offset);
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if (TII->isImmOperandLegal(*MI, FIOperandNum, FIOp))
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return;
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return false;
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}
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// We need to use register here. Check if we can use an SGPR or need
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@ -2185,7 +2183,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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if (!Offset && FrameReg && UseSGPR) {
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FIOp.setReg(FrameReg);
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return;
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return false;
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}
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const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass
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@ -2203,7 +2201,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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else
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MIB.addImm(Offset);
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return;
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return false;
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}
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Register TmpSReg =
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@ -2239,7 +2237,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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.addImm(-Offset);
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}
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return;
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return false;
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}
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bool IsMUBUF = TII->isMUBUF(*MI);
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@ -2248,7 +2246,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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// Convert to a swizzled stack address by scaling by the wave size.
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// In an entry function/kernel the offset is already swizzled.
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bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum));
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bool LiveSCC = RS->isRegUsed(AMDGPU::SCC);
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bool LiveSCC =
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RS->isRegUsed(AMDGPU::SCC) && !MI->definesRegister(AMDGPU::SCC);
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const TargetRegisterClass *RC = IsSALU && !LiveSCC
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? &AMDGPU::SReg_32RegClass
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: &AMDGPU::VGPR_32RegClass;
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@ -2352,11 +2351,12 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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}
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// Don't introduce an extra copy if we're just materializing in a mov.
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if (IsCopy)
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if (IsCopy) {
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MI->eraseFromParent();
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else
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FIOp.ChangeToRegister(ResultReg, false, false, true);
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return;
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return true;
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}
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FIOp.ChangeToRegister(ResultReg, false, false, true);
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return false;
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}
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if (IsMUBUF) {
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@ -2379,7 +2379,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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if (SIInstrInfo::isLegalMUBUFImmOffset(NewOffset) &&
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buildMUBUFOffsetLoadStore(ST, FrameInfo, MI, Index, NewOffset)) {
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MI->eraseFromParent();
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return;
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return true;
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}
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}
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@ -2395,6 +2395,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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}
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}
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}
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return false;
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}
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StringRef SIRegisterInfo::getRegAsmName(MCRegister Reg) const {
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@ -149,7 +149,11 @@ public:
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MachineBasicBlock &RestoreMBB, Register SGPR,
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RegScavenger *RS) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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bool supportsBackwardScavenger() const override {
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return true;
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}
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bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const override;
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@ -39,7 +39,7 @@ public:
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bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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@ -786,7 +786,7 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
|
|||
return false;
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -830,7 +830,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII, this);
|
||||
}
|
||||
if (Done)
|
||||
return;
|
||||
return false;
|
||||
|
||||
// If we get here, the immediate doesn't fit into the instruction. We folded
|
||||
// as much as possible above, handle the rest, providing a register that is
|
||||
|
|
@ -872,6 +872,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// Update the original instruction to use the scratch register.
|
||||
MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ public:
|
|||
|
||||
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -458,7 +458,7 @@ void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
|
|||
(void)Done;
|
||||
}
|
||||
|
||||
void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
MachineInstr &MI = *II;
|
||||
|
|
@ -498,14 +498,14 @@ void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
if (MI.isDebugValue()) {
|
||||
MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
|
||||
MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// Modify MI as necessary to handle as much of 'Offset' as possible
|
||||
assert(MF.getInfo<ARMFunctionInfo>()->isThumbFunction() &&
|
||||
"This eliminateFrameIndex only supports Thumb1!");
|
||||
if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
|
||||
return;
|
||||
return true;
|
||||
|
||||
// If we get here, the immediate doesn't fit into the instruction. We folded
|
||||
// as much as possible above, handle the rest, providing a register that is
|
||||
|
|
@ -596,6 +596,7 @@ void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// Add predicate back if it's needed.
|
||||
if (MI.isPredicable())
|
||||
MIB.add(predOps(ARMCC::AL));
|
||||
return false;
|
||||
}
|
||||
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ public:
|
|||
const ARMBaseInstrInfo &TII) const;
|
||||
void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
|
||||
int64_t Offset) const override;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset,
|
|||
MI.eraseFromParent();
|
||||
}
|
||||
|
||||
void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected SPAdj value");
|
||||
|
|
@ -214,7 +214,7 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
.addImm(Offset);
|
||||
New->getOperand(3).setIsDead();
|
||||
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// If the offset is too big we have to adjust and restore the frame pointer
|
||||
|
|
@ -261,6 +261,7 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
|
||||
assert(isUInt<6>(Offset) && "Offset is out of range");
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
return false;
|
||||
}
|
||||
|
||||
Register AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ public:
|
|||
const MachineFunction &MF) const override;
|
||||
|
||||
/// Stack Frame Processing Methods
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ static void WarnSize(int Offset, MachineFunction &MF, DebugLoc& DL)
|
|||
}
|
||||
}
|
||||
|
||||
void BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected");
|
||||
|
|
@ -90,7 +90,7 @@ void BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
|
||||
.addReg(reg)
|
||||
.addImm(Offset);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
|
||||
|
|
@ -119,6 +119,7 @@ void BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
||||
MI.getOperand(i + 1).ChangeToImmediate(Offset);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
Register BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ struct BPFRegisterInfo : public BPFGenRegisterInfo {
|
|||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ static bool IsLegalOffset(const CSKYInstrInfo *TII, MachineInstr *MI,
|
|||
return false;
|
||||
}
|
||||
|
||||
void CSKYRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool CSKYRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
|
||||
|
|
@ -287,4 +287,5 @@ void CSKYRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
.ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
|
||||
MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ public:
|
|||
|
||||
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -205,7 +205,7 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
|
|||
return Reserved;
|
||||
}
|
||||
|
||||
void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOp,
|
||||
RegScavenger *RS) const {
|
||||
static unsigned ReuseCount = 0;
|
||||
|
|
@ -234,7 +234,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.setDesc(HII.get(Hexagon::A2_addi));
|
||||
MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
|
||||
MI.removeOperand(FIOp+1);
|
||||
return;
|
||||
return false;
|
||||
case Hexagon::PS_fi:
|
||||
// Set up the instruction for updating below.
|
||||
MI.setDesc(HII.get(Hexagon::A2_addi));
|
||||
|
|
@ -346,6 +346,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
|
||||
MI.getOperand(FIOp).ChangeToRegister(BP, false, false, false);
|
||||
MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ public:
|
|||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
|
||||
|
||||
/// Returns true since we may need scavenging for a temporary register
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ static unsigned getRRMOpcodeVariant(unsigned Opcode) {
|
|||
}
|
||||
}
|
||||
|
||||
void LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected");
|
||||
|
|
@ -200,7 +200,7 @@ void LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
.addReg(Reg)
|
||||
.addImm(LPCC::ICC_T);
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
if (isSPLSOpcode(MI.getOpcode()) || isRMOpcode(MI.getOpcode())) {
|
||||
MI.setDesc(TII->get(getRRMOpcodeVariant(MI.getOpcode())));
|
||||
|
|
@ -218,7 +218,7 @@ void LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.getOperand(FIOperandNum + 1)
|
||||
.ChangeToRegister(Reg, /*isDef=*/false, /*isImp=*/false,
|
||||
/*isKill=*/true);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// ALU arithmetic ops take unsigned immediates. If the offset is negative,
|
||||
|
|
@ -239,6 +239,7 @@ void LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
|
|||
|
||||
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|||
return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
|
||||
}
|
||||
|
||||
void LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -155,7 +155,7 @@ void LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
.addReg(FrameReg)
|
||||
.addReg(ScratchReg, RegState::Kill);
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
BuildMI(MBB, II, DL, TII->get(Add), ScratchReg)
|
||||
.addReg(FrameReg)
|
||||
|
|
@ -175,7 +175,7 @@ void LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
.addReg(FrameReg)
|
||||
.addImm(Offset.getFixed());
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
|
||||
// Reload CFRs.
|
||||
|
|
@ -189,10 +189,11 @@ void LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
.add(MI.getOperand(0))
|
||||
.addReg(ScratchReg, RegState::Kill);
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
|
||||
MI.getOperand(FIOperandNum)
|
||||
.ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo {
|
|||
return &LoongArch::GPRRegClass;
|
||||
}
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ BitVector M68kRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
return Reserved;
|
||||
}
|
||||
|
||||
void M68kRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool M68kRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
MachineInstr &MI = *II;
|
||||
|
|
@ -208,6 +208,7 @@ void M68kRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
FIOffset += SPAdj;
|
||||
|
||||
Disp.ChangeToImmediate(FIOffset + Imm);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool M68kRegisterInfo::requiresRegisterScavenging(
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ public:
|
|||
|
||||
/// FrameIndex represent objects inside a abstract stack. We must replace
|
||||
/// FrameIndex with an stack/frame pointer direct reference.
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
|
|||
return &MSP430::GR16RegClass;
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -136,7 +136,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
||||
|
||||
if (Offset == 0)
|
||||
return;
|
||||
return false;
|
||||
|
||||
// We need to materialize the offset via add instruction.
|
||||
Register DstReg = MI.getOperand(0).getReg();
|
||||
|
|
@ -147,11 +147,12 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
|
||||
.addReg(DstReg).addImm(Offset);
|
||||
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
return false;
|
||||
}
|
||||
|
||||
Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ public:
|
|||
getPointerRegClass(const MachineFunction &MF,
|
||||
unsigned Kind = 0) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
|
|||
// FrameIndex represent objects inside a abstract stack.
|
||||
// We must replace FrameIndex with an stack/frame pointer
|
||||
// direct reference.
|
||||
void MipsRegisterInfo::
|
||||
bool MipsRegisterInfo::
|
||||
eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum, RegScavenger *RS) const {
|
||||
MachineInstr &MI = *II;
|
||||
|
|
@ -269,6 +269,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
|||
<< "\n");
|
||||
|
||||
eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
|
||||
return false;
|
||||
}
|
||||
|
||||
Register MipsRegisterInfo::
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ public:
|
|||
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
|
||||
|
||||
/// Stack Frame Processing Methods
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
return Reserved;
|
||||
}
|
||||
|
||||
void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected");
|
||||
|
|
@ -133,6 +133,7 @@ void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// Using I0 as the frame pointer
|
||||
MI.getOperand(FIOperandNum).ChangeToRegister(getFrameRegister(MF), false);
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
return false;
|
||||
}
|
||||
|
||||
Register NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ public:
|
|||
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -1485,7 +1485,7 @@ static unsigned getOffsetONFromFION(const MachineInstr &MI,
|
|||
return OffsetOperandNo;
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -1518,14 +1518,16 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
|
||||
if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
|
||||
lowerDynamicAreaOffset(II);
|
||||
return;
|
||||
// lowerDynamicAreaOffset erases II
|
||||
return true;
|
||||
}
|
||||
|
||||
// Special case for dynamic alloca.
|
||||
if (FPSI && FrameIndex == FPSI &&
|
||||
(OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
|
||||
lowerDynamicAlloc(II);
|
||||
return;
|
||||
// lowerDynamicAlloc erases II
|
||||
return true;
|
||||
}
|
||||
|
||||
if (FPSI && FrameIndex == FPSI &&
|
||||
|
|
@ -1534,37 +1536,38 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 ||
|
||||
OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) {
|
||||
lowerPrepareProbedAlloca(II);
|
||||
return;
|
||||
// lowerPrepareProbedAlloca erases II
|
||||
return true;
|
||||
}
|
||||
|
||||
// Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
|
||||
if (OpC == PPC::SPILL_CR) {
|
||||
lowerCRSpilling(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::RESTORE_CR) {
|
||||
lowerCRRestore(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::SPILL_CRBIT) {
|
||||
lowerCRBitSpilling(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::RESTORE_CRBIT) {
|
||||
lowerCRBitRestore(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) {
|
||||
lowerACCSpilling(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) {
|
||||
lowerACCRestore(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::STXVP && DisableAutoPairedVecSt) {
|
||||
lowerOctWordSpilling(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::SPILL_QUADWORD) {
|
||||
lowerQuadwordSpilling(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
} else if (OpC == PPC::RESTORE_QUADWORD) {
|
||||
lowerQuadwordRestore(II, FrameIndex);
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
|
||||
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
||||
|
|
@ -1621,7 +1624,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
OpC == TargetOpcode::STACKMAP ||
|
||||
OpC == TargetOpcode::PATCHPOINT)) {
|
||||
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// The offset doesn't fit into a single register, scavenge one to build the
|
||||
|
|
@ -1709,6 +1712,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
MI.getOperand(OperandBase + 1).ChangeToRegister(NewReg, false);
|
||||
MI.getOperand(OperandBase).ChangeToImmediate(0);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@ public:
|
|||
|
||||
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
|
||||
int &FrameIdx) const override;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|||
return true;
|
||||
}
|
||||
|
||||
void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
|
||||
|
|
@ -231,7 +231,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
assert(MI.getOperand(0).getReg() == ScratchReg &&
|
||||
"Expected to have written ADDI destination register");
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
|
||||
Offset = StackOffset::get(0, Offset.getScalable());
|
||||
|
|
@ -250,7 +250,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
assert(MI.getOperand(0).getReg() == DestReg &&
|
||||
"Expected to have written ADDI destination register");
|
||||
MI.eraseFromParent();
|
||||
return;
|
||||
return true;
|
||||
}
|
||||
FrameReg = DestReg;
|
||||
FrameRegIsKill = true;
|
||||
|
|
@ -293,6 +293,7 @@ void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// the length of vint32m2_t.
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToRegister(VL, /*isDef=*/false);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
|
|||
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
|
||||
int &FrameIdx) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -24,9 +24,11 @@ struct SPIRVRegisterInfo : public SPIRVGenRegisterInfo {
|
|||
SPIRVRegisterInfo();
|
||||
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override {}
|
||||
RegScavenger *RS = nullptr) const override {
|
||||
return false;
|
||||
}
|
||||
Register getFrameRegister(const MachineFunction &MF) const override {
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II,
|
|||
}
|
||||
|
||||
|
||||
void
|
||||
bool
|
||||
SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -209,7 +209,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
}
|
||||
|
||||
replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
|
||||
|
||||
// replaceFI never removes II
|
||||
return false;
|
||||
}
|
||||
|
||||
Register SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
|||
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
|
||||
unsigned Kind) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
return Reserved;
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -314,7 +314,7 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|||
MI->getDebugExpressionOp().setMetadata(
|
||||
DIExpression::appendOpsToArg(MI->getDebugExpression(), Ops, OpIdx));
|
||||
}
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// See if the offset is in range, or if an equivalent instruction that
|
||||
|
|
@ -374,6 +374,7 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|||
}
|
||||
MI->setDesc(TII->get(OpcodeForOffset));
|
||||
MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ public:
|
|||
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
|
||||
CallingConv::ID CC) const override;
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -477,7 +477,7 @@ void EliminateFrameIndex::processMI(MachineInstr &MI, Register FrameReg,
|
|||
replaceFI(MI, FrameReg, Offset, FIOperandNum);
|
||||
}
|
||||
|
||||
void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
assert(SPAdj == 0 && "Unexpected");
|
||||
|
|
@ -500,6 +500,7 @@ void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
Offset += MI.getOperand(FIOperandNum + offsetToDisp(MI)).getImm();
|
||||
|
||||
EFI.processMI(MI, FrameReg, Offset, FIOperandNum);
|
||||
return false;
|
||||
}
|
||||
|
||||
Register VERegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ public:
|
|||
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
|
||||
unsigned Kind) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
|
|||
return Reserved;
|
||||
}
|
||||
|
||||
void WebAssemblyRegisterInfo::eliminateFrameIndex(
|
||||
bool WebAssemblyRegisterInfo::eliminateFrameIndex(
|
||||
MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger * /*RS*/) const {
|
||||
assert(SPAdj == 0);
|
||||
|
|
@ -82,7 +82,7 @@ void WebAssemblyRegisterInfo::eliminateFrameIndex(
|
|||
MI.getOperand(OffsetOperandNum).setImm(Offset);
|
||||
MI.getOperand(FIOperandNum)
|
||||
.ChangeToRegister(FrameRegister, /*isDef=*/false);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -105,7 +105,7 @@ void WebAssemblyRegisterInfo::eliminateFrameIndex(
|
|||
ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset));
|
||||
MI.getOperand(FIOperandNum)
|
||||
.ChangeToRegister(FrameRegister, /*isDef=*/false);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -133,6 +133,7 @@ void WebAssemblyRegisterInfo::eliminateFrameIndex(
|
|||
.addReg(OffsetOp);
|
||||
}
|
||||
MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*isDef=*/false);
|
||||
return false;
|
||||
}
|
||||
|
||||
Register
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ public:
|
|||
// Code Generation virtual methods.
|
||||
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
||||
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -782,7 +782,7 @@ static bool isFuncletReturnInstr(MachineInstr &MI) {
|
|||
llvm_unreachable("impossible");
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -819,7 +819,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
if (Opc == TargetOpcode::LOCAL_ESCAPE) {
|
||||
MachineOperand &FI = MI.getOperand(FIOperandNum);
|
||||
FI.ChangeToImmediate(FIOffset);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
|
||||
|
|
@ -843,7 +843,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
assert(BasePtr == FramePtr && "Expected the FP as base register");
|
||||
int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
if (MI.getOperand(FIOperandNum+3).isImm()) {
|
||||
|
|
@ -860,6 +860,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
(uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
|
||||
MI.getOperand(FIOperandNum + 3).setOffset(Offset);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned X86RegisterInfo::findDeadCallerSavedReg(
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ public:
|
|||
|
||||
bool canRealignStack(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -250,7 +250,7 @@ XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
|
|||
return false;
|
||||
}
|
||||
|
||||
void
|
||||
bool
|
||||
XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -284,7 +284,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
if (MI.isDebugValue()) {
|
||||
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
|
||||
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
||||
return;
|
||||
return false;
|
||||
}
|
||||
|
||||
// fold constant into offset.
|
||||
|
|
@ -313,6 +313,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// Erase old instruction.
|
||||
MachineBasicBlock &MBB = *MI.getParent();
|
||||
MBB.erase(II);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ public:
|
|||
|
||||
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -155,52 +155,52 @@ define amdgpu_kernel void @kernel_caller_byval() {
|
|||
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
|
||||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; FLATSCR-NEXT: v_mov_b32_e32 v1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:8
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:72
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_lo offset:8
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:16
|
||||
; FLATSCR-NEXT: s_mov_b32 s11, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s10, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s9, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s8, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s7, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s6, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s5, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s0, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s4, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s3, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s2, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:80
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:24
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:88
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:32
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:96
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:40
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:104
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:48
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:112
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:56
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:120
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:64
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:128
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s33 offset:8
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s33 offset:16
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s33 offset:24
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[6:7], off, s33 offset:32
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s33 offset:40
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s33 offset:48
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[12:13], off, s33 offset:56
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s11 offset:24
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s10 offset:32
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s9 offset:40
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s8 offset:48
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s7 offset:56
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s6 offset:64
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s5 offset:72
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s1 offset:80
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 offset:88
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s4 offset:96
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s3 offset:104
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s2 offset:112
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_lo offset:120
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], vcc_hi offset:128
|
||||
; FLATSCR-NEXT: s_mov_b32 s40, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s40 offset:8
|
||||
; FLATSCR-NEXT: s_mov_b32 s39, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s39 offset:16
|
||||
; FLATSCR-NEXT: s_mov_b32 s38, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s38 offset:24
|
||||
; FLATSCR-NEXT: s_mov_b32 s37, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[6:7], off, s37 offset:32
|
||||
; FLATSCR-NEXT: s_mov_b32 s36, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s36 offset:40
|
||||
; FLATSCR-NEXT: s_mov_b32 s35, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s35 offset:48
|
||||
; FLATSCR-NEXT: s_mov_b32 s34, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[12:13], off, s34 offset:56
|
||||
; FLATSCR-NEXT: s_mov_b32 s33, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[14:15], off, s33 offset:64
|
||||
; FLATSCR-NEXT: s_movk_i32 s32, 0x50
|
||||
|
|
|
|||
|
|
@ -308,10 +308,10 @@ define i16 @v_extract_v128i16_varidx(<128 x i16> addrspace(1)* %ptr, i32 %idx) {
|
|||
; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
|
||||
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
|
||||
; GCN-NEXT: v_bfe_u32 v0, v6, 1, 6
|
||||
; GCN-NEXT: v_lshrrev_b32_e64 v5, 6, s33
|
||||
; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GCN-NEXT: v_add_u32_e32 v5, 0x100, v5
|
||||
; GCN-NEXT: v_add_u32_e32 v0, v5, v0
|
||||
; GCN-NEXT: v_add_u32_e32 v2, 0x100, v2
|
||||
; GCN-NEXT: v_add_u32_e32 v0, v2, v0
|
||||
; GCN-NEXT: v_and_b32_e32 v1, 1, v6
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v1
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
|
|
@ -487,10 +487,10 @@ define i64 @v_extract_v32i64_varidx(<32 x i64> addrspace(1)* %ptr, i32 %idx) {
|
|||
; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
|
||||
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
|
||||
; GCN-NEXT: v_and_b32_e32 v0, 31, v6
|
||||
; GCN-NEXT: v_lshrrev_b32_e64 v5, 6, s33
|
||||
; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
||||
; GCN-NEXT: v_add_u32_e32 v5, 0x100, v5
|
||||
; GCN-NEXT: v_add_u32_e32 v1, v5, v0
|
||||
; GCN-NEXT: v_add_u32_e32 v2, 0x100, v2
|
||||
; GCN-NEXT: v_add_u32_e32 v1, v2, v0
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: v_mov_b32_e32 v16, v20
|
||||
; GCN-NEXT: v_mov_b32_e32 v17, v21
|
||||
|
|
|
|||
|
|
@ -458,9 +458,9 @@ define void @store_load_vindex_small_offset_foo(i32 %idx) {
|
|||
; GFX9-NEXT: scratch_load_dword v1, off, s32 glc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x100
|
||||
; GFX9-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX9-NEXT: v_add_u32_e32 v1, vcc_hi, v1
|
||||
; GFX9-NEXT: v_add_u32_e32 v1, vcc_lo, v1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x100
|
||||
|
|
@ -477,13 +477,13 @@ define void @store_load_vindex_small_offset_foo(i32 %idx) {
|
|||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
|
||||
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX10-NEXT: s_add_i32 s0, s32, 0x100
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
|
||||
; GFX10-NEXT: scratch_load_dword v3, off, s32 glc dlc
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX10-NEXT: v_add_nc_u32_e32 v0, vcc_lo, v0
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX10-NEXT: v_add_nc_u32_e32 v1, vcc_lo, v1
|
||||
; GFX10-NEXT: scratch_store_dword v0, v2, off
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
|
|
@ -585,16 +585,16 @@ define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
|
|||
; GFX940-NEXT: scratch_load_dword v0, off, off offset:4 sc0 sc1
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, 15
|
||||
; GFX940-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX940-NEXT: s_lshl_b32 s1, s0, 2
|
||||
; GFX940-NEXT: s_and_b32 s0, s0, 15
|
||||
; GFX940-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX940-NEXT: s_lshl_b32 s0, s0, 2
|
||||
; GFX940-NEXT: scratch_store_dword v1, v0, vcc_hi sc0 sc1
|
||||
; GFX940-NEXT: scratch_store_dword v1, v0, vcc_lo sc0 sc1
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: scratch_load_dword v0, v0, vcc_hi sc0 sc1
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: s_endpgm
|
||||
|
|
@ -613,9 +613,9 @@ define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
|
|||
; GFX11-NEXT: s_lshl_b32 s0, s0, 2
|
||||
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-NEXT: v_mov_b32_e32 v2, s0
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v1, vcc_lo dlc
|
||||
; GFX11-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v1, s0 dlc
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-NEXT: scratch_load_b32 v0, v2, vcc_lo glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: s_endpgm
|
||||
|
|
@ -681,9 +681,9 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
|
|||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_lshlrev_b32_e32 v1, 2, v0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX940-NEXT: v_sub_u32_e32 v0, 0, v0
|
||||
; GFX940-NEXT: scratch_store_dword v1, v2, vcc_hi sc0 sc1
|
||||
; GFX940-NEXT: scratch_store_dword v1, v2, vcc_lo sc0 sc1
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
|
|
@ -696,13 +696,13 @@ define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
|
|||
; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0, v0
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX11-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX11-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-NEXT: scratch_load_b32 v3, off, off offset:4 glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v2, s0 dlc
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-NEXT: scratch_load_b32 v0, v1, vcc_lo offset:124 glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: s_endpgm
|
||||
|
|
@ -731,9 +731,9 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX9-NEXT: scratch_load_dword v1, off, s32 offset:4 glc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX9-NEXT: v_add_u32_e32 v1, vcc_hi, v1
|
||||
; GFX9-NEXT: v_add_u32_e32 v1, vcc_lo, v1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
|
|
@ -750,13 +750,13 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
|
||||
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX10-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
|
||||
; GFX10-NEXT: scratch_load_dword v3, off, s32 offset:4 glc dlc
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX10-NEXT: v_add_nc_u32_e32 v0, vcc_lo, v0
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: v_add_nc_u32_e32 v1, vcc_lo, v1
|
||||
; GFX10-NEXT: scratch_store_dword v0, v2, off
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
|
|
@ -771,9 +771,9 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_lshlrev_b32_e32 v1, 2, v0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX940-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX940-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX940-NEXT: scratch_store_dword v1, v2, vcc_hi sc0 sc1
|
||||
; GFX940-NEXT: scratch_store_dword v1, v2, vcc_lo sc0 sc1
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
|
|
@ -787,13 +787,14 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_and_b32 v1, 15, v0
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX11-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-NEXT: scratch_load_b32 v3, off, s32 offset:4 glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v2, s0 dlc
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: scratch_load_b32 v0, v1, vcc_lo glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ body: |
|
|||
; GFX908-NEXT: S_NOP 0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-LABEL: name: agpr32_restore_clobber_scc
|
||||
; GFX90A: bb.0:
|
||||
|
|
@ -280,7 +282,7 @@ body: |
|
|||
; GFX90A-NEXT: S_NOP 0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -527,6 +529,8 @@ body: |
|
|||
; GFX908-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: bb.2:
|
||||
; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-FLATSCR-LABEL: name: agpr32_restore_clobber_scc
|
||||
; GFX90A-FLATSCR: bb.0:
|
||||
|
|
@ -772,7 +776,7 @@ body: |
|
|||
; GFX90A-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: bb.2:
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -1010,6 +1014,7 @@ body: |
|
|||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
|
||||
|
|
@ -1048,6 +1053,8 @@ body: |
|
|||
; GFX908-NEXT: S_NOP 0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-LABEL: name: agpr64_restore_clobber_scc
|
||||
; GFX90A: bb.0:
|
||||
|
|
@ -1293,7 +1300,7 @@ body: |
|
|||
; GFX90A-NEXT: S_NOP 0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -1542,6 +1549,8 @@ body: |
|
|||
; GFX908-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: bb.2:
|
||||
; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-FLATSCR-LABEL: name: agpr64_restore_clobber_scc
|
||||
; GFX90A-FLATSCR: bb.0:
|
||||
|
|
@ -1787,7 +1796,7 @@ body: |
|
|||
; GFX90A-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: bb.2:
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -2025,6 +2034,7 @@ body: |
|
|||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
|
||||
|
|
@ -2065,6 +2075,8 @@ body: |
|
|||
; GFX908-NEXT: S_NOP 0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-LABEL: name: agpr96_restore_clobber_scc
|
||||
; GFX90A: bb.0:
|
||||
|
|
@ -2311,7 +2323,7 @@ body: |
|
|||
; GFX90A-NEXT: S_NOP 0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -2562,6 +2574,8 @@ body: |
|
|||
; GFX908-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: bb.2:
|
||||
; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-FLATSCR-LABEL: name: agpr96_restore_clobber_scc
|
||||
; GFX90A-FLATSCR: bb.0:
|
||||
|
|
@ -2807,7 +2821,7 @@ body: |
|
|||
; GFX90A-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: bb.2:
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -3045,6 +3059,7 @@ body: |
|
|||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
|
||||
|
|
@ -3081,6 +3096,8 @@ body: |
|
|||
; GFX908-NEXT: S_NOP 0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-LABEL: name: agpr32_save_clobber_scc
|
||||
; GFX90A: bb.0:
|
||||
|
|
@ -3325,7 +3342,7 @@ body: |
|
|||
; GFX90A-NEXT: S_NOP 0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-NEXT: liveins: $agpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -3572,6 +3589,8 @@ body: |
|
|||
; GFX908-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: bb.2:
|
||||
; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-FLATSCR-LABEL: name: agpr32_save_clobber_scc
|
||||
; GFX90A-FLATSCR: bb.0:
|
||||
|
|
@ -3817,7 +3836,7 @@ body: |
|
|||
; GFX90A-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: bb.2:
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $agpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -4055,6 +4074,7 @@ body: |
|
|||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
|
||||
|
|
@ -4092,6 +4112,8 @@ body: |
|
|||
; GFX908-NEXT: S_NOP 0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-LABEL: name: agpr64_save_clobber_scc
|
||||
; GFX90A: bb.0:
|
||||
|
|
@ -4337,7 +4359,7 @@ body: |
|
|||
; GFX90A-NEXT: S_NOP 0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -4586,6 +4608,8 @@ body: |
|
|||
; GFX908-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: bb.2:
|
||||
; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-FLATSCR-LABEL: name: agpr64_save_clobber_scc
|
||||
; GFX90A-FLATSCR: bb.0:
|
||||
|
|
@ -4831,7 +4855,7 @@ body: |
|
|||
; GFX90A-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: bb.2:
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -5069,6 +5093,7 @@ body: |
|
|||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
---
|
||||
|
|
@ -5107,6 +5132,8 @@ body: |
|
|||
; GFX908-NEXT: S_NOP 0
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-LABEL: name: agpr96_save_clobber_scc
|
||||
; GFX90A: bb.0:
|
||||
|
|
@ -5353,7 +5380,7 @@ body: |
|
|||
; GFX90A-NEXT: S_NOP 0
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -5604,6 +5631,8 @@ body: |
|
|||
; GFX908-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: bb.2:
|
||||
; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
|
||||
; GFX908-FLATSCR-NEXT: {{ $}}
|
||||
; GFX908-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX90A-FLATSCR-LABEL: name: agpr96_save_clobber_scc
|
||||
; GFX90A-FLATSCR: bb.0:
|
||||
|
|
@ -5849,7 +5878,7 @@ body: |
|
|||
; GFX90A-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: bb.2:
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55
|
||||
; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
|
||||
; GFX90A-FLATSCR-NEXT: {{ $}}
|
||||
; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5)
|
||||
; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5)
|
||||
|
|
@ -6087,5 +6116,6 @@ body: |
|
|||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
|
|
|
|||
|
|
@ -495,25 +495,25 @@ define amdgpu_kernel void @vload2_private(i16 addrspace(1)* nocapture readonly %
|
|||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
|
||||
; FLATSCR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0
|
||||
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s5, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s4, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1]
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:4
|
||||
; FLATSCR-NEXT: scratch_store_short off, v0, s5 offset:4
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:2
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:6
|
||||
; FLATSCR-NEXT: scratch_store_short off, v0, s4 offset:6
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:4
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 s0, 0
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:8
|
||||
; FLATSCR-NEXT: scratch_store_short off, v0, s0 offset:8
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:4
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_lo offset:4
|
||||
; FLATSCR-NEXT: scratch_load_dword v1, off, vcc_hi offset:6
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
|
||||
|
|
@ -558,29 +558,27 @@ define amdgpu_kernel void @vload2_private(i16 addrspace(1)* nocapture readonly %
|
|||
; FLATSCR_GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
|
||||
; FLATSCR_GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0
|
||||
; FLATSCR_GFX10-NEXT: v_mov_b32_e32 v2, 0
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 s5, 0
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 s4, 0
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; FLATSCR_GFX10-NEXT: global_load_ushort v0, v2, s[0:1]
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, vcc_lo offset:4
|
||||
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, s5 offset:4
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; FLATSCR_GFX10-NEXT: global_load_ushort v0, v2, s[0:1] offset:2
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, vcc_lo offset:6
|
||||
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, s4 offset:6
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; FLATSCR_GFX10-NEXT: global_load_ushort v0, v2, s[0:1] offset:4
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 s1, 0
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 s0, 0
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, vcc_lo offset:8
|
||||
; FLATSCR_GFX10-NEXT: scratch_store_short off, v0, s1 offset:8
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR_GFX10-NEXT: scratch_load_dword v0, off, vcc_lo offset:4
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLATSCR_GFX10-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR_GFX10-NEXT: s_clause 0x1
|
||||
; FLATSCR_GFX10-NEXT: scratch_load_dword v0, off, s0 offset:4
|
||||
; FLATSCR_GFX10-NEXT: scratch_load_dword v1, off, vcc_lo offset:6
|
||||
; FLATSCR_GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR_GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
|
||||
|
|
|
|||
|
|
@ -121,16 +121,16 @@ define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 %in) {
|
|||
; FLAT_SCR_OPT-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s104, exec_lo
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 exec_lo, 3
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s105, 0
|
||||
; FLAT_SCR_OPT-NEXT: scratch_store_dword off, v72, s105
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s4, 0
|
||||
; FLAT_SCR_OPT-NEXT: scratch_store_dword off, v72, s4
|
||||
; FLAT_SCR_OPT-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; FLAT_SCR_OPT-NEXT: v_writelane_b32 v72, s2, 0
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s105, 4
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s4, 4
|
||||
; FLAT_SCR_OPT-NEXT: v_writelane_b32 v72, s3, 1
|
||||
; FLAT_SCR_OPT-NEXT: scratch_store_dword off, v72, s105 ; 4-byte Folded Spill
|
||||
; FLAT_SCR_OPT-NEXT: scratch_store_dword off, v72, s4 ; 4-byte Folded Spill
|
||||
; FLAT_SCR_OPT-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s105, 0
|
||||
; FLAT_SCR_OPT-NEXT: scratch_load_dword v72, off, s105
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 s4, 0
|
||||
; FLAT_SCR_OPT-NEXT: scratch_load_dword v72, off, s4
|
||||
; FLAT_SCR_OPT-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLAT_SCR_OPT-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLAT_SCR_OPT-NEXT: s_mov_b32 exec_lo, s104
|
||||
|
|
@ -255,16 +255,16 @@ define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 %in) {
|
|||
; FLAT_SCR_ARCH-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s104, exec_lo
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 exec_lo, 3
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s105, 0
|
||||
; FLAT_SCR_ARCH-NEXT: scratch_store_dword off, v72, s105
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s4, 0
|
||||
; FLAT_SCR_ARCH-NEXT: scratch_store_dword off, v72, s4
|
||||
; FLAT_SCR_ARCH-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; FLAT_SCR_ARCH-NEXT: v_writelane_b32 v72, s2, 0
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s105, 4
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s4, 4
|
||||
; FLAT_SCR_ARCH-NEXT: v_writelane_b32 v72, s3, 1
|
||||
; FLAT_SCR_ARCH-NEXT: scratch_store_dword off, v72, s105 ; 4-byte Folded Spill
|
||||
; FLAT_SCR_ARCH-NEXT: scratch_store_dword off, v72, s4 ; 4-byte Folded Spill
|
||||
; FLAT_SCR_ARCH-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s105, 0
|
||||
; FLAT_SCR_ARCH-NEXT: scratch_load_dword v72, off, s105
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 s4, 0
|
||||
; FLAT_SCR_ARCH-NEXT: scratch_load_dword v72, off, s4
|
||||
; FLAT_SCR_ARCH-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLAT_SCR_ARCH-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; FLAT_SCR_ARCH-NEXT: s_mov_b32 exec_lo, s104
|
||||
|
|
|
|||
|
|
@ -21,13 +21,13 @@ define amdgpu_kernel void @zero_init_kernel() {
|
|||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: s_mov_b32 s1, 0
|
||||
; GFX9-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:52
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:36
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:20
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:52
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:36
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:20
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:4
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -74,6 +74,7 @@ define amdgpu_kernel void @zero_init_kernel() {
|
|||
; GFX9-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
|
||||
|
|
@ -86,12 +87,11 @@ define amdgpu_kernel void @zero_init_kernel() {
|
|||
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:52
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:36
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:20
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s1, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:52
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:36
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:20
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:4
|
||||
; GFX9-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -129,15 +129,12 @@ define amdgpu_kernel void @zero_init_kernel() {
|
|||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:52
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:36
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:20
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s2, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s1, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s2 offset:52
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:36
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:20
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:4
|
||||
; GFX1010-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -971,8 +968,8 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
|
|||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
|
||||
; GFX9-NEXT: s_mov_b32 s4, 0
|
||||
; GFX9-NEXT: scratch_load_dword v0, off, s4 offset:4 glc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-NEXT: s_mov_b32 s1, s0
|
||||
|
|
@ -982,13 +979,13 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
|
|||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: s_mov_b32 s1, 0
|
||||
; GFX9-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:260
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:276
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:292
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:260
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:276
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:292
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:308
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -1038,13 +1035,15 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
|
|||
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s4, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
|
||||
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
|
||||
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
|
||||
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
|
||||
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s4 offset:4 glc
|
||||
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s2, s0
|
||||
|
|
@ -1053,13 +1052,11 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
|
|||
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:260
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:276
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:292
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s1, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:260
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:276
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:292
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:308
|
||||
; GFX9-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -1090,9 +1087,9 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
|
|||
; GFX1010-PAL-NEXT: s_addc_u32 s3, s3, 0
|
||||
; GFX1010-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
|
||||
; GFX1010-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s4, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX1010-PAL-NEXT: scratch_load_dword v0, off, vcc_lo offset:4 glc dlc
|
||||
; GFX1010-PAL-NEXT: scratch_load_dword v0, off, s4 offset:4 glc dlc
|
||||
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s2, s0
|
||||
|
|
@ -1101,16 +1098,13 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
|
|||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s2, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s1, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:260
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:276
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:292
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s2 offset:260
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:276
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:292
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:308
|
||||
; GFX1010-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -1888,13 +1882,13 @@ define void @store_load_vindex_small_offset_foo(i32 %idx) {
|
|||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
|
||||
; GFX10-NEXT: s_add_i32 s0, s32, 0x100
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, vcc_lo
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX10-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-NEXT: scratch_load_dword v3, off, s32 glc dlc
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-NEXT: scratch_store_dword v0, v2, off
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
|
||||
|
|
@ -1953,13 +1947,13 @@ define void @store_load_vindex_small_offset_foo(i32 %idx) {
|
|||
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-PAL-NEXT: v_and_b32_e32 v1, 15, v0
|
||||
; GFX10-PAL-NEXT: s_add_i32 s0, s32, 0x100
|
||||
; GFX10-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, s0
|
||||
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, vcc_lo
|
||||
; GFX10-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x100
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-PAL-NEXT: scratch_load_dword v3, off, s32 glc dlc
|
||||
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-PAL-NEXT: scratch_store_dword v0, v2, off
|
||||
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
|
||||
|
|
@ -2015,8 +2009,8 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
|
||||
; GFX9-NEXT: s_mov_b32 s4, 0
|
||||
; GFX9-NEXT: scratch_load_dword v0, off, s4 offset:4 glc
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-NEXT: s_mov_b32 s1, s0
|
||||
|
|
@ -2026,13 +2020,13 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX9-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX9-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
|
||||
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
|
||||
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
|
||||
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s1
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -2053,12 +2047,12 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX10-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
|
||||
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
|
||||
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX10-NEXT: s_movk_i32 s2, 0x4004
|
||||
; GFX10-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX10-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s2
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:32
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX10-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -2073,12 +2067,13 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX11-NEXT: s_mov_b32 s3, s0
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
||||
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
|
||||
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
|
||||
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
|
||||
; GFX11-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-NEXT: s_movk_i32 s2, 0x4004
|
||||
; GFX11-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX11-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX11-NEXT: s_clause 0x3
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s2
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s1 offset:16
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s0 offset:32
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
|
||||
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
||||
; GFX11-NEXT: s_endpgm
|
||||
|
|
@ -2088,13 +2083,15 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s4, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX9-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
|
||||
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
|
||||
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
|
||||
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
|
||||
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s4 offset:4 glc
|
||||
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 s2, s0
|
||||
|
|
@ -2103,13 +2100,11 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
|
||||
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
|
||||
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
|
||||
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX9-PAL-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX9-PAL-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
|
||||
; GFX9-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -2123,13 +2118,13 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX940-NEXT: s_mov_b32 s3, s0
|
||||
; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX940-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX940-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX940-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
|
||||
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s1
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
|
||||
; GFX940-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -2144,9 +2139,9 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX1010-PAL-NEXT: s_addc_u32 s3, s3, 0
|
||||
; GFX1010-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
|
||||
; GFX1010-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s4, 0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX1010-PAL-NEXT: scratch_load_dword v0, off, vcc_lo offset:4 glc dlc
|
||||
; GFX1010-PAL-NEXT: scratch_load_dword v0, off, s4 offset:4 glc dlc
|
||||
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s2, s0
|
||||
|
|
@ -2155,16 +2150,13 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 s2, 0x4004
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s2
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:32
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX1010-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -2190,12 +2182,12 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
|
||||
; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
|
||||
; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX1030-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX1030-PAL-NEXT: s_movk_i32 s2, 0x4004
|
||||
; GFX1030-PAL-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX1030-PAL-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s2
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:32
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX1030-PAL-NEXT: s_endpgm
|
||||
;
|
||||
|
|
@ -2210,12 +2202,13 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
|
|||
; GFX11-PAL-NEXT: s_mov_b32 s3, s0
|
||||
; GFX11-PAL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
||||
; GFX11-PAL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
|
||||
; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
|
||||
; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
|
||||
; GFX11-PAL-NEXT: s_movk_i32 vcc_lo, 0x4004
|
||||
; GFX11-PAL-NEXT: s_movk_i32 s2, 0x4004
|
||||
; GFX11-PAL-NEXT: s_movk_i32 s1, 0x4004
|
||||
; GFX11-PAL-NEXT: s_movk_i32 s0, 0x4004
|
||||
; GFX11-PAL-NEXT: s_clause 0x3
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s2
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s1 offset:16
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s0 offset:32
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
|
||||
; GFX11-PAL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
||||
; GFX11-PAL-NEXT: s_endpgm
|
||||
|
|
@ -2242,13 +2235,13 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX9-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX9-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
|
||||
; GFX9-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s1
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -2260,7 +2253,6 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX10-NEXT: scratch_load_dword v0, off, s32 offset:4 glc dlc
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: s_mov_b32 s0, 0
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: s_mov_b32 s1, s0
|
||||
; GFX10-NEXT: s_mov_b32 s2, s0
|
||||
; GFX10-NEXT: s_mov_b32 s3, s0
|
||||
|
|
@ -2268,12 +2260,13 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX10-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX10-NEXT: s_add_i32 s2, s32, 0x4004
|
||||
; GFX10-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX10-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s2
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:32
|
||||
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -2285,18 +2278,20 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX11-NEXT: scratch_load_b32 v0, off, s32 offset:4 glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: s_mov_b32 s0, 0
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-NEXT: s_mov_b32 s1, s0
|
||||
; GFX11-NEXT: s_mov_b32 s2, s0
|
||||
; GFX11-NEXT: s_mov_b32 s3, s0
|
||||
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
||||
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
|
||||
; GFX11-NEXT: s_add_i32 s2, s32, 0x4004
|
||||
; GFX11-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX11-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: s_clause 0x3
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s2
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s1 offset:16
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s0 offset:32
|
||||
; GFX11-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -2314,13 +2309,13 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX9-PAL-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
|
||||
; GFX9-PAL-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
|
||||
; GFX9-PAL-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
|
||||
; GFX9-PAL-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
|
||||
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -2336,69 +2331,41 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX940-NEXT: s_mov_b32 s3, s0
|
||||
; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
||||
; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
|
||||
; GFX940-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX940-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX940-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s1
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX1010-PAL-LABEL: zero_init_large_offset_foo:
|
||||
; GFX1010-PAL: ; %bb.0:
|
||||
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX1010-PAL-NEXT: scratch_load_dword v0, off, s32 offset:4 glc dlc
|
||||
; GFX1010-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX1010-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX1010-PAL-NEXT: s_mov_b32 s3, s0
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX1010-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX1010-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1010-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX1010-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX1010-PAL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX1030-PAL-LABEL: zero_init_large_offset_foo:
|
||||
; GFX1030-PAL: ; %bb.0:
|
||||
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX1030-PAL-NEXT: scratch_load_dword v0, off, s32 offset:4 glc dlc
|
||||
; GFX1030-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX1030-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX1030-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1030-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX1030-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX1030-PAL-NEXT: s_mov_b32 s3, s0
|
||||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX1030-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
|
||||
; GFX1030-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
|
||||
; GFX1030-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
|
||||
; GFX1030-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX1030-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX1030-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX1030-PAL-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX10-PAL-LABEL: zero_init_large_offset_foo:
|
||||
; GFX10-PAL: ; %bb.0:
|
||||
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s32 offset:4 glc dlc
|
||||
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX10-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX10-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX10-PAL-NEXT: s_mov_b32 s3, s0
|
||||
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1
|
||||
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2
|
||||
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3
|
||||
; GFX10-PAL-NEXT: s_add_i32 s2, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s2
|
||||
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16
|
||||
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:32
|
||||
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
|
||||
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX11-PAL-LABEL: zero_init_large_offset_foo:
|
||||
; GFX11-PAL: ; %bb.0:
|
||||
|
|
@ -2407,18 +2374,20 @@ define void @zero_init_large_offset_foo() {
|
|||
; GFX11-PAL-NEXT: scratch_load_b32 v0, off, s32 offset:4 glc dlc
|
||||
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-PAL-NEXT: s_mov_b32 s0, 0
|
||||
; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
||||
; GFX11-PAL-NEXT: s_mov_b32 s1, s0
|
||||
; GFX11-PAL-NEXT: s_mov_b32 s2, s0
|
||||
; GFX11-PAL-NEXT: s_mov_b32 s3, s0
|
||||
; GFX11-PAL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
||||
; GFX11-PAL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo
|
||||
; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:16
|
||||
; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:32
|
||||
; GFX11-PAL-NEXT: s_add_i32 s2, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_add_i32 s1, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_clause 0x3
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s2
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s1 offset:16
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], s0 offset:32
|
||||
; GFX11-PAL-NEXT: scratch_store_b128 off, v[0:3], vcc_lo offset:48
|
||||
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -2986,13 +2955,13 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
|
||||
; GFX10-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, s0
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, vcc_lo
|
||||
; GFX10-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-NEXT: scratch_load_dword v3, off, s32 offset:4 glc dlc
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-NEXT: scratch_store_dword v0, v2, off
|
||||
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
|
||||
|
|
@ -3005,13 +2974,14 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_and_b32 v1, 15, v0
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX11-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-NEXT: scratch_load_b32 v3, off, s32 offset:4 glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
|
||||
; GFX11-NEXT: scratch_store_b32 v0, v2, s0 dlc
|
||||
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-NEXT: scratch_load_b32 v0, v1, vcc_lo glc dlc
|
||||
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -3040,9 +3010,9 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_lshlrev_b32_e32 v1, 2, v0
|
||||
; GFX940-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
; GFX940-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX940-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX940-NEXT: scratch_store_dword v1, v2, vcc_hi sc0 sc1
|
||||
; GFX940-NEXT: scratch_store_dword v1, v2, vcc_lo sc0 sc1
|
||||
; GFX940-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX940-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
|
||||
|
|
@ -3055,13 +3025,13 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-PAL-NEXT: v_and_b32_e32 v1, 15, v0
|
||||
; GFX10-PAL-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, s0
|
||||
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 15
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, vcc_lo
|
||||
; GFX10-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-PAL-NEXT: scratch_load_dword v3, off, s32 offset:4 glc dlc
|
||||
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-PAL-NEXT: v_lshl_add_u32 v1, v1, 2, vcc_lo
|
||||
; GFX10-PAL-NEXT: scratch_store_dword v0, v2, off
|
||||
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX10-PAL-NEXT: scratch_load_dword v0, v1, off glc dlc
|
||||
|
|
@ -3074,13 +3044,14 @@ define void @store_load_vindex_large_offset_foo(i32 %idx) {
|
|||
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-PAL-NEXT: v_dual_mov_b32 v2, 15 :: v_dual_and_b32 v1, 15, v0
|
||||
; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GFX11-PAL-NEXT: s_add_i32 s0, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
||||
; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-PAL-NEXT: scratch_load_b32 v3, off, s32 offset:4 glc dlc
|
||||
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-PAL-NEXT: v_lshlrev_b32_e32 v1, 2, v1
|
||||
; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, vcc_lo dlc
|
||||
; GFX11-PAL-NEXT: scratch_store_b32 v0, v2, s0 dlc
|
||||
; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0
|
||||
; GFX11-PAL-NEXT: s_add_i32 vcc_lo, s32, 0x4004
|
||||
; GFX11-PAL-NEXT: scratch_load_b32 v0, v1, vcc_lo glc dlc
|
||||
; GFX11-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX11-PAL-NEXT: s_setpc_b64 s[30:31]
|
||||
|
|
@ -4138,8 +4109,8 @@ define amdgpu_ps void @large_offset() {
|
|||
; GFX9-NEXT: v_mov_b32_e32 v1, v0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, v0
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, v0
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:3024
|
||||
; GFX9-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:3024
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-NEXT: scratch_load_dwordx4 v[0:3], off, vcc_hi offset:3024 glc
|
||||
|
|
@ -4213,8 +4184,8 @@ define amdgpu_ps void @large_offset() {
|
|||
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
|
||||
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s0
|
||||
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:3024
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:3024
|
||||
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; GFX9-PAL-NEXT: scratch_load_dwordx4 v[0:3], off, vcc_hi offset:3024 glc
|
||||
|
|
|
|||
|
|
@ -89,8 +89,8 @@ body: |
|
|||
; GCN-LABEL: name: func_add_constant_to_fi_uniform_SCC_clobber_i32
|
||||
; GCN: liveins: $sgpr30_sgpr31
|
||||
; GCN-NEXT: {{ $}}
|
||||
; GCN-NEXT: $vcc_hi = S_LSHR_B32 6, $sgpr32, implicit-def dead $scc
|
||||
; GCN-NEXT: renamable $sgpr4 = nuw S_ADD_U32 killed $vcc_hi, 4, implicit-def $scc
|
||||
; GCN-NEXT: $vcc_lo = S_LSHR_B32 6, $sgpr32, implicit-def dead $scc
|
||||
; GCN-NEXT: renamable $sgpr4 = nuw S_ADD_U32 killed $vcc_lo, 4, implicit-def $scc
|
||||
; GCN-NEXT: renamable $sgpr5 = S_ADDC_U32 $sgpr4, 1234567, implicit-def $scc, implicit $scc
|
||||
; GCN-NEXT: $vcc_hi = S_LSHR_B32 $sgpr32, 6, implicit-def $scc
|
||||
; GCN-NEXT: $vcc_hi = S_ADD_I32 killed $vcc_hi, 8, implicit-def $scc
|
||||
|
|
@ -184,3 +184,30 @@ body: |
|
|||
S_SETPC_B64_return killed renamable $sgpr30_sgpr31
|
||||
|
||||
...
|
||||
---
|
||||
name: func_frame_idx_at_the_end_of_bb
|
||||
tracksRegLiveness: true
|
||||
stack:
|
||||
- { id: 0, type: default, offset: 0, size: 8, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
local-offset: 0, debug-info-variable: '', debug-info-expression: '',
|
||||
debug-info-location: '' }
|
||||
machineFunctionInfo:
|
||||
stackPtrOffsetReg: '$sgpr32'
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr31
|
||||
|
||||
; GCN-LABEL: name: func_frame_idx_at_the_end_of_bb
|
||||
; GCN: liveins: $vgpr31
|
||||
; GCN-NEXT: {{ $}}
|
||||
; GCN-NEXT: renamable $vgpr0 = V_AND_B32_e32 1023, killed $vgpr31, implicit $exec
|
||||
; GCN-NEXT: renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec
|
||||
; GCN-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
|
||||
; GCN-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 killed $vgpr1, killed $vgpr0, implicit-def dead $vcc, implicit $exec
|
||||
renamable $vgpr0 = V_AND_B32_e32 1023, killed $vgpr31, implicit $exec
|
||||
renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec
|
||||
renamable $vgpr0 = V_ADD_CO_U32_e32 %stack.0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
|
||||
...
|
||||
|
||||
|
|
|
|||
|
|
@ -42,14 +42,14 @@ define void @callee_with_stack_and_call() #0 {
|
|||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s32
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x800
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[8:9], exec
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[10:11], exec
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v1, s30, 0
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v2, s30, 0
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[8:9]
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[10:11]
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[8:9], exec
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:16
|
||||
|
|
@ -65,15 +65,15 @@ define void @callee_with_stack_and_call() #0 {
|
|||
; NO-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+12
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[6:7], exec
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v1, 0
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v2, 0
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:16
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[6:7]
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
|
||||
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
|
||||
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:16
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 {
|
|||
; CHECK-NEXT: ;;#ASMSTART
|
||||
; CHECK-NEXT: ; def vgpr10
|
||||
; CHECK-NEXT: ;;#ASMEND
|
||||
; CHECK-NEXT: s_add_i32 s34, s33, 0x100100
|
||||
; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s34 ; 4-byte Folded Spill
|
||||
; CHECK-NEXT: s_add_i32 s8, s33, 0x100100
|
||||
; CHECK-NEXT: buffer_store_dword v10, off, s[0:3], s8 ; 4-byte Folded Spill
|
||||
; CHECK-NEXT: s_mov_b64 s[18:19], 8
|
||||
; CHECK-NEXT: s_mov_b32 s8, s16
|
||||
; CHECK-NEXT: s_mov_b32 s9, s17
|
||||
|
|
@ -56,8 +56,8 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 {
|
|||
; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
|
||||
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
|
||||
; CHECK-NEXT: s_add_i32 s6, s33, 0x100100
|
||||
; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s6 ; 4-byte Folded Reload
|
||||
; CHECK-NEXT: s_add_i32 s4, s33, 0x100100
|
||||
; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s4 ; 4-byte Folded Reload
|
||||
; CHECK-NEXT: v_readlane_b32 s4, v40, 1
|
||||
; CHECK-NEXT: s_mov_b32 s5, 0
|
||||
; CHECK-NEXT: s_cmp_eq_u32 s4, s5
|
||||
|
|
@ -66,8 +66,8 @@ define amdgpu_kernel void @test_kernel(i32 %val) #0 {
|
|||
; CHECK-NEXT: buffer_store_dword v10, v0, s[0:3], s33 offen ; 4-byte Folded Spill
|
||||
; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
|
||||
; CHECK-NEXT: ; %bb.1: ; %store
|
||||
; CHECK-NEXT: s_add_i32 s5, s33, 0x100000
|
||||
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s5 ; 4-byte Folded Reload
|
||||
; CHECK-NEXT: s_add_i32 s4, s33, 0x100000
|
||||
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s4 ; 4-byte Folded Reload
|
||||
; CHECK-NEXT: ; implicit-def: $sgpr4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
|
|
|
|||
|
|
@ -235,30 +235,30 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(<3 x i64> addrspace(1
|
|||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_or_b32_e32 v1, 0x12cc, v0
|
||||
; MUBUF-NEXT: v_or_b32_e32 v0, 0x12c8, v0
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v18, 0x4000
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v17, 0x4000
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v16, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v15, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v12, 0
|
||||
; MUBUF-NEXT: buffer_load_dword v8, v13, s[0:3], 0 offen glc
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v14, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v8, v18, s[0:3], 0 offen glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v9, v13, s[0:3], 0 offen offset:4 glc
|
||||
; MUBUF-NEXT: buffer_load_dword v9, v17, s[0:3], 0 offen offset:4 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v2, v13, s[0:3], 0 offen offset:8 glc
|
||||
; MUBUF-NEXT: buffer_load_dword v2, v16, s[0:3], 0 offen offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v3, v13, s[0:3], 0 offen offset:12 glc
|
||||
; MUBUF-NEXT: buffer_load_dword v3, v15, s[0:3], 0 offen offset:12 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v10, v13, s[0:3], 0 offen offset:16 glc
|
||||
; MUBUF-NEXT: buffer_load_dword v10, v14, s[0:3], 0 offen offset:16 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000
|
||||
; MUBUF-NEXT: buffer_load_dword v11, v13, s[0:3], 0 offen offset:20 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v12, 0
|
||||
; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
|
||||
; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
|
||||
; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v7, v8
|
||||
|
|
@ -296,10 +296,10 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(<3 x i64> addrspace(1
|
|||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s2 offset:704 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s3, 0x2000
|
||||
; FLATSCR-NEXT: s_movk_i32 s2, 0x2000
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s2 offset:16 glc
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s3 offset:16 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s2, 0x2000
|
||||
; FLATSCR-NEXT: scratch_load_dwordx4 v[4:7], off, s2 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@ body: |
|
|||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $sgpr4, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK-NEXT: $sgpr5 = S_MOV_B32 524288
|
||||
; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, align 8192, addrspace 5)
|
||||
; CHECK-NEXT: $sgpr4 = S_MOV_B32 524288
|
||||
; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, align 8192, addrspace 5)
|
||||
; CHECK-NEXT: S_BRANCH %bb.1
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.1:
|
||||
|
|
|
|||
|
|
@ -20,84 +20,109 @@ machineFunctionInfo:
|
|||
stackPtrOffsetReg: $sgpr32
|
||||
|
||||
body: |
|
||||
; GFX8-LABEL: name: pei_scavenge_vgpr_spill
|
||||
; GFX8: bb.0:
|
||||
; GFX8-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX8-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX8-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
|
||||
; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
|
||||
; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc
|
||||
; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc
|
||||
; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX8-NEXT: $vcc_lo = S_MOV_B32 8192
|
||||
; GFX8-NEXT: $vgpr0, dead $vcc = V_ADD_CO_U32_e64 killed $vcc_lo, killed $vgpr0, 0, implicit $exec
|
||||
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
; GFX8-NEXT: $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX8-NEXT: $vcc_lo = S_MOV_B32 16384
|
||||
; GFX8-NEXT: $vgpr2, dead $vcc = V_ADD_CO_U32_e64 killed $vcc_lo, killed $vgpr2, 0, implicit $exec
|
||||
; GFX8-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec
|
||||
; GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; GFX8-NEXT: S_BRANCH %bb.1
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.1:
|
||||
; GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -2097152, implicit-def dead $scc
|
||||
; GFX8-NEXT: $sgpr33 = V_READLANE_B32 $vgpr2, 0
|
||||
; GFX8-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX8-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX8-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX9-LABEL: name: pei_scavenge_vgpr_spill
|
||||
; GFX9: bb.0:
|
||||
; GFX9-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX9-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
|
||||
; GFX9-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
|
||||
; GFX9-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc
|
||||
; GFX9-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc
|
||||
; GFX9-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX9-NEXT: $vgpr0 = V_ADD_U32_e32 8192, killed $vgpr0, implicit $exec
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX9-NEXT: $vgpr2 = V_ADD_U32_e32 16384, killed $vgpr2, implicit $exec
|
||||
; GFX9-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr2, $vgpr1, implicit $exec
|
||||
; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; GFX9-NEXT: S_BRANCH %bb.1
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: bb.1:
|
||||
; GFX9-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -2097152, implicit-def dead $scc
|
||||
; GFX9-NEXT: $sgpr33 = V_READLANE_B32 $vgpr2, 0
|
||||
; GFX9-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX9-FLATSCR-LABEL: name: pei_scavenge_vgpr_spill
|
||||
; GFX9-FLATSCR: bb.0:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.1(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 16388, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, killed $sgpr6, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5)
|
||||
; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-FLATSCR-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
|
||||
; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc
|
||||
; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $vcc_lo = S_ADD_I32 $sgpr33, 8192, implicit-def $scc
|
||||
; GFX9-FLATSCR-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vcc_lo, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $vcc_hi = S_ADD_I32 $sgpr33, 16384, implicit-def $scc
|
||||
; GFX9-FLATSCR-NEXT: $vgpr0 = V_OR_B32_e32 killed $vcc_hi, $vgpr1, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: S_BRANCH %bb.1
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -32768, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $sgpr33 = V_READLANE_B32 $vgpr2, 0
|
||||
; GFX9-FLATSCR-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 16388, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr6, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5)
|
||||
; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
|
||||
; GFX8-LABEL: name: pei_scavenge_vgpr_spill
|
||||
; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX8-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX8-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
|
||||
; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
|
||||
; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc
|
||||
; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc
|
||||
; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX8-NEXT: $vcc_lo = S_MOV_B32 8192
|
||||
; GFX8-NEXT: $vgpr0, dead $vcc = V_ADD_CO_U32_e64 killed $vcc_lo, killed $vgpr0, 0, implicit $exec
|
||||
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
; GFX8-NEXT: $vgpr3 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX8-NEXT: $vcc_lo = S_MOV_B32 16384
|
||||
; GFX8-NEXT: $vgpr3, dead $vcc = V_ADD_CO_U32_e64 killed $vcc_lo, killed $vgpr3, 0, implicit $exec
|
||||
; GFX8-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr3, $vgpr1, implicit $exec
|
||||
; GFX8-NEXT: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -2097152, implicit-def dead $scc
|
||||
; GFX8-NEXT: $sgpr33 = V_READLANE_B32 $vgpr2, 0
|
||||
; GFX8-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX8-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX8-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; GFX8-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX9-LABEL: name: pei_scavenge_vgpr_spill
|
||||
; GFX9: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX9-NEXT: {{ $}}
|
||||
; GFX9-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
|
||||
; GFX9-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
|
||||
; GFX9-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc
|
||||
; GFX9-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc
|
||||
; GFX9-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX9-NEXT: $vgpr0 = V_ADD_U32_e32 8192, killed $vgpr0, implicit $exec
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr3 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
|
||||
; GFX9-NEXT: $vgpr3 = V_ADD_U32_e32 16384, killed $vgpr3, implicit $exec
|
||||
; GFX9-NEXT: $vgpr0 = V_OR_B32_e32 killed $vgpr3, $vgpr1, implicit $exec
|
||||
; GFX9-NEXT: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -2097152, implicit-def dead $scc
|
||||
; GFX9-NEXT: $sgpr33 = V_READLANE_B32 $vgpr2, 0
|
||||
; GFX9-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
|
||||
; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr6, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; GFX9-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
; GFX9-FLATSCR-LABEL: name: pei_scavenge_vgpr_spill
|
||||
; GFX9-FLATSCR: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr2
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 16388, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, killed $sgpr6, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5)
|
||||
; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-FLATSCR-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr33, 0, undef $vgpr2
|
||||
; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc
|
||||
; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 32768, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $vcc_hi = S_ADD_I32 $sgpr33, 8192, implicit-def $scc
|
||||
; GFX9-FLATSCR-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vcc_hi, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $vcc_hi = S_ADD_I32 $sgpr33, 16384, implicit-def $scc
|
||||
; GFX9-FLATSCR-NEXT: $vgpr0 = V_OR_B32_e32 killed $vcc_hi, $vgpr1, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $sgpr32 = frame-destroy S_ADD_I32 $sgpr32, -32768, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $sgpr33 = V_READLANE_B32 $vgpr2, 0
|
||||
; GFX9-FLATSCR-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
|
||||
; GFX9-FLATSCR-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 16388, implicit-def dead $scc
|
||||
; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr6, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5)
|
||||
; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; GFX9-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs
|
||||
$vgpr0 = V_MOV_B32_e32 %stack.0, implicit $exec
|
||||
$vgpr0 = V_OR_B32_e32 %stack.1, $vgpr1, implicit $exec
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_ENDPGM 0, amdgpu_allvgprs
|
||||
...
|
||||
|
|
|
|||
|
|
@ -72,7 +72,6 @@
|
|||
; GFX10-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
|
||||
; GFX10-FLATSCR-PAL: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
|
||||
; GFX11-FLATSCR: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, v0
|
||||
; GCN-NOT: s_mov_b32 s0
|
||||
|
||||
; MUBUF-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[HI_OFF:v[0-9]+]],{{.*}} 0x280, [[CLAMP_IDX]]
|
||||
; MUBUF-DAG: v_add{{_|_nc_}}{{i|u}}32_e32 [[LO_OFF:v[0-9]+]],{{.*}} {{v2|0x80}}, [[CLAMP_IDX]]
|
||||
|
|
@ -120,7 +119,6 @@ define amdgpu_ps float @ps_main(i32 %idx) {
|
|||
; GFX10-FLATSCR-PAL: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
|
||||
|
||||
; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
|
||||
; GCN-NOT: s_mov_b32 s0
|
||||
|
||||
; FLATSCR-NOT: SCRATCH_RSRC_DWORD
|
||||
|
||||
|
|
|
|||
|
|
@ -235,6 +235,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -247,6 +248,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -286,7 +288,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $sgpr8
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -301,7 +303,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $sgpr8
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -343,6 +345,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -355,6 +358,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -395,7 +399,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $sgpr8_sgpr9
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -410,7 +414,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $sgpr8_sgpr9
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8_sgpr9
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -440,7 +444,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8, $sgpr9
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
|
||||
; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = V_WRITELANE_B32 $sgpr8, 0, undef $vgpr0
|
||||
|
|
@ -448,22 +452,23 @@ body: |
|
|||
; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = V_WRITELANE_B32 $sgpr9, 0, undef $vgpr1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = V_MOV_B32_e32 8200, implicit $exec
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr1, killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr1
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = V_WRITELANE_B32 $sgpr9, 0, undef $vgpr0
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8, $sgpr9
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -477,6 +482,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8, $sgpr9
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -502,7 +508,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
|
||||
; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
|
|
@ -510,23 +516,23 @@ body: |
|
|||
; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $sgpr8 = V_READLANE_B32 killed $vgpr0, 0
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = V_MOV_B32_e32 16392, implicit $exec
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $sgpr9 = V_READLANE_B32 killed $vgpr1, 0
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr1
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 16392, implicit $exec
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $sgpr9 = V_READLANE_B32 killed $vgpr0, 0
|
||||
; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
|
||||
; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
|
||||
; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $sgpr8, $sgpr9
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8, $sgpr9
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -542,7 +548,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $sgpr8, $sgpr9
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $sgpr8, $sgpr9
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
|
|||
|
|
@ -1,35 +1,10 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=false -verify-machineinstrs -run-pass=si-lower-sgpr-spills,prologepilog -o - %s | FileCheck %s
|
||||
|
||||
# Check that we allocate 2 emergency stack slots if we're spilling
|
||||
# SGPRs to memory and potentially have an offset larger than fits in
|
||||
# the addressing mode of the memory instructions.
|
||||
|
||||
# CHECK-LABEL: name: test
|
||||
# CHECK: stack:
|
||||
# CHECK-NEXT: - { id: 0, name: '', type: spill-slot, offset: 8, size: 4, alignment: 4,
|
||||
# CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
# CHECK-NEXT: - { id: 1, name: '', type: default, offset: 12, size: 4096, alignment: 4,
|
||||
# CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
# CHECK-NEXT: - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4,
|
||||
# CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
# CHECK-NEXT: - { id: 3, name: '', type: default, offset: 4, size: 4, alignment: 4,
|
||||
# CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
|
||||
# CHECK: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
|
||||
# CHECK-NEXT: $vgpr1 = V_WRITELANE_B32 killed $sgpr10, 0, undef $vgpr1
|
||||
# CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
# CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
|
||||
|
||||
|
||||
# CHECK: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
|
||||
# CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5)
|
||||
# CHECK-NEXT: $sgpr10 = V_READLANE_B32 killed $vgpr1, 0
|
||||
# CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
|
||||
---
|
||||
name: test
|
||||
tracksRegLiveness: true
|
||||
|
|
@ -47,6 +22,25 @@ machineFunctionInfo:
|
|||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr30_sgpr31, $sgpr10, $sgpr11
|
||||
; CHECK-LABEL: name: test
|
||||
; CHECK: liveins: $sgpr30_sgpr31, $sgpr10, $sgpr11
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
|
||||
; CHECK-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr2
|
||||
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
|
||||
; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 killed $sgpr10, 0, undef $vgpr2
|
||||
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
|
||||
; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7, implicit killed $vgpr2
|
||||
; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr1
|
||||
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
|
||||
; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5)
|
||||
; CHECK-NEXT: $sgpr10 = V_READLANE_B32 killed $vgpr1, 0
|
||||
; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
|
||||
; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr1
|
||||
; CHECK-NEXT: S_SETPC_B64 $sgpr30_sgpr31, implicit $scc
|
||||
S_CMP_EQ_U32 0, 0, implicit-def $scc
|
||||
SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
|
||||
renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +1,45 @@
|
|||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck -check-prefixes=GCN,MUBUF %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=GCN,FLATSCR %s
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck -check-prefix=MUBUF %s
|
||||
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -mattr=+enable-flat-scratch < %s | FileCheck -check-prefix=FLATSCR %s
|
||||
|
||||
; Test that the VGPR spiller correctly switches to SGPR offsets when the
|
||||
; instruction offset field would overflow, and that it accounts for memory
|
||||
; swizzling.
|
||||
|
||||
; GCN-LABEL: test_inst_offset_kernel
|
||||
define amdgpu_kernel void @test_inst_offset_kernel() {
|
||||
; MUBUF-LABEL: test_inst_offset_kernel:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_add_u32 s0, s0, s7
|
||||
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4092 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4092 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_endpgm
|
||||
;
|
||||
; FLATSCR-LABEL: test_inst_offset_kernel:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_lo offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0xffc
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0xffc
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi offset:8
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_endpgm
|
||||
entry:
|
||||
; Occupy 4092 bytes of scratch, so the offset of the spill of %a just fits in
|
||||
; the instruction offset field.
|
||||
|
|
@ -14,8 +47,8 @@ entry:
|
|||
%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
|
||||
|
||||
%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4092 ; 4-byte Folded Spill
|
||||
; FLATSCR: scratch_store_dword off, v{{[0-9]+}}, s{{[0-9]+}} ; 4-byte Folded Spill
|
||||
|
||||
|
||||
%a = load volatile i32, i32 addrspace(5)* %aptr
|
||||
|
||||
; Force %a to spill.
|
||||
|
|
@ -27,8 +60,42 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_sgpr_offset_kernel
|
||||
define amdgpu_kernel void @test_sgpr_offset_kernel() {
|
||||
; MUBUF-LABEL: test_sgpr_offset_kernel:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_add_u32 s0, s0, s7
|
||||
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_mov_b32 s4, 0x40000
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_mov_b32 s4, 0x40000
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_endpgm
|
||||
;
|
||||
; FLATSCR-LABEL: test_sgpr_offset_kernel:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_lo offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0x1000
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0x1000
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi offset:8
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_endpgm
|
||||
entry:
|
||||
; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
|
||||
; fit in the instruction, and has to live in the SGPR offset.
|
||||
|
|
@ -37,12 +104,7 @@ entry:
|
|||
|
||||
%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
|
||||
; 0x40000 / 64 = 4096 (for wave64)
|
||||
; MUBUF: s_mov_b32 s4, 0x40000
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 ; 4-byte Folded Spill
|
||||
; FLATSCR: s_movk_i32 s2, 0x1000
|
||||
; FLATSCR: scratch_store_dword off, v{{[0-9]+}}, s2 ; 4-byte Folded Spill
|
||||
%a = load volatile i32, i32 addrspace(5)* %aptr
|
||||
|
||||
; Force %a to spill
|
||||
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}" ()
|
||||
|
||||
|
|
@ -52,11 +114,50 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; FIXME: If we fail to scavenge an SGPR in a kernel we don't have a stack
|
||||
; pointer to temporarily update, so we just crash.
|
||||
|
||||
; GCN-LABEL: test_sgpr_offset_function_scavenge_fail_func
|
||||
define void @test_sgpr_offset_function_scavenge_fail_func() #2 {
|
||||
; MUBUF-LABEL: test_sgpr_offset_function_scavenge_fail_func:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1004
|
||||
; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], s32 offen ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1004
|
||||
; MUBUF-NEXT: buffer_load_dword v0, v1, s[0:3], s32 offen ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; FLATSCR-LABEL: test_sgpr_offset_function_scavenge_fail_func:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_add_i32 s8, s32, 0x1004
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s8 ; 4-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_add_i32 s8, s32, 0x1004
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s8 ; 4-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
|
||||
entry:
|
||||
; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
|
||||
; fit in the instruction, and has to live in the SGPR offset.
|
||||
|
|
@ -77,12 +178,6 @@ entry:
|
|||
|
||||
; 0x40000 / 64 = 4096 (for wave64)
|
||||
%a = load volatile i32, i32 addrspace(5)* %aptr
|
||||
|
||||
; MUBUF: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1004
|
||||
; MUBUF-NEXT: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+:[0-9]+}}], s32 offen ; 4-byte Folded Spill
|
||||
|
||||
; FLATSCR: s_add_i32 [[SOFF:s[0-9]+]], s32, 0x1004
|
||||
; FLATSCR: scratch_store_dword off, v{{[0-9]+}}, [[SOFF]] ; 4-byte Folded Spill
|
||||
call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0.0, i32 %asm1.0, i32 %asm2.0, i32 %asm3.0, i32 %asm4.0, i32 %asm5.0, i32 %asm6.0, i32 %asm7.0, i32 %a)
|
||||
|
||||
%asm = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()
|
||||
|
|
@ -96,18 +191,58 @@ entry:
|
|||
%asm7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 7
|
||||
|
||||
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
|
||||
|
||||
; MUBUF: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1004
|
||||
; MUBUF-NEXT: buffer_load_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+:[0-9]+}}], s32 offen ; 4-byte Folded Reload
|
||||
; FLATSCR: s_add_i32 [[SOFF:s[0-9]+]], s32, 0x1004
|
||||
; FLATSCR: scratch_load_dword v{{[0-9]+}}, off, [[SOFF]] ; 4-byte Folded Reload
|
||||
|
||||
; Force %a to spill with no free SGPRs
|
||||
call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0, i32 %asm1, i32 %asm2, i32 %asm3, i32 %asm4, i32 %asm5, i32 %asm6, i32 %asm7, i32 %a)
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @test_sgpr_offset_function_scavenge_fail_kernel() #3 {
|
||||
; MUBUF-LABEL: test_sgpr_offset_function_scavenge_fail_kernel:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_add_u32 s0, s0, s7
|
||||
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1004
|
||||
; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1004
|
||||
; MUBUF-NEXT: buffer_load_dword v0, v1, s[0:3], 0 offen ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_endpgm
|
||||
;
|
||||
; FLATSCR-LABEL: test_sgpr_offset_function_scavenge_fail_kernel:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s8, 0x1004
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s8 ; 4-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_movk_i32 s8, 0x1004
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s8 ; 4-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_endpgm
|
||||
entry:
|
||||
; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
|
||||
; fit in the instruction, and has to live in the SGPR offset.
|
||||
|
|
@ -128,12 +263,6 @@ entry:
|
|||
|
||||
; 0x40000 / 64 = 4096 (for wave64)
|
||||
%a = load volatile i32, i32 addrspace(5)* %aptr
|
||||
|
||||
; MUBUF: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1004
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+:[0-9]+}}], 0 offen ; 4-byte Folded Spill
|
||||
|
||||
; FLATSCR: s_movk_i32 [[SOFF:s[0-9]+]], 0x1004
|
||||
; FLATSCR: scratch_store_dword off, v{{[0-9]+}}, [[SOFF]] ; 4-byte Folded Spill
|
||||
call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0.0, i32 %asm1.0, i32 %asm2.0, i32 %asm3.0, i32 %asm4.0, i32 %asm5.0, i32 %asm6.0, i32 %asm7.0, i32 %a)
|
||||
|
||||
%asm = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()
|
||||
|
|
@ -147,19 +276,57 @@ entry:
|
|||
%asm7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 7
|
||||
|
||||
call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
|
||||
|
||||
; MUBUF: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1004
|
||||
; MUBUF: buffer_load_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+:[0-9]+}}], 0 offen ; 4-byte Folded Reload
|
||||
; FLATSCR: s_movk_i32 [[SOFF:s[0-9]+]], 0x1004
|
||||
; FLATSCR: scratch_load_dword v{{[0-9]+}}, off, [[SOFF]] ; 4-byte Folded Reload
|
||||
|
||||
; Force %a to spill with no free SGPRs
|
||||
call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0, i32 %asm1, i32 %asm2, i32 %asm3, i32 %asm4, i32 %asm5, i32 %asm6, i32 %asm7, i32 %a)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_sgpr_offset_subregs_kernel
|
||||
define amdgpu_kernel void @test_sgpr_offset_subregs_kernel() {
|
||||
; MUBUF-LABEL: test_sgpr_offset_subregs_kernel:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_add_u32 s0, s0, s7
|
||||
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:12 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4088 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:4092 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4088 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_nop 0
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:4092 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ; v[0:1]
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_endpgm
|
||||
;
|
||||
; FLATSCR-LABEL: test_sgpr_offset_subregs_kernel:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, vcc_lo offset:12 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0xff8
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 ; 8-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0xff8
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 ; 8-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ; v[0:1]
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_endpgm
|
||||
entry:
|
||||
; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
|
||||
; still fits below offset 4096 (4088 + 8 - 4 = 4092), and can be placed in
|
||||
|
|
@ -167,11 +334,6 @@ entry:
|
|||
%alloca = alloca i8, i32 4084, align 4, addrspace(5)
|
||||
%bufv1 = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
|
||||
%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
|
||||
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4088 ; 4-byte Folded Spill
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4092 ; 4-byte Folded Spill
|
||||
; FLATSCR: s_movk_i32 [[SOFF:s[0-9]+]], 0xff8
|
||||
; FLATSCR: scratch_store_dwordx2 off, v[{{[0-9:]+}}], [[SOFF]] ; 8-byte Folded Spill
|
||||
%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
|
||||
%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
|
||||
|
||||
|
|
@ -188,8 +350,54 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_inst_offset_subregs_kernel
|
||||
define amdgpu_kernel void @test_inst_offset_subregs_kernel() {
|
||||
; MUBUF-LABEL: test_inst_offset_subregs_kernel:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_add_u32 s0, s0, s7
|
||||
; MUBUF-NEXT: s_addc_u32 s1, s1, 0
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:12 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:16 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_mov_b32 s4, 0x3ff00
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_mov_b32 s4, 0x3ff00
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_nop 0
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ; v[0:1]
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_endpgm
|
||||
;
|
||||
; FLATSCR-LABEL: test_inst_offset_subregs_kernel:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s0, s3
|
||||
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_lo, 0
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, vcc_lo offset:12 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0xffc
|
||||
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s0 ; 8-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_movk_i32 s0, 0xffc
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 ; 8-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ; v[0:1]
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_endpgm
|
||||
entry:
|
||||
; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a
|
||||
; does not fit below offset 4096 (4092 + 8 - 4 = 4096), and has to live
|
||||
|
|
@ -199,11 +407,6 @@ entry:
|
|||
%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
|
||||
|
||||
; 0x3ff00 / 64 = 4092 (for wave64)
|
||||
; MUBUF: s_mov_b32 s4, 0x3ff00
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 ; 4-byte Folded Spill
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 offset:4 ; 4-byte Folded Spill
|
||||
; FLATSCR: s_movk_i32 [[SOFF:s[0-9]+]], 0xffc
|
||||
; FLATSCR: scratch_store_dwordx2 off, v[{{[0-9:]+}}], [[SOFF]] ; 8-byte Folded Spill
|
||||
%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
|
||||
%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
|
||||
|
||||
|
|
@ -220,8 +423,34 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_inst_offset_function
|
||||
define void @test_inst_offset_function() {
|
||||
; MUBUF-LABEL: test_inst_offset_function:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4088 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4088 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; FLATSCR-LABEL: test_inst_offset_function:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:4 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:4088 ; 4-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:4088 ; 4-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:4
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
|
||||
entry:
|
||||
; Occupy enough bytes of scratch, so the offset of the spill of %a
|
||||
; just fits in the instruction offset field when the emergency stack
|
||||
|
|
@ -231,8 +460,8 @@ entry:
|
|||
%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
|
||||
|
||||
%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4088 ; 4-byte Folded Spill
|
||||
; FLATSCR: scratch_store_dword off, v{{[0-9]+}}, s{{[0-9]+}} offset:4088 ; 4-byte Folded Spill
|
||||
|
||||
|
||||
%a = load volatile i32, i32 addrspace(5)* %aptr
|
||||
|
||||
; Force %a to spill.
|
||||
|
|
@ -244,8 +473,38 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_sgpr_offset_function
|
||||
define void @test_sgpr_offset_function() {
|
||||
; MUBUF-LABEL: test_sgpr_offset_function:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_add_i32 s4, s32, 0x40100
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_add_i32 s4, s32, 0x40100
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; FLATSCR-LABEL: test_sgpr_offset_function:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_add_i32 s0, s32, 0x1004
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_add_i32 s0, s32, 0x1004
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:8
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
|
||||
entry:
|
||||
; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
|
||||
; fit in the instruction, and has to live in the SGPR offset.
|
||||
|
|
@ -254,10 +513,6 @@ entry:
|
|||
|
||||
%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
|
||||
; 0x40000 / 64 = 4096 (for wave64)
|
||||
; MUBUF: s_add_i32 s4, s32, 0x40100
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 ; 4-byte Folded Spill
|
||||
; FLATSCR: s_add_i32 s0, s32, 0x1004
|
||||
; FLATSCR: scratch_store_dword off, v{{[0-9]+}}, s0 ; 4-byte Folded Spill
|
||||
%a = load volatile i32, i32 addrspace(5)* %aptr
|
||||
|
||||
; Force %a to spill
|
||||
|
|
@ -269,24 +524,57 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_sgpr_offset_subregs_function
|
||||
define void @test_sgpr_offset_subregs_function() {
|
||||
; MUBUF-LABEL: test_sgpr_offset_subregs_function:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4084 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4088 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4084 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_nop 0
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4088 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ; v[0:1]
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; FLATSCR-LABEL: test_sgpr_offset_subregs_function:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:4084 ; 8-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:4 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:4084 ; 8-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ; v[0:1]
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
|
||||
entry:
|
||||
; We want to test the spill of the last subreg of %a is the highest
|
||||
; valid value for the immediate offset. We enable the emergency
|
||||
; stack slot for large frames, so it's hard to get the frame layout
|
||||
; exactly as we want to test it.
|
||||
;
|
||||
; Occupy 4084 bytes of scratch, so that the spill of the last subreg of %a
|
||||
; still fits below offset 4096 (4084 + 8 - 4 = 4092), and can be placed in
|
||||
; the instruction offset field.
|
||||
%alloca = alloca i8, i32 4084, align 4, addrspace(5)
|
||||
%bufv1 = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
|
||||
%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
|
||||
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4084 ; 4-byte Folded Spill
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4088 ; 4-byte Folded Spill
|
||||
; FLATSCR: scratch_store_dwordx2 off, v[{{[0-9:]+}}], s32 offset:4084 ; 8-byte Folded Spill
|
||||
%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
|
||||
%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
|
||||
|
||||
|
|
@ -303,8 +591,48 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: test_inst_offset_subregs_function
|
||||
define void @test_inst_offset_subregs_function() {
|
||||
; MUBUF-LABEL: test_inst_offset_subregs_function:
|
||||
; MUBUF: ; %bb.0: ; %entry
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_add_i32 s4, s32, 0x3ff00
|
||||
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Spill
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: s_add_i32 s4, s32, 0x3ff00
|
||||
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_nop 0
|
||||
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Reload
|
||||
; MUBUF-NEXT: s_waitcnt vmcnt(0)
|
||||
; MUBUF-NEXT: ;;#ASMSTART
|
||||
; MUBUF-NEXT: ; v[0:1]
|
||||
; MUBUF-NEXT: ;;#ASMEND
|
||||
; MUBUF-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; FLATSCR-LABEL: test_inst_offset_subregs_function:
|
||||
; FLATSCR: ; %bb.0: ; %entry
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:12 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:4092 ; 8-byte Folded Spill
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 offset:8 glc
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s32 offset:4092 ; 8-byte Folded Reload
|
||||
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
|
||||
; FLATSCR-NEXT: ;;#ASMSTART
|
||||
; FLATSCR-NEXT: ; v[0:1]
|
||||
; FLATSCR-NEXT: ;;#ASMEND
|
||||
; FLATSCR-NEXT: s_setpc_b64 s[30:31]
|
||||
entry:
|
||||
; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
|
||||
; does not fit below offset 4096 (408 + 4 + 8 - 4 = 4096), and has to live
|
||||
|
|
@ -314,10 +642,6 @@ entry:
|
|||
%bufv2 = bitcast i8 addrspace(5)* %alloca to <2 x i32> addrspace(5)*
|
||||
|
||||
; 0x3ff0000 / 64 = 4092 (for wave64)
|
||||
; MUBUF: s_add_i32 s4, s32, 0x3ff00
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 ; 4-byte Folded Spill
|
||||
; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s4 offset:4 ; 4-byte Folded Spill
|
||||
; FLATSCR: scratch_store_dwordx2 off, v[{{[0-9:]+}}], s32 offset:4092 ; 8-byte Folded Spill
|
||||
%aptr = getelementptr <2 x i32>, <2 x i32> addrspace(5)* %bufv2, i32 1
|
||||
%a = load volatile <2 x i32>, <2 x i32> addrspace(5)* %aptr
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -48,23 +48,23 @@ body: |
|
|||
; GFX9-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
|
||||
; GFX9-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
|
||||
; GFX9-NEXT: $vcc = IMPLICIT_DEF
|
||||
; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc
|
||||
; GFX9-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0
|
||||
; GFX9-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr2
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr2 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr2, implicit $vcc
|
||||
; GFX9-NEXT: $vgpr2 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr2, implicit $vcc
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr2
|
||||
; GFX9-NEXT: $vcc = IMPLICIT_DEF
|
||||
; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc
|
||||
; GFX9-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0
|
||||
; GFX9-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $exec
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr1
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr1 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr1, implicit $vcc
|
||||
; GFX9-NEXT: $vgpr1 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr1, implicit killed $vcc
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX9-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr2_sgpr3, implicit killed $vgpr1
|
||||
; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
|
|
@ -84,23 +84,23 @@ body: |
|
|||
; GFX10-NEXT: $sgpr96 = S_ADD_U32 $sgpr96, $sgpr9, implicit-def $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
; GFX10-NEXT: $sgpr97 = S_ADDC_U32 $sgpr97, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
; GFX10-NEXT: $vcc = IMPLICIT_DEF
|
||||
; GFX10-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc
|
||||
; GFX10-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0
|
||||
; GFX10-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr2
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr2 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr2, implicit $vcc
|
||||
; GFX10-NEXT: $vgpr2 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr2, implicit $vcc
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr2
|
||||
; GFX10-NEXT: $vcc = IMPLICIT_DEF
|
||||
; GFX10-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc
|
||||
; GFX10-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0
|
||||
; GFX10-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $exec
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr1
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr1 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr1, implicit $vcc
|
||||
; GFX10-NEXT: $vgpr1 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr1, implicit killed $vcc
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX10-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr2_sgpr3, implicit killed $vgpr1
|
||||
; GFX10-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
|
|
@ -114,23 +114,23 @@ body: |
|
|||
; GFX11-NEXT: {{ $}}
|
||||
; GFX11-NEXT: $sgpr33 = S_MOV_B32 0
|
||||
; GFX11-NEXT: $vcc = IMPLICIT_DEF
|
||||
; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc
|
||||
; GFX11-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit $vcc
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0
|
||||
; GFX11-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr2
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr2 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr2, implicit $vcc
|
||||
; GFX11-NEXT: $vgpr2 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr2, implicit $vcc
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr2
|
||||
; GFX11-NEXT: $vcc = IMPLICIT_DEF
|
||||
; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr0, implicit $vcc
|
||||
; GFX11-NEXT: $vgpr0 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr0, implicit killed $vcc
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0
|
||||
; GFX11-NEXT: $sgpr2_sgpr3 = S_MOV_B64 $exec
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr1
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr1 = V_WRITELANE_B32 $vcc_lo, 0, undef $vgpr1, implicit $vcc
|
||||
; GFX11-NEXT: $vgpr1 = V_WRITELANE_B32 $vcc_hi, 1, $vgpr1, implicit killed $vcc
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
|
||||
; GFX11-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %fixed-stack.0, align 16, addrspace 5)
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr2_sgpr3, implicit killed $vgpr1
|
||||
; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
|
||||
; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0
|
||||
; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %fixed-stack.0, align 16, addrspace 5)
|
||||
|
|
|
|||
|
|
@ -412,6 +412,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -432,6 +433,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -451,6 +453,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -470,6 +473,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -483,6 +487,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -517,6 +522,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -537,6 +543,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -556,6 +563,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -576,6 +584,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -589,6 +598,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -624,6 +634,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -644,6 +655,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -663,6 +675,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -684,6 +697,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -697,6 +711,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -730,6 +745,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -750,6 +766,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -769,6 +786,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -788,6 +806,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -801,6 +820,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -835,6 +855,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -855,6 +876,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -874,6 +896,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -894,6 +917,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -907,6 +931,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -942,6 +967,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -962,6 +988,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -981,6 +1008,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -1002,6 +1030,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -1015,6 +1044,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -1144,6 +1174,7 @@ body: |
|
|||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: bb.1:
|
||||
; MUBUF-NEXT: successors: %bb.2(0x80000000)
|
||||
; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
; MUBUF-NEXT: S_NOP 0
|
||||
; MUBUF-NEXT: {{ $}}
|
||||
|
|
@ -1164,6 +1195,7 @@ body: |
|
|||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: bb.1:
|
||||
; GFX9-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
; GFX9-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX9-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -1184,6 +1216,7 @@ body: |
|
|||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: bb.1:
|
||||
; GFX10-FLATSCR-NEXT: successors: %bb.2(0x80000000)
|
||||
; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
; GFX10-FLATSCR-NEXT: S_NOP 0
|
||||
; GFX10-FLATSCR-NEXT: {{ $}}
|
||||
|
|
@ -1203,6 +1236,7 @@ body: |
|
|||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: bb.1:
|
||||
; VMEM-GFX8-NEXT: successors: %bb.2(0x80000000)
|
||||
; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
; VMEM-GFX8-NEXT: S_NOP 0
|
||||
; VMEM-GFX8-NEXT: {{ $}}
|
||||
|
|
@ -1217,6 +1251,7 @@ body: |
|
|||
S_CBRANCH_SCC1 %bb.2, implicit $scc
|
||||
|
||||
bb.1:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255
|
||||
S_NOP 0
|
||||
|
||||
bb.2:
|
||||
|
|
|
|||
|
|
@ -64,9 +64,12 @@ public:
|
|||
Register getFrameRegister(const MachineFunction &MF) const override {
|
||||
return 0;
|
||||
}
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
||||
unsigned FIOperandNum,
|
||||
RegScavenger *RS = nullptr) const override {}
|
||||
RegScavenger *RS = nullptr) const override {
|
||||
return false;
|
||||
|
||||
}
|
||||
};
|
||||
|
||||
class BogusSubtarget : public TargetSubtargetInfo {
|
||||
|
|
|
|||
Loading…
Reference in New Issue