diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 23202937f18e..3e861b0972db 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -312,8 +312,11 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RMFI = MF.getInfo<RISCVMachineFunctionInfo>();
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   auto *CurrentProgramInfo = const_cast<VentusProgramInfo *>(
                                                     STI.getVentusProgramInfo());
+  auto *CurrentRegUsageSet = const_cast<DenseSet<unsigned>*>(
+                                                    STI.getVentusRegUsageSet());
   const RISCVInstrInfo *TII = STI.getInstrInfo();
   MachineBasicBlock::iterator MBBI = MBB.begin();
   bool IsEntryFunction = RMFI->isEntryFunction();
@@ -394,6 +397,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
 
   // Allocate space on the local-mem stack and private-mem stack if necessary.
   if(SPStackSize) {
+    RI->insertRegToSet(MRI, CurrentRegUsageSet, CurrentProgramInfo, SPReg);
     RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
                   StackOffset::getFixed(SPStackSize),
                   MachineInstr::FrameSetup, getStackAlign());
@@ -407,6 +411,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   }
 
   if(TPStackSize) {
+    RI->insertRegToSet(MRI, CurrentRegUsageSet, CurrentProgramInfo, TPReg);
+    RI->insertRegToSet(MRI, CurrentRegUsageSet, CurrentProgramInfo, 
+                        RI->getPrivateMemoryBaseRegister(MF));
     RI->adjustReg(MBB, MBBI, DL, TPReg, TPReg,
                   StackOffset::getFixed(TPStackSize),
                   MachineInstr::FrameSetup, getStackAlign());
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index a7338d94919d..99e04d104494 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -172,17 +172,16 @@ MCRegister RISCVRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
 
 void RISCVRegisterInfo::analyzeRegisterUsage(DenseSet<Register> RewriteRegs,
                                       MachineFunction *MF) const  {
-  auto CurrentProgramInfo = const_cast<VentusProgramInfo*>(
+  auto *CurrentProgramInfo = const_cast<VentusProgramInfo*>(
                     MF->getSubtarget<RISCVSubtarget>().getVentusProgramInfo());
-  MachineRegisterInfo &MRI = MF->getRegInfo();
-  for(auto Reg : RewriteRegs) {
-      if(!isSGPRReg(MRI, Reg))
-        CurrentProgramInfo->VGPRUsage++;
-      else
-        CurrentProgramInfo->SGPRUsage++;
-  }
-  // FIXME: need to add two more because of ra && sp, how to simplify this?
-  CurrentProgramInfo->SGPRUsage += 2;
+  auto *CurrentRegUsageSet = const_cast<DenseSet<unsigned>*>(
+                    MF->getSubtarget<RISCVSubtarget>().getVentusRegUsageSet());
+  const MachineRegisterInfo &MRI = MF->getRegInfo();
+
+  for(auto Reg : RewriteRegs) 
+    insertRegToSet(MRI, CurrentRegUsageSet, CurrentProgramInfo, Reg);
+  
+  insertRegToSet(MRI, CurrentRegUsageSet, CurrentProgramInfo, RISCV::X1);
 }
 
 bool RISCVRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
@@ -195,6 +194,20 @@ bool RISCVRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
   return RC ? isSGPRClass(RC) : false;
 }
 
+void RISCVRegisterInfo::insertRegToSet(const MachineRegisterInfo &MRI, 
+                    DenseSet<unsigned int> *CurrentRegUsageSet, 
+                    VentusProgramInfo *CurrentProgramInfo, Register Reg) const {
+  if (CurrentRegUsageSet->contains(Reg))
+    return;
+
+  CurrentRegUsageSet->insert(Reg);
+
+  if (!isSGPRReg(MRI, Reg))
+    CurrentProgramInfo->VGPRUsage++;
+  else
+    CurrentProgramInfo->SGPRUsage++;
+}
+
 const Register RISCVRegisterInfo::getPrivateMemoryBaseRegister(
                         const MachineFunction &MF) const {
   // FIXME: V0-V31 are used for argument registers, so here we use V32 for
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index da6cfdfd8fca..967f1ab0f589 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -13,6 +13,7 @@
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
 #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
 
+#include "VentusProgramInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
@@ -62,6 +63,11 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
 
   bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
 
+  void insertRegToSet(const MachineRegisterInfo &MRI, 
+                      DenseSet<unsigned int> *CurrentRegUsageSet, 
+                      VentusProgramInfo *CurrentProgramInfo, 
+                      Register Reg) const;
+
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
 
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 67bc6b81f34f..b57ae12b4d8d 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -18,6 +18,7 @@
 #include "RISCVISelLowering.h"
 #include "RISCVInstrInfo.h"
 #include "VentusProgramInfo.h"
+#include "llvm/ADT/DenseSet.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
@@ -125,6 +126,7 @@ private:
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   VentusProgramInfo CurrentProgramInfo = VentusProgramInfo();
+  DenseSet<unsigned> CurrentRegUsageSet;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
@@ -150,6 +152,9 @@ public:
   const VentusProgramInfo *getVentusProgramInfo() const {
     return &CurrentProgramInfo;
   }
+  const DenseSet<unsigned> *getVentusRegUsageSet() const { 
+    return &CurrentRegUsageSet;
+  }
   const RISCVRegisterInfo *getRegisterInfo() const override { return &RegInfo; }
   const RISCVTargetLowering *getTargetLowering() const override {
     return &TLInfo;