[VENTUS][RISCV][NFC] Define interfaces for VENTUS

Our previous design has two stacks, TP&SP, but we only need to store ra to sp,
and restore it from sp, this make it inconvenient to calculate stack offset for
two stack frame offset,  Here we just define interfaces, but we do not really
implement it, if needed, we need to remove callee saved registers, and modify
the related overrided functions

llvm/include/llvm/CodeGen/TargetFrameLowering.h

@@ -259,6 +259,16 @@ public:
     return false;
   }
 
+  /// store registers to certain offset of a specific register
+  virtual bool storeRegToReg(const TargetRegisterInfo *TRI) const {
+    return false;
+  }
+
+  /// load registers from certain offset of a specific register
+  virtual bool loadRegFromReg(const TargetRegisterInfo *TRI) const {
+    return false;
+  }
+
   /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
   /// saved registers and returns true if it isn't possible / profitable to do
   /// so by issuing a series of load instructions via loadRegToStackSlot().

llvm/lib/CodeGen/PrologEpilogInserter.cpp

@@ -613,6 +613,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
       }
     }
   }
+  TFI->storeRegToReg(TRI);
 }
 
 /// Insert restore code for the callee-saved registers used in the function.
@@ -643,6 +644,7 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
       }
     }
   }
+  TFI->loadRegFromReg(TRI);
 }
 
 void PEI::spillCalleeSavedRegs(MachineFunction &MF) {

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

@@ -762,7 +762,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
       // FIXME: Right now, no vgpr callee saved register, maybe later needed
       TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(),
                             RC, TRI);
-    } 
+    }
     // else {
       // FIXME: Right now, no callee saved register for VGPR
       // MF->getFrameInfo().setStackID(CS.getFrameIdx(), RISCVStackID::VGPRSpill);
@@ -886,3 +886,15 @@ bool RISCVFrameLowering::isSupportedStackID(TargetStackID::Value ID) const {
   }
   llvm_unreachable("Invalid RISCVStackID::Value");
 }
+
+/// TODO: Implements this interface
+bool RISCVFrameLowering::storeRegToReg(const TargetRegisterInfo *TRI) const {
+
+  return false;
+}
+
+/// TODO: Implements this interface
+bool RISCVFrameLowering::loadRegFromReg(const TargetRegisterInfo *TRI) const {
+
+  return false;
+}

llvm/lib/Target/RISCV/RISCVFrameLowering.h

@@ -56,6 +56,9 @@ public:
                               MutableArrayRef<CalleeSavedInfo> CSI,
                               const TargetRegisterInfo *TRI) const override;
 
+  bool storeRegToReg(const TargetRegisterInfo *TRI) const override;
+
+  bool loadRegFromReg(const TargetRegisterInfo *TRI) const override;
   // Get the first stack adjustment amount for SplitSPAdjust.
   // Return 0 if we don't want to to split the SP adjustment in prologue and
   // epilogue.