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[DAG] Remove oneuse check in select_cc setgt X, -1, C, ~C fold 

This appears to produce better code, even if the condition may need to
be replicated.
This commit is contained in:
David Green 2021-09-05 16:18:31 +01:00
parent f114ef3731
commit 1b83aaaefa
10 changed files with 118 additions and 147 deletions
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3
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -22881,8 +22881,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
N2C->getAPIntValue() == ~N3C->getAPIntValue() &&
((N1C->isAllOnesValue() && CC == ISD::SETGT) ||
(N1C->isNullValue() && CC == ISD::SETLT)) &&
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1) &&
N0->hasOneUse()) {
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) {
SDValue ASR = DAG.getNode(
ISD::SRA, DL, CmpOpVT, N0,
DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT));

4
llvm/test/CodeGen/AArch64/select-constant-xor.ll
View File

@ -198,9 +198,9 @@ define i32 @selecti32i32_sgt(i32 %a) {
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK-LABEL: oneusecmp:
; CHECK: // %bb.0:
; CHECK-NEXT: asr w8, w0, #31
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #-128
; CHECK-NEXT: cinv w8, w8, ge
; CHECK-NEXT: eor w8, w8, #0x7f
; CHECK-NEXT: csel w9, w2, w1, lt
; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret

69
llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
View File

@ -237,7 +237,7 @@ define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
;
; EG-LABEL: fp_to_sint_i64:
; EG: ; %bb.0: ; %entry
; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@ -277,11 +277,10 @@ define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
; EG-NEXT: SUB_INT T2.W, PS, T1.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
; EG-NEXT: SUB_INT T2.W, PV.W, PS,
; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W,
; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
@ -361,7 +360,7 @@ define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x f
;
; EG-LABEL: fp_to_sint_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@ -429,19 +428,17 @@ define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x f
; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptosi <2 x float> %x to <2 x i64>
@ -567,7 +564,7 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-LABEL: fp_to_sint_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT: CF_END
@ -653,12 +650,11 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: SUB_INT T5.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: OR_INT T1.W, PV.X, literal.y,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z,
; EG-NEXT: -1(nan), 8388608(1.175494e-38)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT: AND_INT T2.Z, PS, literal.z,
@ -673,15 +669,15 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 108:
; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT: NOT_INT T1.W, T6.X,
; EG-NEXT: LSHR * T3.W, T0.W, 1,
@ -708,29 +704,26 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-NEXT: XOR_INT T1.X, PV.W, PS,
; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x,
; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x,
; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X,
; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR * T0.X, PV.W, literal.x,

69
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
View File

@ -184,7 +184,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %
;
; EG-LABEL: fp_to_uint_f32_to_i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@ -224,11 +224,10 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %
; EG-NEXT: SUB_INT T2.W, PS, T1.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
; EG-NEXT: SUB_INT T2.W, PV.W, PS,
; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W,
; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptoui float %x to i64
@ -287,7 +286,7 @@ define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %ou
;
; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
@ -355,19 +354,17 @@ define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %ou
; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptoui <2 x float> %x to <2 x i64>
@ -453,7 +450,7 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT: CF_END
@ -539,12 +536,11 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: SUB_INT T5.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: OR_INT T1.W, PV.X, literal.y,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z,
; EG-NEXT: -1(nan), 8388608(1.175494e-38)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT: AND_INT T2.Z, PS, literal.z,
@ -559,15 +555,15 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 108:
; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT: NOT_INT T1.W, T6.X,
; EG-NEXT: LSHR * T3.W, T0.W, 1,
@ -594,29 +590,26 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-NEXT: XOR_INT T1.X, PV.W, PS,
; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x,
; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x,
; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X,
; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR * T0.X, PV.W, literal.x,

7
llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll
View File

@ -8,7 +8,7 @@ define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in)
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; CHECK-NEXT: TEX 0 @6
; CHECK-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
; CHECK-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; CHECK-NEXT: CF_END
; CHECK-NEXT: PAD
@ -17,9 +17,8 @@ define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in)
; CHECK-NEXT: ALU clause starting at 8:
; CHECK-NEXT: MOV * T0.X, KC0[2].Z,
; CHECK-NEXT: ALU clause starting at 9:
; CHECK-NEXT: SETGT_INT * T0.W, T0.X, literal.x,
; CHECK-NEXT: -1(nan), 0(0.000000e+00)
; CHECK-NEXT: CNDE_INT T0.X, PV.W, 0.0, literal.x,
; CHECK-NEXT: SETGT_INT * T0.W, 0.0, T0.X,
; CHECK-NEXT: CNDE_INT T0.X, PV.W, literal.x, 0.0,
; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
; CHECK-NEXT: 1065353216(1.000000e+00), 2(2.802597e-45)
entry:

22
llvm/test/CodeGen/ARM/select-constant-xor.ll
View File

@ -358,9 +358,9 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK7A-LABEL: oneusecmp:
; CHECK7A: @ %bb.0:
; CHECK7A-NEXT: cmp r0, #0
; CHECK7A-NEXT: mov r0, #127
; CHECK7A-NEXT: mvnmi r0, #127
; CHECK7A-NEXT: movmi r1, r2
; CHECK7A-NEXT: mov r2, #127
; CHECK7A-NEXT: eor r0, r2, r0, asr #31
; CHECK7A-NEXT: add r0, r0, r1
; CHECK7A-NEXT: bx lr
;
@ -371,32 +371,28 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: mov r2, r1
; CHECK6M-NEXT: .LBB10_2:
; CHECK6M-NEXT: asrs r0, r0, #31
; CHECK6M-NEXT: movs r1, #127
; CHECK6M-NEXT: cmp r0, #0
; CHECK6M-NEXT: bpl .LBB10_4
; CHECK6M-NEXT: @ %bb.3:
; CHECK6M-NEXT: mvns r1, r1
; CHECK6M-NEXT: .LBB10_4:
; CHECK6M-NEXT: eors r1, r0
; CHECK6M-NEXT: adds r0, r1, r2
; CHECK6M-NEXT: bx lr
;
; CHECK7M-LABEL: oneusecmp:
; CHECK7M: @ %bb.0:
; CHECK7M-NEXT: cmp r0, #0
; CHECK7M-NEXT: mov.w r0, #127
; CHECK7M-NEXT: it mi
; CHECK7M-NEXT: movmi r1, r2
; CHECK7M-NEXT: it mi
; CHECK7M-NEXT: mvnmi r0, #127
; CHECK7M-NEXT: movs r2, #127
; CHECK7M-NEXT: eor.w r0, r2, r0, asr #31
; CHECK7M-NEXT: add r0, r1
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: oneusecmp:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: cmp r0, #0
; CHECK81M-NEXT: csel r0, r2, r1, mi
; CHECK81M-NEXT: mov.w r1, #127
; CHECK81M-NEXT: cinv r1, r1, mi
; CHECK81M-NEXT: csel r1, r2, r1, mi
; CHECK81M-NEXT: movs r2, #127
; CHECK81M-NEXT: eor.w r0, r2, r0, asr #31
; CHECK81M-NEXT: add r0, r1
; CHECK81M-NEXT: bx lr
%c = icmp sle i32 %a, -1

5
llvm/test/CodeGen/PowerPC/select-constant-xor.ll
View File

@ -129,10 +129,9 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK-LABEL: oneusecmp:
; CHECK: # %bb.0:
; CHECK-NEXT: li 6, 127
; CHECK-NEXT: srawi 6, 3, 31
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, -128
; CHECK-NEXT: isellt 3, 3, 6
; CHECK-NEXT: xori 3, 6, 127
; CHECK-NEXT: isellt 4, 5, 4
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: blr

21
llvm/test/CodeGen/PowerPC/smulfixsat.ll
View File

@ -6,20 +6,15 @@ declare i32 @llvm.smul.fix.sat.i32 (i32, i32, i32)
define i32 @func1(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func1:
; CHECK: # %bb.0:
; CHECK-NEXT: lis 5, 32767
; CHECK-NEXT: mulhw. 6, 3, 4
; CHECK-NEXT: lis 7, -32768
; CHECK-NEXT: mulhw 5, 3, 4
; CHECK-NEXT: mullw 3, 3, 4
; CHECK-NEXT: ori 4, 5, 65535
; CHECK-NEXT: srawi 5, 3, 31
; CHECK-NEXT: cmplw 1, 6, 5
; CHECK-NEXT: bc 12, 0, .LBB0_1
; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: addi 4, 7, 0
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: bclr 12, 6, 0
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: srawi 4, 3, 31
; CHECK-NEXT: cmplw 5, 4
; CHECK-NEXT: srawi 4, 5, 31
; CHECK-NEXT: xori 4, 4, 65535
; CHECK-NEXT: xoris 4, 4, 32767
; CHECK-NEXT: bclr 12, 2, 0
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ori 3, 4, 0
; CHECK-NEXT: blr
%tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)

10
llvm/test/CodeGen/X86/smul_fix_sat.ll
View File

@ -371,6 +371,7 @@ define i64 @func5(i64 %x, i64 %y) {
; X86-NEXT: .cfi_offset %edi, -16
; X86-NEXT: .cfi_offset %ebx, -12
; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
@ -378,13 +379,10 @@ define i64 @func5(i64 %x, i64 %y) {
; X86-NEXT: movl %esp, %edi
; X86-NEXT: movl %ecx, %ebx
; X86-NEXT: xorl %esi, %ebx
; X86-NEXT: sarl $31, %ebx
; X86-NEXT: movl %ebx, %ebp
; X86-NEXT: sarl $31, %ebp
; X86-NEXT: xorl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: movl $-1, %ebx
; X86-NEXT: cmovsl %eax, %ebx
; X86-NEXT: notl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl %esi
@ -393,7 +391,7 @@ define i64 @func5(i64 %x, i64 %y) {
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl %ecx
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax
; X86-NEXT: .cfi_adjust_cfa_offset 4
; X86-NEXT: calll __mulodi4
; X86-NEXT: addl $20, %esp

55
llvm/test/CodeGen/X86/sshl_sat.ll
View File

@ -229,39 +229,38 @@ define i64 @func5(i64 %x, i64 %y) nounwind {
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: pushl %eax
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl %eax, %ebp
; X86-NEXT: shll %cl, %ebp
; X86-NEXT: shldl %cl, %eax, %ebx
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: movl %edx, %ebx
; X86-NEXT: shll %cl, %ebx
; X86-NEXT: movl %eax, %esi
; X86-NEXT: shldl %cl, %edx, %esi
; X86-NEXT: xorl %edi, %edi
; X86-NEXT: testb $32, %cl
; X86-NEXT: cmovnel %ebp, %ebx
; X86-NEXT: cmovnel %edx, %ebp
; X86-NEXT: movl %ebx, %edx
; X86-NEXT: sarl %cl, %edx
; X86-NEXT: movl %ebx, %edi
; X86-NEXT: sarl $31, %edi
; X86-NEXT: cmovnel %ebx, %esi
; X86-NEXT: cmovel %ebx, %edi
; X86-NEXT: movl %edi, (%esp) # 4-byte Spill
; X86-NEXT: movl %esi, %ebx
; X86-NEXT: sarl %cl, %ebx
; X86-NEXT: movl %esi, %ebp
; X86-NEXT: sarl $31, %ebp
; X86-NEXT: testb $32, %cl
; X86-NEXT: cmovel %edx, %edi
; X86-NEXT: movl %ebp, %esi
; X86-NEXT: shrdl %cl, %ebx, %esi
; X86-NEXT: cmovel %ebx, %ebp
; X86-NEXT: shrdl %cl, %esi, %edi
; X86-NEXT: testb $32, %cl
; X86-NEXT: cmovnel %edx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: xorl %ecx, %edi
; X86-NEXT: xorl %eax, %esi
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: movl $-1, %eax
; X86-NEXT: movl $0, %ecx
; X86-NEXT: cmovsl %ecx, %eax
; X86-NEXT: sets %dl
; X86-NEXT: addl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-NEXT: orl %edi, %esi
; X86-NEXT: cmovel %ebp, %eax
; X86-NEXT: cmovel %ebx, %edx
; X86-NEXT: cmovnel %ebx, %edi
; X86-NEXT: xorl %eax, %ebp
; X86-NEXT: xorl {{[0-9]+}}(%esp), %edi
; X86-NEXT: sarl $31, %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: xorl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-NEXT: orl %ebp, %edi
; X86-NEXT: notl %eax
; X86-NEXT: cmovel (%esp), %eax # 4-byte Folded Reload
; X86-NEXT: cmovel %esi, %edx
; X86-NEXT: addl $4, %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx