OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity

[VENTUS][feat] Support varadic function && enable address space in vastart/vaend

This commit is contained in:
zhoujing 2023-08-08 15:45:41 +08:00
parent e68d50e833
commit 198eea9938
5 changed files with 22 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
clang/lib/Basic/Targets/RISCV.cpp
View File

@ -48,22 +48,12 @@ void RISCVTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
TargetInfo::adjust(Diags, Opts);
llvm::Triple Triple = getTriple();
bool isRV32 = Triple.isRISCV32();
// Not OpenCL language, we no not need special data layout
if ((Opts.C99 || Opts.C11 || Opts.C17) && !Opts.OpenCL) {
if(isRV32)
resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
else
resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
}
// Only OpenCL language needs special address mapping
else {
UseAddrSpaceMapMangling = true;
AddrSpaceMap = &VentusAddrSpaceMap;
if(isRV32)
resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128-A5-G1");
else
resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128-A5-G1");
}
UseAddrSpaceMapMangling = true;
AddrSpaceMap = &VentusAddrSpaceMap;
if(isRV32)
resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128-A5-G1");
else
resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128-A5-G1");
}

1
clang/lib/Basic/Targets/RISCV.h
View File

@ -134,6 +134,7 @@ public:
Opts["cl_khr_3d_image_writes"] = true;
Opts["cl_khr_byte_addressable_store"] = true;
Opts["cl_khr_fp64"] = true;
Opts["__cl_clang_variadic_functions"] = true;
}
LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {

4
clang/lib/CodeGen/CGBuiltin.cpp
View File

@ -738,8 +738,8 @@ EncompassingIntegerType(ArrayRef<struct WidthAndSignedness> Types) {
Value *CodeGenFunction::EmitVAStartEnd(Value *ArgValue, bool IsStart) {
llvm::Type *DestType = Int8PtrTy;
if (ArgValue->getType() != DestType)
ArgValue =
Builder.CreateBitCast(ArgValue, DestType, ArgValue->getName().data());
ArgValue = Builder.CreatePointerBitCastOrAddrSpaceCast(
ArgValue, DestType, ArgValue->getName().data());
Intrinsic::ID inst = IsStart ? Intrinsic::vastart : Intrinsic::vaend;
return Builder.CreateCall(CGM.getIntrinsic(inst), ArgValue);

24
clang/test/CodeGen/RISCV/riscv-vararg.c
View File

@ -1,21 +1,23 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -S -emit-llvm -mllvm -riscv-common-data-layout \
// RUN: %clang_cc1 -triple riscv32 -S -emit-llvm \
// RUN: %s -o - | FileCheck --check-prefix=CHECK-RV32 %s
// CHECK-RV32-LABEL: @test_vararg(
// CHECK-RV32-NEXT: entry:
// CHECK-RV32-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4
// CHECK-RV32-NEXT: [[VA:%.*]] = alloca ptr, align 4
// CHECK-RV32-NEXT: [[RETVAL1:%.*]] = alloca i32, align 4
// CHECK-RV32-NEXT: store ptr [[FMT:%.*]], ptr [[FMT_ADDR]], align 4
// CHECK-RV32-NEXT: call void @llvm.va_start(ptr [[VA]])
// CHECK-RV32-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
// CHECK-RV32-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4, addrspace(5)
// CHECK-RV32-NEXT: [[VA:%.*]] = alloca ptr, align 4, addrspace(5)
// CHECK-RV32-NEXT: [[RETVAL2:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-RV32-NEXT: store ptr [[FMT:%.*]], ptr addrspace(5) [[FMT_ADDR]], align 4
// CHECK-RV32-NEXT: [[VA1:%.*]] = addrspacecast ptr addrspace(5) [[VA]] to ptr
// CHECK-RV32-NEXT: call void @llvm.va_start(ptr [[VA1]])
// CHECK-RV32-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr addrspace(5) [[VA]], align 4
// CHECK-RV32-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
// CHECK-RV32-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
// CHECK-RV32-NEXT: store ptr [[ARGP_NEXT]], ptr addrspace(5) [[VA]], align 4
// CHECK-RV32-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
// CHECK-RV32-NEXT: store i32 [[TMP0]], ptr [[RETVAL1]], align 4
// CHECK-RV32-NEXT: call void @llvm.va_end(ptr [[VA]])
// CHECK-RV32-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL1]], align 4
// CHECK-RV32-NEXT: store i32 [[TMP0]], ptr addrspace(5) [[RETVAL2]], align 4
// CHECK-RV32-NEXT: [[VA3:%.*]] = addrspacecast ptr addrspace(5) [[VA]] to ptr
// CHECK-RV32-NEXT: call void @llvm.va_end(ptr [[VA3]])
// CHECK-RV32-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[RETVAL2]], align 4
// CHECK-RV32-NEXT: ret i32 [[TMP1]]
//
int test_vararg(char *fmt,...) {

11
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View File

@ -54,11 +54,6 @@ static cl::opt<bool>
cl::desc("Enable the machine combiner pass"),
cl::init(true), cl::Hidden);
static cl::opt<bool> EnableCommonDataLayout(
"riscv-common-data-layout",
cl::desc("Enable the common data layout for other language(not OpenCL)"),
cl::init(false), cl::Hidden);
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@ -77,12 +72,6 @@ static StringRef computeDataLayout(const Triple &TT, StringRef CPU) {
// return "e-m:e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256"
// "-v256:256-v512:512-v1024:1024-n32:64-S128-A5-G1";
bool IsRV32 = TT.isRISCV32();
if (EnableCommonDataLayout) {
if(IsRV32)
return "e-m:e-p:32:32-i64:64-n32-S128";
else
return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
}
if(!IsRV32)
return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128-A5-G1";
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");