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[VENTUS][fix]Fix missing regext instruction for vmsle instruction 

This bug caused PseudoVMSLT_VI node didn't insert regext.
Now OPENCL-CTS relationals test passed.
This commit is contained in:
ziliangzl 2024-05-21 17:09:48 +08:00
parent 9d966660b6
commit 11b55acb48
1 changed files with 4 additions and 3 deletions
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7
llvm/lib/Target/RISCV/VentusRegextInsertion.cpp
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@ -13,6 +13,7 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h" #include "RISCV.h"
#include "RISCVInstrInfo.h" #include "RISCVInstrInfo.h"
#include "RISCVTargetMachine.h" #include "RISCVTargetMachine.h"
@ -75,7 +76,7 @@ bool VentusRegextInsertion::insertRegext(MachineBasicBlock &MBB,
MachineInstr &MI) { MachineInstr &MI) {
bool hasOverflow = false; bool hasOverflow = false;
if (MI.isPseudo()) if (MI.isPseudo() && RISCVII::isVOPIMM11(MI.getDesc().TSFlags))
return false; return false;
// 3 bits encoding for each rd, rs1, rs2, rs3, total 12 bits. // 3 bits encoding for each rd, rs1, rs2, rs3, total 12 bits.
@ -86,7 +87,7 @@ bool VentusRegextInsertion::insertRegext(MachineBasicBlock &MBB,
MachineOperand &Op = MI.getOperand(i); MachineOperand &Op = MI.getOperand(i);
if (!Op.isReg() || if (!Op.isReg() ||
MI.getDesc().getOperandConstraint(i, MCOI::TIED_TO) != -1 || MI.getDesc().getOperandConstraint(i, MCOI::TIED_TO) != -1 ||
MI.isDebugInstr() || MI.isPseudo()) MI.isDebugInstr())
continue; continue;
uint16_t RegEncodingValue = TRI->getEncodingValue(Op.getReg()); uint16_t RegEncodingValue = TRI->getEncodingValue(Op.getReg());
@ -120,4 +121,4 @@ namespace llvm {
FunctionPass *createVentusRegextInsertionPass() { FunctionPass *createVentusRegextInsertionPass() {
return new VentusRegextInsertion(); return new VentusRegextInsertion();
} }
} // end of namespace llvm } // end of namespace llvm