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[IRCE] Bail out if AddRec in icmp is for another loop (PR58912) 

When IRCE runs on outer loop and sees a check of an AddRec of
inner loop, it crashes with an assert in SCEV that the AddRec
must be loop invariant.
This adds a bail out if the AddRec which is checked in icmp
is for another loop.

Fixes https://github.com/llvm/llvm-project/issues/58912.

Differential Revision: https://reviews.llvm.org/D137822
This commit is contained in:
Dmitry Makogon 2022-11-11 16:49:48 +07:00
parent 3b75979806
commit 10ab29ec6e
2 changed files with 33 additions and 1 deletions
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4
llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
View File

@ -845,6 +845,10 @@ LoopStructure::parseLoopStructure(ScalarEvolution &SE, Loop &L,
// induction variable satisfies some constraint.
const SCEVAddRecExpr *IndVarBase = cast<SCEVAddRecExpr>(LeftSCEV);
if (IndVarBase->getLoop() != &L) {
FailureReason = "LHS in cmp is not an AddRec for this loop";
return None;
}
if (!IndVarBase->isAffine()) {
FailureReason = "LHS in icmp not induction variable";
return None;

30
llvm/test/Transforms/IRCE/iv-for-another-loop.ll
View File

@ -1,12 +1,40 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -irce -irce-print-changed-loops=true < %s | FileCheck %s
; RUN: opt -S -passes=irce -irce-print-changed-loops=true < %s | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
target triple = "x86_64-unknown-linux-gnu"
; REQUIRES: asserts
; XFAIL: *
define void @test() {
; CHECK-LABEL: @test(
; CHECK-NEXT: bb:
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
; CHECK: outer_latch:
; CHECK-NEXT: [[TMP:%.*]] = or i32 [[TMP5:%.*]], 1
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP5]], 1
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP8:%.*]], 0
; CHECK-NEXT: br i1 [[TMP3]], label [[RET2:%.*]], label [[OUTER_HEADER]]
; CHECK: outer_header:
; CHECK-NEXT: [[TMP5]] = phi i32 [ 0, [[BB:%.*]] ], [ [[TMP2]], [[OUTER_LATCH:%.*]] ]
; CHECK-NEXT: br label [[INNER_HEADER:%.*]]
; CHECK: inner_exit:
; CHECK-NEXT: [[TMP12_LCSSA:%.*]] = phi i32 [ [[TMP12:%.*]], [[INNER_HEADER]] ]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP12_LCSSA]], [[TMP5]]
; CHECK-NEXT: [[TMP8]] = add nuw i32 [[TMP12_LCSSA]], [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP5]], 0
; CHECK-NEXT: br i1 [[TMP9]], label [[OUTER_LATCH]], label [[RET1:%.*]]
; CHECK: ret1:
; CHECK-NEXT: ret void
; CHECK: inner_header:
; CHECK-NEXT: [[TMP12]] = phi i32 [ [[TMP14:%.*]], [[INNER_HEADER]] ], [ 0, [[OUTER_HEADER]] ]
; CHECK-NEXT: [[TMP13:%.*]] = or i32 [[TMP12]], 1
; CHECK-NEXT: [[TMP14]] = add nuw nsw i32 [[TMP12]], 1
; CHECK-NEXT: br i1 true, label [[INNER_EXIT:%.*]], label [[INNER_HEADER]]
; CHECK: ret2:
; CHECK-NEXT: ret void
;
bb:
br label %outer_header