Move GetControlFlowKind's logic to DisassemblerLLVMC.cpp
This diff move the logic of `GetControlFlowKind()` from Disassembler.cpp to DisassemblerLLVMC.cpp. Here's details: - Actual logic of GetControlFlowKind() move to `DisassemblerLLVMC.cpp`, and we can check underlying architecture using `DisassemblerScope` there. - With this change, passing 'triple' to `GetControlFlowKind()` is no more required. Reviewed By: wallace Differential Revision: https://reviews.llvm.org/D130320
This commit is contained in:
Walter Erquinigo
parent
4f676c2599
commit
0538e5431a
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@ -83,7 +83,10 @@ public:
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/// The control flow kind of this instruction, or
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/// eInstructionControlFlowKindUnknown if the instruction
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/// can't be classified.
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lldb::InstructionControlFlowKind GetControlFlowKind(const ArchSpec &arch);
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virtual lldb::InstructionControlFlowKind
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GetControlFlowKind(const ExecutionContext *exe_ctx) {
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return lldb::eInstructionControlFlowKindUnknown;
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}
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virtual void
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CalculateMnemonicOperandsAndComment(const ExecutionContext *exe_ctx) = 0;
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@ -571,334 +571,6 @@ Instruction::Instruction(const Address &address, AddressClass addr_class)
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Instruction::~Instruction() = default;
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namespace x86 {
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/// These are the three values deciding instruction control flow kind.
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/// InstructionLengthDecode function decodes an instruction and get this struct.
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///
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/// primary_opcode
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/// Primary opcode of the instruction.
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/// For one-byte opcode instruction, it's the first byte after prefix.
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/// For two- and three-byte opcodes, it's the second byte.
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///
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/// opcode_len
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/// The length of opcode in bytes. Valid opcode lengths are 1, 2, or 3.
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///
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/// modrm
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/// ModR/M byte of the instruction.
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/// Bits[7:6] indicate MOD. Bits[5:3] specify a register and R/M bits[2:0]
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/// may contain a register or specify an addressing mode, depending on MOD.
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struct InstructionOpcodeAndModrm {
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uint8_t primary_opcode;
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uint8_t opcode_len;
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uint8_t modrm;
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};
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/// Determine the InstructionControlFlowKind based on opcode and modrm bytes.
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/// Refer to http://ref.x86asm.net/coder.html for the full list of opcode and
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/// instruction set.
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///
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/// \param[in] opcode_and_modrm
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/// Contains primary_opcode byte, its length, and ModR/M byte.
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/// Refer to the struct InstructionOpcodeAndModrm for details.
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///
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/// \return
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/// The control flow kind of the instruction or
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/// eInstructionControlFlowKindOther if the instruction doesn't affect
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/// the control flow of the program.
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lldb::InstructionControlFlowKind
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MapOpcodeIntoControlFlowKind(InstructionOpcodeAndModrm opcode_and_modrm) {
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uint8_t opcode = opcode_and_modrm.primary_opcode;
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uint8_t opcode_len = opcode_and_modrm.opcode_len;
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uint8_t modrm = opcode_and_modrm.modrm;
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if (opcode_len > 2)
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return lldb::eInstructionControlFlowKindOther;
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if (opcode >= 0x70 && opcode <= 0x7F) {
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindCondJump;
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else
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return lldb::eInstructionControlFlowKindOther;
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}
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if (opcode >= 0x80 && opcode <= 0x8F) {
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if (opcode_len == 2)
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return lldb::eInstructionControlFlowKindCondJump;
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else
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return lldb::eInstructionControlFlowKindOther;
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}
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switch (opcode) {
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case 0x9A:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarCall;
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break;
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case 0xFF:
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if (opcode_len == 1) {
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uint8_t modrm_reg = (modrm >> 3) & 7;
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if (modrm_reg == 2)
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return lldb::eInstructionControlFlowKindCall;
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else if (modrm_reg == 3)
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return lldb::eInstructionControlFlowKindFarCall;
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else if (modrm_reg == 4)
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return lldb::eInstructionControlFlowKindJump;
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else if (modrm_reg == 5)
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return lldb::eInstructionControlFlowKindFarJump;
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}
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break;
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case 0xE8:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindCall;
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break;
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case 0xCD:
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case 0xCC:
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case 0xCE:
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case 0xF1:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarCall;
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break;
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case 0xCF:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarReturn;
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break;
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case 0xE9:
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case 0xEB:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindJump;
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break;
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case 0xEA:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarJump;
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break;
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case 0xE3:
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case 0xE0:
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case 0xE1:
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case 0xE2:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindCondJump;
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break;
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case 0xC3:
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case 0xC2:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindReturn;
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break;
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case 0xCB:
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case 0xCA:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarReturn;
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break;
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case 0x05:
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case 0x34:
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if (opcode_len == 2)
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return lldb::eInstructionControlFlowKindFarCall;
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break;
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case 0x35:
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case 0x07:
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if (opcode_len == 2)
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return lldb::eInstructionControlFlowKindFarReturn;
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break;
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case 0x01:
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if (opcode_len == 2) {
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switch (modrm) {
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case 0xc1:
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return lldb::eInstructionControlFlowKindFarCall;
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case 0xc2:
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case 0xc3:
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return lldb::eInstructionControlFlowKindFarReturn;
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default:
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break;
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}
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}
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break;
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default:
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break;
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}
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return lldb::eInstructionControlFlowKindOther;
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}
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/// Decode an instruction into opcode, modrm and opcode_len.
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/// Refer to http://ref.x86asm.net/coder.html for the instruction bytes layout.
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/// Opcodes in x86 are generally the first byte of instruction, though two-byte
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/// instructions and prefixes exist. ModR/M is the byte following the opcode
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/// and adds additional information for how the instruction is executed.
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///
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/// \param[in] inst_bytes
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/// Raw bytes of the instruction
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///
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///
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/// \param[in] bytes_len
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/// The length of the inst_bytes array.
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///
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/// \param[in] is_exec_mode_64b
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/// If true, the execution mode is 64 bit.
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///
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/// \return
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/// Returns decoded instruction as struct InstructionOpcodeAndModrm, holding
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/// primary_opcode, opcode_len and modrm byte. Refer to the struct definition
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/// for more details.
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/// Otherwise if the given instruction is invalid, returns None.
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llvm::Optional<InstructionOpcodeAndModrm>
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InstructionLengthDecode(const uint8_t *inst_bytes, int bytes_len,
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bool is_exec_mode_64b) {
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int op_idx = 0;
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bool prefix_done = false;
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InstructionOpcodeAndModrm ret = {0, 0, 0};
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// In most cases, the primary_opcode is the first byte of the instruction
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// but some instructions have a prefix to be skipped for these calculations.
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// The following mapping is inspired from libipt's instruction decoding logic
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// in `src/pt_ild.c`
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while (!prefix_done) {
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if (op_idx >= bytes_len)
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return llvm::None;
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ret.primary_opcode = inst_bytes[op_idx];
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switch (ret.primary_opcode) {
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// prefix_ignore
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case 0x26:
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case 0x2e:
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case 0x36:
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case 0x3e:
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case 0x64:
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case 0x65:
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// prefix_osz, prefix_asz
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case 0x66:
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case 0x67:
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// prefix_lock, prefix_f2, prefix_f3
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case 0xf0:
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case 0xf2:
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case 0xf3:
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op_idx++;
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break;
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// prefix_rex
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x46:
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case 0x47:
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case 0x48:
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case 0x49:
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case 0x4a:
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case 0x4b:
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case 0x4c:
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case 0x4d:
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case 0x4e:
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case 0x4f:
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if (is_exec_mode_64b)
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op_idx++;
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else
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prefix_done = true;
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break;
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// prefix_vex_c4, c5
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case 0xc5:
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if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
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prefix_done = true;
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break;
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}
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ret.opcode_len = 2;
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ret.primary_opcode = inst_bytes[op_idx + 2];
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ret.modrm = inst_bytes[op_idx + 3];
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return ret;
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case 0xc4:
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if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
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prefix_done = true;
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break;
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}
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ret.opcode_len = inst_bytes[op_idx + 1] & 0x1f;
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ret.primary_opcode = inst_bytes[op_idx + 3];
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ret.modrm = inst_bytes[op_idx + 4];
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return ret;
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// prefix_evex
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case 0x62:
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if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
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prefix_done = true;
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break;
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}
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ret.opcode_len = inst_bytes[op_idx + 1] & 0x03;
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ret.primary_opcode = inst_bytes[op_idx + 4];
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ret.modrm = inst_bytes[op_idx + 5];
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return ret;
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default:
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prefix_done = true;
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break;
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}
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} // prefix done
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ret.primary_opcode = inst_bytes[op_idx];
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ret.modrm = inst_bytes[op_idx + 1];
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ret.opcode_len = 1;
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// If the first opcode is 0F, it's two- or three- byte opcodes.
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if (ret.primary_opcode == 0x0F) {
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ret.primary_opcode = inst_bytes[++op_idx]; // get the next byte
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if (ret.primary_opcode == 0x38) {
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ret.opcode_len = 3;
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ret.primary_opcode = inst_bytes[++op_idx]; // get the next byte
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ret.modrm = inst_bytes[op_idx + 1];
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} else if (ret.primary_opcode == 0x3A) {
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ret.opcode_len = 3;
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ret.primary_opcode = inst_bytes[++op_idx];
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ret.modrm = inst_bytes[op_idx + 1];
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} else if ((ret.primary_opcode & 0xf8) == 0x38) {
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ret.opcode_len = 0;
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ret.primary_opcode = inst_bytes[++op_idx];
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ret.modrm = inst_bytes[op_idx + 1];
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} else if (ret.primary_opcode == 0x0F) {
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ret.opcode_len = 3;
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// opcode is 0x0F, no needs to update
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ret.modrm = inst_bytes[op_idx + 1];
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} else {
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ret.opcode_len = 2;
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ret.modrm = inst_bytes[op_idx + 1];
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}
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}
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return ret;
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}
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lldb::InstructionControlFlowKind GetControlFlowKind(bool is_exec_mode_64b,
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Opcode m_opcode) {
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llvm::Optional<InstructionOpcodeAndModrm> ret = llvm::None;
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if (m_opcode.GetOpcodeBytes() == nullptr || m_opcode.GetByteSize() <= 0) {
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// x86_64 and i386 instructions are categorized as Opcode::Type::eTypeBytes
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return lldb::eInstructionControlFlowKindUnknown;
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}
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// Opcode bytes will be decoded into primary_opcode, modrm and opcode length.
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// These are the three values deciding instruction control flow kind.
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ret = InstructionLengthDecode((const uint8_t *)m_opcode.GetOpcodeBytes(),
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m_opcode.GetByteSize(), is_exec_mode_64b);
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if (!ret)
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return lldb::eInstructionControlFlowKindUnknown;
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else
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return MapOpcodeIntoControlFlowKind(ret.value());
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}
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} // namespace x86
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lldb::InstructionControlFlowKind
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Instruction::GetControlFlowKind(const ArchSpec &arch) {
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if (arch.GetTriple().getArch() == llvm::Triple::x86)
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return x86::GetControlFlowKind(/*is_exec_mode_64b=*/false, m_opcode);
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else if (arch.GetTriple().getArch() == llvm::Triple::x86_64)
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return x86::GetControlFlowKind(/*is_exec_mode_64b=*/true, m_opcode);
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else
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return eInstructionControlFlowKindUnknown; // not implemented
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}
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AddressClass Instruction::GetAddressClass() {
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if (m_address_class == AddressClass::eInvalid)
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m_address_class = m_address.GetAddressClass();
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@ -946,7 +618,7 @@ void Instruction::Dump(lldb_private::Stream *s, uint32_t max_opcode_byte_size,
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}
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if (show_control_flow_kind) {
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switch (GetControlFlowKind(exe_ctx->GetTargetRef().GetArchitecture())) {
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switch (GetControlFlowKind(exe_ctx)) {
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case eInstructionControlFlowKindUnknown:
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ss.Printf("%-12s", "unknown");
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break;
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@ -85,6 +85,324 @@ private:
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std::unique_ptr<llvm::MCInstPrinter> m_instr_printer_up;
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};
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namespace x86 {
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/// These are the three values deciding instruction control flow kind.
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/// InstructionLengthDecode function decodes an instruction and get this struct.
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///
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/// primary_opcode
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/// Primary opcode of the instruction.
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/// For one-byte opcode instruction, it's the first byte after prefix.
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/// For two- and three-byte opcodes, it's the second byte.
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///
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/// opcode_len
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/// The length of opcode in bytes. Valid opcode lengths are 1, 2, or 3.
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///
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/// modrm
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/// ModR/M byte of the instruction.
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/// Bits[7:6] indicate MOD. Bits[5:3] specify a register and R/M bits[2:0]
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/// may contain a register or specify an addressing mode, depending on MOD.
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struct InstructionOpcodeAndModrm {
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uint8_t primary_opcode;
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uint8_t opcode_len;
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uint8_t modrm;
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};
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/// Determine the InstructionControlFlowKind based on opcode and modrm bytes.
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/// Refer to http://ref.x86asm.net/coder.html for the full list of opcode and
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/// instruction set.
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///
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/// \param[in] opcode_and_modrm
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/// Contains primary_opcode byte, its length, and ModR/M byte.
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/// Refer to the struct InstructionOpcodeAndModrm for details.
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///
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/// \return
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/// The control flow kind of the instruction or
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/// eInstructionControlFlowKindOther if the instruction doesn't affect
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/// the control flow of the program.
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lldb::InstructionControlFlowKind
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MapOpcodeIntoControlFlowKind(InstructionOpcodeAndModrm opcode_and_modrm) {
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uint8_t opcode = opcode_and_modrm.primary_opcode;
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uint8_t opcode_len = opcode_and_modrm.opcode_len;
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uint8_t modrm = opcode_and_modrm.modrm;
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if (opcode_len > 2)
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return lldb::eInstructionControlFlowKindOther;
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if (opcode >= 0x70 && opcode <= 0x7F) {
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindCondJump;
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else
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return lldb::eInstructionControlFlowKindOther;
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}
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if (opcode >= 0x80 && opcode <= 0x8F) {
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if (opcode_len == 2)
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return lldb::eInstructionControlFlowKindCondJump;
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else
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return lldb::eInstructionControlFlowKindOther;
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}
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switch (opcode) {
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case 0x9A:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarCall;
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break;
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case 0xFF:
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if (opcode_len == 1) {
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uint8_t modrm_reg = (modrm >> 3) & 7;
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if (modrm_reg == 2)
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return lldb::eInstructionControlFlowKindCall;
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else if (modrm_reg == 3)
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return lldb::eInstructionControlFlowKindFarCall;
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else if (modrm_reg == 4)
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return lldb::eInstructionControlFlowKindJump;
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else if (modrm_reg == 5)
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return lldb::eInstructionControlFlowKindFarJump;
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}
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break;
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case 0xE8:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindCall;
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break;
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case 0xCD:
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case 0xCC:
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case 0xCE:
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case 0xF1:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarCall;
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break;
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case 0xCF:
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if (opcode_len == 1)
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return lldb::eInstructionControlFlowKindFarReturn;
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break;
|
||||
case 0xE9:
|
||||
case 0xEB:
|
||||
if (opcode_len == 1)
|
||||
return lldb::eInstructionControlFlowKindJump;
|
||||
break;
|
||||
case 0xEA:
|
||||
if (opcode_len == 1)
|
||||
return lldb::eInstructionControlFlowKindFarJump;
|
||||
break;
|
||||
case 0xE3:
|
||||
case 0xE0:
|
||||
case 0xE1:
|
||||
case 0xE2:
|
||||
if (opcode_len == 1)
|
||||
return lldb::eInstructionControlFlowKindCondJump;
|
||||
break;
|
||||
case 0xC3:
|
||||
case 0xC2:
|
||||
if (opcode_len == 1)
|
||||
return lldb::eInstructionControlFlowKindReturn;
|
||||
break;
|
||||
case 0xCB:
|
||||
case 0xCA:
|
||||
if (opcode_len == 1)
|
||||
return lldb::eInstructionControlFlowKindFarReturn;
|
||||
break;
|
||||
case 0x05:
|
||||
case 0x34:
|
||||
if (opcode_len == 2)
|
||||
return lldb::eInstructionControlFlowKindFarCall;
|
||||
break;
|
||||
case 0x35:
|
||||
case 0x07:
|
||||
if (opcode_len == 2)
|
||||
return lldb::eInstructionControlFlowKindFarReturn;
|
||||
break;
|
||||
case 0x01:
|
||||
if (opcode_len == 2) {
|
||||
switch (modrm) {
|
||||
case 0xc1:
|
||||
return lldb::eInstructionControlFlowKindFarCall;
|
||||
case 0xc2:
|
||||
case 0xc3:
|
||||
return lldb::eInstructionControlFlowKindFarReturn;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return lldb::eInstructionControlFlowKindOther;
|
||||
}
|
||||
|
||||
/// Decode an instruction into opcode, modrm and opcode_len.
|
||||
/// Refer to http://ref.x86asm.net/coder.html for the instruction bytes layout.
|
||||
/// Opcodes in x86 are generally the first byte of instruction, though two-byte
|
||||
/// instructions and prefixes exist. ModR/M is the byte following the opcode
|
||||
/// and adds additional information for how the instruction is executed.
|
||||
///
|
||||
/// \param[in] inst_bytes
|
||||
/// Raw bytes of the instruction
|
||||
///
|
||||
///
|
||||
/// \param[in] bytes_len
|
||||
/// The length of the inst_bytes array.
|
||||
///
|
||||
/// \param[in] is_exec_mode_64b
|
||||
/// If true, the execution mode is 64 bit.
|
||||
///
|
||||
/// \return
|
||||
/// Returns decoded instruction as struct InstructionOpcodeAndModrm, holding
|
||||
/// primary_opcode, opcode_len and modrm byte. Refer to the struct definition
|
||||
/// for more details.
|
||||
/// Otherwise if the given instruction is invalid, returns None.
|
||||
llvm::Optional<InstructionOpcodeAndModrm>
|
||||
InstructionLengthDecode(const uint8_t *inst_bytes, int bytes_len,
|
||||
bool is_exec_mode_64b) {
|
||||
int op_idx = 0;
|
||||
bool prefix_done = false;
|
||||
InstructionOpcodeAndModrm ret = {0, 0, 0};
|
||||
|
||||
// In most cases, the primary_opcode is the first byte of the instruction
|
||||
// but some instructions have a prefix to be skipped for these calculations.
|
||||
// The following mapping is inspired from libipt's instruction decoding logic
|
||||
// in `src/pt_ild.c`
|
||||
while (!prefix_done) {
|
||||
if (op_idx >= bytes_len)
|
||||
return llvm::None;
|
||||
|
||||
ret.primary_opcode = inst_bytes[op_idx];
|
||||
switch (ret.primary_opcode) {
|
||||
// prefix_ignore
|
||||
case 0x26:
|
||||
case 0x2e:
|
||||
case 0x36:
|
||||
case 0x3e:
|
||||
case 0x64:
|
||||
case 0x65:
|
||||
// prefix_osz, prefix_asz
|
||||
case 0x66:
|
||||
case 0x67:
|
||||
// prefix_lock, prefix_f2, prefix_f3
|
||||
case 0xf0:
|
||||
case 0xf2:
|
||||
case 0xf3:
|
||||
op_idx++;
|
||||
break;
|
||||
|
||||
// prefix_rex
|
||||
case 0x40:
|
||||
case 0x41:
|
||||
case 0x42:
|
||||
case 0x43:
|
||||
case 0x44:
|
||||
case 0x45:
|
||||
case 0x46:
|
||||
case 0x47:
|
||||
case 0x48:
|
||||
case 0x49:
|
||||
case 0x4a:
|
||||
case 0x4b:
|
||||
case 0x4c:
|
||||
case 0x4d:
|
||||
case 0x4e:
|
||||
case 0x4f:
|
||||
if (is_exec_mode_64b)
|
||||
op_idx++;
|
||||
else
|
||||
prefix_done = true;
|
||||
break;
|
||||
|
||||
// prefix_vex_c4, c5
|
||||
case 0xc5:
|
||||
if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
|
||||
prefix_done = true;
|
||||
break;
|
||||
}
|
||||
|
||||
ret.opcode_len = 2;
|
||||
ret.primary_opcode = inst_bytes[op_idx + 2];
|
||||
ret.modrm = inst_bytes[op_idx + 3];
|
||||
return ret;
|
||||
|
||||
case 0xc4:
|
||||
if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
|
||||
prefix_done = true;
|
||||
break;
|
||||
}
|
||||
ret.opcode_len = inst_bytes[op_idx + 1] & 0x1f;
|
||||
ret.primary_opcode = inst_bytes[op_idx + 3];
|
||||
ret.modrm = inst_bytes[op_idx + 4];
|
||||
return ret;
|
||||
|
||||
// prefix_evex
|
||||
case 0x62:
|
||||
if (!is_exec_mode_64b && (inst_bytes[op_idx + 1] & 0xc0) != 0xc0) {
|
||||
prefix_done = true;
|
||||
break;
|
||||
}
|
||||
ret.opcode_len = inst_bytes[op_idx + 1] & 0x03;
|
||||
ret.primary_opcode = inst_bytes[op_idx + 4];
|
||||
ret.modrm = inst_bytes[op_idx + 5];
|
||||
return ret;
|
||||
|
||||
default:
|
||||
prefix_done = true;
|
||||
break;
|
||||
}
|
||||
} // prefix done
|
||||
|
||||
ret.primary_opcode = inst_bytes[op_idx];
|
||||
ret.modrm = inst_bytes[op_idx + 1];
|
||||
ret.opcode_len = 1;
|
||||
|
||||
// If the first opcode is 0F, it's two- or three- byte opcodes.
|
||||
if (ret.primary_opcode == 0x0F) {
|
||||
ret.primary_opcode = inst_bytes[++op_idx]; // get the next byte
|
||||
|
||||
if (ret.primary_opcode == 0x38) {
|
||||
ret.opcode_len = 3;
|
||||
ret.primary_opcode = inst_bytes[++op_idx]; // get the next byte
|
||||
ret.modrm = inst_bytes[op_idx + 1];
|
||||
} else if (ret.primary_opcode == 0x3A) {
|
||||
ret.opcode_len = 3;
|
||||
ret.primary_opcode = inst_bytes[++op_idx];
|
||||
ret.modrm = inst_bytes[op_idx + 1];
|
||||
} else if ((ret.primary_opcode & 0xf8) == 0x38) {
|
||||
ret.opcode_len = 0;
|
||||
ret.primary_opcode = inst_bytes[++op_idx];
|
||||
ret.modrm = inst_bytes[op_idx + 1];
|
||||
} else if (ret.primary_opcode == 0x0F) {
|
||||
ret.opcode_len = 3;
|
||||
// opcode is 0x0F, no needs to update
|
||||
ret.modrm = inst_bytes[op_idx + 1];
|
||||
} else {
|
||||
ret.opcode_len = 2;
|
||||
ret.modrm = inst_bytes[op_idx + 1];
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
lldb::InstructionControlFlowKind GetControlFlowKind(bool is_exec_mode_64b,
|
||||
Opcode m_opcode) {
|
||||
llvm::Optional<InstructionOpcodeAndModrm> ret = llvm::None;
|
||||
|
||||
if (m_opcode.GetOpcodeBytes() == nullptr || m_opcode.GetByteSize() <= 0) {
|
||||
// x86_64 and i386 instructions are categorized as Opcode::Type::eTypeBytes
|
||||
return lldb::eInstructionControlFlowKindUnknown;
|
||||
}
|
||||
|
||||
// Opcode bytes will be decoded into primary_opcode, modrm and opcode length.
|
||||
// These are the three values deciding instruction control flow kind.
|
||||
ret = InstructionLengthDecode((const uint8_t *)m_opcode.GetOpcodeBytes(),
|
||||
m_opcode.GetByteSize(), is_exec_mode_64b);
|
||||
if (!ret)
|
||||
return lldb::eInstructionControlFlowKindUnknown;
|
||||
else
|
||||
return MapOpcodeIntoControlFlowKind(ret.value());
|
||||
}
|
||||
|
||||
} // namespace x86
|
||||
|
||||
class InstructionLLVMC : public lldb_private::Instruction {
|
||||
public:
|
||||
InstructionLLVMC(DisassemblerLLVMC &disasm,
|
||||
|
|
@ -223,6 +541,19 @@ public:
|
|||
}
|
||||
}
|
||||
|
||||
lldb::InstructionControlFlowKind
|
||||
GetControlFlowKind(const lldb_private::ExecutionContext *exe_ctx) override {
|
||||
DisassemblerScope disasm(*this, exe_ctx);
|
||||
if (disasm){
|
||||
if (disasm->GetArchitecture().GetMachine() == llvm::Triple::x86)
|
||||
return x86::GetControlFlowKind(/*is_64b=*/false, m_opcode);
|
||||
else if (disasm->GetArchitecture().GetMachine() == llvm::Triple::x86_64)
|
||||
return x86::GetControlFlowKind(/*is_64b=*/true, m_opcode);
|
||||
}
|
||||
|
||||
return eInstructionControlFlowKindUnknown;
|
||||
}
|
||||
|
||||
void CalculateMnemonicOperandsAndComment(
|
||||
const lldb_private::ExecutionContext *exe_ctx) override {
|
||||
DataExtractor data;
|
||||
|
|
|
|||
|
|
@ -137,7 +137,8 @@ TEST_F(TestGetControlFlowKindx86, TestX86_64Instruction) {
|
|||
for (size_t i = 0; i < num_of_instructions; ++i) {
|
||||
InstructionSP inst_sp;
|
||||
inst_sp = inst_list.GetInstructionAtIndex(i);
|
||||
InstructionControlFlowKind kind = inst_sp->GetControlFlowKind(arch);
|
||||
ExecutionContext exe_ctx (nullptr, nullptr, nullptr);
|
||||
InstructionControlFlowKind kind = inst_sp->GetControlFlowKind(&exe_ctx);
|
||||
EXPECT_EQ(kind, result[i]);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue