OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 2
Code Issues Packages Projects Releases Wiki Activity

AMDGPU/GlobalISel: Fix introducing f16 fmed3 for gfx8

This commit is contained in:
Matt Arsenault 2022-01-18 20:46:51 -05:00
parent 4f89157b9d
commit 052503979e
2 changed files with 137 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
View File

@ -36,6 +36,7 @@ protected:
MachineIRBuilder &B;
MachineFunction &MF;
MachineRegisterInfo &MRI;
const GCNSubtarget &Subtarget;
const RegisterBankInfo &RBI;
const TargetRegisterInfo &TRI;
const SIInstrInfo &TII;
@ -44,9 +45,9 @@ protected:
public:
AMDGPURegBankCombinerHelper(MachineIRBuilder &B, CombinerHelper &Helper)
: B(B), MF(B.getMF()), MRI(*B.getMRI()),
RBI(*MF.getSubtarget().getRegBankInfo()),
TRI(*MF.getSubtarget().getRegisterInfo()),
TII(*MF.getSubtarget<GCNSubtarget>().getInstrInfo()), Helper(Helper){};
Subtarget(MF.getSubtarget<GCNSubtarget>()),
RBI(*Subtarget.getRegBankInfo()), TRI(*Subtarget.getRegisterInfo()),
TII(*Subtarget.getInstrInfo()), Helper(Helper){};
bool isVgprRegBank(Register Reg);
Register getAsVgpr(Register Reg);
@ -193,7 +194,10 @@ bool AMDGPURegBankCombinerHelper::matchFPMinMaxToMed3(
MachineInstr &MI, Med3MatchInfo &MatchInfo) {
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
if (Ty != LLT::scalar(16) && Ty != LLT::scalar(32))
// med3 for f16 is only available on gfx9+, and not available for v2f16.
if ((Ty != LLT::scalar(16) || !Subtarget.hasMed3_16()) &&
Ty != LLT::scalar(32))
return false;
auto OpcodeTriple = getMinMaxPair(MI.getOpcode());

129
llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
View File

@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-LABEL: test_min_max_ValK0_K1_f32:
@ -8,6 +9,12 @@ define float @test_min_max_ValK0_K1_f32(float %a) #0 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_ValK0_K1_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan float @llvm.maxnum.f32(float %a, float 2.0)
%fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 4.0)
ret float %fmed
@ -20,6 +27,12 @@ define float @test_min_max_K0Val_K1_f32(float %a) #1 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_K0Val_K1_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan float @llvm.maxnum.f32(float 2.0, float %a)
%fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 4.0)
ret float %fmed
@ -35,6 +48,14 @@ define half @test_min_K1max_ValK0_f16(half %a) #0 {
; GFX10-NEXT: v_max_f16_e32 v0, v0, v0
; GFX10-NEXT: v_med3_f16 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_K1max_ValK0_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call half @llvm.maxnum.f16(half %a, half 2.0)
%fmed = call half @llvm.minnum.f16(half 4.0, half %maxnum)
ret half %fmed
@ -47,6 +68,13 @@ define half @test_min_K1max_K0Val_f16(half %a) #1 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f16 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_K1max_K0Val_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan half @llvm.maxnum.f16(half 2.0, half %a)
%fmed = call nnan half @llvm.minnum.f16(half 4.0, half %maxnum)
ret half %fmed
@ -60,6 +88,12 @@ define float @test_max_min_ValK1_K0_f32(float %a) #0 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_min_ValK1_K0_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan float @llvm.minnum.f32(float %a, float 4.0)
%fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 2.0)
ret float %fmed
@ -72,6 +106,12 @@ define float @test_max_min_K1Val_K0_f32(float %a) #1 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_min_K1Val_K0_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan float @llvm.minnum.f32(float 4.0, float %a)
%fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 2.0)
ret float %fmed
@ -84,6 +124,13 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f16 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_K0min_ValK1_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0
; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan half @llvm.minnum.f16(half %a, half 4.0)
%fmed = call nnan half @llvm.maxnum.f16(half 2.0, half %minnum)
ret half %fmed
@ -96,6 +143,13 @@ define half @test_max_K0min_K1Val_f16(half %a) #1 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f16 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_K0min_K1Val_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0
; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan half @llvm.minnum.f16(half 4.0, half %a)
%fmed = call nnan half @llvm.maxnum.f16(half 2.0, half %minnum)
ret half %fmed
@ -110,6 +164,12 @@ define float @test_min_max_global_nnan(float %a) #2 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_global_nnan:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call float @llvm.maxnum.f32(float %a, float 2.0)
%fmed = call float @llvm.minnum.f32(float %maxnum, float 4.0)
ret float %fmed
@ -122,6 +182,12 @@ define float @test_max_min_global_nnan(float %a) #2 {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_min_global_nnan:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call float @llvm.minnum.f32(float %a, float 4.0)
%fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0)
ret float %fmed
@ -140,6 +206,13 @@ define float @test_min_max_K0_gt_K1(float %a) #0 {
; GFX10-NEXT: v_max_f32_e32 v0, 4.0, v0
; GFX10-NEXT: v_min_f32_e32 v0, 2.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_K0_gt_K1:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f32_e32 v0, 4.0, v0
; GFX8-NEXT: v_min_f32_e32 v0, 2.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan float @llvm.maxnum.f32(float %a, float 4.0)
%fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 2.0)
ret float %fmed
@ -154,6 +227,13 @@ define float @test_max_min_K0_gt_K1(float %a) #0 {
; GFX10-NEXT: v_min_f32_e32 v0, 2.0, v0
; GFX10-NEXT: v_max_f32_e32 v0, 4.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_min_K0_gt_K1:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f32_e32 v0, 2.0, v0
; GFX8-NEXT: v_max_f32_e32 v0, 4.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call nnan float @llvm.minnum.f32(float %a, float 2.0)
%fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 4.0)
ret float %fmed
@ -168,6 +248,13 @@ define float @test_min_max_non_inline_const(float %a) #0 {
; GFX10-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX10-NEXT: v_min_f32_e32 v0, 0x41000000, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_non_inline_const:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX8-NEXT: v_min_f32_e32 v0, 0x41000000, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan float @llvm.maxnum.f32(float %a, float 2.0)
%fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 8.0)
ret float %fmed
@ -183,6 +270,13 @@ define double @test_min_max_f64(double %a) #0 {
; GFX10-NEXT: v_max_f64 v[0:1], v[0:1], 2.0
; GFX10-NEXT: v_min_f64 v[0:1], v[0:1], 4.0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], 2.0
; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], 4.0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan double @llvm.maxnum.f64(double %a, double 2.0)
%fmed = call nnan double @llvm.minnum.f64(double %maxnum, double 4.0)
ret double %fmed
@ -196,6 +290,19 @@ define <2 x half> @test_min_max_v2f16(<2 x half> %a) #0 {
; GFX10-NEXT: v_pk_max_f16 v0, v0, 2.0 op_sel_hi:[1,0]
; GFX10-NEXT: v_pk_min_f16 v0, v0, 4.0 op_sel_hi:[1,0]
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_v2f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 0x4000
; GFX8-NEXT: v_max_f16_e32 v1, 2.0, v0
; GFX8-NEXT: v_max_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 16
; GFX8-NEXT: v_min_f16_e32 v1, 4.0, v1
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call nnan <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half 2.0, half 2.0>)
%fmed = call nnan <2 x half> @llvm.minnum.v2f16(<2 x half> %maxnum, <2 x half> <half 4.0, half 4.0>)
ret <2 x half> %fmed
@ -212,6 +319,13 @@ define float @test_min_max_maybe_NaN_input_ieee_false(float %a) #1 {
; GFX10-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX10-NEXT: v_min_f32_e32 v0, 4.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_min_max_maybe_NaN_input_ieee_false:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX8-NEXT: v_min_f32_e32 v0, 4.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%maxnum = call float @llvm.maxnum.f32(float %a, float 2.0)
%fmed = call float @llvm.minnum.f32(float %maxnum, float 4.0)
ret float %fmed
@ -227,6 +341,13 @@ define float @test_max_min_maybe_NaN_input_ieee_false(float %a) #1 {
; GFX10-NEXT: v_min_f32_e32 v0, 4.0, v0
; GFX10-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_min_maybe_NaN_input_ieee_false:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_f32_e32 v0, 4.0, v0
; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call float @llvm.minnum.f32(float %a, float 4.0)
%fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0)
ret float %fmed
@ -242,6 +363,14 @@ define float @test_max_min_maybe_NaN_input_ieee_true(float %a) #0 {
; GFX10-NEXT: v_min_f32_e32 v0, 4.0, v0
; GFX10-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_max_min_maybe_NaN_input_ieee_true:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX8-NEXT: v_min_f32_e32 v0, 4.0, v0
; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
%minnum = call float @llvm.minnum.f32(float %a, float 4.0)
%fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0)
ret float %fmed