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[DAG] Extract helper for (neg x) [nfc] 

This is a frequently reoccurring pattern, let's factor it out.

Differential Revision: https://reviews.llvm.org/D135301
This commit is contained in:
Philip Reames 2022-10-06 13:10:58 -07:00 committed by Philip Reames
parent 9dd0476293
commit 04bb32e58a
5 changed files with 17 additions and 17 deletions
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3
llvm/include/llvm/CodeGen/SelectionDAG.h
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@ -926,6 +926,9 @@ public:
/// BooleanContent for type OpVT or truncating it.
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);
/// Create negative operation as (SUB 0, Val).
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT);
/// Create a bitwise NOT operation as (XOR Val, -1).
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);

15
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3981,8 +3981,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
// fold (mul x, -1) -> 0-x
if (N1IsConst && ConstValue1.isAllOnes())
return DAG.getNode(ISD::SUB, DL, VT,
DAG.getConstant(0, DL, VT), N0);
return DAG.getNegative(N0, DL, VT);
// fold (mul x, (1 << c)) -> x << c
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
@ -4049,7 +4048,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
DAG.getConstant(TZeros, DL, VT)))
: DAG.getNode(MathOp, DL, VT, Shl, N0);
if (ConstValue1.isNegative())
R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
R = DAG.getNegative(R, DL, VT);
return R;
}
}
@ -4303,7 +4302,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
// fold (sdiv X, -1) -> 0-X
ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (N1C && N1C->isAllOnes())
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
return DAG.getNegative(N0, DL, VT);
// fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
if (N1C && N1C->getAPIntValue().isMinSignedValue())
@ -8682,8 +8681,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
// fold (not (add X, -1)) -> (neg X)
if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD &&
isAllOnesOrAllOnesSplat(N0.getOperand(1))) {
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
N0.getOperand(0));
return DAG.getNegative(N0.getOperand(0), DL, VT);
}
// fold (xor (and x, y), y) -> (and (not x), y)
@ -11305,8 +11303,7 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
if (SatCC == ISD::SETUGT && Other.getOpcode() == ISD::ADD &&
ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUSUBSAT,
/*AllowUndefs*/ true)) {
OpRHS = DAG.getNode(ISD::SUB, DL, VT,
DAG.getConstant(0, DL, VT), OpRHS);
OpRHS = DAG.getNegative(OpRHS, DL, VT);
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
}
@ -12394,7 +12391,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND &&
TLI.isOperationLegalOrCustom(ISD::SUB, VT)) {
SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(1).getOperand(0), DL, VT);
return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Zext);
return DAG.getNegative(Zext, DL, VT);
}
// Eliminate this sign extend by doing a decrement in the destination type:
// sext i32 ((zext i8 X to i32) + (-1)) to i64 --> (zext i8 X to i64) + (-1)

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -1461,6 +1461,10 @@ SDValue SelectionDAG::getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
return getZeroExtendInReg(Op, DL, VT);
}
SDValue SelectionDAG::getNegative(SDValue Val, const SDLoc &DL, EVT VT) {
return getNode(ISD::SUB, DL, VT, getConstant(0, DL, VT), Val);
}
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) {
return getNode(ISD::XOR, DL, VT, Val, getAllOnesConstant(DL, VT));

3
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -3421,8 +3421,7 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
Values[i] =
DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i));
if (Negate)
Values[i] = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT),
Values[i]);
Values[i] = DAG.getNegative(Values[i], dl, VT);
}
} else {
for (unsigned i = 0; i != NumValues; ++i) {

9
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -3254,8 +3254,7 @@ static SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
// For CTTZ_ZERO_UNDEF, we need to extract the lowest set bit using X & -X.
// The trailing zero count is equal to log2 of this single bit value.
if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF) {
SDValue Neg =
DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Src);
SDValue Neg = DAG.getNegative(Src, DL, VT);
Src = DAG.getNode(ISD::AND, DL, VT, Src, Neg);
}
@ -8207,8 +8206,7 @@ performSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
DAG.ComputeNumSignBits(Src.getOperand(0)) > 32) {
SDLoc DL(N);
SDValue Freeze = DAG.getFreeze(Src.getOperand(0));
SDValue Neg =
DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, MVT::i64), Freeze);
SDValue Neg = DAG.getNegative(Freeze, DL, VT);
Neg = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Neg,
DAG.getValueType(MVT::i32));
return DAG.getNode(ISD::SMAX, DL, MVT::i64, Freeze, Neg);
@ -9458,8 +9456,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
DAG.getConstant(1, DL, VT));
else
Neg = LHS;
SDValue Mask = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
Neg); // -(and (x, 0x1))
SDValue Mask = DAG.getNegative(Neg, DL, VT); // -x
SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
return DAG.getNode(Opcode, DL, VT, And, Src2); // And Op y
}