UnityChipVerification/rtl/Tage_SC.txt

34 lines
916 B
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./rtl/TageSC/CAMTemplate.sv
./rtl/TageSC/CAMTemplate_32.sv
./rtl/TageSC/CAMTemplate_33.sv
./rtl/TageSC/FoldedSRAMTemplate.sv
./rtl/TageSC/FoldedSRAMTemplate_1.sv
./rtl/TageSC/FoldedSRAMTemplate_20.sv
./rtl/TageSC/SCTable.sv
./rtl/TageSC/SCTable_1.sv
./rtl/TageSC/SCTable_2.sv
./rtl/TageSC/SCTable_3.sv
./rtl/TageSC/SRAMTemplate_14.sv
./rtl/TageSC/SRAMTemplate_15.sv
./rtl/TageSC/SRAMTemplate_34.sv
./rtl/TageSC/SRAMTemplate_35.sv
./rtl/TageSC/TageBTable.sv
./rtl/TageSC/TageTable.sv
./rtl/TageSC/TageTable_1.sv
./rtl/TageSC/TageTable_2.sv
./rtl/TageSC/TageTable_3.sv
./rtl/TageSC/Tage_SC.sv
./rtl/TageSC/array_4.sv
./rtl/TageSC/array_5.sv
./rtl/TageSC/array_6.sv
./rtl/TageSC/array_7.sv
./rtl/TageSC/data_mem_0_8x3.sv
./rtl/TageSC/data_mem_16x12.sv
./rtl/TageSC/data_mem_8x4.sv
#
./rtl/WrBypass/WrBypass.sv
./rtl/WrBypass/WrBypass_32.sv
./rtl/WrBypass/WrBypass_33.sv
./rtl/common/ext_sram.v
./rtl/common/DelayN_2.sv