commit d68baa43d18d0673cb18413d6212ce712d4ef280 Author: DawnMagnet Date: Mon Aug 8 15:54:26 2022 +0800 first commit diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..dd37921 --- /dev/null +++ b/.cproject @@ -0,0 +1,170 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.project b/.project new file mode 100644 index 0000000..4b38aff --- /dev/null +++ b/.project @@ -0,0 +1,37 @@ + + + JSInterpreter-TencentOS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..34a20f5 --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..abb7fd1 --- /dev/null +++ b/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,73 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"\u5B57\u6BB5\u65E0\u6CD5\u88AB\u89E3\u6790\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"\u51FD\u6570\u65E0\u6CD5\u88AB\u89E3\u6790\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"\u65E0\u6548\u53C2\u6570\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"\u65B9\u6CD5\u65E0\u6CD5\u88AB\u89E3\u6790\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"\u672A\u4F7F\u7528\u7684\u9759\u6001\u51FD\u6570\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} diff --git a/.template b/.template new file mode 100644 index 0000000..5fb446f --- /dev/null +++ b/.template @@ -0,0 +1,18 @@ +Target Path=obj\JSInterpreter-TencentOS.hex +Address=0x08000000 +Erase All=true +Program=true +Verify=true +Reset=true + +Toolchain=RISC-V +Series=CH32V307 +Description=TencentOS is a series of operating systems independently developed by Tencent, mainly including TS (TencentOS server operating system), TT (TencentOS tiny Internet of things operating system) and te (TencentOS edge computing operating system). It provides a full stack OS layout based on business scenarios for the three subsystems of computing storage network (cloud data center, edge and Internet of things) + +PeripheralVersion=1.7 + + +Vendor=WCH +MCU=CH32V307WCU6 +Mcu Type=CH32V30x +Link=WCH-Link diff --git a/Core/core_riscv.c b/Core/core_riscv.c new file mode 100644 index 0000000..88f4dac --- /dev/null +++ b/Core/core_riscv.c @@ -0,0 +1,419 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : RISC-V Core Peripheral Access Layer Source File +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/********************************************************************* + * @fn __get_FFLAGS + * + * @brief Return the Floating-Point Accrued Exceptions + * + * @return fflags value + */ +uint32_t __get_FFLAGS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FFLAGS + * + * @brief Set the Floating-Point Accrued Exceptions + * + * @param value - set FFLAGS value + * + * @return none + */ +void __set_FFLAGS(uint32_t value) +{ + __ASM volatile ("csrw fflags, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FRM + * + * @brief Return the Floating-Point Dynamic Rounding Mode + * + * @return frm value + */ +uint32_t __get_FRM(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FRM + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set frm value + * + * @return none + */ +void __set_FRM(uint32_t value) +{ + __ASM volatile ("csrw frm, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FCSR + * + * @brief Return the Floating-Point Control and Status Register + * + * @return fcsr value + */ +uint32_t __get_FCSR(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FCSR + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set fcsr value + * + * @return none + */ +void __set_FCSR(uint32_t value) +{ + __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MIE + * + * @brief Return the Machine Interrupt Enable Register + * + * @return mie value + */ +uint32_t __get_MIE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mie" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set mie value + * + * @return none + */ +void __set_MIE(uint32_t value) +{ + __ASM volatile ("csrw mie, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/Core/core_riscv.h b/Core/core_riscv.h new file mode 100644 index 0000000..3c63c1a --- /dev/null +++ b/Core/core_riscv.h @@ -0,0 +1,373 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : RISC-V Core Peripheral Access Layer Header File for CH32V30x +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO u32 CTLR; + __IO u32 SR; + __IO u64 CNT; + __IO u64 CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn: Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn: Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn: Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn: Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn: Interrupt Numbers + * + * @return None + */ +RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn: Interrupt Numbers + * + * @return None + */ +RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn: Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * priority - + * bit7 - pre-emption priority + * bit6~bit4 - subpriority + * @return None + */ +RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return None + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return None + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); + asm volatile ("wfi"); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn -Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * @return None + */ +RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else{ + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return None + */ +RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + + +/* Core_Exported_Functions */ +extern uint32_t __get_FFLAGS(void); +extern void __set_FFLAGS(uint32_t value); +extern uint32_t __get_FRM(void); +extern void __set_FRM(uint32_t value); +extern uint32_t __get_FCSR(void); +extern void __set_FCSR(uint32_t value); +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MIE(void); +extern void __set_MIE(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + + +#endif + + + + + diff --git a/Debug/debug.c b/Debug/debug.c new file mode 100644 index 0000000..b9ef9b4 --- /dev/null +++ b/Debug/debug.c @@ -0,0 +1,193 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : debug.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for UART +* Printf , Delay functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "debug.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)) + ; + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)) + ; + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length + * + * @return size: Data length + */ +__attribute__((used)) int _write(int fd, char *buf, int size) +{ + int i; + + for(i = 0; i < size; i++) + { +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } + + return size; +} + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + + + diff --git a/Debug/debug.h b/Debug/debug.h new file mode 100644 index 0000000..b02a1e3 --- /dev/null +++ b/Debug/debug.h @@ -0,0 +1,36 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : debug.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for UART +* Printf , Delay functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#include "stdio.h" +#include "ch32v30x.h" + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#define DEBUG DEBUG_UART1 +//#define DEBUG DEBUG_UART2 +//#define DEBUG DEBUG_UART3 + + +void Delay_Init(void); +void Delay_Us (uint32_t n); +void Delay_Ms (uint32_t n); +void USART_Printf_Init(uint32_t baudrate); + +#endif + + + diff --git a/JSInterpreter-TencentOS.wvproj b/JSInterpreter-TencentOS.wvproj new file mode 100644 index 0000000..e890260 --- /dev/null +++ b/JSInterpreter-TencentOS.wvproj @@ -0,0 +1,3 @@ +:?+z9`Yf{3 +Sa IZ2 !U0: 91?FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/Peripheral/inc/ch32v30x.h b/Peripheral/inc/ch32v30x.h new file mode 100644 index 0000000..bf48e2a --- /dev/null +++ b/Peripheral/inc/ch32v30x.h @@ -0,0 +1,5242 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer Header File. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_H +#define __CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +//#define CH32V30x_D8 /* CH32V303x */ +#define CH32V30x_D8C /* CH32V307x-CH32V305x */ + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTicK_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + +#ifdef CH32V30x_D8 + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + FSMC_IRQn = 64, /* FSMC global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + OTG_FS_IRQn = 83, /* OTGFS global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#endif + +#ifdef CH32V30x_D8C + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + FSMC_IRQn = 64, /* FSMC global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 77, /* ETH global Interrupt */ + ETH_WKUP_IRQn = 78, /* ETH WakeUp Interrupt */ + CAN2_TX_IRQn = 79, /* CAN2 TX Interrupts */ + CAN2_RX0_IRQn = 80, /* CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 81, /* CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 82, /* CAN2 SCE Interrupt */ + OTG_FS_IRQn = 83, /* OTGFS global Interrupt */ + USBHSWakeup_IRQn = 84, /* USBHS WakeUp Interrupt */ + USBHS_IRQn = 85, /* USBHS global Interrupt */ + DVP_IRQn = 86, /* DVP global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#endif +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn + + +#include +#include "core_riscv.h" +#include "system_ch32v30x.h" + + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* FSMC Bank1 Registers */ +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/* FSMC Bank1E Registers */ +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/* FSMC Bank2 Registers */ +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* SDIO Registers */ +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + +/* RNG Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; +} RNG_TypeDef; + +/* DVP Registers */ +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t IER; + __IO uint8_t Reserved0; + __IO uint16_t ROW_NUM; + __IO uint16_t COL_NUM; + __IO uint32_t DMA_BUF0; + __IO uint32_t DMA_BUF1; + __IO uint8_t IFR; + __IO uint8_t STATUS; + __IO uint16_t Reserved1; + __IO uint16_t ROW_CNT; + __IO uint16_t Reserved2; + __IO uint16_t HOFFCNT; + __IO uint16_t VST; + __IO uint16_t CAPCNT; + __IO uint16_t VLINE; + __IO uint32_t DR; +} DVP_TypeDef; + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve2; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBOTG_FS_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBOTGH_FS_TypeDef; + +/* Ethernet MAC */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + + + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define UART6_BASE (APB1PERIPH_BASE + 0x1800) +#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) +#define UART8_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) +#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) +#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) +#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) +#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) +#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) +#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define USBFS_BASE ((uint32_t)0x50000000) +#define DVP_BASE ((uint32_t)0x50050000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + +#define OB_BASE ((uint32_t)0x1FFFF800) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define UART6 ((USART_TypeDef *) UART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TKey1 ((ADC_TypeDef *) ADC1_BASE) +#define TKey2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) +#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) +#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) +#define USBOTG_FS ((USBOTG_FS_TypeDef *)USBFS_BASE) +#define USBOTG_H_FS ((USBOTGH_FS_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *) EXTEN_BASE) +#define OPA ((OPA_TypeDef *) OPA_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) + +#define DVP ((DVP_TypeDef *) DVP_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + +#define OB ((OB_TypeDef *) OB_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_BTIMR register ********************/ +#define CAN_BTIMR_BRP ((uint32_t)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTIMR_TS1 ((uint32_t)0x000F0000) /* Time Segment 1 */ +#define CAN_BTIMR_TS2 ((uint32_t)0x00700000) /* Time Segment 2 */ +#define CAN_BTIMR_SJW ((uint32_t)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTIMR_LBKM ((uint32_t)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTIMR_SILM ((uint32_t)0x80000000) /* Silent Mode */ + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + + + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + +/******************* Bit definition for FLASH_ACTLR register ******************/ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ +#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */ +#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */ +#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */ +#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */ +#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */ +#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */ +#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */ +#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */ + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* for other CH32V30x */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ +/* for CH32V307 */ +#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ +#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ +#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ +#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint16_t)0x1000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* RNG */ +/******************************************************************************/ +/******************** Bit definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN ((uint32_t)0x00000004) +#define RNG_CR_IE ((uint32_t)0x00000008) + +/******************** Bit definition for RNG_SR register *******************/ +#define RNG_SR_DRDY ((uint32_t)0x00000001) +#define RNG_SR_CECS ((uint32_t)0x00000002) +#define RNG_SR_SECS ((uint32_t)0x00000004) +#define RNG_SR_CEIS ((uint32_t)0x00000020) +#define RNG_SR_SEIS ((uint32_t)0x00000040) + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ + + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + + + +#include "ch32v30x_conf.h" + + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/Peripheral/inc/ch32v30x_adc.h b/Peripheral/inc/ch32v30x_adc.h new file mode 100644 index 0000000..f1375b1 --- /dev/null +++ b/Peripheral/inc/ch32v30x_adc.h @@ -0,0 +1,228 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_ADC_H +#define __CH32V30x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +}ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef* ADCx); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/Peripheral/inc/ch32v30x_bkp.h b/Peripheral/inc/ch32v30x_bkp.h new file mode 100644 index 0000000..16daced --- /dev/null +++ b/Peripheral/inc/ch32v30x_bkp.h @@ -0,0 +1,97 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_BKP_H +#define __CH32V30x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_can.h b/Peripheral/inc/ch32v30x_can.h new file mode 100644 index 0000000..a5326a4 --- /dev/null +++ b/Peripheral/inc/ch32v30x_can.h @@ -0,0 +1,366 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_CAN_H +#define __CH32V30x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + + +/* CAN_flags */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_crc.h b/Peripheral/inc/ch32v30x_crc.h new file mode 100644 index 0000000..6a4055c --- /dev/null +++ b/Peripheral/inc/ch32v30x_crc.h @@ -0,0 +1,37 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CRC firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_CRC_H +#define __CH32V30x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_dac.h b/Peripheral/inc/ch32v30x_dac.h new file mode 100644 index 0000000..1041ae1 --- /dev/null +++ b/Peripheral/inc/ch32v30x_dac.h @@ -0,0 +1,120 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DAC firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DAC_H +#define __CH32V30x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DAC Init structure definition */ +typedef struct +{ + uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + + +/* DAC_trigger_selection */ +#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ + +/* DAC_wave_generation */ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) + + +/* DAC_lfsrunmask_triangleamplitude */ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ + +/* DAC_output_buffer */ +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) + +/* DAC_Channel_selection */ +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) + +/* DAC_data_alignment */ +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) + +/* DAC_wave_generation */ +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) + + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_dbgmcu.h b/Peripheral/inc/ch32v30x_dbgmcu.h new file mode 100644 index 0000000..f762309 --- /dev/null +++ b/Peripheral/inc/ch32v30x_dbgmcu.h @@ -0,0 +1,35 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DBGMCU firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DBGMCU_H +#define __CH32V30x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_dma.h b/Peripheral/inc/ch32v30x_dma.h new file mode 100644 index 0000000..34cefbf --- /dev/null +++ b/Peripheral/inc/ch32v30x_dma.h @@ -0,0 +1,268 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DMA_H +#define __CH32V30x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) +#define DMA2_IT_GL6 ((uint32_t)0x10100000) +#define DMA2_IT_TC6 ((uint32_t)0x10200000) +#define DMA2_IT_HT6 ((uint32_t)0x10400000) +#define DMA2_IT_TE6 ((uint32_t)0x10800000) +#define DMA2_IT_GL7 ((uint32_t)0x11000000) +#define DMA2_IT_TC7 ((uint32_t)0x12000000) +#define DMA2_IT_HT7 ((uint32_t)0x14000000) +#define DMA2_IT_TE7 ((uint32_t)0x18000000) + +#define DMA2_IT_GL8 ((uint32_t)0x20000001) +#define DMA2_IT_TC8 ((uint32_t)0x20000002) +#define DMA2_IT_HT8 ((uint32_t)0x20000004) +#define DMA2_IT_TE8 ((uint32_t)0x20000008) +#define DMA2_IT_GL9 ((uint32_t)0x20000010) +#define DMA2_IT_TC9 ((uint32_t)0x20000020) +#define DMA2_IT_HT9 ((uint32_t)0x20000040) +#define DMA2_IT_TE9 ((uint32_t)0x20000080) +#define DMA2_IT_GL10 ((uint32_t)0x20000100) +#define DMA2_IT_TC10 ((uint32_t)0x20000200) +#define DMA2_IT_HT10 ((uint32_t)0x20000400) +#define DMA2_IT_TE10 ((uint32_t)0x20000800) +#define DMA2_IT_GL11 ((uint32_t)0x20001000) +#define DMA2_IT_TC11 ((uint32_t)0x20002000) +#define DMA2_IT_HT11 ((uint32_t)0x20004000) +#define DMA2_IT_TE11 ((uint32_t)0x20008000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x10100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x10200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x10400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x10800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x11000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x12000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x14000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x18000000) + +#define DMA2_FLAG_GL8 ((uint32_t)0x20000001) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000002) +#define DMA2_FLAG_HT8 ((uint32_t)0x20000004) +#define DMA2_FLAG_TE8 ((uint32_t)0x20000008) +#define DMA2_FLAG_GL9 ((uint32_t)0x20000010) +#define DMA2_FLAG_TC9 ((uint32_t)0x20000020) +#define DMA2_FLAG_HT9 ((uint32_t)0x20000040) +#define DMA2_FLAG_TE9 ((uint32_t)0x20000080) +#define DMA2_FLAG_GL10 ((uint32_t)0x20000100) +#define DMA2_FLAG_TC10 ((uint32_t)0x20000200) +#define DMA2_FLAG_HT10 ((uint32_t)0x20000400) +#define DMA2_FLAG_TE10 ((uint32_t)0x20000800) +#define DMA2_FLAG_GL11 ((uint32_t)0x20001000) +#define DMA2_FLAG_TC11 ((uint32_t)0x20002000) +#define DMA2_FLAG_HT11 ((uint32_t)0x20004000) +#define DMA2_FLAG_TE11 ((uint32_t)0x20008000) + + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_dvp.h b/Peripheral/inc/ch32v30x_dvp.h new file mode 100644 index 0000000..deafaeb --- /dev/null +++ b/Peripheral/inc/ch32v30x_dvp.h @@ -0,0 +1,67 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DVP firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_DVP_H +#define __CH32V30x_DVP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DVP Data Mode */ +typedef enum +{ + Video_Mode = 0, + JPEG_Mode, +}DVP_Data_ModeTypeDef; + + +/* DVP DMA */ +typedef enum +{ + DVP_DMA_Disable = 0, + DVP_DMA_Enable, +}DVP_DMATypeDef; + +/* DVP FLAG and FIFO Reset */ +typedef enum +{ + DVP_FLAG_FIFO_RESET_Disable = 0, + DVP_FLAG_FIFO_RESET_Enable, +}DVP_FLAG_FIFO_RESETTypeDef; + +/* DVP RX Reset */ +typedef enum +{ + DVP_RX_RESET_Disable = 0, + DVP_RX_RESET_Enable, +}DVP_RX_RESETTypeDef; + + + +void DVP_INTCfg( uint8_t s, uint8_t i ); +void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i); +void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/Peripheral/inc/ch32v30x_eth.h b/Peripheral/inc/ch32v30x_eth.h new file mode 100644 index 0000000..49931c6 --- /dev/null +++ b/Peripheral/inc/ch32v30x_eth.h @@ -0,0 +1,1333 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ETH firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_ETH_H +#define __CH32V30x_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +#define PHY_10BASE_T_LINKED 1 +#define PHY_10BASE_T_NOT_LINKED 0 + +#define DMA_TPS_Mask ((uint32_t)0x00700000) +#define DMA_RPS_Mask ((uint32_t)0x000E0000) + +/* ETH Init structure definition */ +typedef struct { + uint32_t ETH_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t ETH_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_CarrierSense; /* Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ETH_Speed; /* Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + uint32_t ETH_ReceiveOwn; /* Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t ETH_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ETH_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t ETH_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_BackOffLimit; /* Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t ETH_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t ETH_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t ETH_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ETH_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t ETH_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t ETH_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t ETH_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t ETH_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t ETH_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + uint32_t ETH_DMAArbitration; /* Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +}ETH_InitTypeDef; + + + +/* ETH delay.Just for Ethernet */ +#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ + +/* definition for Ethernet frame */ +#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/* ETH DMA structure definition */ +typedef struct +{ + uint32_t Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* Timeout threshold of Reading or writing PHY registers */ +#define PHY_READ_TO ((uint32_t)0x004FFFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/* Delay time after reset PHY */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + +/* Delay time after configure PHY */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register */ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR +#define PHY_STATUS 0x10 +#define PHY_MDIX 0x1E + +/* Bit or field definition for PHY basic control register */ +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ +#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ + + +/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ +#define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) +#define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) + +/* MAC autoNegotiation enable or disable */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) + +/* MAC watchdog enable or disable */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) + +/* Bit description - MAC jabber enable or disable */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) + +/* Value of minimum IFG between frames during transmission */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +/* MAC carrier sense enable or disable */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) + +/* MAC speed */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define ETH_Speed_1000M ((uint32_t)0x00008000) + +/* MAC receive own enable or disable */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) + +/* MAC Loopback mode enable or disable */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) + +/* MAC fullDuplex or halfDuplex */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) + +/* MAC offload checksum enable or disable */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) + +/* MAC transmission retry enable or disable */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) + +/* MAC automatic pad CRC strip enable or disable */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) + +/* MAC deferral check enable or disable */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) + +/* Bit description : MAC receive all frame enable or disable */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) + +/* MAC Pass control frames */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +/* MAC broadcast frames reception */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) + +/* MAC destination address filter */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) + +/* MAC Promiscuous mode enable or disable */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) + +/* MAC multicast frames filter */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) + +/* MAC unicast frames filter */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) + +/* Bit description : MAC zero quanta pause */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) + +/* Field description : MAC pause low threshold */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ + +/* MAC unicast pause frame detect enable or disable*/ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) + +/* MAC receive flow control frame enable or disable */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC transmit flow control enable or disable */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC VLAN tag comparison */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) + +/* MAC flag */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ + +/* MAC interrupt */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ + +/* MAC address */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) + +/* MAC address filter select */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) + +/* MAC address mask */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ + + +/******************************************************************************/ +/* */ +/* MAC Descriptor Register */ +/* */ +/******************************************************************************/ + +/* DMA descriptor segment */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ + +/* DMA descriptor checksum setting */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +/* DMA RX & TX buffer */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ + + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ + +/* DMA drop TCPIP checksum error frame enable or disable */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) + +/* DMA receive store forward enable or disable */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA flush received frame enable or disable */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) + +/* DMA transmit store forward enable or disable */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA transmit threshold control */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +/* DMA forward error frames */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) + +/* DMA forward undersized good frames enable or disable */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) + +/* DMA receive threshold control */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +/* DMA second frame operate enable or disable */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) + +/* Address aligned beats enable or disable */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) + +/* DMA Fixed burst enable or disable */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) + + +/* RX DMA burst length */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + + +/* TX DMA burst length */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +/* DMA arbitration_round robin */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) + +/* DMA interrupt FALG */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ + +/* DMA interrupt */ +#define ETH_DMA_IT_PHYLINK ((uint32_t)0x80000000) /* Internal PHY link status change interrupt */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ + +/* DMA transmit process */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ + +/* DMA receive Process */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* DMA overflow */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ + + +/********************************************************************************* +* Ethernet PMT defines +**********************************************************************************/ + +/* PMT flag */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ + +/********************************************************************************* +* Ethernet MMC defines +**********************************************************************************/ + +/* MMC TX interrupt flag */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* MMC RX interrupt flag */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + + +/* MMC description */ +#define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ + + +/********************************************************************************* +* Ethernet PTP defines +**********************************************************************************/ + +/* PTP fine update method or coarse Update method */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ + + +/* PTP time stamp control */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ + +/* PTP positive/negative time value */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ + + +/******************************************************************************/ +/* */ +/* PTP Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + + +/******************************************************************************/ +/* */ +/* ETH MAC Register */ +/* */ +/******************************************************************************/ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ + +/* +Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ + +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ + +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* +/* ETH MMC Register +/* +/******************************************************************************/ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ + +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + + +/******************************************************************************/ +/* +/* ETH Precise Clock Protocol Register +/* +/******************************************************************************/ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ + +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ + +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ + +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ + +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ + +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ + +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ + +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +/******************************************************************************/ +/* +/* ETH DMA Register +/* +/******************************************************************************/ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ + +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ + +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ + +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + + +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) + + +void ETH_DeInit(void); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +FlagStatus ETH_GetlinkStaus (void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); +void delay_clk (uint32_t nCount); +void printf_dmasr (void); +void print_dmasr_tbus(void); +void print_dmasr_rps(void); +void print_dmasr_tps(void); +uint32_t ETH_HandleRxPkt(uint8_t *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); + +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_exti.h b/Peripheral/inc/ch32v30x_exti.h new file mode 100644 index 0000000..2b2d0c3 --- /dev/null +++ b/Peripheral/inc/ch32v30x_exti.h @@ -0,0 +1,90 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_EXTI_H +#define __CH32V30x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_flash.h b/Peripheral/inc/ch32v30x_flash.h new file mode 100644 index 0000000..1ae39d5 --- /dev/null +++ b/Peripheral/inc/ch32v30x_flash.h @@ -0,0 +1,144 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the FLASH +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_FLASH_H +#define __CH32V30x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */ + + +/*Functions used for all devices*/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf); +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); +void FLASH_Enhance_Mode(FunctionalState NewState); + +/* New function used for all devices */ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/Peripheral/inc/ch32v30x_fsmc.h b/Peripheral/inc/ch32v30x_fsmc.h new file mode 100644 index 0000000..33dcc60 --- /dev/null +++ b/Peripheral/inc/ch32v30x_fsmc.h @@ -0,0 +1,287 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the FSMC +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_FSMC_H +#define __CH32V30x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#include "ch32v30x.h" + + +/* FSMC Init structure definition */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /* Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /* Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + + +/* FSMC_NORSRAM_Bank */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) + +/* FSMC_NAND_Bank */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) + +/* FSMC_Data_Address_Bus_Multiplexing */ +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +/* FSMC_Memory_Type */ +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) + +/* FSMC_Data_Width */ +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) + +/* FSMC_Burst_Access_Mode */ +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +/* FSMC_AsynchronousWait */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +/* FSMC_Wait_Signal_Polarity */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +/* FSMC_Wrap_Mode */ +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) + +/* FSMC_Wait_Timing */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +/* FSMC_Write_Operation */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) + +/* FSMC_Wait_Signal */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) + +/* FSMC_Extended_Mode */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +/* FSMC_Write_Burst */ +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) + +/* FSMC_Access_Mode */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) + +/* FSMC_Wait_feature */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) + +/* FSMC_ECC */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) + +/* FSMC_ECC_Page_Size */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +/* FSMC_Interrupt_sources */ +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) + +/* FSMC_Flags */ +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) + + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch32v30x_gpio.h b/Peripheral/inc/ch32v30x_gpio.h new file mode 100644 index 0000000..1dd7ad1 --- /dev/null +++ b/Peripheral/inc/ch32v30x_gpio.h @@ -0,0 +1,197 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_GPIO_H +#define __CH32V30x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +/* PCFR2 */ +#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ +#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ +#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ +#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* Ethernet_Media_Interface */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_i2c.h b/Peripheral/inc/ch32v30x_i2c.h new file mode 100644 index 0000000..d3723c5 --- /dev/null +++ b/Peripheral/inc/ch32v30x_i2c.h @@ -0,0 +1,211 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_I2C_H +#define __CH32V30x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + + +/**************************************************************************************** +* I2C State Monitoring Functions +****************************************************************************************/ + +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/Peripheral/inc/ch32v30x_iwdg.h b/Peripheral/inc/ch32v30x_iwdg.h new file mode 100644 index 0000000..0276d85 --- /dev/null +++ b/Peripheral/inc/ch32v30x_iwdg.h @@ -0,0 +1,56 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_IWDG_H +#define __CH32V30x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_misc.h b/Peripheral/inc/ch32v30x_misc.h new file mode 100644 index 0000000..bd79689 --- /dev/null +++ b/Peripheral/inc/ch32v30x_misc.h @@ -0,0 +1,46 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_misc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* miscellaneous firmware library functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30X_MISC_H +#define __CH32V30X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* NVIC Init Structure definition */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + + +/* Preemption_Priority_Group */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) +#define NVIC_PriorityGroup_4 ((uint32_t)0x04) + + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_opa.h b/Peripheral/inc/ch32v30x_opa.h new file mode 100644 index 0000000..4fd5f01 --- /dev/null +++ b/Peripheral/inc/ch32v30x_opa.h @@ -0,0 +1,75 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* OPA firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_OPA_H +#define __CH32V30x_OPA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +#define OPA_PSEL_OFFSET 3 +#define OPA_NSEL_OFFSET 2 +#define OPA_MODE_OFFSET 1 + + +/* OPA member enumeration */ +typedef enum +{ + OPA1=0, + OPA2, + OPA3, + OPA4 +}OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0=0, + CHP1 +}OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0=0, + CHN1 +}OPA_NSEL_TypeDef; + +/* OPA Mode enumeration */ +typedef enum +{ + OUT_IO_ADC=0, + OUT_IO +}OPA_Mode_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ +}OPA_InitTypeDef; + + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef* OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_pwr.h b/Peripheral/inc/ch32v30x_pwr.h new file mode 100644 index 0000000..3fc9329 --- /dev/null +++ b/Peripheral/inc/ch32v30x_pwr.h @@ -0,0 +1,64 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the PWR +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_PWR_H +#define __CH32V30x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_rcc.h b/Peripheral/inc/ch32v30x_rcc.h new file mode 100644 index 0000000..1acccde --- /dev/null +++ b/Peripheral/inc/ch32v30x_rcc.h @@ -0,0 +1,456 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RCC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_RCC_H +#define __CH32V30x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#ifdef CH32V30x_D8 +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +#else +#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + +#endif + +/* PLL_multiplication_factor */ +#ifdef CH32V30x_D8 +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +#else +#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000) +#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000) +#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000) +#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000) +#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000) +#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000) +#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000) +#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000) +#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000) +#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000) +#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000) +#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000) +#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000) +#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000) +#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000) +#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000) + +#endif + +/* PREDIV1_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) +#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) +#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) +#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) +#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) +#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) +#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) +#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) +#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) +#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) +#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) +#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) +#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) +#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) +#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + +#endif + +/* PREDIV1_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) +#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + +#endif + +/* PREDIV2_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) +#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) +#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) +#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) +#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) +#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) +#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) +#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) +#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) +#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) +#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) +#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) +#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) +#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) +#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + +#endif + +/* PLL2_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100) +#define RCC_PLL2Mul_4 ((uint32_t)0x00000200) +#define RCC_PLL2Mul_5 ((uint32_t)0x00000300) +#define RCC_PLL2Mul_6 ((uint32_t)0x00000400) +#define RCC_PLL2Mul_7 ((uint32_t)0x00000500) +#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) +#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) +#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) +#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) +#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) +#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) +#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) +#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00) +#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) +#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + +#endif + +/* PLL3_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000) +#define RCC_PLL3Mul_4 ((uint32_t)0x00002000) +#define RCC_PLL3Mul_5 ((uint32_t)0x00003000) +#define RCC_PLL3Mul_6 ((uint32_t)0x00004000) +#define RCC_PLL3Mul_7 ((uint32_t)0x00005000) +#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) +#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) +#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) +#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) +#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) +#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) +#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) +#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000) +#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) +#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + +#endif + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifdef CH32V30x_D8C +#define RCC_IT_PLL2RDY ((uint8_t)0x20) +#define RCC_IT_PLL3RDY ((uint8_t)0x40) + +#endif + +/* USB_OTG_FS_clock_source */ +#define RCC_OTGFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_OTGFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_OTGFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02) + +/* I2S2_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* I2S3_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000) +#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) +#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) +#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifdef CH32V30x_D8C +#define RCC_MCO_PLL2CLK ((uint8_t)0x08) +#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) +#define RCC_MCO_XT1 ((uint8_t)0x0A) +#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + +#endif + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifdef CH32V30x_D8C +#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) +#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + +#endif + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RNG_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) +#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) + +#endif + +/* ETH1G_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) +#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) +#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) + +#endif + +/* USBFS_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_USBPLL_Div1 ((uint32_t)0x00) +#define RCC_USBPLL_Div2 ((uint32_t)0x01) +#define RCC_USBPLL_Div3 ((uint32_t)0x02) +#define RCC_USBPLL_Div4 ((uint32_t)0x03) +#define RCC_USBPLL_Div5 ((uint32_t)0x04) +#define RCC_USBPLL_Div6 ((uint32_t)0x05) +#define RCC_USBPLL_Div7 ((uint32_t)0x06) +#define RCC_USBPLL_Div8 ((uint32_t)0x07) + +#endif + +/* USBHSPLL_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00) +#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01) + +#endif + +/* USBHSPLLCKREF_clock_select */ +#ifdef CH32V30x_D8C +#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00) +#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01) +#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02) +#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03) + +#endif + +/* OTGUSBCLK48M_clock_source */ +#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00) +#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01) + + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKADJcmd(FunctionalState NewState); +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource); + +#ifdef CH32V30x_D8C +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); +void RCC_PLL2Config(uint32_t RCC_PLL2Mul); +void RCC_PLL2Cmd(FunctionalState NewState); +void RCC_PLL3Config(uint32_t RCC_PLL3Mul); +void RCC_PLL3Cmd(FunctionalState NewState); +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource); +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource); +void RCC_ETH1G_125Mcmd(FunctionalState NewState); +void RCC_USBHSConfig(uint32_t RCC_USBHS); +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource); +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource); +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_rng.h b/Peripheral/inc/ch32v30x_rng.h new file mode 100644 index 0000000..99f7cac --- /dev/null +++ b/Peripheral/inc/ch32v30x_rng.h @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* RNG firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_RNG_H +#define __CH32V30x_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif +#include "ch32v30x.h" + + /* RNG_flags_definition*/ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ + +/* RNG_interrupts_definition */ +#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ + + +void RNG_Cmd(FunctionalState NewState); +uint32_t RNG_GetRandomNumber(void); +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch32v30x_rtc.h b/Peripheral/inc/ch32v30x_rtc.h new file mode 100644 index 0000000..60e90ee --- /dev/null +++ b/Peripheral/inc/ch32v30x_rtc.h @@ -0,0 +1,54 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the RTC +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_RTC_H +#define __CH32V30x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_sdio.h b/Peripheral/inc/ch32v30x_sdio.h new file mode 100644 index 0000000..12d4c4e --- /dev/null +++ b/Peripheral/inc/ch32v30x_sdio.h @@ -0,0 +1,254 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_sdio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the SDIO +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_SDIO_H +#define __CH32V30x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SDIO Init structure definition */ +typedef struct +{ + uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /* Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + + +typedef struct +{ + uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /* Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* SDIO_Clock_Edge */ +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) + +/* SDIO_Clock_Bypass */ +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) + +/* SDIO_Clock_Power_Save */ +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) + +/* SDIO_Bus_Wide */ +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) + +/* SDIO_Hardware_Flow_Control */ +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) + +/* SDIO_Power_State */ +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) + +/* SDIO_Interrupt_sources */ +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Response_Type */ +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) + +/* SDIO_Wait_Interrupt_State */ +#define SDIO_Wait_No ((uint32_t)0x00000000) +#define SDIO_Wait_IT ((uint32_t)0x00000100) +#define SDIO_Wait_Pend ((uint32_t)0x00000200) + +/* SDIO_CPSM_State */ +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) + +/* SDIO_Response_Registers */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +/* SDIO_Data_Block_Size */ +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) + +/* SDIO_Transfer_Direction */ +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) + +/* SDIO_Transfer_Type */ +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) + +/* SDIO_DPSM_State */ +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) + +/* SDIO_Flags */ +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Read_Wait_Mode */ +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) + + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch32v30x_spi.h b/Peripheral/inc/ch32v30x_spi.h new file mode 100644 index 0000000..94391de --- /dev/null +++ b/Peripheral/inc/ch32v30x_spi.h @@ -0,0 +1,229 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_SPI_H +#define __CH32V30x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + + uint16_t I2S_Mode; /* Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + + diff --git a/Peripheral/inc/ch32v30x_tim.h b/Peripheral/inc/ch32v30x_tim.h new file mode 100644 index 0000000..0ea77da --- /dev/null +++ b/Peripheral/inc/ch32v30x_tim.h @@ -0,0 +1,515 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_TIM_H +#define __CH32V30x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/Peripheral/inc/ch32v30x_usart.h b/Peripheral/inc/ch32v30x_usart.h new file mode 100644 index 0000000..f394494 --- /dev/null +++ b/Peripheral/inc/ch32v30x_usart.h @@ -0,0 +1,195 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_USART_H +#define __CH32V30x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_wwdg.h b/Peripheral/inc/ch32v30x_wwdg.h new file mode 100644 index 0000000..610582f --- /dev/null +++ b/Peripheral/inc/ch32v30x_wwdg.h @@ -0,0 +1,42 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the WWDG +* firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_WWDG_H +#define __CH32V30x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/src/ch32v30x_adc.c b/Peripheral/src/ch32v30x_adc.c new file mode 100644 index 0000000..2896a40 --- /dev/null +++ b/Peripheral/src/ch32v30x_adc.c @@ -0,0 +1,1180 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ADC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_adc.h" +#include "ch32v30x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if(ADCx == ADC2) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + for(i = 0; i < 10; i++) + { + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)) + ; + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)) + ; + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + + t = (t / 6) + ((t % 6) / 3); + + return (int16_t)(2048 - (int16_t)t); +} diff --git a/Peripheral/src/ch32v30x_bkp.c b/Peripheral/src/ch32v30x_bkp.c new file mode 100644 index 0000000..e7420b7 --- /dev/null +++ b/Peripheral/src/ch32v30x_bkp.c @@ -0,0 +1,242 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the BKP firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_bkp.h" +#include "ch32v30x_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/Peripheral/src/ch32v30x_can.c b/Peripheral/src/ch32v30x_can.c new file mode 100644 index 0000000..9b64390 --- /dev/null +++ b/Peripheral/src/ch32v30x_can.c @@ -0,0 +1,1207 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CAN firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_can.h" +#include "ch32v30x_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 or 2 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef *CANx) +{ + if(CANx == CAN1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. + * CAN_InitStatus_Failed. + * CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ; + + while(((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if(CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if(CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if(CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if(CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if(CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if(CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while(((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if(CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber) << 8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage) +{ + uint8_t transmit_mailbox = 0; + + if((CANx->TSTATR & CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if((CANx->TSTATR & CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if((CANx->TSTATR & CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if(transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if(TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | + TxMessage->IDE | + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch(TransmitMailbox) + { + case(CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case(CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case(CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch(state) + { + case(0x0): + state = CAN_TxStatus_Pending; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t)state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox) +{ + switch(Mailbox) + { + case(CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case(CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case(CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if(RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + uint8_t message_pending = 0; + + if(FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0 & (uint32_t)0x03); + } + else if(FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if(CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP | CAN_CTLR_INRQ)); + + while(((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t)status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef *CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if((CANx->STATR & (CAN_STATR_SLAK | CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef *CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx) +{ + uint8_t errorcode = 0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC) >> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC) >> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + + if(CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO1) != (uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch(CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default: + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + switch(CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} diff --git a/Peripheral/src/ch32v30x_crc.c b/Peripheral/src/ch32v30x_crc.c new file mode 100644 index 0000000..3ae9236 --- /dev/null +++ b/Peripheral/src/ch32v30x_crc.c @@ -0,0 +1,98 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CRC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/Peripheral/src/ch32v30x_dac.c b/Peripheral/src/ch32v30x_dac.c new file mode 100644 index 0000000..566e0c7 --- /dev/null +++ b/Peripheral/src/ch32v30x_dac.c @@ -0,0 +1,302 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DAC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +****************************************************************************************/ +#include "ch32v30x_dac.h" +#include "ch32v30x_rcc.h" + +/* CTLR register Mask */ +#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTR masks */ +#define DUAL_SWTR_SET ((uint32_t)0x00000003) +#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/********************************************************************* + * @fn DAC_DeInit + * + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * + * @return none + */ +void DAC_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/********************************************************************* + * @fn DAC_Init + * + * @brief Initializes the DAC peripheral according to the specified parameters in + * the DAC_InitStruct. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_InitStruct - pointer to a DAC_InitTypeDef structure. + * + * @return none + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + tmpreg1 = DAC->CTLR; + tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel); + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + tmpreg1 |= tmpreg2 << DAC_Channel; + DAC->CTLR = tmpreg1; +} + +/********************************************************************* + * @fn DAC_StructInit + * + * @brief Fills each DAC_InitStruct member with its default value. + * + * @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized. + * + * @return none + */ +void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct) +{ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/********************************************************************* + * @fn DAC_Cmd + * + * @brief Enables or disables the specified DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_EN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_EN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_DMACmd + * + * @brief Enables or disables the specified DAC channel DMA request. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SoftwareTriggerCmd + * + * @brief Enables or disables the selected DAC channel software trigger. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/********************************************************************* + * @fn DAC_DualSoftwareTriggerCmd + * + * @brief Enables or disables the two DAC channel software trigger. + * + * @param NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= DUAL_SWTR_SET; + } + else + { + DAC->SWTR &= DUAL_SWTR_RESET; + } +} + +/********************************************************************* + * @fn DAC_WaveGenerationCmd + * + * @brief Enables or disables the selected DAC channel wave generation. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_Wave - Specifies the wave type to enable or disable. + * DAC_Wave_Noise - noise wave generation + * DAC_Wave_Triangle - triangle wave generation + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= DAC_Wave << DAC_Channel; + } + else + { + DAC->CTLR &= ~(DAC_Wave << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SetChannel1Data + * + * @brief Set the specified data holding register value for DAC channel1. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetChannel2Data + * + * @brief Set the specified data holding register value for DAC channel2. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetDualChannelData + * + * @brief Set the specified data holding register value for two DAC. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * Data1 - Data for DAC Channel1. + * Data2 - Data for DAC Channel2 + * + * @return none + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + if(DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = data; +} + +/********************************************************************* + * @fn DAC_GetDataOutputValue + * + * @brief Returns the last data output value of the selected DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * + * @return none + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + return (uint16_t)(*(__IO uint32_t *)tmp); +} diff --git a/Peripheral/src/ch32v30x_dbgmcu.c b/Peripheral/src/ch32v30x_dbgmcu.c new file mode 100644 index 0000000..87b286f --- /dev/null +++ b/Peripheral/src/ch32v30x_dbgmcu.c @@ -0,0 +1,36 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DBGMCU firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +****************************************************************************************/ +#include "ch32v30x_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} diff --git a/Peripheral/src/ch32v30x_dma.c b/Peripheral/src/ch32v30x_dma.c new file mode 100644 index 0000000..30aaffe --- /dev/null +++ b/Peripheral/src/ch32v30x_dma.c @@ -0,0 +1,690 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DMA firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_dma.h" +#include "ch32v30x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) +#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9)) +#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10)) +#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) +#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel1) + { + DMA2->INTFCR |= DMA2_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel2) + { + DMA2->INTFCR |= DMA2_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel3) + { + DMA2->INTFCR |= DMA2_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel4) + { + DMA2->INTFCR |= DMA2_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel5) + { + DMA2->INTFCR |= DMA2_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel6) + { + DMA2->INTFCR |= DMA2_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel7) + { + DMA2->INTFCR |= DMA2_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel8) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel9) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel10) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel11) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_FLAG; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_FLAG; + } + else + { + DMA1->INTFCR = DMAy_FLAG; + } +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_IT; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_IT; + } + else + { + DMA1->INTFCR = DMAy_IT; + } +} diff --git a/Peripheral/src/ch32v30x_dvp.c b/Peripheral/src/ch32v30x_dvp.c new file mode 100644 index 0000000..15e5515 --- /dev/null +++ b/Peripheral/src/ch32v30x_dvp.c @@ -0,0 +1,133 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DVP firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_dvp.h" + +/********************************************************************* + * @fn DVP_INTCfg + * + * @brief DVP interrupt configuration + * + * @param s - interrupt enable + * ENABLE + * DISABLE + * i - interrupt type + * RB_DVP_IE_STP_FRM + * RB_DVP_IE_FIFO_OV + * RB_DVP_IE_FRM_DONE + * RB_DVP_IE_ROW_DONE + * RB_DVP_IE_STR_FRM + * + * @return none + */ +void DVP_INTCfg(uint8_t s, uint8_t i) +{ + if(s) + { + DVP->IER |= i; + } + else + { + DVP->IER &= ~i; + } +} + +/********************************************************************* + * @fn DVP_Mode + * + * @brief DVP mode + * + * @param s - data bit width + * RB_DVP_D8_MOD + * RB_DVP_D10_MOD + * RB_DVP_D12_MOD + * i - interrupt type + * Video_Mode + * JPEG_Mode + * + * @return none + */ +void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i) +{ + DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD; + + if(s) + { + DVP->CR0 |= s; + } + else + { + DVP->CR0 &= ~(3 << 4); + } + + if(i) + { + DVP->CR0 |= RB_DVP_JPEG; + } + else + { + DVP->CR0 &= ~RB_DVP_JPEG; + } +} + +/********************************************************************* + * @fn DVP_Cfg + * + * @brief DVP configuration + * + * @param s - DMA enable control + * DVP_DMA_Enable + * DVP_DMA_Disable + * i - DVP all clear + * DVP_FLAG_FIFO_RESET_Enable + * DVP_FLAG_FIFO_RESET_Disable + * j - receive reset enable + * DVP_RX_RESET_Enable + * DVP_RX_RESET_Disable + * + * @return none + */ +void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) +{ + switch(s) + { + case DVP_DMA_Enable: + DVP->CR1 |= RB_DVP_DMA_EN; + break; + case DVP_DMA_Disable: + DVP->CR1 &= ~RB_DVP_DMA_EN; + break; + default: + break; + } + + switch(i) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_ALL_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_ALL_CLR; + break; + default: + break; + } + + switch(j) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_RCV_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_RCV_CLR; + break; + default: + break; + } +} diff --git a/Peripheral/src/ch32v30x_eth.c b/Peripheral/src/ch32v30x_eth.c new file mode 100644 index 0000000..53c3411 --- /dev/null +++ b/Peripheral/src/ch32v30x_eth.c @@ -0,0 +1,2522 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ETH firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_eth.h" +#include "ch32v30x_rcc.h" + +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/********************************************************************* + * @fn ETH_DeInit + * + * @brief ETH hardware initialize again. + * + * @return none + */ +#ifdef CH32V30x_D8C +void ETH_DeInit(void) +{ + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); +} + +#endif + +/********************************************************************* + * @fn ETH_StructInit + * + * @brief Fills each ETH_InitStruct member with its default value. + * + * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) +{ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/********************************************************************* + * @fn ETH_Start + * + * @brief Enables ENET MAC and DMA reception/transmission. + * + * @return none + */ +void ETH_Start(void) +{ + ETH_MACTransmissionCmd(ENABLE); + ETH_FlushTransmitFIFO(); + ETH_MACReceptionCmd(ENABLE); + ETH_DMATransmissionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); +} + +/********************************************************************* + * @fn ETH_HandleTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * + * @param ppkt - pointer to the application's packet buffer to transmit. + * FrameLength - Tx Packet size. + * + * @return ETH_ERROR - in case of Tx desc owned by DMA. + * ETH_SUCCESS - for correct transmission. + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandleRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt. + * + * @param ppkt - pointer to the application packet receive buffer. + * + * @return ETH_ERROR - if there is error in reception + * framelength - received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn ETH_GetRxPktSize + * + * @brief Get the size of received the received packet. + * + * @return framelength - received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + return frameLength; +} + +/********************************************************************* + * @fn ETH_DropRxPkt + * + * @brief Drop a Received packet. + * + * @return none + */ +void ETH_DropRxPkt(void) +{ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/********************************************************************* + * @fn ETH_ReadPHYRegister + * + * @brief Read a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * + * @return ETH_ERROR - in case of timeout. + * MAC MIIDR register value - Data read from the selected PHY register. + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg &= ~ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + return (uint16_t)(ETH->MACMIIDR); +} + +/********************************************************************* + * @fn ETH_WritePHYRegister + * + * @brief Write to a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * PHYValue - the value to write. + * + * @return ETH_ERROR - in case of timeout. + * ETH_SUCCESS - for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg |= ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIDR = PHYValue; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + + if(timeout >= PHY_WRITE_TO) + { + return ETH_ERROR; + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_PHYLoopBackCmd + * + * @brief Enables or disables the PHY loopBack mode. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * NewState - new state of the PHY loopBack mode. + * + * @return ETH_ERROR - in case of bad PHY configuration. + * ETH_SUCCESS - for correct PHY configuration. + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if(NewState != DISABLE) + { + tmpreg |= PHY_Loopback; + } + else + { + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/********************************************************************* + * @fn ETH_MACTransmissionCmd + * + * @brief Enables or disables the MAC transmission. + * + * @param NewState - new state of the MAC transmission. + * + * @return none + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/********************************************************************* + * @fn ETH_MACReceptionCmd + * + * @brief Enables or disables the MAC reception. + * + * @param NewState - new state of the MAC reception. + * + * @return none + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/********************************************************************* + * @fn ETH_GetFlowControlBusyStatus + * + * @brief Enables or disables the MAC reception. + * + * @return The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_InitiatePauseControlFrame + * + * @brief Initiate a Pause Control Frame (Full-duplex only). + * + * @return none + */ +void ETH_InitiatePauseControlFrame(void) +{ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/********************************************************************* + * @fn ETH_BackPressureActivationCmd + * + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * + * @param NewState - new state of the MAC BackPressure operation activation. + * + * @return none + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/********************************************************************* + * @fn ETH_GetMACFlagStatus + * + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * + * @param ETH_MAC_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMACITStatus + * + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * + * @return The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_MACITConfig + * + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * NewState - new state of the specified ETHERNET MAC interrupts. + * + * @return none + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/********************************************************************* + * @fn ETH_MACAddressConfig + * + * @brief Configures the selected MAC address. + * + * @param MacAddr - The MAC addres to configure. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; +} + +/********************************************************************* + * @fn ETH_GetMACAddress + * + * @brief Get the selected MAC address. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)); + + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)); + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/********************************************************************* + * @fn ETH_MACAddressPerfectFilterCmd + * + * @brief Enables or disables the Address filter module uses the specified. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * NewState - new state of the specified ETHERNET MAC address use. + * + * @return none + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE); + } +} + +/********************************************************************* + * @fn ETH_MACAddressFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Filter - specifies the used frame received field for comparaison. + * ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the + * SA fields of the received frame. + * ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the + * DA fields of the received frame. + * + * @return none + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + if(Filter != ETH_MAC_AddressFilter_DA) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA); + } +} + +/********************************************************************* + * @fn ETH_MACAddressMaskBytesFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * MaskByte - specifies the used address bytes for comparaison + * ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0]. + * ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24]. + * ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16]. + * ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8]. + * ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0]. + * + * @return none + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC); + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} + +/********************************************************************* + * @fn ETH_DMATxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list + * TxBuff - Pointer on the first TxBuffer list + * TxBuffCount - Number of the used Tx desc in the list + * + * @return none + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMATxDescRingInit + * + * @brief Initializes the DMA Tx descriptors in ring mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * TxBuff1 - Pointer on the first TxBuffer1 list. + * TxBuff2 - Pointer on the first TxBuffer2 list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (TxBuffCount - 1)) + { + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * ETH_DMATxDescFlag - specifies the flag to check. + * ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine + * ETH_DMATxDesc_IC - Interrupt on completetion + * ETH_DMATxDesc_LS - Last Segment + * ETH_DMATxDesc_FS - First Segment + * ETH_DMATxDesc_DC - Disable CRC + * ETH_DMATxDesc_DP - Disable Pad + * ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable + * ETH_DMATxDesc_TER - Transmit End of Ring + * ETH_DMATxDesc_TCH - Second Address Chained + * ETH_DMATxDesc_TTSS - Tx Time Stamp Status + * ETH_DMATxDesc_IHE - IP Header Error + * ETH_DMATxDesc_ES - Error summary + * ETH_DMATxDesc_JT - Jabber Timeout + * ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush + * ETH_DMATxDesc_PCE - Payload Checksum Error + * ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission + * ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver + * ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision + * ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions + * ETH_DMATxDesc_VF - VLAN Frame + * ETH_DMATxDesc_CC - Collision Count + * ETH_DMATxDesc_ED - Excessive Deferral + * ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory + * ETH_DMATxDesc_DB - Deferred Bit + * + * @return The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescCollisionCount + * + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * + * @param pointer on a DMA Tx descriptor. + * + * @return The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/********************************************************************* + * @fn ETH_SetDMATxDescOwnBit + * + * @brief Set the specified DMA Tx Desc Own bit. + * + * @param DMATxDesc - Pointer on a Tx desc + * + * @return none + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_DMATxDescTransmitITConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param Pointer on a Tx desc. + * NewState - new state of the DMA Tx Desc transmit interrupt. + * + * @return none + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescFrameSegmentConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param PDMATxDesc - Pointer on a Tx desc. + * ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment. + * + * @return none + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/********************************************************************* + * @fn ETH_DMATxDescChecksumInsertionConfig + * + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion. + * + * @return none + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/********************************************************************* + * @fn ETH_DMATxDescCRCCmd + * + * @brief Enables or disables the DMA Tx Desc CRC. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc CRC. + * + * @return none + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Tx Desc end of ring. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc end of ring. + * + * @return none + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescSecondAddressChainedCmd + * + * @brief Enables or disables the DMA Tx Desc second address chained. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc second address chained. + * + * @return none + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescShortFramePaddingCmd + * + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @return none + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescTimeStampCmd + * + * @brief Enables or disables the DMA Tx Desc time stamp. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc time stamp. + * + * @return none + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescBufferSizeConfig + * + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc - Pointer on a Tx desc. + * BufferSize1 - specifies the Tx desc buffer1 size. + * RxBuff2 - Pointer on the first RxBuffer2 list + * BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used). + * + * @return none + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/********************************************************************* + * @fn ETH_DMARxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_DMARxDescRingInit + * + * @brief Initializes the DMA Rx descriptors in ring mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff1 - Pointer on the first RxBuffer1 list. + * RxBuff2 - Pointer on the first RxBuffer2 list + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (RxBuffCount - 1)) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * ETH_DMARxDescFlag - specifies the flag to check. + * ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine + * ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame + * ETH_DMARxDesc_ES - Error summary + * ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame + * ETH_DMARxDesc_SAF - SA Filter Fail for the received frame + * ETH_DMARxDesc_LE - Frame size not matching with length field + * ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow + * ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame + * ETH_DMARxDesc_FS - First descriptor of the frame + * ETH_DMARxDesc_LS - Last descriptor of the frame + * ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * ETH_DMARxDesc_LC - Late collision occurred during reception + * ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3 + * ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception + * ETH_DMARxDesc_RE - Receive error: error reported by MII interface + * ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits + * ETH_DMARxDesc_CE - CRC error + * ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @return The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetDMARxDescOwnBit + * + * @brief Set the specified DMA Rx Desc Own bit. + * + * @param DMARxDesc - Pointer on a Rx desc + * + * @return none + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFrameLength + * + * @brief Returns the specified DMA Rx Desc frame length. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor + * + * @return The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/********************************************************************* + * @fn ETH_DMARxDescReceiveITConfig + * + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * + * @param DMARxDesc - Pointer on a Rx desc + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/********************************************************************* + * @fn ETH_DMARxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Rx Desc end of ring. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc end of ring. + * + * @return none + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/********************************************************************* + * @fn ETH_DMARxDescSecondAddressChainedCmd + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc second address chained. + * + * @return none + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/********************************************************************* + * @fn ETH_GetDMARxDescBufferSize + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * DMARxDesc_Buffer - specifies the DMA Rx Desc buffer. + * ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1 + * ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2 + * + * @return The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/********************************************************************* + * @fn ETH_SoftwareReset + * + * @brief Resets all MAC subsystem internal registers and logic. + * + * @return none + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/********************************************************************* + * @fn ETH_GetSoftwareResetStatus + * + * @brief Checks whether the ETHERNET software reset bit is set or not. + * + * @return The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + printf("ETH->DMABMR is:%08x\n", ETH->DMABMR); + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetlinkStaus + * + * @brief Checks whether the internal 10BASE-T PHY is link or not. + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetlinkStaus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & 0x80000000) != (uint32_t)RESET) + { + bitstatus = PHY_10BASE_T_LINKED; + } + else + { + bitstatus = PHY_10BASE_T_NOT_LINKED; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMAFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * + * @param ETH_DMA_FLAG - specifies the flag to check. + * ETH_DMA_FLAG_TST - Time-stamp trigger flag + * ETH_DMA_FLAG_PMT - PMT flag + * ETH_DMA_FLAG_MMC - MMC flag + * ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access + * ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr + * ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ET - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Underflow flag + * ETH_DMA_FLAG_RO - Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearFlag + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_FLAG - specifies the flag to clear. + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ETI - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Transmit Underflow flag + * ETH_DMA_FLAG_RO - Receive Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return none + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + ETH->DMASR = (uint32_t)ETH_DMA_FLAG; +} + +/********************************************************************* + * @fn ETH_GetDMAITStatus + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_TST - Time-stamp trigger interrupt + * ETH_DMA_IT_PMT - PMT interrupt + * ETH_DMA_IT_MMC - MMC interrupt + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearITPendingBit + * + * @brief Clears the ETHERNETs DMA IT pending bit. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ETI - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Transmit Underflow interrupt + * ETH_DMA_IT_RO - Receive Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return none + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + ETH->DMASR = (uint32_t)ETH_DMA_IT; +} + +/********************************************************************* + * @fn ETH_GetTransmitProcessState + * + * @brief Returns the ETHERNET DMA Transmit Process State. + * + * @return The new ETHERNET DMA Transmit Process State - + * ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued + * ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor + * ETH_DMA_TransmitProcess_Waiting - Running - waiting for status + * ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory + * ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe + * ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/********************************************************************* + * @fn ETH_GetReceiveProcessState + * + * @brief Returns the ETHERNET DMA Receive Process State. + * + * @return The new ETHERNET DMA Receive Process State: + * ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued + * ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor + * ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet + * ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable + * ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor + * ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/********************************************************************* + * @fn ETH_FlushTransmitFIFO + * + * @brief Clears the ETHERNET transmit FIFO. + * + * @return none + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/********************************************************************* + * @fn ETH_GetFlushTransmitFIFOStatus + * + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * + * @return The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMATransmissionCmd + * + * @brief Enables or disables the DMA transmission. + * + * @param NewState - new state of the DMA transmission. + * + * @return none + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/********************************************************************* + * @fn ETH_DMAReceptionCmd + * + * @brief Enables or disables the DMA reception. + * + * @param NewState - new state of the DMA reception. + * + * @return none + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/********************************************************************* + * @fn ETH_DMAITConfig + * + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * + * @param ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * NewState - new state of the specified ETHERNET DMA interrupts. + * + * @return new state of the specified ETHERNET DMA interrupts. + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT); + } +} + +/********************************************************************* + * @fn ETH_GetDMAOverflowStatus + * + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * + * @param ETH_DMA_Overflow - specifies the DMA overflow flag to check. + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * + * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetRxOverflowMissedFrameCounter + * + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * + * @return The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); +} + +/********************************************************************* + * @fn ETH_GetBufferUnavailableMissedFrameCounter + * + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * + * @return The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHTDR register value. + * + * @return The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHRDR register value. + * + * @return The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * + * @return The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return (DMATxDescToSet->Buffer1Addr); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * + * @return The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/********************************************************************* + * @fn ETH_ResumeDMATransmission + * + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * + * @return none + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResumeDMAReception + * + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register. + * + * @return none + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResetWakeUpFrameFilterRegisterPointer + * + * @brief Reset Wakeup frame filter register pointer. + * + * @return none + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/********************************************************************* + * @fn ETH_SetWakeUpFrameFilterRegister + * + * @brief Populates the remote wakeup frame registers. + * + * @param Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * + * @return none + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) + { + ETH->MACRWUFFR = Buffer[i]; + } +} + +/********************************************************************* + * @fn ETH_GlobalUnicastWakeUpCmd + * + * @brief Enables or disables any unicast packet filtered by the MAC address. + * + * @param NewState - new state of the MAC Global Unicast Wake-Up. + * + * @return none + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/********************************************************************* + * @fn ETH_GetPMTFlagStatus + * + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * + * @param ETH_PMT_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_WakeUpFrameDetectionCmd + * + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * + * @param NewState - new state of the MAC Wake-Up Frame Detection. + * + * @return none + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/********************************************************************* + * @fn ETH_MagicPacketDetectionCmd + * + * @brief Enables or disables the MAC Magic Packet Detection. + * + * @param NewState - new state of the MAC Magic Packet Detection. + * + * @return none + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/********************************************************************* + * @fn ETH_PowerDownCmd + * + * @brief Enables or disables the MAC Power Down. + * + * @param NewState - new state of the MAC Power Down. + * + * @return none + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterFreezeCmd + * + * @brief Enables or disables the MMC Counter Freeze. + * + * @param NewState - new state of the MMC Counter Freeze. + * + * @return none + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/********************************************************************* + * @fn ETH_MMCResetOnReadCmd + * + * @brief Enables or disables the MMC Reset On Read. + * + * @param NewState - new state of the MMC Reset On Read. + * + * @return none + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterRolloverCmd + * + * @brief Enables or disables the MMC Counter Stop Rollover. + * + * @param NewState - new state of the MMC Counter Stop Rollover. + * + * @return none + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/********************************************************************* + * @fn ETH_MMCCountersReset + * + * @brief Resets the MMC Counters. + * + * @return none + */ +void ETH_MMCCountersReset(void) +{ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/********************************************************************* + * @fn ETH_MMCITConfig + * + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value. + * ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value. + * NewState - new state of the specified ETHERNET MMC interrupts. + * + * @return none + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + ETH_MMC_IT &= 0xEFFFFFFF; + + if(NewState != DISABLE) + { + ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + if(NewState != DISABLE) + { + ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/********************************************************************* + * @fn ETH_GetMMCITStatus + * + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value . + * ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value. + * + * @return The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMMCRegister + * + * @brief Get the specified ETHERNET MMC register value. + * + * @param ETH_MMCReg - specifies the ETHERNET MMC register. + * ETH_MMCCR - MMC CR register + * ETH_MMCRIR - MMC RIR register + * ETH_MMCTIR - MMC TIR register + * ETH_MMCRIMR - MMC RIMR register + * ETH_MMCTIMR - MMC TIMR register + * ETH_MMCTGFSCCR - MMC TGFSCCR register + * ETH_MMCTGFMSCCR - MMC TGFMSCCR register + * ETH_MMCTGFCR - MMC TGFCR register + * ETH_MMCRFCECR - MMC RFCECR register + * ETH_MMCRFAECR - MMC RFAECR register + * ETH_MMCRGUFCR - MMC RGUFCRregister + * + * @return The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampAddend + * + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampInterruptTrigger + * + * @brief Enable the PTP Time Stamp interrupt trigger + * + * @return none + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampUpdate + * + * @brief Updated the PTP system time with the Time Stamp Update register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/********************************************************************* + * @fn ETH_InitializePTPTimeStamp + * + * @brief Initialize the PTP Time Stamp. + * + * @return none + */ +void ETH_InitializePTPTimeStamp(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/********************************************************************* + * @fn ETH_PTPUpdateMethodConfig + * + * @brief Selects the PTP Update method. + * + * @param UpdateMethod - the PTP Update method. + * + * @return none + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + if(UpdateMethod != ETH_PTP_CoarseUpdate) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/********************************************************************* + * @fn ETH_PTPTimeStampCmd + * + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * + * @param NewState - new state of the PTP time stamp for transmit and receive frames. + * + * @return none + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/********************************************************************* + * @fn ETH_GetPTPFlagStatus + * + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * + * @param The new state of ETHERNET PTP Flag (SET or RESET). + * + * @return none + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetPTPSubSecondIncrement + * + * @brief Sets the system time Sub-Second Increment value. + * + * @param SubSecondValue - specifies the PTP Sub-Second Increment Register value. + * + * @return none + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + ETH->PTPSSIR = SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampUpdate + * + * @brief Sets the Time Stamp update sign and values. + * + * @param Sign - specifies the PTP Time update value sign. + * SecondValue - specifies the PTP Time update second value. + * SubSecondValue - specifies the PTP Time update sub-second value. + * + * @return none + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + ETH->PTPTSHUR = SecondValue; + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampAddend + * + * @brief Sets the Time Stamp Addend value. + * + * @param Value - specifies the PTP Time Stamp Addend Register value. + * + * @return none + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/********************************************************************* + * @fn ETH_SetPTPTargetTime + * + * @brief Sets the Target Time registers values. + * + * @param HighValue - specifies the PTP Target Time High Register value. + * LowValue - specifies the PTP Target Time Low Register value. + * + * @return none + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + ETH->PTPTTHR = HighValue; + ETH->PTPTTLR = LowValue; +} + +/********************************************************************* + * @fn ETH_GetPTPRegister + * + * @brief Get the specified ETHERNET PTP register value. + * + * @param ETH_PTPReg - specifies the ETHERNET PTP register. + * ETH_PTPTSCR - Sub-Second Increment Register + * ETH_PTPSSIR - Sub-Second Increment Register + * ETH_PTPTSHR - Time Stamp High Register + * ETH_PTPTSLR - Time Stamp Low Register + * ETH_PTPTSHUR - Time Stamp High Update Register + * ETH_PTPTSLUR - Time Stamp Low Update Register + * ETH_PTPTSAR - Time Stamp Addend Register + * ETH_PTPTTHR - Target Time High Register + * ETH_PTPTTLR - Target Time Low Register + * + * @return The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/********************************************************************* + * @fn ETH_DMAPTPTxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * DMAPTPTxDescTab - Pointer on the first PTP Tx desc list. + * TxBuff - Pointer on the first TxBuffer list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, + uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMAPTPRxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * DMAPTPRxDescTab - Pointer on the first PTP Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, + uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_HandlePTPTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet buffer to transmit. + * FrameLength - Tx Packet size. + * PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values. + * + * @return none. + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + do + { + timeout++; + } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandlePTPRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet receive buffer. + * PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values. + * + * @return ETH_ERROR - if there is error in reception. + * framelength - received packet size if packet reception is correct. + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn RGMII_TXC_Delay + * + * @brief Delay time. + * + * @return none + */ +void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time) +{ + if(clock_polarity) + { + ETH->MACCR |= (uint32_t)(1 << 1); + } + else + { + ETH->MACCR &= ~(uint32_t)(1 << 1); + } + if(delay_time <= 7) + { + ETH->MACCR |= (uint32_t)(delay_time << 29); + } +} diff --git a/Peripheral/src/ch32v30x_exti.c b/Peripheral/src/ch32v30x_exti.c new file mode 100644 index 0000000..afeb0ab --- /dev/null +++ b/Peripheral/src/ch32v30x_exti.c @@ -0,0 +1,180 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the EXTI firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +***************************************************************************************/ +#include "ch32v30x_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/Peripheral/src/ch32v30x_flash.c b/Peripheral/src/ch32v30x_flash.c new file mode 100644 index 0000000..0a5750c --- /dev/null +++ b/Peripheral/src/ch32v30x_flash.c @@ -0,0 +1,981 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the FLASH firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +***************************************************************************************/ +#include "ch32v30x_flash.h" + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FAST_LOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_BER64 ((uint32_t)0x00080000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/********************************************************************* + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_UnlockBank1 + * + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * equivalent to FLASH_Unlock function. + * + * @return none + */ +void FLASH_UnlockBank1(void) +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_LockBank1 + * + * @brief Locks the FLASH Bank1 Program Erase Controller. + * + * @return none + */ +void FLASH_LockBank1(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(page size 4KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllBank1Pages + * + * @brief Erases all Bank1 FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + return status; +} + +/********************************************************************* + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + uint32_t Address = 0x1FFFF800; + __IO uint8_t i; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + /* Write 0xFF */ + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Address + 2 * i) = 0x00FF; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); + + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH_Sectors = (uint32_t)(~FLASH_Sectors); + WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[4] = WRP0_Data; + pbuf[5] = WRP1_Data; + pbuf[6] = WRP2_Data; + pbuf[7] = WRP3_Data; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + if(NewState == DISABLE) + pbuf[0] = 0x5AA5; + else + pbuf[0] = 0x00FF; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_PGERR - FLASH Program error flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_PGERR - FLASH Program error flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_64K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 64KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF0000; + + FLASH->CTLR |= CR_BER64; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER64; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) +{ + uint8_t size = 64; + + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + + while(size) + { + *(uint32_t *)Page_Address = *(uint32_t *)pbuf; + Page_Address += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_Access_Clock_Cfg + * + * @brief Config FLASH Access Clock(Need to unlock ) + * + * @param FLASH_Access_CLK - + * FLASH_Access_SYSTEM_HALF - System clock/2 + * FLASH_Access_SYSTEM - System clock + * + * @return none + */ +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) +{ + FLASH->CTLR &= ~(1 << 25); + FLASH->CTLR |= FLASH_Access_CLK; +} + +/********************************************************************* + * @fn FLASH_Enhance_Mode + * + * @brief Read FLASH Enhance Mode + * + * @param + * Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return none + */ +void FLASH_Enhance_Mode(FunctionalState NewState) +{ + if(NewState) + { + FLASH->CTLR |= (1 << 24); + } + else + { + FLASH->CTLR &= ~(1 << 24); + FLASH->CTLR |= (1 << 22); + } +} + diff --git a/Peripheral/src/ch32v30x_fsmc.c b/Peripheral/src/ch32v30x_fsmc.c new file mode 100644 index 0000000..6da3b53 --- /dev/null +++ b/Peripheral/src/ch32v30x_fsmc.c @@ -0,0 +1,501 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the FSMC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_fsmc.h" +#include "ch32v30x_rcc.h" + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) + +/********************************************************************* + * @fn FSMC_NORSRAMDeInit + * + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * + * @param FSMC_Bank- + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1. + * + * @return none + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/********************************************************************* + * @fn FSMC_NANDDeInit + * + * @brief Deinitializes the FSMC NAND Banks registers to their default + * reset values. + * + * @param FSMC_Bank - + * FSMC_Bank2_NAND - FSMC Bank2 NAND. + * + * @return none + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMInit + * + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * + * @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * + * @return none + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/********************************************************************* + * @fn FSMC_NANDInit + * + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * + * @return none + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMStructInit + * + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * + * @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/********************************************************************* + * @fn FSMC_NANDStructInit + * + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/********************************************************************* + * @fn FSMC_NORSRAMCmd + * + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1 + * FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2 + * FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3 + * FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4 + * NewStateENABLE or DISABLE. + * + * @return none + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/********************************************************************* + * @fn FSMC_NANDCmd + * + * @brief Enables or disables the specified NAND Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_Bank3_NAND - FSMC Bank3 NAND + * NewStat - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_NANDECCCmd + * + * @brief Enables or disables the FSMC NAND ECC feature. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_GetECC + * + * @brief Returns the error correction code register value. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return eccval - The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + eccval = FSMC_Bank2->ECCR2; + } + + return (eccval); +} + +/********************************************************************* + * @fn FSMC_ITConfig + * + * @brief Enables or disables the specified FSMC interrupts. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_IT - specifies the FSMC interrupt sources to be enabled or disabled. + * FSMC_IT_RisingEdge - Rising edge detection interrupt. + * FSMC_IT_Level - Level edge detection interrupt. + * FSMC_IT_FallingEdge - Falling edge detection interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + } +} + +/********************************************************************* + * @fn FSMC_GetFlagStatus + * + * @brief Checks whether the specified FSMC flag is set or not. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_FLAG - specifies the flag to check. + * FSMC_FLAG_RisingEdge - Rising egde detection Flag. + * FSMC_FLAG_Level - Level detection Flag. + * FSMC_FLAG_FallingEdge - Falling egde detection Flag. + * FSMC_FLAG_FEMPT - Fifo empty Flag. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + + if((tmpsr & FSMC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn FSMC_ClearFlag + * + * @brief Clears the FSMC's pending flags. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_FLAG - specifies the flag to check. + * FSMC_FLAG_RisingEdge - Rising egde detection Flag. + * FSMC_FLAG_Level - Level detection Flag. + * FSMC_FLAG_FallingEdge - Falling egde detection Flag. + * + * @return none + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } +} + +/********************************************************************* + * @fn FSMC_GetITStatus + * + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_IT - specifies the FSMC interrupt source to check. + * FSMC_IT_RisingEdge - Rising edge detection interrupt. + * FSMC_IT_Level - Level edge detection interrupt. + * FSMC_IT_FallingEdge - Falling edge detection interrupt. + * + * @return ITStatus - The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn FSMC_ClearITPendingBit + * + * @brief Clears the FSMC's interrupt pending bits. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_IT - specifies the FSMC interrupt source to check. + * FSMC_IT_RisingEdge - Rising edge detection interrupt. + * FSMC_IT_Level - Level edge detection interrupt. + * FSMC_IT_FallingEdge - Falling edge detection interrupt. + * + * @return none + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } +} diff --git a/Peripheral/src/ch32v30x_gpio.c b/Peripheral/src/ch32v30x_gpio.c new file mode 100644 index 0000000..169646f --- /dev/null +++ b/Peripheral/src/ch32v30x_gpio.c @@ -0,0 +1,566 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the GPIO firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_gpio.h" +#include "ch32v30x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_SetL - to clear the port pin. + * Bit_SetH - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD01 - PD01 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x80000000) == 0x80000000) + { /* PCFR2 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + } + else + { /* PCFR1 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_ETH_MediaInterfaceConfig + * + * @brief Selects the Ethernet media interface. + * + * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. + * GPIO_ETH_MediaInterface_MII - MII mode + * GPIO_ETH_MediaInterface_RMII - RMII mode + * + * @return none + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + if(GPIO_ETH_MediaInterface) + { + AFIO->PCFR1 |= (1 << 23); + } + else + { + AFIO->PCFR1 &= ~(1 << 23); + } +} diff --git a/Peripheral/src/ch32v30x_i2c.c b/Peripheral/src/ch32v30x_i2c.c new file mode 100644 index 0000000..17da0e4 --- /dev/null +++ b/Peripheral/src/ch32v30x_i2c.c @@ -0,0 +1,972 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the I2C firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_i2c.h" +#include "ch32v30x_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EV4. + * I2C_EVENT_MASTER_MODE_SELECT - EV5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EV7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9. + * + * @return none + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return none + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/Peripheral/src/ch32v30x_iwdg.c b/Peripheral/src/ch32v30x_iwdg.c new file mode 100644 index 0000000..7c66893 --- /dev/null +++ b/Peripheral/src/ch32v30x_iwdg.c @@ -0,0 +1,120 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the IWDG firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/Peripheral/src/ch32v30x_misc.c b/Peripheral/src/ch32v30x_misc.c new file mode 100644 index 0000000..6c12011 --- /dev/null +++ b/Peripheral/src/ch32v30x_misc.c @@ -0,0 +1,107 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_misc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the miscellaneous firmware functions . +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*********************************************************************************/ +#include "ch32v30x_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 4 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority + * 1 bits for subpriority + * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority + * 0 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ + uint8_t tmppre = 0; + + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + else + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); + } + else + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); + } + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); + } + else + { + tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); + } + } + else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); + } + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/Peripheral/src/ch32v30x_opa.c b/Peripheral/src/ch32v30x_opa.c new file mode 100644 index 0000000..f157794 --- /dev/null +++ b/Peripheral/src/ch32v30x_opa.c @@ -0,0 +1,84 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the OPA firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +***************************************************************************************/ +#include "ch32v30x_opa.h" + +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + OPA->CR = 0; +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = OPA->CR; + tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + OPA->CR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->Mode = OUT_IO; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->OPA_NUM = OPA1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); + } + else + { + OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); + } +} diff --git a/Peripheral/src/ch32v30x_pwr.c b/Peripheral/src/ch32v30x_pwr.c new file mode 100644 index 0000000..a36907d --- /dev/null +++ b/Peripheral/src/ch32v30x_pwr.c @@ -0,0 +1,321 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the PWR firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V + * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V + * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V + * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V + * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V + * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V + * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V + * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_CWUF; + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return none + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby w power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} diff --git a/Peripheral/src/ch32v30x_rcc.c b/Peripheral/src/ch32v30x_rcc.c new file mode 100644 index 0000000..63ce4e3 --- /dev/null +++ b/Peripheral/src/ch32v30x_rcc.c @@ -0,0 +1,1424 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RCC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) /* 103 */ +#define CFGR0_PLL_Mask_1 ((uint32_t)0xFFC2FFFF) /* 107 */ + +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* CFGR2 register bit mask */ +#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) +#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) +#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) +#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + +#ifdef CH32V30x_D8C + RCC->CFGR0 &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR0 &= (uint32_t)0xF0FF0000; +#endif + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return SUCCESS - HSE oscillator is stable and ready to use. + * ERROR - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock + * entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * For CH32V307 - + * RCC_PLLMul_18_EXTEN + * RCC_PLLMul_3_EXTEN + * RCC_PLLMul_4_EXTEN + * RCC_PLLMul_5_EXTEN + * RCC_PLLMul_6_EXTEN + * RCC_PLLMul_7_EXTEN + * RCC_PLLMul_8_EXTEN + * RCC_PLLMul_9_EXTEN + * RCC_PLLMul_10_EXTEN + * RCC_PLLMul_11_EXTEN + * RCC_PLLMul_12_EXTEN + * RCC_PLLMul_13_EXTEN + * RCC_PLLMul_14_EXTEN + * RCC_PLLMul_6_5_EXTEN + * RCC_PLLMul_15_EXTEN + * RCC_PLLMul_16_EXTEN + * For other CH32V30x - + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + tmpreg &= CFGR0_PLL_Mask; + } + else + { /* for CH32V307 */ + tmpreg &= CFGR0_PLL_Mask_1; + } + + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 15); + } + else + { + RCC->BDCTLR &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = (pllmull >> 18) + 2; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + if(pllmull == 17) + pllmull = 18; + } + else + { /* for CH32V307 */ + if(pllmull == 2) + pllmull = 18; + if(pllmull == 15) + { + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) + pllmull = 15; + if(pllmull == 17) + pllmull = 16; + } + + if(pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + } + + if(Pll_6_5 == 1) + RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2); + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_CRC. + * RCC_AHBPeriph_FSMC + * RCC_AHBPeriph_RNG + * RCC_AHBPeriph_SDIO + * RCC_AHBPeriph_USBHS + * RCC_AHBPeriph_OTG_FS + * RCC_AHBPeriph_DVP + * RCC_AHBPeriph_ETH_MAC + * RCC_AHBPeriph_ETH_MAC_Tx + * RCC_AHBPeriph_ETH_MAC_Rx + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 16); + } + else + { + RCC->BDCTLR &= ~(1 << 16); + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * RCC_MCO_PLL2CLK - PLL2 clock selected + * RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected + * RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected + * RCC_MCO_PLL3CLK - PLL3 clock selected + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_PLL2RDY - PLL2 clock ready. + * RCC_FLAG_PLL3RDY - PLL3 clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else if(tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ + +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_PREDIV1Config + * + * @brief Configures the PREDIV1 division factor. + * + * @param RCC_PREDIV1_Source - specifies the PREDIV1 clock source. + * RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock + * RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock + * RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x[1,16] + * + * @return none + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PREDIV2Config + * + * @brief Configures the PREDIV2 division factor. + * + * @param RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * + * @return none + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PREDIV2; + tmpreg |= RCC_PREDIV2_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Config + * + * @brief Configures the PLL2 multiplication factor. + * + * @param RCC_PLL2Mul - specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * + * @return none + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL2MUL; + tmpreg |= RCC_PLL2Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Cmd + * + * @brief Enables or disables the PLL2. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 26); + } + else + { + RCC->CTLR &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn RCC_PLL3Config + * + * @brief Configures the PLL3 multiplication factor. + * + * @param RCC_PLL3Mul - specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * + * @return none + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL3MUL; + tmpreg |= RCC_PLL3Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL3Cmd + * + * @brief Enables or disables the PLL3. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 28); + } + else + { + RCC->CTLR &= ~(1 << 28); + } +} + +/********************************************************************* + * @fn RCC_OTGFSCLKConfig + * + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * + * @param RCC_OTGFSCLKSource - specifies the USB OTG FS clock source. + * RCC_OTGFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1 + * selected as USB OTG FS clock source + * RCC_OTGFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2 + * selected as USB OTG FS clock source + * RCC_OTGFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3 + * selected as USB OTG FS clock source + * + * @return none + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + RCC->CFGR0 &= ~(3 << 22); + RCC->CFGR0 |= RCC_OTGFSCLKSource << 22; +} + +/********************************************************************* + * @fn RCC_I2S2CLKConfig + * + * @brief Configures the I2S2 clock source(I2S2CLK). + * + * @param RCC_I2S2CLKSource - specifies the I2S2 clock source. + * RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry + * RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry + * + * @return none + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + RCC->CFGR2 &= ~(1 << 17); + RCC->CFGR2 |= RCC_I2S2CLKSource << 17; +} + +/********************************************************************* + * @fn RCC_I2S3CLKConfig + * + * @brief Configures the I2S3 clock source(I2S2CLK). + * + * @param RCC_I2S3CLKSource - specifies the I2S3 clock source. + * RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry + * RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry + * + * @return none + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + RCC->CFGR2 &= ~(1 << 18); + RCC->CFGR2 |= RCC_I2S3CLKSource << 18; +} + +/********************************************************************* + * @fn RCC_AHBPeriphResetCmd + * + * @brief Forces or releases AHB peripheral reset. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. + * RCC_AHBPeriph_OTG_FS + * RCC_AHBPeriph_ETH_MAC + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKADJcmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ADCCLKADJcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR0 |= (1 << 31); + } + else + { + RCC->CFGR0 &= ~(1 << 31); + } +} + +/********************************************************************* + * @fn RCC_RNGCLKConfig + * + * @brief Configures the RNG clock source. + * + * @param RCC_RNGCLKSource - specifies the RNG clock source. + * RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry + * RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry + * + * @return none + */ +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource) +{ + RCC->CFGR2 &= ~(1 << 19); + RCC->CFGR2 |= RCC_RNGCLKSource << 19; +} + +/********************************************************************* + * @fn RCC_ETH1GCLKConfig + * + * @brief Configures the ETH1G clock source. + * + * @param RCC_RNGCLKSource - specifies the ETH1G clock source. + * RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PB1_IN - GPIO PB1 input clock selected as ETH1G clock entry + * + * @return none + */ +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource) +{ + RCC->CFGR2 &= ~(3 << 20); + RCC->CFGR2 |= RCC_ETH1GCLKSource << 20; +} + +/********************************************************************* + * @fn RCC_ETH1G_125Mcmd + * + * @brief Enable ETH1G 125M. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ETH1G_125Mcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 22); + } + else + { + RCC->CFGR2 &= ~(1 << 22); + } +} + +/********************************************************************* + * @fn RCC_USBHSConfig + * + * @brief Configures the USBHS clock. + * + * @param RCC_USBHS - defines the USBHS clock divider. + * RCC_USBPLL_Div1 - USBHS clock = USBPLL. + * RCC_USBPLL_Div2 - USBHS clock = USBPLL/2. + * RCC_USBPLL_Div3 - USBHS clock = USBPLL/3. + * RCC_USBPLL_Div4 - USBHS clock = USBPLL/4. + * RCC_USBPLL_Div5 - USBHS clock = USBPLL/5. + * RCC_USBPLL_Div6 - USBHS clock = USBPLL/6. + * RCC_USBPLL_Div7 - USBHS clock = USBPLL/7. + * RCC_USBPLL_Div8 - USBHS clock = USBPLL/8. + * + * @return none + */ +void RCC_USBHSConfig(uint32_t RCC_USBHS) +{ + RCC->CFGR2 &= ~(7 << 24); + RCC->CFGR2 |= RCC_USBHS << 24; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCLKConfig + * + * @brief Configures the USBHSPLL clock source. + * + * @param RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source. + * RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry + * RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry + * + * @return none + */ +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource) +{ + RCC->CFGR2 &= ~(1 << 27); + RCC->CFGR2 |= RCC_USBHSPLLCLKSource << 27; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCKREFCLKConfig + * + * @brief Configures the USBHSPLL reference clock. + * + * @param RCC_USBHSPLLCKREFCLKSource - Select reference clock. + * RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz. + * RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz. + * RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz. + * RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz. + * + * @return none + */ +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource) +{ + RCC->CFGR2 &= ~(3 << 28); + RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource << 28; +} + +/********************************************************************* + * @fn RCC_USBHSPHYPLLALIVEcmd + * + * @brief Enable USBHS PHY control. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 30); + } + else + { + RCC->CFGR2 &= ~(1 << 30); + } +} + +/********************************************************************* + * @fn RCC_USBCLK48MConfig + * + * @brief Configures the USB clock 48MHz source. + * + * @param RCC_USBCLK48MSource - specifies the USB clock 48MHz source. + * RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry + * RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry + * + * @return none + */ +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource) +{ + RCC->CFGR2 &= ~(1 << 31); + RCC->CFGR2 |= RCC_USBCLK48MSource << 31; +} diff --git a/Peripheral/src/ch32v30x_rng.c b/Peripheral/src/ch32v30x_rng.c new file mode 100644 index 0000000..bd68c07 --- /dev/null +++ b/Peripheral/src/ch32v30x_rng.c @@ -0,0 +1,152 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RNG firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ +#include "ch32v30x_rng.h" +#include "ch32v30x_rcc.h" + +/********************************************************************* + * @fn RNG_Cmd + * + * @brief Enables or disables the RNG peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RNG_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_RNGEN; + } + else + { + RNG->CR &= ~RNG_CR_RNGEN; + } +} + +/********************************************************************* + * @fn RNG_GetRandomNumber + * + * @brief Returns a 32-bit random number. + * + * @return 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + return RNG->DR; +} + +/********************************************************************* + * @fn RNG_ITConfig + * + * @brief Enables or disables the RNG interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return 32-bit random number. + */ +void RNG_ITConfig(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_IE; + } + else + { + RNG->CR &= ~RNG_CR_IE; + } +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG flag is set or not. + * + * @param RNG_FLAG - specifies the RNG flag to check. + * RNG_FLAG_DRDY - Data Ready flag. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearFlag + * + * @brief Clears the RNG flags. + * + * @param RNG_FLAG - specifies the flag to clear. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG interrupt has occurred or not. + * + * @param RNG_IT - specifies the RNG interrupt source to check. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return bitstatusSET or RESET. + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + + if((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearITPendingBit + * + * @brief Clears the RNG interrupt pending bit(s). + * + * @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + RNG->SR = (uint8_t)~RNG_IT; +} diff --git a/Peripheral/src/ch32v30x_rtc.c b/Peripheral/src/ch32v30x_rtc.c new file mode 100644 index 0000000..09eee43 --- /dev/null +++ b/Peripheral/src/ch32v30x_rtc.c @@ -0,0 +1,273 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RTC firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +********************************************************************************/ +#include "ch32v30x_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if(high1 != high2) + { + return (((uint32_t)high2 << 16) | RTC->CNTL); + } + else + { + return (((uint32_t)high1 << 16) | low); + } +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC APB clock + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} diff --git a/Peripheral/src/ch32v30x_sdio.c b/Peripheral/src/ch32v30x_sdio.c new file mode 100644 index 0000000..7241dd1 --- /dev/null +++ b/Peripheral/src/ch32v30x_sdio.c @@ -0,0 +1,670 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_SDIO.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SDIO firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_sdio.h" +#include "ch32v30x_rcc.h" + +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/********************************************************************* + * @fn SDIO_DeInit + * + * @brief Deinitializes the SDIO peripheral registers to their default + * reset values. + * + * @return RTC counter value + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/********************************************************************* + * @fn SDIO_Init + * + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * + * @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * + * @return None + */ +void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = SDIO->CLKCR; + tmpreg &= CLKCR_CLEAR_MASK; + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + SDIO->CLKCR = tmpreg; +} + +/********************************************************************* + * @fn SDIO_StructInit + * + * @brief Fills each SDIO_InitStruct member with its default value. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct) +{ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/********************************************************************* + * @fn SDIO_ClockCmd + * + * @brief Enables or disables the SDIO Clock. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CLKCR |= (1 << 8); + else + SDIO->CLKCR &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_SetPowerState + * + * @brief Sets the power status of the controller. + * + * @param SDIO_PowerState - new state of the Power state. + * SDIO_PowerState_OFF + * SDIO_PowerState_ON + * + * @return none + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/********************************************************************* + * @fn SDIO_GetPowerState + * + * @brief Gets the power status of the controller. + * + * @param CounterValue - RTC counter new value. + * + * @return power state - + * 0x00 - Power OFF + * 0x02 - Power UP + * 0x03 - Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/********************************************************************* + * @fn SDIO_ITConfig + * + * @brief Enables or disables the SDIO interrupts. + * + * @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled. + * SDIO_IT_CCRCFAIL + * SDIO_IT_DCRCFAIL + * SDIO_IT_CTIMEOUT + * SDIO_IT_DTIMEOUT + * SDIO_IT_TXUNDERR + * SDIO_IT_RXOVERR + * SDIO_IT_CMDREND + * SDIO_IT_CMDSENT + * SDIO_IT_DATAEND + * SDIO_IT_STBITERR + * SDIO_IT_DBCKEND + * SDIO_IT_CMDACT + * SDIO_IT_TXACT + * SDIO_IT_RXACT + * SDIO_IT_TXFIFOHE + * SDIO_IT_RXFIFOHF + * SDIO_IT_TXFIFOF + * SDIO_IT_RXFIFOF + * SDIO_IT_TXFIFOE + * SDIO_IT_RXFIFOE + * SDIO_IT_TXDAVL + * SDIO_IT_RXDAVL + * SDIO_IT_SDIOIT + * SDIO_IT_CEATAEND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SDIO->MASK |= SDIO_IT; + } + else + { + SDIO->MASK &= ~SDIO_IT; + } +} + +/********************************************************************* + * @fn SDIO_DMACmd + * + * @brief Enables or disables the SDIO DMA request. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 3); + else + SDIO->DCTRL &= ~(1 << 3); +} + +/********************************************************************* + * @fn SDIO_SendCommand + * + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for + * ddthe SDIO command. + * + * @return none + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + + tmpreg = SDIO->CMD; + tmpreg &= CMD_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + SDIO->CMD = tmpreg; +} + +/********************************************************************* + * @fn SDIO_CmdStructInit + * + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * + * @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetCommandResponse + * + * @brief Returns command index of last command for which response received. + * + * @return Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/********************************************************************* + * @fn SDIO_GetResponse + * + * @brief Returns response received from the card for the last command. + * + * @param SDIO_RESP - Specifies the SDIO response register. + * SDIO_RESP1 - Response Register 1 + * SDIO_RESP2 - Response Register 2 + * SDIO_RESP3 - Response Register 3 + * SDIO_RESP4 - Response Register 4 + * + * @return Returns the command index of the last command response received. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn SDIO_DataConfig + * + * @brief Initializes the SDIO data path according to the specified + * + * @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * + * @return none + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + tmpreg = SDIO->DCTRL; + tmpreg &= DCTRL_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + SDIO->DCTRL = tmpreg; +} + +/********************************************************************* + * @fn SDIO_DataStructInit + * + * @brief Fills each SDIO_DataInitStruct member with its default value. + * + * @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef + * structure which will be initialized. + * + * @return RTC counter value + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetDataCounter + * + * @brief Returns number of remaining data bytes to be transferred. + * + * @return Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/********************************************************************* + * @fn SDIO_ReadData + * + * @brief Read one data word from Rx FIFO. + * + * @return Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/********************************************************************* + * @fn SDIO_WriteData + * + * @brief Write one data word to Tx FIFO. + * + * @param Data - 32-bit data word to write. + * + * @return RTC counter value + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/********************************************************************* + * @fn SDIO_GetFIFOCount + * + * @brief Returns the number of words left to be written to or read from FIFO. + * + * @return Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/********************************************************************* + * @fn SDIO_StartSDIOReadWait + * + * @brief Starts the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 8); + else + SDIO->DCTRL &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_StopSDIOReadWait + * + * @brief Stops the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 9); + else + SDIO->DCTRL &= ~(1 << 9); +} + +/********************************************************************* + * @fn SDIO_SetSDIOReadWaitMode + * + * @brief Sets one of the two options of inserting read wait interval. + * + * @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode. + * SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK + * SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2 + * + * @return none + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + if(SDIO_ReadWaitMode) + SDIO->DCTRL |= (1 << 10); + else + SDIO->DCTRL &= ~(1 << 10); +} + +/********************************************************************* + * @fn SDIO_SetSDIOOperation + * + * @brief Enables or disables the SD I/O Mode Operation. + * + * @param NewState: ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 11); + else + SDIO->DCTRL &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_SendSDIOSuspendCmd + * + * @brief Enables or disables the SD I/O Mode suspend command sending. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 11); + else + SDIO->CMD &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_CommandCompletionCmd + * + * @brief Enables or disables the command completion signal. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 12); + else + SDIO->CMD &= ~(1 << 12); +} + +/********************************************************************* + * @fn SDIO_CEATAITCmd + * + * @brief Enables or disables the CE-ATA interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 13); + else + SDIO->CMD &= ~(1 << 13); +} + +/********************************************************************* + * @fn SDIO_SendCEATACmd + * + * @brief Sends CE-ATA command (CMD61). + * + * @param NewState - ENABLE or DISABLE. + * + * @return RTC counter value + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 14); + else + SDIO->CMD &= ~(1 << 14); +} + +/********************************************************************* + * @fn SDIO_GetFlagStatus + * + * @brief Checks whether the specified SDIO flag is set or not. + * + * @param SDIO_FLAG - specifies the flag to check. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode. + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_CMDACT - Command transfer in progress + * SDIO_FLAG_TXACT - Data transmit in progress + * SDIO_FLAG_RXACT - Data receive in progress + * SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty + * SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full + * SDIO_FLAG_TXFIFOF - Transmit FIFO full + * SDIO_FLAG_RXFIFOF - Receive FIFO full + * SDIO_FLAG_TXFIFOE - Transmit FIFO empty + * SDIO_FLAG_RXFIFOE - Receive FIFO empty + * SDIO_FLAG_TXDAVL - Data available in transmit FIFO + * SDIO_FLAG_RXDAVL - Data available in receive FIFO + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received + * for CMD61 + * + * @return ITStatus - SET or RESET + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearFlag + * + * @brief Clears the SDIO's pending flags. + * + * @param SDIO_FLAG - specifies the flag to clear. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return none + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + SDIO->ICR = SDIO_FLAG; +} + +/********************************************************************* + * @fn SDIO_GetITStatus + * + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt + * SDIO_IT_CMDACT - Command transfer in progress interrupt + * SDIO_IT_TXACT - Data transmit in progress interrupt + * SDIO_IT_RXACT - Data receive in progress interrupt + * SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt + * SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt + * SDIO_IT_TXFIFOF - Transmit FIFO full interrupt + * SDIO_IT_RXFIFOF - Receive FIFO full interrupt + * SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt + * SDIO_IT_RXFIFOE - Receive FIFO empty interrupt + * SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt + * SDIO_IT_RXDAVL - Data available in receive FIFO interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt + * + * @return ITStatusSET or RESET + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearITPendingBit + * + * @brief Clears the SDIO's interrupt pending bits. + * + * @param SDIO_IT - specifies the interrupt pending bit to clear. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return RTC counter value + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + SDIO->ICR = SDIO_IT; +} diff --git a/Peripheral/src/ch32v30x_spi.c b/Peripheral/src/ch32v30x_spi.c new file mode 100644 index 0000000..105d182 --- /dev/null +++ b/Peripheral/src/ch32v30x_spi.c @@ -0,0 +1,646 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SPI firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*********************************************************************************/ +#include "ch32v30x_spi.h" +#include "ch32v30x_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if(SPIx == SPI3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->I2SCFGR &= SPI_Mode_Select; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn I2S_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * (configured in I2S mode). + * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @return none + */ +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + tmpreg = SPIx->I2SCFGR; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + packetlength = 1; + } + else + { + packetlength = 2; + } + + if(((uint32_t)SPIx) == SPI2_BASE) + { + tmp = I2S2_CLOCK_SRC; + } + else + { + tmp = I2S3_CLOCK_SRC; + } + + RCC_GetClocksFreq(&RCC_Clocks); + + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + tmp = tmp / 10; + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sodd = (uint16_t)(i2sodd << 8); + } + + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + i2sdiv = 2; + i2sodd = 0; + } + + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + SPIx->I2SCFGR = tmpreg; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn I2S_StructInit + * + * @brief Fills each I2S_InitStruct member with its default value. + * + * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) +{ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn I2S_Cmd + * + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI/I2S interrupts. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return none + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * + * @return none + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/Peripheral/src/ch32v30x_tim.c b/Peripheral/src/ch32v30x_tim.c new file mode 100644 index 0000000..182ab10 --- /dev/null +++ b/Peripheral/src/ch32v30x_tim.c @@ -0,0 +1,2366 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the TIM firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_tim.h" +#include "ch32v30x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if(TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if(TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if(TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if(TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if(TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/Peripheral/src/ch32v30x_usart.c b/Peripheral/src/ch32v30x_usart.c new file mode 100644 index 0000000..b7749ce --- /dev/null +++ b/Peripheral/src/ch32v30x_usart.c @@ -0,0 +1,826 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the USART firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_usart.h" +#include "ch32v30x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */ +#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if(USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if(USARTx == UART6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE); + } + else if(USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else if(USARTx == UART8) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else + { + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_CTS - CTS change interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + if(USART_IT == USART_IT_CTS) + { + } + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_OverSampling8Cmd + * + * @brief Enables or disables the USART's 8x oversampling mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_OVER8_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_OVER8_Reset; + } +} + +/********************************************************************* + * @fn USART_OneBitMethodCmd + * + * @brief Enables or disables the USART's one bit sampling method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_ONEBITE_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_ONEBITE_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_CTS - CTS Change flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return none + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(USART_FLAG == USART_FLAG_CTS) + { + } + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_CTS - CTS Change flag. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + } + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_CTS - CTS change interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return none + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + if(USART_IT == USART_IT_CTS) + { + } + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_CTS - CTS change interrupt. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + if(USART_IT == USART_IT_CTS) + { + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/Peripheral/src/ch32v30x_wwdg.c b/Peripheral/src/ch32v30x_wwdg.c new file mode 100644 index 0000000..fad4677 --- /dev/null +++ b/Peripheral/src/ch32v30x_wwdg.c @@ -0,0 +1,139 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the WWDG firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +**********************************************************************************/ +#include "ch32v30x_wwdg.h" +#include "ch32v30x_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/Startup/startup_ch32v30x.S b/Startup/startup_ch32v30x.S new file mode 100644 index 0000000..3030734 --- /dev/null +++ b/Startup/startup_ch32v30x.S @@ -0,0 +1,386 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : startup_ch32v30x.s +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x vector table for eclipse toolchain. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00100073 + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* TAMPER */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line 0 */ + .word EXTI1_IRQHandler /* EXTI Line 1 */ + .word EXTI2_IRQHandler /* EXTI Line 2 */ + .word EXTI3_IRQHandler /* EXTI Line 3 */ + .word EXTI4_IRQHandler /* EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1_2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word RNG_IRQHandler /* RNG */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word ETH_IRQHandler /* ETH */ + .word ETH_WKUP_IRQHandler /* ETH WakeUp */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* OTGFS */ + .word USBHSWakeup_IRQHandler /* USBHS Wakeup */ + .word USBHS_IRQHandler /* USBHS */ + .word DVP_IRQHandler /* DVP */ + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word TIM9_BRK_IRQHandler /* TIM9 Break */ + .word TIM9_UP_IRQHandler /* TIM9 Update */ + .word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .word TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .word TIM10_BRK_IRQHandler /* TIM10 Break */ + .word TIM10_UP_IRQHandler /* TIM10 Update */ + .word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .word TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + + .option rvc; + + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak TAMPER_IRQHandler /* TAMPER */ + .weak RTC_IRQHandler /* RTC */ + .weak FLASH_IRQHandler /* Flash */ + .weak RCC_IRQHandler /* RCC */ + .weak EXTI0_IRQHandler /* EXTI Line 0 */ + .weak EXTI1_IRQHandler /* EXTI Line 1 */ + .weak EXTI2_IRQHandler /* EXTI Line 2 */ + .weak EXTI3_IRQHandler /* EXTI Line 3 */ + .weak EXTI4_IRQHandler /* EXTI Line 4 */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC1_2_IRQHandler /* ADC1_2 */ + .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ + .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_IRQHandler /* TIM2 */ + .weak TIM3_IRQHandler /* TIM3 */ + .weak TIM4_IRQHandler /* TIM4 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak I2C2_EV_IRQHandler /* I2C2 Event */ + .weak I2C2_ER_IRQHandler /* I2C2 Error */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak SPI2_IRQHandler /* SPI2 */ + .weak USART1_IRQHandler /* USART1 */ + .weak USART2_IRQHandler /* USART2 */ + .weak USART3_IRQHandler /* USART3 */ + .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .weak TIM8_BRK_IRQHandler /* TIM8 Break */ + .weak TIM8_UP_IRQHandler /* TIM8 Update */ + .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .weak RNG_IRQHandler /* RNG */ + .weak FSMC_IRQHandler /* FSMC */ + .weak SDIO_IRQHandler /* SDIO */ + .weak TIM5_IRQHandler /* TIM5 */ + .weak SPI3_IRQHandler /* SPI3 */ + .weak UART4_IRQHandler /* UART4 */ + .weak UART5_IRQHandler /* UART5 */ + .weak TIM6_IRQHandler /* TIM6 */ + .weak TIM7_IRQHandler /* TIM7 */ + .weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .weak ETH_IRQHandler /* ETH */ + .weak ETH_WKUP_IRQHandler /* ETH WakeUp */ + .weak CAN2_TX_IRQHandler /* CAN2 TX */ + .weak CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .weak CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .weak CAN2_SCE_IRQHandler /* CAN2 SCE */ + .weak OTG_FS_IRQHandler /* OTGFS */ + .weak USBHSWakeup_IRQHandler /* USBHS Wakeup */ + .weak USBHS_IRQHandler /* USBHS */ + .weak DVP_IRQHandler /* DVP */ + .weak UART6_IRQHandler /* UART6 */ + .weak UART7_IRQHandler /* UART7 */ + .weak UART8_IRQHandler /* UART8 */ + .weak TIM9_BRK_IRQHandler /* TIM9 Break */ + .weak TIM9_UP_IRQHandler /* TIM9 Update */ + .weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .weak TIM10_BRK_IRQHandler /* TIM10 Break */ + .weak TIM10_UP_IRQHandler /* TIM10 Update */ + .weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + +NMI_Handler: 1: j 1b +HardFault_Handler: 1: j 1b +Ecall_M_Mode_Handler: 1: j 1b +Ecall_U_Mode_Handler: 1: j 1b +Break_Point_Handler: 1: j 1b +SysTick_Handler: 1: j 1b +SW_handler: 1: j 1b +WWDG_IRQHandler: 1: j 1b +PVD_IRQHandler: 1: j 1b +TAMPER_IRQHandler: 1: j 1b +RTC_IRQHandler: 1: j 1b +FLASH_IRQHandler: 1: j 1b +RCC_IRQHandler: 1: j 1b +EXTI0_IRQHandler: 1: j 1b +EXTI1_IRQHandler: 1: j 1b +EXTI2_IRQHandler: 1: j 1b +EXTI3_IRQHandler: 1: j 1b +EXTI4_IRQHandler: 1: j 1b +DMA1_Channel1_IRQHandler: 1: j 1b +DMA1_Channel2_IRQHandler: 1: j 1b +DMA1_Channel3_IRQHandler: 1: j 1b +DMA1_Channel4_IRQHandler: 1: j 1b +DMA1_Channel5_IRQHandler: 1: j 1b +DMA1_Channel6_IRQHandler: 1: j 1b +DMA1_Channel7_IRQHandler: 1: j 1b +ADC1_2_IRQHandler: 1: j 1b +USB_HP_CAN1_TX_IRQHandler: 1: j 1b +USB_LP_CAN1_RX0_IRQHandler: 1: j 1b +CAN1_RX1_IRQHandler: 1: j 1b +CAN1_SCE_IRQHandler: 1: j 1b +EXTI9_5_IRQHandler: 1: j 1b +TIM1_BRK_IRQHandler: 1: j 1b +TIM1_UP_IRQHandler: 1: j 1b +TIM1_TRG_COM_IRQHandler: 1: j 1b +TIM1_CC_IRQHandler: 1: j 1b +TIM2_IRQHandler: 1: j 1b +TIM3_IRQHandler: 1: j 1b +TIM4_IRQHandler: 1: j 1b +I2C1_EV_IRQHandler: 1: j 1b +I2C1_ER_IRQHandler: 1: j 1b +I2C2_EV_IRQHandler: 1: j 1b +I2C2_ER_IRQHandler: 1: j 1b +SPI1_IRQHandler: 1: j 1b +SPI2_IRQHandler: 1: j 1b +USART1_IRQHandler: 1: j 1b +USART2_IRQHandler: 1: j 1b +USART3_IRQHandler: 1: j 1b +EXTI15_10_IRQHandler: 1: j 1b +RTCAlarm_IRQHandler: 1: j 1b +USBWakeUp_IRQHandler: 1: j 1b +TIM8_BRK_IRQHandler: 1: j 1b +TIM8_UP_IRQHandler: 1: j 1b +TIM8_TRG_COM_IRQHandler: 1: j 1b +TIM8_CC_IRQHandler: 1: j 1b +RNG_IRQHandler: 1: j 1b +FSMC_IRQHandler: 1: j 1b +SDIO_IRQHandler: 1: j 1b +TIM5_IRQHandler: 1: j 1b +SPI3_IRQHandler: 1: j 1b +UART4_IRQHandler: 1: j 1b +UART5_IRQHandler: 1: j 1b +TIM6_IRQHandler: 1: j 1b +TIM7_IRQHandler: 1: j 1b +DMA2_Channel1_IRQHandler: 1: j 1b +DMA2_Channel2_IRQHandler: 1: j 1b +DMA2_Channel3_IRQHandler: 1: j 1b +DMA2_Channel4_IRQHandler: 1: j 1b +DMA2_Channel5_IRQHandler: 1: j 1b +ETH_IRQHandler: 1: j 1b +ETH_WKUP_IRQHandler: 1: j 1b +CAN2_TX_IRQHandler: 1: j 1b +CAN2_RX0_IRQHandler: 1: j 1b +CAN2_RX1_IRQHandler: 1: j 1b +CAN2_SCE_IRQHandler: 1: j 1b +OTG_FS_IRQHandler: 1: j 1b +USBHSWakeup_IRQHandler: 1: j 1b +USBHS_IRQHandler: 1: j 1b +DVP_IRQHandler: 1: j 1b +UART6_IRQHandler: 1: j 1b +UART7_IRQHandler: 1: j 1b +UART8_IRQHandler: 1: j 1b +TIM9_BRK_IRQHandler: 1: j 1b +TIM9_UP_IRQHandler: 1: j 1b +TIM9_TRG_COM_IRQHandler: 1: j 1b +TIM9_CC_IRQHandler: 1: j 1b +TIM10_BRK_IRQHandler: 1: j 1b +TIM10_UP_IRQHandler: 1: j 1b +TIM10_TRG_COM_IRQHandler: 1: j 1b +TIM10_CC_IRQHandler: 1: j 1b +DMA2_Channel6_IRQHandler: 1: j 1b +DMA2_Channel7_IRQHandler: 1: j 1b +DMA2_Channel8_IRQHandler: 1: j 1b +DMA2_Channel9_IRQHandler: 1: j 1b +DMA2_Channel10_IRQHandler: 1: j 1b +DMA2_Channel11_IRQHandler: 1: j 1b + + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack +2: + /* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + /* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + li t0, 0x1f + csrw 0xbc0, t0 + + /* Enable nested and hardware stack */ + li t0, 0x1f + csrw 0x804, t0 + /* Enable floating point and interrupt */ + li t0, 0x7800 + csrs mstatus, t0 + + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/TencentOS_Tiny/TOS_CONFIG/tos_config.h b/TencentOS_Tiny/TOS_CONFIG/tos_config.h new file mode 100644 index 0000000..6d77d51 --- /dev/null +++ b/TencentOS_Tiny/TOS_CONFIG/tos_config.h @@ -0,0 +1,64 @@ +#ifndef INC_TOS_CONFIG_H_ +#define INC_TOS_CONFIG_H_ + +#include "ch32v30x.h" +#include "stddef.h" + + +#define TOS_CFG_TASK_PRIO_MAX 10u + + +#define TOS_CFG_ROUND_ROBIN_EN 0u + + +#define TOS_CFG_OBJECT_VERIFY 0u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u + + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x3000 + +#define TOS_CFG_MAIL_QUEUE_EN 1u + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_TIMER_EN 0u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_CPU_SYSTICK_PRIO 0xF0 //V307ȼλЧ + +#if (TOS_CFG_QUEUE_EN > 0u) +#define TOS_CFG_MSG_EN 1u +#else +#define TOS_CFG_MSG_EN 0u +#endif + + +#define TOS_CFG_MSG_POOL_SIZE 10u + + +#define TOS_CFG_IDLE_TASK_STK_SIZE 512u + + +#define TOS_CFG_IRQ_STK_SIZE 512u + + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + + +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) + + +#define TOS_CFG_TIMER_AS_PROC 1u + + + +#endif /* INC_TOS_CONFIG_H_ */ diff --git a/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu.h b/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu.h new file mode 100644 index 0000000..bda4e08 --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu.h @@ -0,0 +1,173 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_H_ +#define _TOS_CPU_H_ +#include "port_config.h" + +typedef struct cpu_context_st { + cpu_data_t mepc; + cpu_data_t mstatus; + union { cpu_data_t x1, ra; }; + union { cpu_data_t x3, gp; }; + union { cpu_data_t x4, tp; }; + union { cpu_data_t x5, t0; }; + union { cpu_data_t x6, t1; }; + union { cpu_data_t x7, t2; }; + union { cpu_data_t x8, s0, fp; }; + union { cpu_data_t x9, s1; }; + union { cpu_data_t x10, a0; }; + union { cpu_data_t x11, a1; }; + union { cpu_data_t x12, a2; }; + union { cpu_data_t x13, a3; }; + union { cpu_data_t x14, a4; }; + union { cpu_data_t x15, a5; }; + union { cpu_data_t x16, a6; }; + union { cpu_data_t x17, a7; }; + union { cpu_data_t x18, s2; }; + union { cpu_data_t x19, s3; }; + union { cpu_data_t x20, s4; }; + union { cpu_data_t x21, s5; }; + union { cpu_data_t x22, s6; }; + union { cpu_data_t x23, s7; }; + union { cpu_data_t x24, s8; }; + union { cpu_data_t x25, s9; }; + union { cpu_data_t x26, s10; }; + union { cpu_data_t x27, s11; }; + union { cpu_data_t x28, t3; }; + union { cpu_data_t x29, t4; }; + union { cpu_data_t x30, t5; }; + union { cpu_data_t x31, t6; }; + +#if ARCH_RISCV_FPU + /* float reg table */ + union { cpu_data_t f0, ft0; }; + union { cpu_data_t f1, ft1; }; + union { cpu_data_t f2, ft2; }; + union { cpu_data_t f3, ft3; }; + union { cpu_data_t f4, ft4; }; + union { cpu_data_t f5, ft5; }; + union { cpu_data_t f6, ft6; }; + union { cpu_data_t f7, ft7; }; + union { cpu_data_t f8, fs0; }; + union { cpu_data_t f9, fs1; }; + union { cpu_data_t f10, fa0; }; + union { cpu_data_t f11, fa1; }; + union { cpu_data_t f12, fa2; }; + union { cpu_data_t f13, fa3; }; + union { cpu_data_t f14, fa4; }; + union { cpu_data_t f15, fa5; }; + union { cpu_data_t f16, fa6; }; + union { cpu_data_t f17, fa7; }; + union { cpu_data_t f18, fs2; }; + union { cpu_data_t f19, fs3; }; + union { cpu_data_t f20, fs4; }; + union { cpu_data_t f21, fs5; }; + union { cpu_data_t f22, fs6; }; + union { cpu_data_t f23, fs7; }; + union { cpu_data_t f24, fs8; }; + union { cpu_data_t f25, fs9; }; + union { cpu_data_t f26, fs10; }; + union { cpu_data_t f27, fs11; }; + union { cpu_data_t f28, ft8; }; + union { cpu_data_t f29, ft9; }; + union { cpu_data_t f30, ft10;}; + union { cpu_data_t f31, ft11;}; +#endif +} cpu_context_t; + + +__API__ uint32_t tos_cpu_clz(uint32_t val); + +__API__ void tos_cpu_int_disable(void); + +__API__ void tos_cpu_int_enable(void); + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void); + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr); + + +__KNL__ void cpu_init(void); + +__KNL__ void cpu_reset(void); + +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick); + +__KNL__ void cpu_sched_start(void); + +__KNL__ void cpu_context_switch(void); + +__KNL__ void cpu_irq_context_switch(void); + +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size); + +#if TOS_CFG_TICKLESS_EN > 0u + +__KNL__ void cpu_systick_resume(void); + +__KNL__ void cpu_systick_suspend(void); + +__KNL__ void cpu_systick_reload_reset(void); + +__KNL__ void cpu_systick_pending_reset(void); + +__KNL__ k_time_t cpu_systick_max_delay_millisecond(void); + +__KNL__ void cpu_systick_expires_set(k_time_t millisecond); + +__KNL__ void cpu_systick_reset(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__KNL__ void cpu_sleep_mode_enter(void); + +__KNL__ void cpu_stop_mode_enter(void); + +__KNL__ void cpu_standby_mode_enter(void); + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +#error "unsupport now" + +#endif + +/* Allocates CPU status register word. */ +#define TOS_CPU_CPSR_ALLOC() cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u + +/* Save CPU status word & disable interrupts.*/ +#define TOS_CPU_INT_DISABLE() \ + do { \ + cpu_cpsr = tos_cpu_cpsr_save(); \ + } while (0) + +/* Restore CPU status word. */ +#define TOS_CPU_INT_ENABLE() \ + do { \ + tos_cpu_cpsr_restore(cpu_cpsr); \ + } while (0) + + +#endif /* _TOS_CPU_H_ */ diff --git a/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu_def.h b/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu_def.h new file mode 100644 index 0000000..14f046d --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu_def.h @@ -0,0 +1,33 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_DEF_H_ +#define _TOS_CPU_DEF_H_ + +#define CPU_WORD_SIZE_08 1 +#define CPU_WORD_SIZE_16 2 +#define CPU_WORD_SIZE_32 3 +#define CPU_WORD_SIZE_64 4 + +#define CPU_STK_GROWTH_ASCENDING 1 +#define CPU_STK_GROWTH_DESCENDING 2 + +#define CPU_BYTE_ORDER_LITTLE_ENDIAN 1 +#define CPU_BYTE_ORDER_BIG_ENDIAN 2 + +#endif /* _TOS_CPU_DEF_H_ */ + diff --git a/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu_types.h b/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu_types.h new file mode 100644 index 0000000..5fc71a7 --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/common/include/tos_cpu_types.h @@ -0,0 +1,55 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_TYPES_H_ +#define _TOS_CPU_TYPES_H_ + +/* CPU address type based on address bus size. */ +#if (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_addr_t; +#elif (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_addr_t; +#else +typedef uint8_t cpu_addr_t; +#endif + +/* CPU data type based on data bus size. */ +#if (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_data_t; +#elif (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_data_t; +#else +typedef uint8_t cpu_data_t; +#endif + +#if (TOS_CFG_CPU_HRTIMER_EN > 0) +#if (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08) +typedef uint8_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64) +typedef uint64_t cpu_hrtimer_t; +#else +typedef uint32_t cpu_hrtimer_t; +#endif +#else +typedef uint32_t cpu_hrtimer_t; +#endif + +typedef cpu_addr_t cpu_cpsr_t; + +#endif diff --git a/TencentOS_Tiny/arch/risc-v/common/include/tos_fault.h b/TencentOS_Tiny/arch/risc-v/common/include/tos_fault.h new file mode 100644 index 0000000..3728ccb --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/common/include/tos_fault.h @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_FAULT_H_ +#define _TOS_FAULT_H_ + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +#error "unsupport now" + +#endif + +#endif /* _TOS_FAULT_H_ */ diff --git a/TencentOS_Tiny/arch/risc-v/common/tos_cpu.c b/TencentOS_Tiny/arch/risc-v/common/tos_cpu.c new file mode 100644 index 0000000..9496aca --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/common/tos_cpu.c @@ -0,0 +1,191 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include + +#ifndef TOS_CFG_IRQ_STK_SIZE +#warning "did not specify the irq stack size, use default value" +#define TOS_CFG_IRQ_STK_SIZE 128 +#endif + +__aligned(4) k_stack_t k_irq_stk[TOS_CFG_IRQ_STK_SIZE]; +k_stack_t *k_irq_stk_top = k_irq_stk + TOS_CFG_IRQ_STK_SIZE; + + +__API__ void tos_cpu_int_disable(void) +{ + port_int_disable(); +} + +__API__ void tos_cpu_int_enable(void) +{ + port_int_enable(); +} + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void) +{ + return port_cpsr_save(); +} + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) +{ + port_cpsr_restore(cpsr); +} + + +__KNL__ void cpu_context_switch(void) +{ + port_context_switch(); +} + +__KNL__ void cpu_irq_context_switch(void) +{ + + port_irq_context_switch(); +} + +__KNL__ void cpu_sched_start(void) +{ + port_sched_start(); +} + +__KNL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +{ + port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); + port_systick_config(cycle_per_tick); +} + +__KNL__ void cpu_init(void) { + + // reserve storage space for sp registers + k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) - sizeof(cpu_data_t)); + + k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) & 0xFFFFFFFC); + + k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; + + cpu_systick_init(k_cpu_cycle_per_tick); + port_cpu_init(); +} + + +/* + +Inx Offset Register +31 124 x31 t6 +32 120 x30 t5 +29 116 x29 t4 +28 112 x28 t3 +27 108 x27 s11 +26 104 x26 s10 +25 100 x25 s9 +24 096 x24 s8 +23 092 x23 s7 +22 088 x22 s6 +21 084 x21 s5 +20 080 x20 s4 +19 076 x19 s3 +18 072 x18 s2 +17 068 x17 a7 +16 064 x16 a6 +15 060 x15 a5 +14 056 x14 a4 +13 052 x13 a3 +12 048 x12 a2 +11 044 x11 a1 +10 040 x10 a0 +09 036 x9 s1 +08 032 x8 s0/fp +07 028 x7 t2 +06 024 x6 t1 +05 020 x5 t0 +04 016 x4 tp +03 012 x3 gp +02 008 x1 ra +01 004 mstatus +00 000 mepc + +*/ + +__KNL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size) +{ + cpu_data_t *sp = 0; + cpu_context_t *regs = 0; + + sp = (cpu_data_t *)&stk_base[stk_size]; + sp = (cpu_data_t *)((cpu_addr_t)(sp) & 0xFFFFFFFC); + + sp -= (sizeof(cpu_context_t)/sizeof(cpu_data_t)); + + regs = (cpu_context_t*) sp; + + for(int i=1; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i++) { + *(sp + i) = 0xACEADD00 | ((i / 10) << 4) | (i % 10); + } + + cpu_data_t gp = 0; + __ASM__ __VOLATILE__ ("mv %0, gp":"=r"(gp)); + + regs->gp = (cpu_data_t)gp; // global pointer + regs->a0 = (cpu_data_t)arg; // argument + regs->ra = (cpu_data_t)exit; // return address + regs->mstatus = (cpu_data_t)0x00007880; // return to machine mode and enable interrupt + regs->mepc = (cpu_data_t)entry; // task entry + + return (k_stack_t*)sp; +} + + +__API__ uint32_t tos_cpu_clz(uint32_t val) +{ + uint32_t nbr_lead_zeros = 0; + + if (!(val & 0xFFFF0000)) { + val <<= 16; + nbr_lead_zeros += 16; + } + + if (!(val & 0xFF000000)) { + val <<= 8; + nbr_lead_zeros += 8; + } + + if (!(val & 0xF0000000)) { + val <<= 4; + nbr_lead_zeros += 4; + } + + if (!(val & 0xC0000000)) { + val <<= 2; + nbr_lead_zeros += 2; + } + + if (!(val & 0x80000000)) { + nbr_lead_zeros += 1; + } + + if (!val) { + nbr_lead_zeros += 1; + } + + return (nbr_lead_zeros); +} + diff --git a/TencentOS_Tiny/arch/risc-v/rv32/gcc/port.h b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port.h new file mode 100644 index 0000000..dfa9c16 --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port.h @@ -0,0 +1,94 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_H_ +#define _PORT_H_ + +#ifndef __ASSEMBLER__ + + +/* defined by wch */ +#define GET_INT_SP() {asm("mv t0, sp");asm("lw sp, k_irq_stk_top");asm("sw t0,0(sp)");} +#define FREE_INT_SP() {asm("lw sp,0(sp)");} +__PORT__ void sw_clearpend(void); + + + +__PORT__ void port_int_disable(void); //at port.s + +__PORT__ void port_int_enable(void); //at port.s + +/* risc-v cpsr˺ڶȡmstatus,MIE */ +__PORT__ cpu_cpsr_t port_cpsr_save(void); //at port.s + +/* risc-v cpsr,˺mstatusֵ */ +__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); //at port.s + + +__PORT__ void port_cpu_reset(void); //at port.c + +__PORT__ void port_sched_start(void) __NO_RETURN__; //at port.s + +__PORT__ void port_context_switch(void); //at port.c + +__PORT__ void port_irq_context_switch(void); //at port.c + +__PORT__ void port_systick_config(uint32_t cycle_per_tick); //at port.c + +__PORT__ void port_systick_priority_set(uint32_t prio); //at port.c + +__PORT__ void port_cpu_init(); //at port.c + + + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ void port_systick_resume(void); + +__PORT__ void port_systick_suspend(void); + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick); + +__PORT__ void port_systick_pending_reset(void); + +__PORT__ k_time_t port_systick_max_delay_millisecond(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void); + +__PORT__ void port_stop_mode_enter(void); + +__PORT__ void port_standby_mode_enter(void); + +#endif + + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +__PORT__ void HardFault_Handler(void); + +__PORT__ void port_fault_diagnosis(void); +#endif + +#endif /* __ASSEMBLER__ */ + + +#define REGBYTES 4 + +#endif /* _PORT_H_ */ diff --git a/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.c b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.c new file mode 100644 index 0000000..1532db2 --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.c @@ -0,0 +1,170 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include +#include "ch32v30x.h" +#include "core_riscv.h" + + +__PORT__ void port_int_disable(void) +{ + asm("csrw mstatus, %0" : :"r"(0x7800)); +} + +__PORT__ void port_int_enable(void) +{ + asm("csrw mstatus, %0" : :"r"(0x7888)); +} + +__PORT__ cpu_cpsr_t port_cpsr_save(void) +{ + cpu_cpsr_t value=0; + asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800)); + return value; +} +__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr) +{ + asm("csrw mstatus, %0": :"r"(cpsr)); +} + + +__PORT__ void port_cpu_reset(void) +{ + NVIC_SystemReset(); +} + +/* clear soft interrupt */ +__PORT__ void sw_clearpend(void) +{ + SysTick->CTLR &= ~(1<<31); +} + +/* trigger software interrupt */ +__PORT__ void port_context_switch(void) +{ + SysTick->CTLR |= (1<<31); +} + +/* trigger software interrupt */ +__PORT__ void port_irq_context_switch(void) +{ + SysTick->CTLR |= (1<<31); +} + +__PORT__ void port_systick_config(uint32_t cycle_per_tick) +{ + SysTick->CTLR=0; + SysTick->SR=0; + SysTick->CNT=0; + SysTick->CMP=cycle_per_tick-1; + SysTick->CTLR=0xF; +} + +__PORT__ void port_systick_priority_set(uint32_t prio) +{ + NVIC_SetPriority(SysTicK_IRQn, prio); +} + +__PORT__ void port_cpu_init() +{ + NVIC_SetPriority(Software_IRQn,0xf0); + NVIC_EnableIRQ(SysTicK_IRQn); + NVIC_EnableIRQ(Software_IRQn); +} + + +void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void SysTick_Handler(void) +{ + GET_INT_SP(); /* лжջ */ + if (tos_knl_is_running()) + { + tos_knl_irq_enter(); + SysTick->SR=0; + tos_tick_handler(); + tos_knl_irq_leave(); + } + FREE_INT_SP(); /* ͷжջ */ +} + + +#if TOS_CFG_TICKLESS_EN > 0u +__PORT__ k_time_t port_systick_max_delay_millisecond(void) +{ + k_time_t max_millisecond; + uint32_t max_cycle; + + max_cycle = 0xffffffff; // systick 64λõ32λ + max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second + return max_millisecond; +} + +__PORT__ void port_systick_resume(void) +{ + SysTick->CTLR |= (3<<0); +} + +__PORT__ void port_systick_suspend(void) +{ + SysTick->CTLR &= ~(3<<0); +} + +__PORT__ k_cycle_t port_systick_max_reload_cycle(void) +{ + return 0xffffffff; +} + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick) +{ + port_systick_config(cycle_per_tick); +} + +__PORT__ void port_systick_pending_reset(void) +{ + PFIC->IPRR[0] |= (1<<12); //clear pend +} + +#endif + + +#if TOS_CFG_PWR_MGR_EN > 0u +__PORT__ void port_sleep_mode_enter(void) +{ + /* only CPU sleep */ + PFIC->SCTLR |= (1<<2); + __WFI(); + PFIC->SCTLR &= ~(1<<2); +} + +__PORT__ void port_stop_mode_enter(void) +{ + PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI); +} + +__PORT__ void port_standby_mode_enter(void) +{ + PWR_EnterSTANDBYMode(); +} + +#endif + + + + + + + diff --git a/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_config.h b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_config.h new file mode 100644 index 0000000..616fdf1 --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_config.h @@ -0,0 +1,142 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_CONFIG_H_ +#define _PORT_CONFIG_H_ + +/* FPU is used */ +#define ARCH_RISCV_FPU 0u + +#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING +#define TOS_CFG_CPU_HRTIMER_EN 0u +#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u +#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN + + + +/* int reg offset table */ +#define __reg_mepc_OFFSET 0x00 +#define __reg_mstatus_OFFSET 0x04 +#define __reg_x1_OFFSET 0x08 +#define __reg_x3_OFFSET 0x0C +#define __reg_x4_OFFSET 0x10 +#define __reg_x5_OFFSET 0x14 +#define __reg_x6_OFFSET 0x18 +#define __reg_x7_OFFSET 0x1C +#define __reg_x8_OFFSET 0x20 +#define __reg_x9_OFFSET 0x24 +#define __reg_x10_OFFSET 0x28 +#define __reg_x11_OFFSET 0x2C +#define __reg_x12_OFFSET 0x30 +#define __reg_x13_OFFSET 0x34 +#define __reg_x14_OFFSET 0x38 +#define __reg_x15_OFFSET 0x3C +#define __reg_x16_OFFSET 0x40 +#define __reg_x17_OFFSET 0x44 +#define __reg_x18_OFFSET 0x48 +#define __reg_x19_OFFSET 0x4C +#define __reg_x20_OFFSET 0x50 +#define __reg_x21_OFFSET 0x54 +#define __reg_x22_OFFSET 0x58 +#define __reg_x23_OFFSET 0x5C +#define __reg_x24_OFFSET 0x60 +#define __reg_x25_OFFSET 0x64 +#define __reg_x26_OFFSET 0x68 +#define __reg_x27_OFFSET 0x6C +#define __reg_x28_OFFSET 0x70 +#define __reg_x29_OFFSET 0x74 +#define __reg_x30_OFFSET 0x78 +#define __reg_x31_OFFSET 0x7C + +#define __reg_mepc__OFFSET __reg_mepc_OFFSET +#define __reg_mstatus__OFFSET __reg_mstatus_OFFSET +#define __reg_ra__OFFSET __reg_x1_OFFSET +#define __reg_gp__OFFSET __reg_x3_OFFSET +#define __reg_tp__OFFSET __reg_x4_OFFSET +#define __reg_t0__OFFSET __reg_x5_OFFSET +#define __reg_t1__OFFSET __reg_x6_OFFSET +#define __reg_t2__OFFSET __reg_x7_OFFSET +#define __reg_s0__OFFSET __reg_x8_OFFSET +#define __reg_fp__OFFSET __reg_x8_OFFSET +#define __reg_s1__OFFSET __reg_x9_OFFSET +#define __reg_a0__OFFSET __reg_x10_OFFSET +#define __reg_a1__OFFSET __reg_x11_OFFSET +#define __reg_a2__OFFSET __reg_x12_OFFSET +#define __reg_a3__OFFSET __reg_x13_OFFSET +#define __reg_a4__OFFSET __reg_x14_OFFSET +#define __reg_a5__OFFSET __reg_x15_OFFSET +#define __reg_a6__OFFSET __reg_x16_OFFSET +#define __reg_a7__OFFSET __reg_x17_OFFSET +#define __reg_s2__OFFSET __reg_x18_OFFSET +#define __reg_s3__OFFSET __reg_x19_OFFSET +#define __reg_s4__OFFSET __reg_x20_OFFSET +#define __reg_s5__OFFSET __reg_x21_OFFSET +#define __reg_s6__OFFSET __reg_x22_OFFSET +#define __reg_s7__OFFSET __reg_x23_OFFSET +#define __reg_s8__OFFSET __reg_x24_OFFSET +#define __reg_s9__OFFSET __reg_x25_OFFSET +#define __reg_s10__OFFSET __reg_x26_OFFSET +#define __reg_s11__OFFSET __reg_x27_OFFSET +#define __reg_t3__OFFSET __reg_x28_OFFSET +#define __reg_t4__OFFSET __reg_x29_OFFSET +#define __reg_t5__OFFSET __reg_x30_OFFSET +#define __reg_t6__OFFSET __reg_x31_OFFSET + + +#if ARCH_RISCV_FPU +/* float reg offset table */ +#define __reg_f0_OFFSET 0x00 +#define __reg_f1_OFFSET 0x04 +#define __reg_f2_OFFSET 0x08 +#define __reg_f3_OFFSET 0x0C +#define __reg_f4_OFFSET 0x10 +#define __reg_f5_OFFSET 0x14 +#define __reg_f6_OFFSET 0x18 +#define __reg_f7_OFFSET 0x1C +#define __reg_f8_OFFSET 0x20 +#define __reg_f9_OFFSET 0x24 +#define __reg_f10_OFFSET 0x28 +#define __reg_f11_OFFSET 0x2C +#define __reg_f12_OFFSET 0x30 +#define __reg_f13_OFFSET 0x34 +#define __reg_f14_OFFSET 0x38 +#define __reg_f15_OFFSET 0x3C +#define __reg_f16_OFFSET 0x40 +#define __reg_f17_OFFSET 0x44 +#define __reg_f18_OFFSET 0x48 +#define __reg_f19_OFFSET 0x4C +#define __reg_f20_OFFSET 0x50 +#define __reg_f21_OFFSET 0x54 +#define __reg_f22_OFFSET 0x58 +#define __reg_f23_OFFSET 0x5C +#define __reg_f24_OFFSET 0x60 +#define __reg_f25_OFFSET 0x64 +#define __reg_f26_OFFSET 0x68 +#define __reg_f27_OFFSET 0x6C +#define __reg_f28_OFFSET 0x70 +#define __reg_f29_OFFSET 0x74 +#define __reg_f30_OFFSET 0x78 +#define __reg_f31_OFFSET 0x7C + +#endif + + + +#endif /* _PORT_CONFIG_H_ */ + diff --git a/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.S b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.S new file mode 100644 index 0000000..a5967ad --- /dev/null +++ b/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.S @@ -0,0 +1,293 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + #include "port_config.h" + +.global port_sched_start +.extern k_curr_task +.extern k_next_task + +.text +.align 2 +.type port_sched_start, %function +port_sched_start: + + /* load sp from k_curr_task->sp */ + lw t0, k_curr_task + /* sp = k_curr_task->sp */ + lw sp, (t0) + j restore_context + + +.align 2 +.type restore_context, %function +restore_context: + // restore context + lw t0, __reg_mepc_OFFSET(sp) + csrw mepc, t0 + lw t0, __reg_mstatus_OFFSET(sp) + csrw mstatus, t0 + + lw x1, __reg_x1_OFFSET(sp) + lw x3, __reg_x3_OFFSET(sp) + lw x4, __reg_x4_OFFSET(sp) + lw x5, __reg_x5_OFFSET(sp) + lw x6, __reg_x6_OFFSET(sp) + lw x7, __reg_x7_OFFSET(sp) + lw x8, __reg_x8_OFFSET(sp) + lw x9, __reg_x9_OFFSET(sp) + lw x10, __reg_x10_OFFSET(sp) + lw x11, __reg_x11_OFFSET(sp) + lw x12, __reg_x12_OFFSET(sp) + lw x13, __reg_x13_OFFSET(sp) + lw x14, __reg_x14_OFFSET(sp) + lw x15, __reg_x15_OFFSET(sp) + lw x16, __reg_x16_OFFSET(sp) + lw x17, __reg_x17_OFFSET(sp) + lw x18, __reg_x18_OFFSET(sp) + lw x19, __reg_x19_OFFSET(sp) + lw x20, __reg_x20_OFFSET(sp) + lw x21, __reg_x21_OFFSET(sp) + lw x22, __reg_x22_OFFSET(sp) + lw x23, __reg_x23_OFFSET(sp) + lw x24, __reg_x24_OFFSET(sp) + lw x25, __reg_x25_OFFSET(sp) + lw x26, __reg_x26_OFFSET(sp) + lw x27, __reg_x27_OFFSET(sp) + lw x28, __reg_x28_OFFSET(sp) + lw x29, __reg_x29_OFFSET(sp) + lw x30, __reg_x30_OFFSET(sp) + lw x31, __reg_x31_OFFSET(sp) + addi sp, sp, 128 + +#if ARCH_RISCV_FPU + flw f0, __reg_f0_OFFSET(sp) + flw f1, __reg_f1_OFFSET(sp) + flw f2, __reg_f2_OFFSET(sp) + flw f3, __reg_f3_OFFSET(sp) + flw f4, __reg_f4_OFFSET(sp) + flw f5, __reg_f5_OFFSET(sp) + flw f6, __reg_f6_OFFSET(sp) + flw f7, __reg_f7_OFFSET(sp) + flw f8, __reg_f8_OFFSET(sp) + flw f9, __reg_f9_OFFSET(sp) + flw f10, __reg_f10_OFFSET(sp) + flw f11, __reg_f11_OFFSET(sp) + flw f12, __reg_f12_OFFSET(sp) + flw f13, __reg_f13_OFFSET(sp) + flw f14, __reg_f14_OFFSET(sp) + flw f15, __reg_f15_OFFSET(sp) + flw f16, __reg_f16_OFFSET(sp) + flw f17, __reg_f17_OFFSET(sp) + flw f18, __reg_f18_OFFSET(sp) + flw f19, __reg_f19_OFFSET(sp) + flw f20, __reg_f20_OFFSET(sp) + flw f21, __reg_f21_OFFSET(sp) + flw f22, __reg_f22_OFFSET(sp) + flw f23, __reg_f23_OFFSET(sp) + flw f24, __reg_f24_OFFSET(sp) + flw f25, __reg_f25_OFFSET(sp) + flw f26, __reg_f26_OFFSET(sp) + flw f27, __reg_f27_OFFSET(sp) + flw f28, __reg_f28_OFFSET(sp) + flw f29, __reg_f29_OFFSET(sp) + flw f30, __reg_f30_OFFSET(sp) + flw f31, __reg_f31_OFFSET(sp) + addi sp, sp, 128 +#endif + + mret + + +/* just switch at Software interrupt */ +.align 2 +.global SW_handler +SW_handler: +#if ARCH_RISCV_FPU + addi sp, sp, -128 + fsw f0, __reg_f0_OFFSET(sp) + fsw f1, __reg_f1_OFFSET(sp) + fsw f2, __reg_f2_OFFSET(sp) + fsw f3, __reg_f3_OFFSET(sp) + fsw f4, __reg_f4_OFFSET(sp) + fsw f5, __reg_f5_OFFSET(sp) + fsw f6, __reg_f6_OFFSET(sp) + fsw f7, __reg_f7_OFFSET(sp) + fsw f8, __reg_f8_OFFSET(sp) + fsw f9, __reg_f9_OFFSET(sp) + fsw f10, __reg_f10_OFFSET(sp) + fsw f11, __reg_f11_OFFSET(sp) + fsw f12, __reg_f12_OFFSET(sp) + fsw f13, __reg_f13_OFFSET(sp) + fsw f14, __reg_f14_OFFSET(sp) + fsw f15, __reg_f15_OFFSET(sp) + fsw f16, __reg_f16_OFFSET(sp) + fsw f17, __reg_f17_OFFSET(sp) + fsw f18, __reg_f18_OFFSET(sp) + fsw f19, __reg_f19_OFFSET(sp) + fsw f20, __reg_f20_OFFSET(sp) + fsw f21, __reg_f21_OFFSET(sp) + fsw f22, __reg_f22_OFFSET(sp) + fsw f23, __reg_f23_OFFSET(sp) + fsw f24, __reg_f24_OFFSET(sp) + fsw f25, __reg_f25_OFFSET(sp) + fsw f26, __reg_f26_OFFSET(sp) + fsw f27, __reg_f27_OFFSET(sp) + fsw f28, __reg_f28_OFFSET(sp) + fsw f29, __reg_f29_OFFSET(sp) + fsw f30, __reg_f30_OFFSET(sp) + fsw f31, __reg_f31_OFFSET(sp) +#endif + addi sp, sp, -128 + sw t0, __reg_x5_OFFSET(sp) + + /* disable HPE */ + li t0, 0x20 + csrs 0x804, t0 + + csrr t0, mstatus + sw t0, __reg_mstatus_OFFSET(sp) + csrr t0, mepc + sw t0, __reg_mepc_OFFSET(sp) + + sw x1, __reg_x1_OFFSET(sp) + sw x3, __reg_x3_OFFSET(sp) + sw x4, __reg_x4_OFFSET(sp) + + sw x6, __reg_x6_OFFSET(sp) + sw x7, __reg_x7_OFFSET(sp) + sw x8, __reg_x8_OFFSET(sp) + sw x9, __reg_x9_OFFSET(sp) + sw x10, __reg_x10_OFFSET(sp) + sw x11, __reg_x11_OFFSET(sp) + sw x12, __reg_x12_OFFSET(sp) + sw x13, __reg_x13_OFFSET(sp) + sw x14, __reg_x14_OFFSET(sp) + sw x15, __reg_x15_OFFSET(sp) + sw x16, __reg_x16_OFFSET(sp) + sw x17, __reg_x17_OFFSET(sp) + sw x18, __reg_x18_OFFSET(sp) + sw x19, __reg_x19_OFFSET(sp) + sw x20, __reg_x20_OFFSET(sp) + sw x21, __reg_x21_OFFSET(sp) + sw x22, __reg_x22_OFFSET(sp) + sw x23, __reg_x23_OFFSET(sp) + sw x24, __reg_x24_OFFSET(sp) + sw x25, __reg_x25_OFFSET(sp) + sw x26, __reg_x26_OFFSET(sp) + sw x27, __reg_x27_OFFSET(sp) + sw x28, __reg_x28_OFFSET(sp) + sw x29, __reg_x29_OFFSET(sp) + sw x30, __reg_x30_OFFSET(sp) + sw x31, __reg_x31_OFFSET(sp) + + /* switch to irq stk */ + mv t0, sp + lw sp, k_irq_stk_top /* cpu_initмȥһֿռ */ + sw t0, 0(sp) + /* clear software interrupt */ + call sw_clearpend + /* resume sp */ + lw sp, 0(sp) + + la t0, k_curr_task // t0 = &k_curr_task + la t1, k_next_task // t1 = &k_next_task + // save sp to k_curr_task.sp + lw t2, (t0) + sw sp, (t2) + + # switch task + # k_curr_task = k_next_task + lw t1, (t1) + sw t1, (t0) + # load new task sp + lw sp, (t1) + + /* new thread restore */ + lw t0, __reg_mstatus_OFFSET(sp) + csrw mstatus, t0 + lw t0, __reg_mepc_OFFSET(sp) + csrw mepc, t0 + + lw x1, __reg_x1_OFFSET(sp) + lw x3, __reg_x3_OFFSET(sp) + lw x4, __reg_x4_OFFSET(sp) + lw x5, __reg_x5_OFFSET(sp) + lw x6, __reg_x6_OFFSET(sp) + lw x7, __reg_x7_OFFSET(sp) + lw x8, __reg_x8_OFFSET(sp) + lw x9, __reg_x9_OFFSET(sp) + lw x10, __reg_x10_OFFSET(sp) + lw x11, __reg_x11_OFFSET(sp) + lw x12, __reg_x12_OFFSET(sp) + lw x13, __reg_x13_OFFSET(sp) + lw x14, __reg_x14_OFFSET(sp) + lw x15, __reg_x15_OFFSET(sp) + lw x16, __reg_x16_OFFSET(sp) + lw x17, __reg_x17_OFFSET(sp) + lw x18, __reg_x18_OFFSET(sp) + lw x19, __reg_x19_OFFSET(sp) + lw x20, __reg_x20_OFFSET(sp) + lw x21, __reg_x21_OFFSET(sp) + lw x22, __reg_x22_OFFSET(sp) + lw x23, __reg_x23_OFFSET(sp) + lw x24, __reg_x24_OFFSET(sp) + lw x25, __reg_x25_OFFSET(sp) + lw x26, __reg_x26_OFFSET(sp) + lw x27, __reg_x27_OFFSET(sp) + lw x28, __reg_x28_OFFSET(sp) + lw x29, __reg_x29_OFFSET(sp) + lw x30, __reg_x30_OFFSET(sp) + lw x31, __reg_x31_OFFSET(sp) + addi sp, sp, 128 + +#if ARCH_RISCV_FPU + flw f0, __reg_f0_OFFSET(sp) + flw f1, __reg_f1_OFFSET(sp) + flw f2, __reg_f2_OFFSET(sp) + flw f3, __reg_f3_OFFSET(sp) + flw f4, __reg_f4_OFFSET(sp) + flw f5, __reg_f5_OFFSET(sp) + flw f6, __reg_f6_OFFSET(sp) + flw f7, __reg_f7_OFFSET(sp) + flw f8, __reg_f8_OFFSET(sp) + flw f9, __reg_f9_OFFSET(sp) + flw f10, __reg_f10_OFFSET(sp) + flw f11, __reg_f11_OFFSET(sp) + flw f12, __reg_f12_OFFSET(sp) + flw f13, __reg_f13_OFFSET(sp) + flw f14, __reg_f14_OFFSET(sp) + flw f15, __reg_f15_OFFSET(sp) + flw f16, __reg_f16_OFFSET(sp) + flw f17, __reg_f17_OFFSET(sp) + flw f18, __reg_f18_OFFSET(sp) + flw f19, __reg_f19_OFFSET(sp) + flw f20, __reg_f20_OFFSET(sp) + flw f21, __reg_f21_OFFSET(sp) + flw f22, __reg_f22_OFFSET(sp) + flw f23, __reg_f23_OFFSET(sp) + flw f24, __reg_f24_OFFSET(sp) + flw f25, __reg_f25_OFFSET(sp) + flw f26, __reg_f26_OFFSET(sp) + flw f27, __reg_f27_OFFSET(sp) + flw f28, __reg_f28_OFFSET(sp) + flw f29, __reg_f29_OFFSET(sp) + flw f30, __reg_f30_OFFSET(sp) + flw f31, __reg_f31_OFFSET(sp) + addi sp, sp, 128 +#endif + + mret diff --git a/TencentOS_Tiny/kernel/core/include/tos_barrier.h b/TencentOS_Tiny/kernel/core/include/tos_barrier.h new file mode 100644 index 0000000..a8a0f9f --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_barrier.h @@ -0,0 +1,90 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_BARRIER_H_ +#define _TOS_BARRIER_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_BARRIER_EN > 0 + +typedef struct k_barrier_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_barrier_cnt_t count; +} k_barrier_t; + +/** + * @brief Create a thread barrier. + * + * @attention the count must be greater then zero. + * + * @param[in] barrier the barrier. + * @param[in] count the number of threads(task) must call tos_barrier_pend before any of them successfully return from the call. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BARRIER_COUNT_INVALID the count is equals to zero. + */ +__API__ k_err_t tos_barrier_create(k_barrier_t *barrier, k_barrier_cnt_t count); + +/** + * @brief Destroy a thread barrier. + * + * @attention + * + * @param[in] barrier the barrier. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BARRIER_COUNT_INVALID the count is equals to zero. + */ +__API__ k_err_t tos_barrier_destroy(k_barrier_t *barrier); + +/** + * @brief Pend on a barrier. + * + * @attention until (countdownlatch->count) of tasks have called the pend, the pender would wake up. + * + * @param[in] barrier the barrier. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BARRIER_OVERFLOW the barrier is pended too many times. + */ +__API__ k_err_t tos_barrier_pend(k_barrier_t *barrier); + +/** + * @brief Reset a barrier. + * + * @attention + * + * @param[in] barrier the barrier. + * @param[in] count the count of the barrier to be reset. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_barrier_reset(k_barrier_t *barrier, k_barrier_cnt_t count); + +#endif /* TOS_CFG_BARRIER_EN */ + +__CDECLS_END + +#endif /* _TOS_BARRIER_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_binary_heap.h b/TencentOS_Tiny/kernel/core/include/tos_binary_heap.h new file mode 100644 index 0000000..0a12136 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_binary_heap.h @@ -0,0 +1,180 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_BINARY_HEAP_H_ +#define _TOS_BINARY_HEAP_H_ + +__CDECLS_BEGIN + +typedef int (*k_bin_heap_cmp)(void *first, void *second); + +typedef struct k_binary_heap_st { + knl_obj_t knl_obj; + + size_t total; + + k_bin_heap_cmp cmp; + size_t item_size; + size_t item_cnt; + uint8_t *pool; +} k_bin_heap_t; + +#define BIN_HEAP_FIRST_ITEM(bin_heap) (void *)(&bin_heap->pool[0]) +#define BIN_HEAP_LAST_ITEM(bin_heap) (void *)(&bin_heap->pool[bin_heap->total * bin_heap->item_size]) +#define BIN_HEAP_THE_ITEM(bin_heap, index) (void *)(&bin_heap->pool[index * bin_heap->item_size]) + +#define BIN_HEAP_PARENT(index) ((index - 1) / 2) +#define BIN_HEAP_RCHILD(index) (2 * (index + 1)) +#define BIN_HEAP_LSIBLING(index) (index - 1) + +/** + * @brief Create a binary heap. + * create a binary heap. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * @param[in] pool pool buffer of the binary heap. + * @param[in] item_cnt item count of the binary heap. + * @param[in] item_size size of each item of the binary heap. + * @param[in] cmp compare function to determine two items which is bigger or smaller. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_bin_heap_create(k_bin_heap_t *bin_heap, void *pool, size_t item_cnt, size_t item_size, k_bin_heap_cmp cmp); + +/** + * @brief Destroy a binary heap. + * destroy a binary heap. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_bin_heap_destroy(k_bin_heap_t *bin_heap); + +/** + * @brief Create a binary heap with a dynamic allocated pool. + * create a binary heap with a dynamic allocated pool. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * @param[in] item_cnt item count of the binary heap. + * @param[in] item_size size of each item of the binary heap. + * @param[in] cmp compare function to determine two items which is bigger or smaller. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_bin_heap_create_dyn(k_bin_heap_t *bin_heap, size_t item_cnt, size_t item_size, k_bin_heap_cmp cmp); + +/** + * @brief Destroy a binary heap with a dynamic allocated pool. + * destroy a binary heap with a dynamic allocated pool. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_bin_heap_destroy_dyn(k_bin_heap_t *bin_heap); + +/** + * @brief Push an item. + * push an item into the binary heap. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * @param[in] item the item to be pushed. + * @param[in] item_size size of the item(should be consistent with the item_size passed to tos_bin_heap_create). + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BIN_HEAP_ITEM_SIZE_NOT_MATCH the item_size is not consistent with the item_size passed to tos_bin_heap_create. + * @retval #K_ERR_BIN_HEAP_FULL the binary heap is full. + */ +__API__ k_err_t tos_bin_heap_push(k_bin_heap_t *bin_heap, void *item, size_t item_size); + +/** + * @brief Pop an item. + * pop an item from the binary heap. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * @param[out] item buffer to hold the item poped. + * @param[out] item_size size of the item poped(should be consistent with the item_size passed to tos_bin_heap_create). + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BIN_HEAP_EMPTY the ring queue is empty. + */ +__API__ k_err_t tos_bin_heap_pop(k_bin_heap_t *bin_heap, void *item, size_t *item_size); + +/** + * @brief Flush the binary heap. + * flush the binary heap. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_bin_heap_flush(k_bin_heap_t *bin_heap); + +/** + * @brief Whether the binary heap is empty. + * Whether the binary heap is empty. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * + * @return whether the binary heap is emtpy. + * @retval #0 the binary heap is not empty. + * @retval #Not 0 the binary heap is empty. + */ +__API__ int tos_bin_heap_is_empty(k_bin_heap_t *bin_heap); + +/** + * @brief Whether the binary heap is full. + * Whether the binary heap is full. + * + * @attention None + * + * @param[in] bin_heap pointer to the handler of the binary heap. + * + * @return whether the binary hea is full. + * @retval #0 the binary hea is not full. + * @retval #Not 0 the binary hea is full. + */ +__API__ int tos_bin_heap_is_full(k_bin_heap_t *bin_heap); + +__CDECLS_END + +#endif /* _TOS_BINARY_HEAP_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_bitmap.h b/TencentOS_Tiny/kernel/core/include/tos_bitmap.h new file mode 100644 index 0000000..975fd59 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_bitmap.h @@ -0,0 +1,152 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_BITMAP_H_ +#define _TOS_BITMAP_H_ + +typedef uint32_t k_bmtbl_t; + +typedef struct k_bitmap_st { + knl_obj_t knl_obj; + + uint32_t bit_ndx_max; + uint32_t bit_max; + k_bmtbl_t *bitmap_tbl; +} k_bitmap_t; + +#define K_BITMAP_SLOT_SIZE (sizeof(k_bmtbl_t) * 8) /* in bits */ + +#define K_BITMAP_TBL_SIZE(bit_max) ((bit_max + K_BITMAP_SLOT_SIZE - 1) / K_BITMAP_SLOT_SIZE) + +#define K_BITMAP_NDX(bit) ((bit) >> 5u) /* bit / K_BITMAP_SLOT_SIZE */ + +#define K_BITMAP_BIT(bit) ((uint32_t)1u << (K_BITMAP_SLOT_SIZE - 1u - ((bit) & (K_BITMAP_SLOT_SIZE - 1u)))) + +#define TOS_BITMAP_SIZE(bit_max) (K_BITMAP_TBL_SIZE(bit_max)) + +/** + * @brief Create a bitmap with all bit are set to 0. + * + * @attention the size of bitmap_tabl can be caculated by the macro TOS_BITMAP_SIZE + * + * @param[in] bitmap pointer to the handler of the bitmap. + * @param[in] bitmap_tbl bitmap table buffer. + * @param[in] bit_max maximal bit. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_OBJ_PTR_NULL bitmap is NULL. + */ +__API__ k_err_t tos_bitmap_create_empty(k_bitmap_t *bitmap, k_bmtbl_t *bitmap_tbl, uint32_t bit_max); + +/** + * @brief Create a bitmap with all bit are set to 1. + * + * @attention the size of bitmap_tabl can be caculated by the macro TOS_BITMAP_SIZE + * + * @param[in] bitmap pointer to the handler of the bitmap. + * @param[in] bitmap_tbl bitmap table buffer. + * @param[in] bit_max maximal bit. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_OBJ_PTR_NULL bitmap is NULL. + */ +__API__ k_err_t tos_bitmap_create_full(k_bitmap_t *bitmap, k_bmtbl_t *bitmap_tbl, uint32_t bit_max); + +/** + * @brief Destroy the bitmap. + * + * @attention + * + * @param[in] bitmap pointer to the handler of the bitmap. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_OBJ_PTR_NULL bitmap is NULL. + */ +__API__ k_err_t tos_bitmap_destroy(k_bitmap_t *bitmap); + +/** + * @brief Set a certain bit of the bitmap to 1. + * + * @attention + * + * @param[in] bitmap pointer to the handler of the bitmap. + * @param[in] bit the bit to set. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BITMAP_EXCEED bit is larger than the bit_max passed to tos_bitmap_create_*. + */ +__API__ k_err_t tos_bitmap_set(k_bitmap_t *bitmap, uint32_t bit); + +/** + * @brief Set a certain bit of the bitmap to 0. + * + * @attention + * + * @param[in] bitmap pointer to the handler of the bitmap. + * @param[in] bit the bit to set. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_BITMAP_EXCEED bit is larger than the bit_max passed to tos_bitmap_create_*. + */ +__API__ k_err_t tos_bitmap_reset(k_bitmap_t *bitmap, uint32_t bit); + +/** + * @brief Test whether a certain bit of the bitmap is 1. + * + * @attention + * + * @param[in] bitmap pointer to the handler of the bitmap. + * @param[in] bit the bit to set. + * + * @return whether the bit is 1 + * @retval #K_TRUE the certain bit is 1. + * @retval #K_FALSE the certain bit is not 1(that means is 0). + */ +__API__ int tos_bitmap_is_set(k_bitmap_t *bitmap, uint32_t bit); + +/** + * @brief Test whether a certain bit of the bitmap is 0. + * + * @attention + * + * @param[in] bitmap pointer to the handler of the bitmap. + * @param[in] bit the bit to set. + * + * @return whether the bit is 0 + * @retval #K_TRUE the certain bit is 0. + * @retval #K_FALSE the certain bit is not 0(that means is 1). + */ +__API__ int tos_bitmap_is_reset(k_bitmap_t *bitmap, uint32_t bit); + +/** + * @brief Get the lowest significant bit of the bitmap. + * + * @attention The very first bit which is set to 1. + * + * @param[in] bitmap pointer to the handler of the bitmap. + * + * @return the lowest significant bit of the bitmap. + */ +__API__ int tos_bitmap_lsb(k_bitmap_t *bitmap); + +#endif /* _TOS_BITMAP_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_char_fifo.h b/TencentOS_Tiny/kernel/core/include/tos_char_fifo.h new file mode 100644 index 0000000..c863521 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_char_fifo.h @@ -0,0 +1,191 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CHAR_FIFO_H_ +#define _TOS_CHAR_FIFO_H_ + +__CDECLS_BEGIN + +typedef struct k_char_fifo_st { + knl_obj_t knl_obj; + + k_ring_q_t ring_q; +} k_chr_fifo_t; + +/** + * @brief Create a character fifo. + * Create a character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the fifo. + * @param[in] buffer memory buffer provided to be as the inner buffer. + * @param[in] size size of the memory buffer. + * + * @return errno + * @retval #K_ERR_OBJ_PTR_NULL fifo is a NULL pointer. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_chr_fifo_create(k_chr_fifo_t *chr_fifo, void *buffer, size_t size); + +/** + * @brief Destroy a character fifo. + * Destroy a character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the fifo. + * + * @return errno + * @retval #K_ERR_OBJ_PTR_NULL fifo is a NULL pointer. + * @retval #K_ERR_OBJ_INVALID not a valid pointer to a fifo. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_chr_fifo_destroy(k_chr_fifo_t *chr_fifo); + +/** + * @brief Create a character fifo with a dynamic allocated buffer. + * Create a character fifo with a dynamic allocated buffer. + * + * @attention the buffer is dynamic allocated(tos_mmheap_alloc) + * + * @param[in] fifo pointer to the handler of the fifo. + * @param[in] fifo_size size of the fifo. + * + * @return errno + * @retval #K_ERR_OBJ_PTR_NULL fifo is a NULL pointer. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_chr_fifo_create_dyn(k_chr_fifo_t *chr_fifo, size_t fifo_size); + +/** + * @brief Destroy a character fifo with a dynamic allocated buffer. + * Destroy a character fifo with a dynamic allocated buffer. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the fifo. + * + * @return errno + * @retval #K_ERR_OBJ_PTR_NULL fifo is a NULL pointer. + * @retval #K_ERR_OBJ_INVALID not a valid pointer to a fifo. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_chr_fifo_destroy_dyn(k_chr_fifo_t *chr_fifo); + +/** + * @brief Push data into character fifo. + * Push one single data into the character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * @param[in] data data to push into the fifo. + * + * @return errno + * @retval #K_ERR_RING_Q_FULL the character fifo is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_chr_fifo_push(k_chr_fifo_t *chr_fifo, uint8_t data); + +/** + * @brief Push stream into character fifo. + * Push a stream data into the character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * @param[IN] stream stream to be pushed into the character fifo. + * @param[OUT] size size of the stream. + * + * @return the actual number of the data pushed into the character fifo. + */ +__API__ int tos_chr_fifo_push_stream(k_chr_fifo_t *chr_fifo, uint8_t *stream, size_t size); + +/** + * @brief Pop data from character fifo. + * Pop one single data from the character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * @param[OUT] out one signle buffer to hold the data poped from the character fifo. + * + * @return errno + * @retval #K_ERR_FIFO_EMPTY the character fifo is empty. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_chr_fifo_pop(k_chr_fifo_t *chr_fifo, uint8_t *out); + +/** + * @brief Pop stream from character fifo. + * Pop a stream data from the character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * @param[OUT] buffer pointer to the buffer to receive the stream poped. + * @param[OUT] size size of the buffer. + * + * @return the actual number of the data poped from the character fifo. + */ +__API__ int tos_chr_fifo_pop_stream(k_chr_fifo_t *chr_fifo, uint8_t *buffer, size_t size); + +/** + * @brief Flush character fifo. + * Flush/reset the character fifo. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * + * @return None. + */ +__API__ k_err_t tos_chr_fifo_flush(k_chr_fifo_t *chr_fifo); + +/** + * @brief Whether the character fifo is empty. + * Whether the character fifo is empty. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * + * @return whether the character fifo is emtpy. + * @retval #0 the character fifo is not empty. + * @retval #Not 0 the character fifo is empty. + */ +__API__ int tos_chr_fifo_is_empty(k_chr_fifo_t *chr_fifo); + +/** + * @brief Whether the character fifo is full. + * Whether the character fifo is full. + * + * @attention None + * + * @param[in] fifo pointer to the handler of the character fifo. + * + * @return whether the character fifo is full. + * @retval #0 the character fifo is not full. + * @retval #Not 0 the character fifo is full. + */ +__API__ int tos_chr_fifo_is_full(k_chr_fifo_t *chr_fifo); + +__CDECLS_END + +#endif /* _TOS_CHAR_FIFO_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_compiler.h b/TencentOS_Tiny/kernel/core/include/tos_compiler.h new file mode 100644 index 0000000..6723855 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_compiler.h @@ -0,0 +1,166 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_COMPILER_H_ +#define _TOS_COMPILER_H_ + +/* function with __API__ prefix, api for user */ +#define __API__ + +/* function with __KNL__ prefix, only for kernel */ +#define __KNL__ + +/* function with __HOOK__ prefix, should be implemented by user */ +#define __HOOK__ + +/* function with __DEBUG__ prefix, only for debug */ +#define __DEBUG__ + +/* function with __PORT__ is architecture depended */ +#define __PORT__ + +/* CPP header guards */ +#ifdef __cplusplus +#define __CDECLS_BEGIN extern "C" { +#define __CDECLS_END } +#else +#define __CDECLS_BEGIN +#define __CDECLS_END +#endif + +/*------------------ RealView Compiler -----------------*/ +#if defined(__CC_ARM) + +#define ARMCC_V5 + +#define __ASM__ __asm +#define __VOLATILE__ volatile + +#define __INLINE__ inline +#define __STATIC__ static + +#if (__ARMCC_VERSION < 5060750) // how to know the exact number? +#define __STATIC_INLINE__ static +#else +#define __STATIC_INLINE__ static inline +#endif + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +#define __UNUSED__ __attribute__((__unused__)) +#define __USED__ __attribute__((__used__)) +#define __PACKED__ __attribute__((packed)) +#define __ALIGNED__(x) __attribute__((aligned(x))) +#define __PURE__ __attribute__((__pure__)) +#define __CONST__ __attribute__((__const__)) +#define __NO_RETURN__ __attribute__((__noreturn__)) +#define __WEAK__ __attribute__((weak)) + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#define ARMCC_V6 + +#define __ASM__ __asm +#define __VOLATILE__ volatile + +#define __INLINE__ inline +#define __STATIC__ static +#define __STATIC_INLINE__ static inline + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +#define __UNUSED__ __attribute__((__unused__)) +#define __USED__ __attribute__((__used__)) +#define __PACKED__ __attribute__((packed)) +#define __ALIGNED__(x) __attribute__((aligned(x))) +#define __PURE__ __attribute__((__pure__)) +#define __CONST__ __attribute__((__const__)) +#define __NO_RETURN__ __attribute__((__noreturn__)) +#define __NAKED__ __attribute__((naked)) +#define __WEAK__ __attribute__((weak)) + +/*------------------ ICC Compiler ----------------------*/ +#elif defined(__ICCARM__) || defined(__ICC430__) // __IAR_SYSTEMS_ICC__ + +#define __ASM__ __asm +#define __VOLATILE__ volatile + +#define __INLINE__ inline +#define __STATIC__ static +#define __STATIC_INLINE__ static inline + +#define likely(x) (x) +#define unlikely(x) (x) +#define __UNUSED__ +#define __USED__ +#define __PACKED__ +#define __ALIGNED__(x) +#define __PURE__ +#define __CONST__ +#define __NO_RETURN__ +#define __NAKED__ +#define __WEAK__ __weak + +/*------------------ ICC Compiler for STM8/AVR ----------------------*/ +#elif defined(__IAR_SYSTEMS_ICC__) + +#define __ASM__ __asm +#define __VOLATILE__ volatile + +#define __INLINE__ inline +#define __STATIC__ static +#define __STATIC_INLINE__ static inline + +#define likely(x) (x) +#define unlikely(x) (x) +#define __UNUSED__ +#define __USED__ +#define __PACKED__ +#define __ALIGNED__(x) +#define __PURE__ +#define __CONST__ +#define __NO_RETURN__ +#define __NAKED__ +#define __WEAK__ __weak + +/*------------------ GNU Compiler ----------------------*/ +#elif defined(__GNUC__) + +#define __ASM__ __asm +#define __VOLATILE__ volatile + +#define __INLINE__ inline +#define __STATIC__ static +#define __STATIC_INLINE__ static inline + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +#define __UNUSED__ __attribute__((__unused__)) +#define __USED__ __attribute__((__used__)) +#define __PACKED__ __attribute__((packed)) +#define __ALIGNED__(x) __attribute__((aligned(x))) +#define __PURE__ __attribute__((__pure__)) +#define __CONST__ __attribute__((__const__)) +#define __NO_RETURN__ __attribute__((__noreturn__)) +#define __NAKED__ __attribute__((naked)) +#define __WEAK__ __attribute__((weak)) + +#endif + +#endif /* _TOS_COMPILER_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_completion.h b/TencentOS_Tiny/kernel/core/include/tos_completion.h new file mode 100644 index 0000000..45cba41 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_completion.h @@ -0,0 +1,154 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_COMPLETION_H_ +#define _TOS_COMPLETION_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_COMPLETION_EN > 0 + +typedef uint16_t completion_done_t; + +typedef struct k_completion_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + completion_done_t done; +} k_completion_t; + +/** + * @brief Create a completion. + * create a completion. + * + * @attention None + * + * @param[in] completion pointer to the handler of the completion. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_create(k_completion_t *completion); + +/** + * @brief Destroy a completion. + * destroy a completion. + * + * @attention None + * + * @param[in] completion pointer to the handler of the completion. + * + * @return errcode + * @retval #K_ERR_OBJ_INVALID completion is not a valid pointer to completion + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_destroy(k_completion_t *completion); + +/** + * @brief Pend a completion. + * pend a completion. + * + * @attention None + * + * @param[in] completion pointer to the handler of the completion. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the completion we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_pend_timed(k_completion_t *completion, k_tick_t timeout); + +/** + * @brief Pend a completion. + * pend a completion. + * + * @attention None + * + * @param[in] completion pointer to the handler of the completion. + * + * @return errcode + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_DESTROY the completion we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_pend(k_completion_t *completion); + +/** + * @brief Post a completion. + * post a completion and wakeup one pending task. + * + * @attention when tos_completion_post return successfully, only one task who are waitting for the completion will be woken up. + * + * @param[in] completion pointer to the handler of the completion. + * + * @return errcode + * @retval #K_ERR_COMPLETION_OVERFLOW we are nesting post a completion too much. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_post(k_completion_t *completion); + +/** + * @brief Post a completion. + * post a completion and wakeup all the pending task. + * + * @attention when tos_completion_post_all return successfully, all of the tasks who are waitting for the completion will be woken up. + * + * @param[in] completion pointer to the handler of the completion. + * + * @return errcode + * @retval #K_ERR_COMPLETION_OVERFLOW we are nesting post a completion too much. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_post_all(k_completion_t *completion); + +/** + * @brief Reset a completion. + * reset a completion to un-done. + * + * @attention None. + * + * @param[in] completion pointer to the handler of the completion. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_completion_reset(k_completion_t *completion); + +/** + * @brief Test whether a completion is done. + * test whether a completion is done. + * + * @attention None + * + * @param[in] completion pointer to the handler of the completion. + * + * @return whether a completion is done + * @retval K_TRUE the completion is done. + * @retval K_FALSE the completion is not done. + */ +__API__ int tos_completion_is_done(k_completion_t *completion); + +#endif /* TOS_CFG_COMPLETION_EN */ + +__CDECLS_END + +#endif /* _TOS_COMPLETION_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_config_check.h b/TencentOS_Tiny/kernel/core/include/tos_config_check.h new file mode 100644 index 0000000..3e4b1e2 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_config_check.h @@ -0,0 +1,96 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CONFIG_CHECK_H_ +#define _TOS_CONFIG_CHECK_H_ + +#if TOS_CFG_EVENT_DRIVEN_EN > 0u + +#if TOS_CFG_TICKLESS_EN == 1u +#error "INVALID config, tickless not supported in event-driven yet" +#endif + +#if (TOS_CFG_MMHEAP_EN > 0u) && (TOS_CFG_MMHEAP_DEFAULT_POOL_EN > 0u) +#if !defined(TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE) || (TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE == 0u) +#error "INVALID config, must define a valid TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE" +#endif +#endif + +#else /* TOS_CFG_EVENT_DRIVEN_EN */ + +#if TOS_CFG_TASK_PRIO_MAX < 8u +#error "INVALID config, TOS_CFG_TASK_PRIO_MAX must be >= 8" +#endif + +#if ((TOS_CFG_TIMER_EN > 0u) && !defined(TOS_CFG_TIMER_AS_PROC)) +#error "UNDECLARED config, TOS_CFG_TIMER_AS_PROC" +#endif + +#if (TOS_CFG_MMHEAP_EN > 0u) && (TOS_CFG_MMHEAP_DEFAULT_POOL_EN > 0u) +#if !defined(TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE) || (TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE == 0u) +#error "INVALID config, must define a valid TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE" +#endif +#endif + +#ifndef TOS_CFG_CPU_HRTIMER_EN +#error "UNDECLARED config, TOS_CFG_CPU_HRTIMER_EN should be declared in 'port_config.h'" +#elif (TOS_CFG_CPU_HRTIMER_EN > 0u) && !defined(TOS_CFG_CPU_HRTIMER_SIZE) +#error "UNDECLARED config, TOS_CFG_CPU_HRTIMER_SIZE should be declared in 'port_config.h'" +#elif (TOS_CFG_CPU_HRTIMER_EN > 0u) && ((TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_08) && \ + (TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_16) && \ + (TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_32) && \ + (TOS_CFG_CPU_HRTIMER_SIZE != CPU_WORD_SIZE_64)) +#error "INVALID config, TOS_CFG_CPU_HRTIMER_SIZE" +#endif + +#ifndef TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT +#error "UNDECLARED config, TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT, should be declared in 'port_config.h'" +#endif + +#ifndef TOS_CFG_CPU_BYTE_ORDER +#error "UNDECLARED config, TOS_CFG_CPU_BYTE_ORDER, should be declared in 'port_config.h'" +#endif + +#ifndef TOS_CFG_CPU_STK_GROWTH +#error "UNDECLARED config, TOS_CFG_CPU_STK_GROWTH, should be declared in 'port_config.h'" +#elif ((TOS_CFG_CPU_STK_GROWTH != CPU_STK_GROWTH_ASCENDING) && \ + (TOS_CFG_CPU_STK_GROWTH != CPU_STK_GROWTH_DESCENDING)) +#error "INVALID config, TOS_CFG_CPU_STK_GROWTH" +#endif + +#ifndef TOS_CFG_CPU_ADDR_SIZE +#error "UNDECLARED config, TOS_CFG_CPU_ADDR_SIZE, should be declared in 'port_config.h'" +#elif ((TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_08) && \ + (TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_16) && \ + (TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_32) && \ + (TOS_CFG_CPU_ADDR_SIZE != CPU_WORD_SIZE_64)) +#error "INVALID config, TOS_CFG_CPU_ADDR_SIZE" +#endif + +#ifndef TOS_CFG_CPU_DATA_SIZE +#error "UNDECLARED config, TOS_CFG_CPU_DATA_SIZE, should be declared in 'port_config.h'" +#elif ((TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_08) && \ + (TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_16) && \ + (TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_32) && \ + (TOS_CFG_CPU_DATA_SIZE != CPU_WORD_SIZE_64)) +#error "INVALID config, TOS_CFG_CPU_DATA_SIZE" +#endif + +#endif /* TOS_CFG_EVENT_DRIVEN_EN */ + +#endif /* _TOS_CONFIG_CHECK_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_config_default.h b/TencentOS_Tiny/kernel/core/include/tos_config_default.h new file mode 100644 index 0000000..e76c3fc --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_config_default.h @@ -0,0 +1,264 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CONFIG_DEFAULT_H_ +#define _TOS_CONFIG_DEFAULT_H_ + +#ifndef TOS_CFG_EVENT_DRIVEN_EN +#define TOS_CFG_EVENT_DRIVEN_EN 0u +#endif + +#if TOS_CFG_EVENT_DRIVEN_EN > 0u + +///////////////////////////////////////// +// disable round robin +#ifdef TOS_CFG_ROUND_ROBIN_EN +#undef TOS_CFG_ROUND_ROBIN_EN +#endif +#define TOS_CFG_ROUND_ROBIN_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable dynamic task create +#ifdef TOS_CFG_TASK_DYNAMIC_CREATE_EN +#undef TOS_CFG_TASK_DYNAMIC_CREATE_EN +#endif +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable event +#ifdef TOS_CFG_EVENT_EN +#undef TOS_CFG_EVENT_EN +#endif +#define TOS_CFG_EVENT_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable mutex +#ifdef TOS_CFG_MUTEX_EN +#undef TOS_CFG_MUTEX_EN +#endif +#define TOS_CFG_MUTEX_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable semaphore +#ifdef TOS_CFG_SEM_EN +#undef TOS_CFG_SEM_EN +#endif +#define TOS_CFG_SEM_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable the "traditional" timer +#ifdef TOS_CFG_TIMER_EN +#undef TOS_CFG_TIMER_EN +#endif +#define TOS_CFG_TIMER_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable stack draught depth detact +#ifdef TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN +#undef TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN +#endif +#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 0u +///////////////////////////////////////// + + +///////////////////////////////////////// +// enable mmheap +#ifndef TOS_CFG_MMHEAP_EN +#define TOS_CFG_MMHEAP_EN 0u +#endif + +#ifndef TOS_CFG_MMHEAP_DEFAULT_POOL_EN +#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u +#endif +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable default +#ifndef TOS_CFG_FAULT_BACKTRACE_EN +#define TOS_CFG_FAULT_BACKTRACE_EN 0u +#endif +///////////////////////////////////////// + +///////////////////////////////////////// +#ifndef TOS_CFG_CPU_SYSTICK_PRIO +#define TOS_CFG_CPU_SYSTICK_PRIO 0u +#endif +///////////////////////////////////////// + + +///////////////////////////////////////// +// disable default +#ifndef TOS_CFG_PWR_MGR_EN +#define TOS_CFG_PWR_MGR_EN 0u +#endif + +#ifndef TOS_CFG_TICKLESS_EN +#define TOS_CFG_TICKLESS_EN 0u +#endif + + +///////////////////////////////////////// +// we donot really need these, it's a compromise to the compiler. +#ifndef TOS_CFG_TASK_PRIO_MAX +#define TOS_CFG_TASK_PRIO_MAX 8u +#endif + +#ifndef TOS_CFG_IDLE_TASK_STK_SIZE +#define TOS_CFG_IDLE_TASK_STK_SIZE 128u +#endif +///////////////////////////////////////// + + +///////////////////////////////////////// + +#else /* TOS_CFG_EVENT_DRIVEN_EN */ + +#ifndef TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN +#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 0u +#endif + +#ifndef TOS_CFG_TASK_DYNAMIC_CREATE_EN +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u +#endif + +#ifndef TOS_CFG_ROUND_ROBIN_EN +#define TOS_CFG_ROUND_ROBIN_EN 0u +#endif + +#ifndef TOS_CFG_EVENT_EN +#define TOS_CFG_EVENT_EN 0u +#endif + +#ifndef TOS_CFG_MUTEX_EN +#define TOS_CFG_MUTEX_EN 0u +#endif + +#ifndef TOS_CFG_MESSAGE_QUEUE_EN +#define TOS_CFG_MESSAGE_QUEUE_EN 0u +#endif + +#ifndef TOS_CFG_MAIL_QUEUE_EN +#define TOS_CFG_MAIL_QUEUE_EN 0u +#endif + +#ifndef TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN +#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 0u +#endif + +#ifndef TOS_CFG_PRIORITY_MAIL_QUEUE_EN +#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 0u +#endif + +#ifndef TOS_CFG_SEM_EN +#define TOS_CFG_SEM_EN 0u +#endif + +#ifndef TOS_CFG_TIMER_EN +#define TOS_CFG_TIMER_EN 0u +#endif + +#if (TOS_CFG_TIMER_EN > 0u) && !defined(TOS_CFG_TIMER_AS_PROC) +#define TOS_CFG_TIMER_AS_PROC 0u +#endif + +#ifndef TOS_CFG_IDLE_TASK_STK_SIZE +#define TOS_CFG_IDLE_TASK_STK_SIZE 128u +#endif + +#ifndef TOS_CFG_OBJECT_VERIFY_EN +#define TOS_CFG_OBJECT_VERIFY_EN 0u +#endif + +#ifndef TOS_CFG_LIBC_PRINTF_EN +#define TOS_CFG_LIBC_PRINTF_EN 1u // we enable this by default +#endif + +#if (TOS_CFG_TIMER_AS_PROC == 0u) && !defined(TOS_CFG_TIMER_TASK_PRIO) +#define TOS_CFG_TIMER_TASK_PRIO (k_prio_t)(K_TASK_PRIO_IDLE - (k_prio_t)1u) +#endif + +#if (TOS_CFG_TIMER_AS_PROC == 0u) && !defined(TOS_CFG_TIMER_TASK_STK_SIZE) +#define TOS_CFG_TIMER_TASK_STK_SIZE 128u +#endif + +#ifndef TOS_CFG_CPU_SYSTICK_PRIO +#define TOS_CFG_CPU_SYSTICK_PRIO 0u +#endif + +#ifndef TOS_CFG_CPU_TICK_PER_SECOND +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u +#endif + +#ifndef TOS_CFG_CPU_CLOCK +#define TOS_CFG_CPU_CLOCK 16000000u +#endif + +#ifndef TOS_CFG_TASK_PRIO_MAX +#define TOS_CFG_TASK_PRIO_MAX 8u +#endif + +#ifndef TOS_CFG_MMHEAP_EN +#define TOS_CFG_MMHEAP_EN 0u +#endif + +#ifndef TOS_CFG_MMHEAP_DEFAULT_POOL_EN +#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u +#endif + +#ifndef TOS_CFG_PWR_MGR_EN +#define TOS_CFG_PWR_MGR_EN 0u +#endif + +#ifndef TOS_CFG_TICKLESS_EN +#define TOS_CFG_TICKLESS_EN 0u +#endif + +#if (TOS_CFG_PWR_MGR_EN > 0u) || (TOS_CFG_TICKLESS_EN > 0u) +#if TOS_CFG_IDLE_TASK_STK_SIZE < 256 +#undef TOS_CFG_IDLE_TASK_STK_SIZE +#define TOS_CFG_IDLE_TASK_STK_SIZE 256u +#endif +#endif + +#if (TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u) +#if TOS_CFG_IDLE_TASK_STK_SIZE < 512 +#undef TOS_CFG_IDLE_TASK_STK_SIZE +#define TOS_CFG_IDLE_TASK_STK_SIZE 512u +#endif +#endif + +#ifndef TOS_CFG_FAULT_BACKTRACE_EN +#define TOS_CFG_FAULT_BACKTRACE_EN 0u +#endif + +#endif /* TOS_CFG_EVENT_DRIVEN_EN */ + +#endif /* _TOS_CONFIG_DEFAULT_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_countdownlatch.h b/TencentOS_Tiny/kernel/core/include/tos_countdownlatch.h new file mode 100644 index 0000000..8a4645c --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_countdownlatch.h @@ -0,0 +1,122 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_COUNTDOWNLATCH_H_ +#define _TOS_COUNTDOWNLATCH_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_COUNTDOWNLATCH_EN > 0 +typedef struct k_countdownlatch_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_countdownlatch_cnt_t count; +} k_countdownlatch_t; + +/** + * @brief Create a countdown-latch. + * create a countdown latch. + * + * @attention the count is how many posts have been done the pender would wakeup. + * + * @param[in] countdownlatch pointer to the handler of the countdown-latch. + * @param[in] count the count to wait of the countdown-latch. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_countdownlatch_create(k_countdownlatch_t *countdownlatch, k_countdownlatch_cnt_t count); + +/** + * @brief Destroy a countdown-latch. + * destroy a countdown-latch. + * + * @attention None + * + * @param[in] countdownlatch pointer to the handler of the countdown-latch. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_countdownlatch_destroy(k_countdownlatch_t *countdownlatch); + +/** + * @brief Pend a countdown-latch. + * pend a countdown-latch. + * + * @attention The task will keep blocked until the countdown-latch is obtained or a timeout comes. + * + * @param[in] countdownlatch pointer to the handler of the countdown-latch. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_countdownlatch_pend_timed(k_countdownlatch_t *countdownlatch, k_tick_t timeout); + +/** + * @brief Pend a countdown-latch. + * pend a countdown latch. + * + * @attention until (countdownlatch->count) of tasks have done the post, the pender would wake up. + * + * @param[in] countdownlatch pointer to the handler of the countdown-latch. + * + * @return errcode + * @retval #K_ERR_PEND_SCHED_LOCKED the schedule is locked. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_countdownlatch_pend(k_countdownlatch_t *countdownlatch); + +/** + * @brief Post a countdown-latch. + * post a countdown-latch. + * + * @attention until (countdownlatch->count) of tasks have done the post, the pender would wake up. + * + * @param[in] countdownlatch pointer to the handler of the countdown-latch. + * + * @return errcode + * @retval #K_ERR_COUNTDOWNLATCH_OVERFLOW we are posting the countdown-latch too much. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_countdownlatch_post(k_countdownlatch_t *countdownlatch); + +/** + * @brief Reset a countdown-latch. + * reset a countdown-latch's count. + * + * @attention None. + * + * @param[in] countdownlatch pointer to the handler of the countdown-latch. + * @param[in] count the count to wait of the countdown-latch. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_countdownlatch_reset(k_countdownlatch_t *countdownlatch, k_countdownlatch_cnt_t count); + +#endif /* TOS_CFG_COUNTDOWNLATCH_EN */ + +__CDECLS_END + +#endif /* _TOS_COUNTDOWNLATCH_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_event.h b/TencentOS_Tiny/kernel/core/include/tos_event.h new file mode 100644 index 0000000..6357bf1 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_event.h @@ -0,0 +1,139 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_EVENT_H_ +#define _TOS_EVENT_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_EVENT_EN > 0 + +// if we are pending an event, for any flag we expect is set is ok, this flag should be passed to tos_event_pend +#define TOS_OPT_EVENT_PEND_ANY (k_opt_t)0x0001 + +// if we are pending an event, must all the flag we expect is set is ok, this flag should be passed to tos_event_pend +#define TOS_OPT_EVENT_PEND_ALL (k_opt_t)0x0002 + +// if we are pending an event, and we wanna clear the event's flag after we read, this flag should be passed to tos_event_pend +/* ATTENTION: + we can pass both TOS_OPT_EVENT_PEND_CLR and TOS_OPT_EVENT_PEND_ANY, or TOS_OPT_EVENT_PEND_CLR and TOS_OPT_EVENT_PEND_ALL + to tos_event_pend, if we wanna do this, a (TOS_OPT_EVENT_PEND_CLR | TOS_OPT_EVENT_PEND_ANY) or + (TOS_OPT_EVENT_PEND_CLR | TOS_OPT_EVENT_PEND_ALL) should be passed. + but, (TOS_OPT_EVENT_PEND_ANY | TOS_OPT_EVENT_PEND_ALL) is invalid, we cannot both wanna any and all flag is set. + */ +#define TOS_OPT_EVENT_PEND_CLR (k_opt_t)0x0004 + +typedef enum opt_event_post_en { + OPT_EVENT_POST_KEP, + OPT_EVENT_POST_CLR, +} opt_event_post_t; + +typedef struct k_event_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_event_flag_t flag; +} k_event_t; + +/** + * @brief Create an event. + * create an event. + * + * @attention None + * + * @param[in] event pointer to the handler of the event. + * @param[in] init_flag initial flag of the event. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_event_create(k_event_t *event, k_event_flag_t init_flag); + +/** + * @brief Destroy an event. + * destroy an event. + * + * @attention None + * + * @param[in] event pointer to the handler of the event. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_event_destroy(k_event_t *event); + +/** + * @brief Pend an event. + * pend an event. + * + * @attention if opt is TOS_OPT_EVENT_PEND_ANY, any of the flag_expect is set is ok; + * if opt is TOS_OPT_EVENT_PEND_ALL�� must all the flag_expect is set is ok. + * + * @param[in] event pointer to the handler of the event. + * @param[in] flag_expect the flag we expect from the event. + * @param[OUT] flag_match if we get the flag we expect, what exactly they are? + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * @param[in] opt option for pend. + * + * @return errcode + * @retval #K_ERR_EVENT_PEND_OPT_INVALID opt is invalid + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the event we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_event_pend(k_event_t *event, k_event_flag_t flag_expect, k_event_flag_t *flag_match, k_tick_t timeout, k_opt_t opt); + +/** + * @brief Post an event. + * post an event. + * + * @attention if you are posting an event in tos_event_post, event's own flag will be overwrited by the flag we post. + * eg. if an event's own flag is 0x0001, and we are posting a flag 0x0030, after the post, the event's flag + * will be overwrited to 0x0030. + * + * @param[in] event pointer to the handler of the event. + * @param[in] flag the flag we post. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_event_post(k_event_t *event, k_event_flag_t flag); + +/** + * @brief Post an event. + * post an event, and keep the original own flag of the event. + * + * @attention the original own flag of the event will be keeped. + * eg.if an event's own flag is 0x0001, and we are posting a flag 0x0030, after the post, the event's flag + * will be changed to 0x0031(0x0030 | 0x0001), which means the event's original flag is keeped. + * + * @param[in] event pointer to the handler of the event. + * @param[in] flag the flag we post. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_event_post_keep(k_event_t *event, k_event_flag_t flag); + +#endif + +__CDECLS_END + +#endif /* _TOS_EVENT_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_global.h b/TencentOS_Tiny/kernel/core/include/tos_global.h new file mode 100644 index 0000000..16d14ab --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_global.h @@ -0,0 +1,106 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_GLOBAL_H_ +#define _TOS_GLOBAL_H_ + +/* interrupt nesting count */ +extern k_nesting_t k_irq_nest_cnt; + +/* schedule lock nesting count */ +extern k_nesting_t k_sched_lock_nest_cnt; + +/* kernel running state */ +extern knl_state_t k_knl_state; + +/* ready queue of tasks */ +extern readyqueue_t k_rdyq; + +/* ticks since boot up */ +extern k_tick_t k_tick_count; + +/* current task */ +extern k_task_t *k_curr_task; +/* next task to run */ +extern k_task_t *k_next_task; + +/* idle task related stuff */ +extern k_task_t k_idle_task; +extern k_stack_t k_idle_task_stk[]; +extern k_stack_t *const k_idle_task_stk_addr; +extern size_t const k_idle_task_stk_size; + +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u +/* list to hold all the destroyed dynamic created tasks */ +extern k_list_t k_dead_task_list; +#endif + +/* list to hold all the tasks for statistics */ +extern k_list_t k_stat_list; + +/* list to hold all the tasks delayed or pend for timeout */ +extern k_list_t k_tick_list; + +/* how many ticks will be triggered in a second */ +extern k_tick_t k_cpu_tick_per_second; + +/* how many cycle per tick */ +extern k_cycle_t k_cpu_cycle_per_tick; + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +extern k_fault_log_writer_t k_fault_log_writer; + +#endif + +#if TOS_CFG_MMHEAP_EN > 0u +#if TOS_CFG_MMHEAP_DEFAULT_POOL_EN > 0u +extern uint8_t k_mmheap_default_pool[] __ALIGNED__(4); +#endif +extern k_mmheap_ctl_t k_mmheap_ctl; +#endif + +#if TOS_CFG_ROUND_ROBIN_EN > 0u +extern k_timeslice_t k_robin_default_timeslice; +#endif + +#if TOS_CFG_TIMER_EN > 0u +/* list holding all the timer */ +extern timer_ctl_t k_timer_ctl; +#if TOS_CFG_TIMER_AS_PROC == 0u +extern k_task_t k_timer_task; +extern k_stack_t k_timer_task_stk[]; +extern k_prio_t const k_timer_task_prio; +extern k_stack_t *const k_timer_task_stk_addr; +extern size_t const k_timer_task_stk_size; +#endif +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u +extern pm_device_ctl_t k_pm_device_ctl; + +extern idle_pwrmgr_mode_t k_idle_pwr_mgr_mode; + +extern k_cpu_lpwr_mode_t k_cpu_lpwr_mode; +#endif + +#if TOS_CFG_TICKLESS_EN > 0u +extern k_tickless_wkup_alarm_t *k_tickless_wkup_alarm[__LOW_POWER_MODE_DUMMY]; +#endif + +#endif /* _TOS_GLOBAL_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_k.h b/TencentOS_Tiny/kernel/core/include/tos_k.h new file mode 100644 index 0000000..a9584ee --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_k.h @@ -0,0 +1,73 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_K_H_ +#define _TOS_K_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if TOS_CFG_PWR_MGR_EN > 0u +#include +#if TOS_CFG_TICKLESS_EN > 0u +#include +#endif +#endif +#include +#include + +#endif /* _TOS_K_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_kerr.h b/TencentOS_Tiny/kernel/core/include/tos_kerr.h new file mode 100644 index 0000000..91cf8be --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_kerr.h @@ -0,0 +1,136 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_ERR_H_ +#define _TOS_ERR_H_ + +typedef enum k_err_en { + K_ERR_NONE = 0u, + + K_ERR_BARRIER_COUNT_INVALID = 5u, + K_ERR_BARRIER_OVERFLOW, + + K_ERR_BITMAP_EXCEED = 10u, + + K_ERR_BIN_HEAP_FULL = 15u, + K_ERR_BIN_HEAP_EMPTY, + K_ERR_BIN_HEAP_ITEM_SIZE_NOT_MATCH, + + K_ERR_COMPLETION_OVERFLOW = 25u, + + K_ERR_COUNTDOWNLATCH_OVERFLOW = 50u, + + K_ERR_DELAY_ZERO = 100u, + K_ERR_DELAY_FOREVER, + + K_ERR_EVENT_PEND_OPT_INVALID = 200u, + + K_ERR_IN_IRQ = 400u, + + K_ERR_KNL_NOT_RUNNING = 500u, + K_ERR_KNL_RUNNING, + + K_ERR_LOCK_NESTING_OVERFLOW = 600u, + + K_ERR_MMBLK_POOL_FULL = 700u, + K_ERR_MMBLK_POOL_EMPTY, + K_ERR_MMBLK_INVALID_BLK_SIZE, + K_ERR_MMBLK_INVALID_POOL_ADDR, + K_ERR_MMBLK_POOL_OUT_OF_MEMORY, + K_ERR_MMBLK_OUT_OF_MEMORY, + + K_ERR_MMHEAP_INVALID_POOL_ADDR = 800u, + K_ERR_MMHEAP_INVALID_POOL_SIZE, + K_ERR_MMHEAP_POOL_OVERFLOW, + K_ERR_MMHEAP_POOL_ALREADY_EXIST, + K_ERR_MMHEAP_POOL_NOT_EXIST, + + K_ERR_MUTEX_NOT_OWNER = 1000u, + K_ERR_MUTEX_NESTING, + K_ERR_MUTEX_NESTING_OVERFLOW, + + K_ERR_OBJ_PTR_NULL = 1100u, + K_ERR_OBJ_INVALID, + K_ERR_OBJ_INVALID_ALLOC_TYPE, + + K_ERR_OUT_OF_MEMORY = 1150u, + + K_ERR_PEND_NOWAIT = 1200u, + K_ERR_PEND_SCHED_LOCKED, + K_ERR_PEND_ABNORMAL, + K_ERR_PEND_TIMEOUT, + K_ERR_PEND_DESTROY, + K_ERR_PEND_OWNER_DIE, + + K_ERR_PM_DEVICE_ALREADY_REG = 1300u, + K_ERR_PM_DEVICE_OVERFLOW, + K_ERR_PM_WKUP_SOURCE_NOT_INSTALL, + + K_ERR_PRIO_Q_EMPTY = 1400u, + K_ERR_PRIO_Q_FULL, + K_ERR_PRIO_Q_SLOT_NOT_TAKEN, + K_ERR_PRIO_Q_ITEM_SIZE_NOT_MATCH, + + K_ERR_RING_Q_FULL = 1500u, + K_ERR_RING_Q_EMPTY, + K_ERR_RING_Q_ITEM_SIZE_NOT_MATCH, + + K_ERR_RWLOCK_READERS_TO_MANY = 1600u, + K_ERR_RWLOCK_IS_READING, + K_ERR_RWLOCK_IS_WRITTING, + K_ERR_RWLOCK_NOT_READING, + K_ERR_RWLOCK_NOT_WRITTING, + K_ERR_RWLOCK_NOT_TAKEN, + K_ERR_RWLOCK_WAITING_WRITERS_TO_MANY, + + K_ERR_SCHED_LOCKED = 1700u, + K_ERR_SCHED_NOT_LOCKED, + + K_ERR_SEM_OVERFLOW = 1800u, + + K_ERR_TASK_ALREADY_CREATED = 1900u, + K_ERR_TASK_DESTROY_IDLE, + K_ERR_TASK_NOT_DELAY, + K_ERR_TASK_PRIO_INVALID, + K_ERR_TASK_RESUME_SELF, + K_ERR_TASK_SUSPENDED, + K_ERR_TASK_SUSPEND_IDLE, + K_ERR_TASK_STK_OVERFLOW, + K_ERR_TASK_STK_SIZE_INVALID, + K_ERR_TASK_OUT_OF_MEMORY, + + K_ERR_TICKLESS_WKUP_ALARM_NOT_INSTALLED = 2000u, + K_ERR_TICKLESS_WKUP_ALARM_NO_INIT, + K_ERR_TICKLESS_WKUP_ALARM_INIT_FAILED, + + K_ERR_TIMER_INACTIVE = 2100u, + K_ERR_TIMER_DELAY_FOREVER, + K_ERR_TIMER_PERIOD_FOREVER, + K_ERR_TIMER_INVALID_DELAY, + K_ERR_TIMER_INVALID_PERIOD, + K_ERR_TIMER_INVALID_STATE, + K_ERR_TIMER_INVALID_OPT, + K_ERR_TIMER_STOPPED, + K_ERR_TIMER_RUNNING, + + K_ERR_SEM_OUT_OF_MEMORY = 2200u, + + K_ERR_MUTEX_OUT_OF_MEMORY = 2300u, +} k_err_t; + +#endif /* _TOS_ERR_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_klib.h b/TencentOS_Tiny/kernel/core/include/tos_klib.h new file mode 100644 index 0000000..f40277e --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_klib.h @@ -0,0 +1,128 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_KLIB_H_ +#define _TOS_KLIB_H_ + +#include +#include +#include +#include + +#define __MACRO_BEGIN do { +#define __MACRO_END } while (0) + +#define TOS_OFFSET_OF_FIELD(type, field) \ + ((uint32_t)&(((type *)0)->field)) + +#define TOS_CONTAINER_OF_FIELD(ptr, type, field) \ + ((type *)((uint8_t *)(ptr) - TOS_OFFSET_OF_FIELD(type, field))) + +#define TOS_COUNT_OF(array) (sizeof(array) / sizeof(array[0])) + +#define TOS_PTR_SANITY_CHECK(ptr) \ + __MACRO_BEGIN \ + if (unlikely(!(ptr))) { \ + return K_ERR_OBJ_PTR_NULL; \ + } \ + __MACRO_END + +#define TOS_PTR_SANITY_CHECK_RC(ptr, return_code) \ + __MACRO_BEGIN \ + if (unlikely(!(ptr))) { \ + return return_code; \ + } \ + __MACRO_END + +#define TOS_IN_IRQ_CHECK() \ + __MACRO_BEGIN \ + if (unlikely(knl_is_inirq())) { \ + return K_ERR_IN_IRQ; \ + } \ + __MACRO_END + +#if TOS_CFG_OBJECT_VERIFY_EN > 0u + +#define TOS_OBJ_INIT(obj, obj_type) knl_object_init(&obj->knl_obj, obj_type) +#define TOS_OBJ_DEINIT(obj) knl_object_deinit(&obj->knl_obj) + +#define TOS_OBJ_VERIFY(obj, obj_type) \ + __MACRO_BEGIN \ + if (!knl_object_verify(&obj->knl_obj, obj_type)) { \ + return K_ERR_OBJ_INVALID; \ + } \ + __MACRO_END + +#define TOS_OBJ_VERIFY_RC(obj, obj_type, return_code) \ + __MACRO_BEGIN \ + if (!knl_object_verify(&obj->knl_obj, obj_type)) { \ + return return_code; \ + } \ + __MACRO_END + +#define TOS_OBJ_TEST(obj, obj_type) \ + __MACRO_BEGIN \ + if (knl_object_verify(&obj->knl_obj, obj_type)) { \ + return K_ERR_OBJ_INVALID; \ + } \ + __MACRO_END + +#define TOS_OBJ_TEST_RC(obj, obj_type, return_code) \ + __MACRO_BEGIN \ + if (knl_object_verify(&obj->knl_obj, obj_type)) { \ + return return_code; \ + } \ + __MACRO_END + +#else + +#define TOS_OBJ_INIT(obj, obj_type) +#define TOS_OBJ_DEINIT(obj) +#define TOS_OBJ_VERIFY(obj, obj_type) +#define TOS_OBJ_VERIFY_RC(obj, obj_type, return_code) +#define TOS_OBJ_TEST(obj, obj_type) +#define TOS_OBJ_TEST_RC(obj, obj_type, return_code) + +#endif + +#if TOS_CFG_LIBC_PRINTF_EN > 0u +#define LIBC_PRINTF printf +#else +#define LIBC_PRINTF(...) +#endif + +// currently we use default microlib supplied by mdk +#define tos_kprintf(...) LIBC_PRINTF(__VA_ARGS__); + +#define tos_kprintln(...) \ + LIBC_PRINTF(__VA_ARGS__); \ + LIBC_PRINTF("\n"); + +#define TOS_ASSERT_AUX(exp, function, line) \ + if (!(exp)) { \ + tos_kprintln("assert failed: %s %d\n", function, line); \ + tos_knl_sched_lock(); \ + tos_cpu_int_disable(); \ + while (K_TRUE) { \ + ; \ + } \ + } + +#define TOS_ASSERT(exp) TOS_ASSERT_AUX(exp, __FUNCTION__, __LINE__) + +#endif /* _TOS_KLIB_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_ktypes.h b/TencentOS_Tiny/kernel/core/include/tos_ktypes.h new file mode 100644 index 0000000..774d936 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_ktypes.h @@ -0,0 +1,57 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_KTYPES_H_ +#define _TOS_KTYPES_H_ + +#include +#include + +typedef uint8_t k_prio_t; +typedef uint8_t k_stack_t; +typedef uint8_t k_task_state_t; +typedef struct k_task_st k_task_t; + +typedef uint8_t k_nesting_t; + +typedef uint16_t k_opt_t; + +typedef uint16_t k_sem_cnt_t; +typedef uint32_t k_event_flag_t; +typedef uint16_t k_barrier_cnt_t; +typedef uint16_t k_countdownlatch_cnt_t; + +typedef uint32_t k_time_t; +typedef uint32_t k_timeslice_t; + +typedef uint32_t k_cycle_t; + +#if TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_08 +typedef uint32_t k_tick_t; +#else +typedef uint64_t k_tick_t; +#endif + +#define K_TRUE (1u) +#define K_FALSE (0u) + +#ifndef K_NULL +#define K_NULL 0 +#endif + +#endif /* _TOS_KTYPES_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_list.h b/TencentOS_Tiny/kernel/core/include/tos_list.h new file mode 100644 index 0000000..7a135fa --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_list.h @@ -0,0 +1,146 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_LIST_H_ +#define _TOS_LIST_H_ + +__CDECLS_BEGIN + +typedef struct k_list_node_st { + struct k_list_node_st *next; + struct k_list_node_st *prev; +} k_list_t; + +#define TOS_LIST_NODE(node) \ + { &(node), &(node) } + +#define TOS_LIST_DEFINE(list) \ + k_list_t list = { &(list), &(list) } + +#define TOS_LIST_ENTRY(node, type, field) \ + TOS_CONTAINER_OF_FIELD(node, type, field) + +#define TOS_LIST_FIRST_ENTRY(list, type, field) \ + TOS_LIST_ENTRY((list)->next, type, field) + +#define TOS_LIST_FIRST_ENTRY_OR_NULL(list, type, field) \ + (tos_list_empty(list) ? K_NULL : TOS_LIST_FIRST_ENTRY(list, type, field)) + +#define TOS_LIST_FOR_EACH(curr, list) \ + for (curr = (list)->next; curr != (list); curr = curr->next) + +#define TOS_LIST_FOR_EACH_PREV(curr, list) \ + for (curr = (list)->prev; curr != (list); curr = curr->prev) + +#define TOS_LIST_FOR_EACH_SAFE(curr, next, list) \ + for (curr = (list)->next, next = curr->next; curr != (list); \ + curr = next, next = curr->next) + +#define TOS_LIST_FOR_EACH_PREV_SAFE(curr, next, list) \ + for (curr = (list)->prev, next = curr->prev; \ + curr != (list); \ + curr = next, next = curr->prev) + +#define TOS_LIST_FOR_EACH_ENTRY(entry, type, field, list) \ + for (entry = TOS_LIST_ENTRY((list)->next, type, field); \ + &entry->field != (list); \ + entry = TOS_LIST_ENTRY(entry->field.next, type, field)) + +#define TOS_LIST_FOR_EACH_ENTRY_REVERSE(entry, type, field, list) \ + for (entry = TOS_LIST_ENTRY((list)->prev, type, field); \ + &entry->field != (list); \ + entry = TOS_LIST_ENTRY(entry->field.prev, type, field)) + +#define TOS_LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, type, field, list) \ + for (entry = TOS_LIST_ENTRY((list)->next, type, field), \ + tmp = TOS_LIST_ENTRY(entry->field.next, type, field); \ + &entry->field != (list); \ + entry = tmp, tmp = TOS_LIST_ENTRY(entry->field.next, type, field)) + +#define TOS_LIST_FOR_EACH_ENTRY_SAFE_REVERSE(entry, tmp, type, field, list) \ + for (entry = TOS_LIST_ENTRY((list)->prev, type, field), \ + tmp = TOS_LIST_ENTRY(entry->field.prev, type, field); \ + &entry->field != (list); \ + entry = tmp, tmp = TOS_LIST_ENTRY(entry->field.prev, type, field)) + +__STATIC_INLINE__ void _list_add(k_list_t *node, k_list_t *prev, k_list_t *next) +{ + next->prev = node; + node->next = next; + node->prev = prev; + prev->next = node; +} + +__STATIC_INLINE__ void _list_del(k_list_t *prev, k_list_t *next) +{ + next->prev = prev; + prev->next = next; +} + +__STATIC_INLINE__ void _list_del_node(k_list_t *node) +{ + _list_del(node->prev, node->next); +} + +__API__ __STATIC_INLINE__ void tos_list_init(k_list_t *list) +{ + list->next = list; + list->prev = list; +} + +__API__ __STATIC_INLINE__ void tos_list_add(k_list_t *node, k_list_t *list) +{ + _list_add(node, list, list->next); +} + +__API__ __STATIC_INLINE__ void tos_list_add_tail(k_list_t *node, k_list_t *list) +{ + _list_add(node, list->prev, list); +} + +__API__ __STATIC_INLINE__ void tos_list_del(k_list_t *node) +{ + _list_del(node->prev, node->next); +} + +__API__ __STATIC_INLINE__ void tos_list_del_init(k_list_t *node) +{ + _list_del_node(node); + tos_list_init(node); +} + +__API__ __STATIC_INLINE__ void tos_list_move(k_list_t *node, k_list_t *list) +{ + _list_del_node(node); + tos_list_add(node, list); +} + +__API__ __STATIC_INLINE__ void tos_list_move_tail(k_list_t *node, k_list_t *list) +{ + _list_del_node(node); + tos_list_add_tail(node, list); +} + +__API__ __STATIC_INLINE__ int tos_list_empty(const k_list_t *list) +{ + return list->next == list; +} + +__CDECLS_END + +#endif /* _TOS_LIST_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_mail_queue.h b/TencentOS_Tiny/kernel/core/include/tos_mail_queue.h new file mode 100644 index 0000000..1371166 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_mail_queue.h @@ -0,0 +1,159 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_MAIL_QUEUE_H_ +#define _TOS_MAIL_QUEUE_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_MAIL_QUEUE_EN > 0u + +typedef struct k_mail_queue_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_ring_q_t ring_q; +} k_mail_q_t; + +/** + * @brief Create a mail queue. + * create a mail queue. + * + * @attention a MAIL is a buffer with a certain size. + * + * @param[in] mail_q pointer to the handler of the mail queue. + * @param[in] pool pool buffer of the mail queue. + * @param[in] mail_cnt mail count of the mail queue. + * @param[in] mail_size size of each mail in the mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_create(k_mail_q_t *mail_q, void *pool, size_t mail_cnt, size_t mail_size); + +/** + * @brief Destroy a mail queue. + * destroy a mail queue. + * + * @attention None + * + * @param[in] mail_q pointer to the handler of the mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_destroy(k_mail_q_t *mail_q); + +/** + * @brief Create a mail queue with dynamic allocated pool. + * create a mail queue with dynamic allocated pool. + * + * @attention a MAIL is a buffer with a certain size. + * + * @param[in] mail_q pointer to the handler of the mail queue. + * @param[in] mail_cnt mail count of the mail queue. + * @param[in] mail_size size of each mail in the mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_create_dyn(k_mail_q_t *mail_q, size_t mail_cnt, size_t mail_size); + +/** + * @brief Destroy a mail queue with dynamic allocated pool. + * destroy a mail queue with dynamic allocated pool. + * + * @attention None + * + * @param[in] mail_q pointer to the handler of the mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_destroy_dyn(k_mail_q_t *mail_q); + +/** + * @brief Flush the mail queue. + * flush the mail queue. + * + * @attention None + * + * @param[in] mail_q pointer to the handler of the mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_flush(k_mail_q_t *mail_q); + +/** + * @brief Pend a mail queue. + * pend a mail queue. + * + * @attention we WILL perform a memcpy when mail_buf is received(a MAIL is a buffer with a certain size). + * + * @param[in] mail_q pointer to the handler of the mail queue. + * @param[OUT] mail_buf a pointer to the mail buffer we wanna receive. + * @param[OUT] mail_size size of the mail buffer received(should be consistent with the mail_size passed to tos_mail_q_create). + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the queue we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_pend(k_mail_q_t *mail_q, void *mail_buf, size_t *mail_size, k_tick_t timeout); + +/** + * @brief Post a mail queue. + * post a mail queue and wakeup one pending task. + * + * @attention when tos_mail_q_post return successfully, only one task who are waitting for the mail queue will be woken up. + * + * @param[in] mail_q pointer to the handler of the mail queue. + * @param[in] mail_buf the mail to post(a MAIL is a buffer). + * @param[in] mail_size the size of the mail to post(a MAIL is just a buffer). + * + * @return errcode + * @retval #K_ERR_RING_Q_FULL the mail queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_post(k_mail_q_t *mail_q, void *mail_buf, size_t mail_size); + +/** + * @brief Post a mail queue. + * post a mail queue and wakeup all the pending task. + * + * @attention when tos_mail_q_post_all return successfully, all of the tasks who are waitting for the message queue will be woken up. + * + * @param[in] mail_q pointer to the handler of the mail queue. + * @param[in] mail_buf the mail to post(a MAIL is a buffer). + * @param[in] mail_size the size of the mail to post(a MAIL is just a buffer). + * + * @return errcode + * @retval #K_ERR_RING_Q_FULL the mail queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mail_q_post_all(k_mail_q_t *mail_q, void *mail_buf, size_t mail_size); + +#endif + +__CDECLS_END + +#endif /* _TOS_MAIL_QUEUE_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_message_queue.h b/TencentOS_Tiny/kernel/core/include/tos_message_queue.h new file mode 100644 index 0000000..78a6f96 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_message_queue.h @@ -0,0 +1,154 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_MESSAGE_QUEUE_H_ +#define _TOS_MESSAGE_QUEUE_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_MESSAGE_QUEUE_EN > 0u + +typedef struct k_message_queue_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_ring_q_t ring_q; +} k_msg_q_t; + +/** + * @brief Create a message queue. + * create a message queue. + * + * @attention a MESSAGE is a "void *" pointer. + * + * @param[in] msg_q pointer to the handler of the message queue. + * @param[in] pool pool buffer of the message queue. + * @param[in] msg_cnt message count of the message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_create(k_msg_q_t *msg_q, void *pool, size_t msg_cnt); + +/** + * @brief Destroy a message queue. + * destroy a message queue. + * + * @attention None + * + * @param[in] msg_q pointer to the handler of the message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_destroy(k_msg_q_t *msg_q); + +/** + * @brief Create a message queue with dynamic allocated pool. + * create a message queue with dynamic allocated pool. + * + * @attention a MESSAGE is a "void *" pointer. + * + * @param[in] msg_q pointer to the handler of the message queue. + * @param[in] msg_cnt message count of the message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_create_dyn(k_msg_q_t *msg_q, size_t msg_cnt); + +/** + * @brief Destroy a message queue with dynamic allocated pool. + * destroy a message queue with dynamic allocated pool. + * + * @attention None + * + * @param[in] msg_q pointer to the handler of the message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_destroy_dyn(k_msg_q_t *msg_q); + +/** + * @brief Flush the message queue. + * flush the message queue. + * + * @attention None + * + * @param[in] msg_q pointer to the handler of the message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_flush(k_msg_q_t *msg_q); + +/** + * @brief Pend a message queue. + * pend a message queue. + * + * @attention we DONNOT perform a memcpy when msg_ptr is received(a MESSAGE is just a pointer). + * + * @param[in] msg_q pointer to the handler of the message queue. + * @param[OUT] msg_ptr a pointer to the message we wanna receive. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the queue we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_pend(k_msg_q_t *msg_q, void **msg_ptr, k_tick_t timeout); + +/** + * @brief Post a message queue. + * post a message queue and wakeup one pending task. + * + * @attention when tos_msg_q_post return successfully, only one task who are waitting for the message queue will be woken up. + * + * @param[in] msg_q pointer to the handler of the message queue. + * @param[in] msg_ptr the message to post(a MESSAGE is just a pointer). + * + * @return errcode + * @retval #K_ERR_RING_Q_FULL the message queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_post(k_msg_q_t *msg_q, void *msg_ptr); + +/** + * @brief Post a message queue. + * post a message queue and wakeup all the pending task. + * + * @attention when tos_msg_q_post_all return successfully, all of the tasks who are waitting for the message queue will be woken up. + * + * @param[in] msg_q pointer to the handler of the message queue. + * @param[in] msg_ptr the message to post(a MESSAGE is just a pointer). + * + * @return errcode + * @retval #K_ERR_RING_Q_FULL the message queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_msg_q_post_all(k_msg_q_t *msg_q, void *msg_ptr); + +#endif + +__CDECLS_END + +#endif /* _TOS_MESSAGE_QUEUE_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_mmblk.h b/TencentOS_Tiny/kernel/core/include/tos_mmblk.h new file mode 100644 index 0000000..8d784b5 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_mmblk.h @@ -0,0 +1,132 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_MMBLK_H_ +#define _TOS_MMBLK_H_ + +__CDECLS_BEGIN + +#define K_MMBLK_NEXT_BLK(blk_curr, blk_size) ((void *)((cpu_addr_t)blk_curr + blk_size)) +#define K_MMBLK_ALIGN_MASK (sizeof(void *) - 1u) + +typedef struct k_mmblk_pool_st { + knl_obj_t knl_obj; + + void *pool_start; + void *free_list; + size_t blk_size; + size_t blk_max; + size_t blk_free; +} k_mmblk_pool_t; + +/** + * @brief Create a memory manage block pool. + * Create a memory manage block pool. + * + * @attention None + * + * @param[in] mbp pointer to the memory block pool handler. + * @param[in] pool_start start address of the pool. + * @param[in] blk_num number of the blocks in the pool. + * @param[in] blk_size size of each block in the pool. + * + * @return errcode + * @retval #K_ERR_MMBLK_INVALID_POOL_ADDR start address of the pool is invalid. + * @retval #K_ERR_MMBLK_INVALID_BLK_SIZE size of the block is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmblk_pool_create(k_mmblk_pool_t *mbp, void *pool_start, size_t blk_num, size_t blk_size); + +/** + * @brief Destroy a memory manage block pool. + * Destroy a memory manage block pool. + * + * @attention None + * + * @param[in] mbp pointer to the memory block pool handler. + * + * @return errcode + * @retval #K_ERR_OBJ_INVALID mbp is not a valid memory block pool handler. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmblk_pool_destroy(k_mmblk_pool_t *mbp); + +/** + * @brief Create a dynamic memory manage block pool. + * Create a dynamic memory manage block pool. + * + * @attention None + * + * @param[in] mbp pointer to the pointer of memory block pool handler. + * @param[in] blk_num number of the blocks in the pool. + * @param[in] blk_size size of each block in the pool. + * + * @return errcode + * @retval #K_ERR_MMBLK_INVALID_POOL_ADDR start address of the pool is invalid. + * @retval #K_ERR_MMBLK_INVALID_BLK_SIZE size of the block is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmblk_pool_create_dyn(k_mmblk_pool_t **mbp, size_t blk_num, size_t blk_size); + +/** + * @brief Destroy a dynamic memory manage block pool. + * Destroy a memory dynamic manage block pool. + * + * @attention None + * + * @param[in] mbp pointer to the memory block pool handler. + * + * @return errcode + * @retval #K_ERR_OBJ_INVALID mbp is not a valid memory block pool handler. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmblk_pool_destroy_dyn(k_mmblk_pool_t *mbp); + +/** + * @brief Allocate a memory manage block. + * Allocate a memory manage block. + * + * @attention None + * + * @param[in] mbp pointer to the memory block pool handler. + * @param[in] blk start address of the memory manage block. + * + * @return errcode + * @retval #K_ERR_MMBLK_POOL_EMPTY the pool is empty. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmblk_alloc(k_mmblk_pool_t *mbp, void **blk); + +/** + * @brief Free a memory manage block. + * Free a memory manage block. + * + * @attention None + * + * @param[in] mbp pointer to the memory block pool handler. + * @param[in] blk start address of the memory manage block. + * + * @return errcode + * @retval #K_ERR_MMBLK_POOL_FULL the pool is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmblk_free(k_mmblk_pool_t *mbp, void *blk); + +#endif + +__CDECLS_END + diff --git a/TencentOS_Tiny/kernel/core/include/tos_mmheap.h b/TencentOS_Tiny/kernel/core/include/tos_mmheap.h new file mode 100644 index 0000000..76de172 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_mmheap.h @@ -0,0 +1,277 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +/* +** Two Level Segregated Fit memory allocator, version 3.1. +** Written by Matthew Conte +** http://tlsf.baisoku.org +** +** Based on the original documentation by Miguel Masmano: +** http://www.gii.upv.es/tlsf/main/docs +** +** This implementation was written to the specification +** of the document, therefore no GPL restrictions apply. +** +** Copyright (c) 2006-2016, Matthew Conte +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions are met: +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** * Neither the name of the copyright holder nor the +** names of its contributors may be used to endorse or promote products +** derived from this software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL MATTHEW CONTE BE LIABLE FOR ANY +** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _TOS_MMHEAP_H_ +#define _TOS_MMHEAP_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_MMHEAP_EN > 0u + +/** + * log2 of number of linear subdivisions of block sizes. Larger + * values require more memory in the control structure. Values of + * 4 or 5 are typical. + */ +#define K_MMHEAP_SL_INDEX_COUNT_LOG2 5 + +/* All allocation sizes and addresses are aligned to 4 bytes. */ +#define K_MMHEAP_ALIGN_SIZE_LOG2 2 +#define K_MMHEAP_ALIGN_SIZE (1 << K_MMHEAP_ALIGN_SIZE_LOG2) + +/* + * We support allocations of sizes up to (1 << K_MMHEAP_FL_INDEX_MAX) bits. + * However, because we linearly subdivide the second-level lists, and + * our minimum size granularity is 4 bytes, it doesn't make sense to + * create first-level lists for sizes smaller than K_MMHEAP_SL_INDEX_COUNT * 4, + * or (1 << (K_MMHEAP_SL_INDEX_COUNT_LOG2 + 2)) bytes, as there we will be + * trying to split size ranges into more slots than we have available. + * Instead, we calculate the minimum threshold size, and place all + * blocks below that size into the 0th first-level list. + */ +#define K_MMHEAP_FL_INDEX_MAX 30 +#define K_MMHEAP_SL_INDEX_COUNT (1 << K_MMHEAP_SL_INDEX_COUNT_LOG2) +#define K_MMHEAP_FL_INDEX_SHIFT (K_MMHEAP_SL_INDEX_COUNT_LOG2 + K_MMHEAP_ALIGN_SIZE_LOG2) +#define K_MMHEAP_FL_INDEX_COUNT (K_MMHEAP_FL_INDEX_MAX - K_MMHEAP_FL_INDEX_SHIFT + 1) + +#define K_MMHEAP_SMALL_BLOCK_SIZE (1 << K_MMHEAP_FL_INDEX_SHIFT) + +#define K_MMHEAP_BLOCK_CURR_FREE (1 << 0) +#define K_MMHEAP_BLOCK_PREV_FREE (1 << 1) +#define K_MMHEAP_BLOCK_SIZE_MASK ~(K_MMHEAP_BLOCK_CURR_FREE | K_MMHEAP_BLOCK_PREV_FREE) +#define K_MMHEAP_BLOCK_STATE_MASK (K_MMHEAP_BLOCK_CURR_FREE | K_MMHEAP_BLOCK_PREV_FREE) + +typedef struct k_mmheap_information_st { + uint32_t used; /* space is used */ + uint32_t free; /* space is free */ +} k_mmheap_info_t; + +/** + * Block structure. + * + * There are several implementation subtleties involved: + * - The prev_phys_block field is only valid if the previous block is free. + * - The prev_phys_block field is actually stored at the end of the + * previous block. It appears at the beginning of this structure only to + * simplify the implementation. + * - The next_free / prev_free fields are only valid if the block is free. + */ +typedef struct mmheap_blk_st { + struct mmheap_blk_st *prev_phys_blk; + + size_t size; + + struct mmheap_blk_st *next_free; + struct mmheap_blk_st *prev_free; +} mmheap_blk_t; + +/** + * A free block must be large enough to store its header minus the size of + * the prev_phys_block field, and no larger than the number of addressable + * bits for FL_INDEX. + */ +#define K_MMHEAP_BLK_SIZE_MIN (sizeof(mmheap_blk_t) - sizeof(mmheap_blk_t *)) +#define K_MMHEAP_BLK_SIZE_MAX (1 << K_MMHEAP_FL_INDEX_MAX) + +#define K_MMHEAP_BLK_HEADER_OVERHEAD (sizeof(size_t)) +#define K_MMHEAP_BLK_START_OFFSET (TOS_OFFSET_OF_FIELD(mmheap_blk_t, size) + sizeof(size_t)) + +#define K_MMHEAP_POOL_MAX 3 + +/** + * memory heap control + */ +typedef struct k_mmheap_control_st { + int pool_cnt; + void *pool_start[K_MMHEAP_POOL_MAX]; + + mmheap_blk_t block_null; /**< Empty lists point at this block to indicate they are free. */ + + uint32_t fl_bitmap; /**< Bitmaps for free lists. */ + uint32_t sl_bitmap[K_MMHEAP_FL_INDEX_COUNT]; + + mmheap_blk_t *blocks[K_MMHEAP_FL_INDEX_COUNT][K_MMHEAP_SL_INDEX_COUNT]; /**< Head of free lists. */ +} k_mmheap_ctl_t; + +/** + * @brief Add a pool. + * Add addtional pool to the heap. + * + * @attention None + * + * @param[in] pool_start start address of the pool. + * @param[in] pool_size size of the pool. + * + * @return errcode + * @retval #K_ERR_MMHEAP_INVALID_POOL_ADDR start address of the pool is invalid. + * @retval #K_ERR_MMHEAP_INVALID_POOL_SIZE size of the pool is invalid. + * @retval #K_ERR_MMHEAP_POOL_OVERFLOW too many pools are added. + * @retval #K_ERR_MMHEAP_POOL_ALREADY_EXIST the pool is already exist. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmheap_pool_add(void *pool_start, size_t pool_size); + +/** + * @brief Remove a pool. + * Remove a pool from the heap. + * + * @attention None + * + * @param[in] pool_start start address of the pool. + * + * @return errcode + * @retval #K_ERR_OBJ_PTR_NULL start address of the pool is NULL + * @retval #K_ERR_MMHEAP_POOL_NOT_EXIST the pool is not exist + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmheap_pool_rmv(void *pool_start); + +/** + * @brief Alloc memory. + * Allocate size bytes and returns a pointer to the allocated memory. + * + * @attention size should no bigger than K_MMHEAP_BLK_SIZE_MAX. + * + * @param[in] size size of the memory. + * + * @return the pointer to the allocated memory. + */ +__API__ void *tos_mmheap_alloc(size_t size); + +__API__ void *tos_mmheap_calloc(size_t num, size_t size); + +/** + * @brief Alloc start address aligned memory from the heap. + * Alloc aligned address and specified size memory from the heap. + * + * @attention + * + * @param[in] size size of the memory. + * @param[in] align address align mask of the memory. + * + * @return the pointer to the allocated memory. + */ +__API__ void *tos_mmheap_aligned_alloc(size_t size, size_t align); + +/** + * @brief Realloc memory from the heap. + * Change the size of the memory block pointed to by ptr to size bytes. + * + * @attention + *
    + *
  • if ptr is K_NULL, then the call is equivalent to tos_mmheap_alloc(size), for all values of size. + *
  • if ptr is if size is equal to zero, and ptr is not K_NULL, then the call is equivalent to tos_mmheap_free(ptr). + *
+ * + * @param[in] ptr old pointer to the memory space. + * @param[in] size new size of the memory space. + * + * @return the new pointer to the allocated memory. + */ +__API__ void *tos_mmheap_realloc(void *ptr, size_t size); + +/** + * @brief Free the memory. + * Free the memory space pointed to by ptr, which must have been returned by a previous call to tos_mmheap_alloc(), tos_mmheap_aligned_alloc(), or tos_mmheap_realloc(). + * + * @attention + * + * @param[in] ptr pointer to the memory. + * + * @return None. + */ +__API__ void tos_mmheap_free(void *ptr); + +/** + * @brief Check the pool. + * + * @attention + * + * @param[in] pool_start start address of the pool. + * @param[out] info pointer to the information struct. + * + * @return errcode. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmheap_pool_check(void *pool_start, k_mmheap_info_t *info); + +/** + * @brief Check the heap. + * + * @attention + * + * @param[out] info pointer to the information struct. + * + * @return errcode. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mmheap_check(k_mmheap_info_t *info); + +__KNL__ k_err_t mmheap_init(void); + +__KNL__ k_err_t mmheap_init_with_pool(void *pool_start, size_t pool_size); + +#else /* if mmheap is not enabled, use libc instead */ + +#define tos_mmheap_alloc malloc +#define tos_mmheap_calloc calloc +#define tos_mmheap_realloc realloc +#define tos_mmheap_free free + +#endif + +__CDECLS_END + +#endif /* _TOS_MMHEAP_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_mutex.h b/TencentOS_Tiny/kernel/core/include/tos_mutex.h new file mode 100644 index 0000000..8c4cca8 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_mutex.h @@ -0,0 +1,133 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_MUTEX_H_ +#define _TOS_MUTEX_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_MUTEX_EN > 0u + +typedef struct k_mutex_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_nesting_t pend_nesting; + k_task_t *owner; + k_prio_t owner_orig_prio; + k_list_t owner_anchor; +} k_mutex_t; + +/** + * @brief Create a mutex. + * create a mutex. + * + * @attention None + * + * @param[in] mutex pointer to the handler of the mutex. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mutex_create(k_mutex_t *mutex); + +/** + * @brief Create a dynamic mutex. + * create a dynamic mutex. + * + * @attention None + * + * @param[in] mutex pointer to the pointer of the mutex. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mutex_create_dyn(k_mutex_t **mutex); + +/** + * @brief Destroy a mutex. + * destroy a mutex. + * + * @attention None + * + * @param[in] mutex pointer to the handler of the mutex. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mutex_destroy(k_mutex_t *mutex); + +/** + * @brief Pend a mutex. + * pend a mutex. + * + * @attention The task will keep blocked until the mutex is obtained or a timeout comes. + * + * @param[in] mutex pointer to the handler of the mutex. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_MUTEX_NESTING_OVERFLOW we are the owner of the mutex, and we are nesting pend too much on this mutex. + * @retval #K_ERR_MUTEX_NESTING we are the owner of the mutex, and we are nesting pend on it. + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the mutex we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mutex_pend_timed(k_mutex_t *mutex, k_tick_t timeout); + +/** + * @brief Pend a mutex. + * pend a mutex. + * + * @attention The task will keep blocked until the mutex is obtained. + * + * @param[in] mutex pointer to the handler of the mutex. + * + * @return errcode + * @retval #K_ERR_MUTEX_NESTING_OVERFLOW we are the owner of the mutex, and we are nesting pend too much on this mutex. + * @retval #K_ERR_MUTEX_NESTING we are the owner of the mutex, and we are nesting pend on it. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_DESTROY the mutex we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mutex_pend(k_mutex_t *mutex); + +/** + * @brief Post a mutex. + * post a mutex. + * + * @attention None + * + * @param[in] mutex pointer to the handler of the mutex. + * + * @return errcode + * @retval #K_ERR_MUTEX_NOT_OWNER we are posting a mutex of which the owner is not us. + * @retval #K_ERR_MUTEX_NESTING we are posting a mutex owned by us, and we are still in a nesting. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_mutex_post(k_mutex_t *mutex); + +__KNL__ void mutex_release(k_mutex_t *mutex); + +#endif + +__CDECLS_END + +#endif /* _TOS_MUTEX_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_pend.h b/TencentOS_Tiny/kernel/core/include/tos_pend.h new file mode 100644 index 0000000..1b36f53 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_pend.h @@ -0,0 +1,73 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_PEND_H_ +#define _TOS_PEND_H_ + +__CDECLS_BEGIN + +/** + * The reason why we wakeup from a pend. + * when we wakeup, we need to know why. + */ +typedef enum pend_state_en { + PEND_STATE_NONE, /**< nothing. */ + PEND_STATE_POST, /**< someone has post, we get what we want. */ + PEND_STATE_TIMEOUT, /**< a post has never came until time is out. */ + PEND_STATE_DESTROY, /**< someone has destroyed what we are pending for. */ + PEND_STATE_OWNER_DIE, /**< the pend object owner task is destroyed. */ +} pend_state_t; + +typedef enum opt_post_en { + OPT_POST_ONE, + OPT_POST_ALL, +} opt_post_t; + +typedef struct pend_object_st { + k_list_t list; +} pend_obj_t; + +__KNL__ void pend_object_init(pend_obj_t *object); + +__KNL__ void pend_object_deinit(pend_obj_t *object); + +__KNL__ int pend_is_nopending(pend_obj_t *object); + +__KNL__ k_prio_t pend_highest_pending_prio_get(pend_obj_t *object); + +__KNL__ k_task_t *pend_highest_pending_task_get(pend_obj_t *object); + +__KNL__ void pend_list_remove(k_task_t *task); + +__KNL__ void pend_list_adjust(k_task_t *task); + +__KNL__ k_err_t pend_state2errno(pend_state_t state); + +__KNL__ void pend_task_wakeup(k_task_t *task, pend_state_t state); + +__KNL__ void pend_task_block(k_task_t *task, pend_obj_t *object, k_tick_t timeout); + +__KNL__ void pend_wakeup_one(pend_obj_t *object, pend_state_t state); + +__KNL__ void pend_wakeup_all(pend_obj_t *object, pend_state_t state); + +__KNL__ void pend_wakeup(pend_obj_t *object, pend_state_t state, opt_post_t opt); + +__CDECLS_END + +#endif /* _TOS_PEND_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_priority_mail_queue.h b/TencentOS_Tiny/kernel/core/include/tos_priority_mail_queue.h new file mode 100644 index 0000000..9d66920 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_priority_mail_queue.h @@ -0,0 +1,167 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_PRIORITY_MAIL_QUEUE_H_ +#define _TOS_PRIORITY_MAIL_QUEUE_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_PRIORITY_MAIL_QUEUE_EN > 0u + +typedef struct k_priority_mail_queue_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + + void *prio_q_mgr_array; + k_prio_q_t prio_q; +} k_prio_mail_q_t; + +/** + * @brief Create a priority mail queue. + * create a priority mail queue. + * + * @attention a MAIL is a buffer with a certain size. + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * @param[in] pool pool buffer of the priority mail queue. + * @param[in] mail_cnt mail count of the priority mail queue. + * @param[in] mail_size size of each mail in the priority mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_create(k_prio_mail_q_t *prio_mail_q, void *pool, size_t mail_cnt, size_t mail_size); + +/** + * @brief Destroy a priority mail queue. + * destroy a priority mail queue. + * + * @attention None + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_destroy(k_prio_mail_q_t *prio_mail_q); + +/** + * @brief Create a priority mail queue with dynamic allocated pool. + * create a priority mail queue with dynamic allocated pool. + * + * @attention a MAIL is a buffer with a certain size. + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * @param[in] mail_cnt mail count of the priority mail queue. + * @param[in] mail_size size of each mail in the priority mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_create_dyn(k_prio_mail_q_t *prio_mail_q, size_t mail_cnt, size_t mail_size); + +/** + * @brief Destroy a priority mail queue with dynamic allocated pool. + * destroy a priority mail queue with dynamic allocated pool. + * + * @attention None + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_destroy_dyn(k_prio_mail_q_t *prio_mail_q); + +/** + * @brief Flush the priority mail queue. + * flush the priority mail queue. + * + * @attention None + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_flush(k_prio_mail_q_t *prio_mail_q); + +/** + * @brief Pend a priority mail queue. + * pend a priority mail queue. + * + * @attention + * 1. we WILL perform a memcpy when mail_buf is received(a MAIL is a buffer with a certain size). + * 2. With priority mail queue, if the poster has post several mail with different priority, the pender will receive + * the mail in priority order(numerically bigger, actually smaller, means the mail with highest priority(numerically + * smallest) will be received first, then the second highest priority mail, and so on). + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * @param[OUT] mail_buf a pointer to the mail buffer we wanna receive. + * @param[OUT] mail_size size of the mail buffer received(should be consistent with the mail_size passed to tos_prio_mail_q_create). + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the queue we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_pend(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t *mail_size, k_tick_t timeout); + +/** + * @brief Post a priority mail queue. + * post a priority mail queue and wakeup one pending task. + * + * @attention when tos_prio_mail_q_post return successfully, only one task who are waitting for the mail queue will be woken up. + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * @param[in] mail_buf the mail to post(a MAIL is a buffer). + * @param[in] mail_size the size of the mail to post(a MAIL is just a buffer). + * @param[in] prio the priority of the mail. + * + * @return errcode + * @retval #K_ERR_PRIO_Q_FULL the mail queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_post(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t mail_size, k_prio_t prio); + +/** + * @brief Post a priority mail queue. + * post a priority mail queue and wakeup all the pending task. + * + * @attention when tos_prio_mail_q_post_all return successfully, all of the tasks who are waitting for the message queue will be woken up. + * + * @param[in] prio_mail_q pointer to the handler of the priority mail queue. + * @param[in] mail_buf the mail to post(a MAIL is a buffer). + * @param[in] mail_size the size of the mail to post(a MAIL is just a buffer). + * @param[in] prio the priority of the mail. + * + * @return errcode + * @retval #K_ERR_PRIO_Q_FULL the mail queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_mail_q_post_all(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t mail_size, k_prio_t prio); + +#endif /* TOS_CFG_PRIORITY_MAIL_QUEUE_EN */ + +__CDECLS_END + +#endif /* _TOS_PRIORITY_MAIL_QUEUE_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_priority_message_queue.h b/TencentOS_Tiny/kernel/core/include/tos_priority_message_queue.h new file mode 100644 index 0000000..cd43263 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_priority_message_queue.h @@ -0,0 +1,162 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_PRIORITY_MESSAGE_QUEUE_H_ +#define _TOS_PRIORITY_MESSAGE_QUEUE_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN > 0u + +typedef struct k_priority_message_queue_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + + void *prio_q_mgr_array; + k_prio_q_t prio_q; +} k_prio_msg_q_t; + +/** + * @brief Create a priority message queue. + * create a priority message queue. + * + * @attention a MESSAGE is a "void *" pointer. + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * @param[in] pool pool buffer of the priority message queue. + * @param[in] msg_cnt message count of the priority message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_create(k_prio_msg_q_t *prio_msg_q, void *pool, size_t msg_cnt); + +/** + * @brief Destroy a priority message queue. + * destroy a priority message queue. + * + * @attention None + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_destroy(k_prio_msg_q_t *prio_msg_q); + +/** + * @brief Create a priority message queue with dynamic allocated pool. + * create a priority message queue with dynamic allocated pool. + * + * @attention a MESSAGE is a "void *" pointer. + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * @param[in] msg_cnt message count of the priority message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_create_dyn(k_prio_msg_q_t *prio_msg_q, size_t msg_cnt); + +/** + * @brief Destroy a priority message queue with dynamic allocated pool. + * destroy a priority message queue with dynamic allocated pool. + * + * @attention None + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_destroy_dyn(k_prio_msg_q_t *prio_msg_q); + +/** + * @brief Flush the priority message queue. + * flush the priority message queue. + * + * @attention None + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_flush(k_prio_msg_q_t *prio_msg_q); + +/** + * @brief Pend a priority message queue. + * pend a priority message queue. + * + * @attentio + * 1. we DONNOT perform a memcpy when msg_ptr is received(a MESSAGE is just a pointer). + * 2. With priority message queue, if the poster has post several message with different priority, the pender will receive + * the message in priority order(numerically bigger, actually smaller, means the message with highest priority(numerically + * smallest) will be received first, then the second highest priority message, and so on). + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * @param[OUT] msg_ptr a pointer to the message we wanna receive. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the queue we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_pend(k_prio_msg_q_t *prio_msg_q, void **msg_ptr, k_tick_t timeout); + +/** + * @brief Post a priority message queue. + * post a priority message queue and wakeup one pending task. + * + * @attention when tos_prio_msg_q_post return successfully, only one task who are waitting for the priority message queue will be woken up. + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * @param[in] msg_ptr the message to post(a MESSAGE is just a pointer). + * @param[in] prio the priority of the message. + * + * @return errcode + * @retval #K_ERR_PRIO_Q_FULL the priority message queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_post(k_prio_msg_q_t *prio_msg_q, void *msg_ptr, k_prio_t prio); + +/** + * @brief Post a priority message queue. + * post a priority message queue and wakeup all the pending task. + * + * @attention when tos_prio_msg_q_post_all return successfully, all of the tasks who are waitting for the priority message queue will be woken up. + * + * @param[in] prio_msg_q pointer to the handler of the priority message queue. + * @param[in] msg_ptr the priority message to post(a MESSAGE is just a pointer). + * @param[in] prio the priority of the message. + * + * @return errcode + * @retval #K_ERR_PRIO_Q_FULL the priority message queue is full. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_msg_q_post_all(k_prio_msg_q_t *prio_msg_q, void *msg_ptr, k_prio_t prio); + +#endif + +__CDECLS_END + +#endif /* _TOS_PRIORITY_MESSAGE_QUEUE_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_priority_queue.h b/TencentOS_Tiny/kernel/core/include/tos_priority_queue.h new file mode 100644 index 0000000..729cc84 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_priority_queue.h @@ -0,0 +1,209 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_PRIORITY_QUEUE_H_ +#define _TOS_PRIORITY_QUEUE_H_ + +__CDECLS_BEGIN + +typedef uint16_t prio_q_slot_t; + +typedef struct prio_q_pool_manager_entry_st { + prio_q_slot_t next; +} prio_q_pool_mgr_ent_t; + +typedef struct prio_q_pool_manager_st { + prio_q_slot_t first_free; + prio_q_pool_mgr_ent_t *pool_mgr_ent_array; +} prio_q_pool_mgr_t; + +typedef struct prio_q_priority_manager_entry_st { + k_prio_t priority; + prio_q_slot_t slot; +} prio_q_prio_mgr_ent_t; + +typedef struct prio_q_prio_manager_st { + k_bin_heap_t prio_mgr_bin_heap; + prio_q_prio_mgr_ent_t *prio_mgr_ent_pool; +} prio_q_prio_mgr_t; + +typedef struct k_priority_queue_st { + knl_obj_t knl_obj; + + prio_q_pool_mgr_t pool_mgr; + prio_q_prio_mgr_t prio_mgr; + + size_t total; + size_t item_size; + size_t item_cnt; + + uint8_t *mgr_pool; + uint8_t *data_pool; +} k_prio_q_t; + +#define PRIO_Q_POOL_SLOT_INVALID ((prio_q_slot_t)-1) + +#define PRIO_Q_POOL_MGR_ENT_ARRAY_SIZE(item_cnt) \ + (item_cnt * sizeof(prio_q_pool_mgr_ent_t)) + +#define PRIO_Q_PRIO_MGR_ENT_POOL_SIZE(item_cnt) \ + (item_cnt * sizeof(prio_q_prio_mgr_ent_t)) + +#define PRIO_Q_THE_ITEM(prio_q, slot) (void *)(&prio_q->data_pool[slot * prio_q->item_size]) + +// get the size of mgr_array to create a priority queue +#define TOS_PRIO_Q_MGR_ARRAY_SIZE(item_cnt) \ + (PRIO_Q_POOL_MGR_ENT_ARRAY_SIZE(item_cnt) + PRIO_Q_PRIO_MGR_ENT_POOL_SIZE(item_cnt)) + +/** + * @brief Create a priority queue. + * create a priority queue. + * + * @attention if we wanna create a priority queue, we should offer a manager array buffer of which the size can be calculated by TOS_PRIO_Q_MGR_ARRAY_SIZE. + * + * @param[in] prio_q pointer to the handler of the priority queue. + * @param[in] mgr_array manager array buffer of the priority queue. + * @param[in] pool pool buffer of the priority queue. + * @param[in] item_cnt item count of the priority queue. + * @param[in] item_size size of each item of the priority queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_q_create(k_prio_q_t *prio_q, void *mgr_array, void *pool, size_t item_cnt, size_t item_size); + +/** + * @brief Destroy a priority queue. + * destroy a priority queue. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of the bpriority queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_q_destroy(k_prio_q_t *prio_q); + +/** + * @brief Create a priority queue with dynamic allocated mgr array and data pool. + * create a priority queue with dynamic allocated mgr array and data pool. + * + * @attention if we wanna create a priority queue, we should offer a manager array buffer of which the size can be calculated by TOS_PRIO_Q_MGR_ARRAY_SIZE. + * + * @param[in] prio_q pointer to the handler of the priority queue. + * @param[in] item_cnt item count of the priority queue. + * @param[in] item_size size of each item of the priority queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_q_create_dyn(k_prio_q_t *prio_q, size_t item_cnt, size_t item_size); + +/** + * @brief Destroy a priority queue with dynamic allocated mgr array and data pool. + * destroy a priority queue with dynamic allocated mgr array and data pool. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of the bpriority queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_q_destroy_dyn(k_prio_q_t *prio_q); + +/** + * @brief Enqueue an priority queue. + * enqueue an item into the priority queue. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of priority queue. + * @param[in] item the item to be enqueued. + * @param[in] item_size size of the item(should be consistent with the item_size passed to tos_prio_q_create). + * @param[in] prio priority of the item to be enqueued(should be consistent with the item_size passed to tos_prio_q_create). + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_PRIO_Q_ITEM_SIZE_NOT_MATCH the item_size is not consistent with the item_size passed to tos_prio_q_create. + * @retval #K_ERR_PRIO_Q_FULL the priority queue is full. + */ +__API__ k_err_t tos_prio_q_enqueue(k_prio_q_t *prio_q, void *item, size_t item_size, k_prio_t prio); + +/** + * @brief Dequeue an item. + * dequeue an item from the priority queue. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of the priority queue. + * @param[out] item buffer to hold the item dequeued. + * @param[out] item_size size of the item dequeued(should be consistent with the item_size passed to tos_prio_q_create). + * @param[out] prio priority of the item dequeued. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_PRIO_Q_EMPTY the priority queue is empty. + */ +__API__ k_err_t tos_prio_q_dequeue(k_prio_q_t *prio_q, void *item, size_t *item_size, k_prio_t *prio); + +/** + * @brief Flush the priority queue. + * flush the priority queue. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of the priority queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_prio_q_flush(k_prio_q_t *prio_q); + +/** + * @brief Whether the priority queue is empty. + * Whether the priority queue is empty. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of the priority queue. + * + * @return whether the priority queue is emtpy. + * @retval #0 the priority queue is not empty. + * @retval #Not 0 the priority queue is empty. + */ +__API__ int tos_prio_q_is_empty(k_prio_q_t *prio_q); + +/** + * @brief Whether the priority queue is full. + * Whether the priority queue is full. + * + * @attention None + * + * @param[in] prio_q pointer to the handler of the priority queue. + * + * @return whether the priority queue is full. + * @retval #0 the priority queue is not full. + * @retval #Not 0 the priority queue is full. + */ +__API__ int tos_prio_q_is_full(k_prio_q_t *prio_q); + +__CDECLS_END + +#endif /* _TOS_PRIORITY_QUEUE_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_ring_queue.h b/TencentOS_Tiny/kernel/core/include/tos_ring_queue.h new file mode 100644 index 0000000..0c5c2e8 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_ring_queue.h @@ -0,0 +1,173 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_RING_QUEUE_H_ +#define _TOS_RING_QUEUE_H_ + +typedef struct k_ring_queue_st { + knl_obj_t knl_obj; + + uint16_t head; + uint16_t tail; + size_t total; + + uint8_t *pool; + + size_t item_size; + size_t item_cnt; +} k_ring_q_t; + +#define RING_HEAD_ITEM(ring_q) (uint8_t *)(&ring_q->pool[ring_q->head * ring_q->item_size]) +#define RING_TAIL_ITEM(ring_q) (uint8_t *)(&ring_q->pool[ring_q->tail * ring_q->item_size]) +#define RING_NEXT(ring_q, index) ((index + 1) % ring_q->item_cnt) + +/** + * @brief Create a ring queue. + * create a ring queue. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * @param[in] pool pool buffer of the ring queue. + * @param[in] item_cnt item count of the ring queue. + * @param[in] item_size size of each item of the ring queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_ring_q_create(k_ring_q_t *ring_q, void *pool, size_t item_cnt, size_t item_size); + +/** + * @brief Destroy a ring queue. + * destroy a ring queue. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_OBJ_INVALID_ALLOC_TYPE invalid alloc type(is dynamic allocated not static) + */ +__API__ k_err_t tos_ring_q_destroy(k_ring_q_t *ring_q); + +/** + * @brief Create a ring queue with dynamic allocated pool. + * create a ring queue with dynamic allocated pool. + * + * @attention pool inside is dynamic allocated. + * + * @param[in] ring_q pointer to the handler of the ring queue. + * @param[in] item_cnt item count of the ring queue. + * @param[in] item_size size of each item of the ring queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_OUT_OF_MEMORY out of memory + */ +__API__ k_err_t tos_ring_q_create_dyn(k_ring_q_t *ring_q, size_t item_cnt, size_t item_size); + +/** + * @brief Destroy a ring queue with a dynamic allocated pool. + * destroy a ring queue with a dynamic allocated pool. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_OBJ_INVALID_ALLOC_TYPE invalid alloc type(is static allocated not dynamic) + */ +__API__ k_err_t tos_ring_q_destroy_dyn(k_ring_q_t *ring_q); + +/** + * @brief Enqueue an item. + * enqueue an item into the ring queue. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * @param[in] item the item to be enqueued. + * @param[in] item_size size of the item(should be consistent with the item_size passed to tos_ring_q_create). + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RING_Q_ITEM_SIZE_NOT_MATCH the item_size is not consistent with the item_size passed to tos_ring_q_create. + * @retval #K_ERR_RING_Q_FULL the ring queue is full. + */ +__API__ k_err_t tos_ring_q_enqueue(k_ring_q_t *ring_q, void *item, size_t item_size); + +/** + * @brief Dequeue an item. + * dequeue an item from the ring queue. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * @param[out] item buffer to hold the item dequeued. + * @param[out] item_size size of the item dequeued(should be consistent with the item_size passed to tos_ring_q_create). + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RING_Q_EMPTY the ring queue is empty. + */ +__API__ k_err_t tos_ring_q_dequeue(k_ring_q_t *ring_q, void *item, size_t *item_size); + +/** + * @brief Flush the ring queue. + * flush the ring queue. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_ring_q_flush(k_ring_q_t *ring_q); + +/** + * @brief Whether the ring queue is empty. + * Whether the ring queue is empty. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * + * @return whether the ring queue is emtpy. + * @retval #0 the ring queue is not empty. + * @retval #Not 0 the ring queue is empty. + */ +__API__ int tos_ring_q_is_empty(k_ring_q_t *ring_q); + +/** + * @brief Whether the ring queue is full. + * Whether the ring queue is full. + * + * @attention None + * + * @param[in] ring_q pointer to the handler of the ring queue. + * + * @return whether the ring queue is full. + * @retval #0 the ring queue is not full. + * @retval #Not 0 the ring queue is full. + */ +__API__ int tos_ring_q_is_full(k_ring_q_t *ring_q); + +#endif + diff --git a/TencentOS_Tiny/kernel/core/include/tos_robin.h b/TencentOS_Tiny/kernel/core/include/tos_robin.h new file mode 100644 index 0000000..675ed90 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_robin.h @@ -0,0 +1,57 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_ROBIN_H_ +#define _TOS_ROBIN_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_ROUND_ROBIN_EN > 0u + +/** + * @brief Set time slice. + * Set time slice of a task. + * + * @attention None + * + * @param[in] task pointer to the handler of the task. + * @param[in] timeslice time slice of the task + * + * @return None + */ +__API__ void tos_robin_timeslice_set(k_task_t *task, k_timeslice_t timeslice); + +/** + * @brief Configure round robin. + * Set the default time slice of the task. + * + * @attention None + * + * @param[in] default_timeslice default time slice of the task. + * + * @return None + */ +__API__ void tos_robin_default_timeslice_config(k_timeslice_t default_timeslice); + +__KNL__ void robin_sched(k_prio_t prio); + +#endif /* TOS_CFG_ROUND_ROBIN_EN */ + +__CDECLS_END + +#endif /* _TOS_ROBIN_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_rwlock.h b/TencentOS_Tiny/kernel/core/include/tos_rwlock.h new file mode 100644 index 0000000..37bed08 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_rwlock.h @@ -0,0 +1,192 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_RWLOCK_H_ +#define _TOS_RWLOCK_H_ + +__CDECLS_BEGIN + +#if (TOS_CFG_SEM_EN > 0u) && (TOS_CFG_MUTEX_EN > 0u) + +typedef uint16_t rw_cnt_t; + +typedef struct k_rwlock_st { + knl_obj_t knl_obj; + + k_mutex_t lock; + k_sem_t signal; + + rw_cnt_t n_readers; /* how many readers are reading? */ + rw_cnt_t n_writers; /* how many writers are waiting to obtain the wlock? */ + int is_writting; +} k_rwlock_t; + +/** + * @brief Create a read-write lock. + * + * @attention a read-write lock can be hold by multi-readers, that means simultaneously reading is allowed; + * but a read-write lock can only be hold by one writes, that means simultaneously writting or read while writting is not allowed. + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_rwlock_create(k_rwlock_t *rwlock); + +/** + * @brief Destroy a read-write lock. + * + * @attention + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_rwlock_destroy(k_rwlock_t *rwlock); + +/** + * @brief Pend on the read-lock of a read-write lock. + * + * @attention if one reader already hold the read-lock, other reader can hold the read-lock simultaneously. + * and no writers can hold the write-lock. + * + * @param[in] rwlock the read-write lock. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_READERS_TO_MANY too many reader are holding the read-lock + */ +__API__ k_err_t tos_rwlock_rpend_timed(k_rwlock_t *rwlock, k_tick_t timeout); + +/** + * @brief Pend on the read-lock of a read-write lock. + * + * @attention if one reader already hold the read-lock, other reader can hold the read-lock simultaneously. + * and no writers can hold the write-lock. + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_READERS_TO_MANY too many reader are holding the read-lock + */ +__API__ k_err_t tos_rwlock_rpend(k_rwlock_t *rwlock); + +/** + * @brief Try pend on the read-lock of a read-write lock. + * + * @attention Try means just take a look, if can obtain the read-lock, then we obtain it; otherwise, just return with no-waiting. + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_IS_WRITTING the read-write lock is hold by a writter(is writting). + */ +__API__ k_err_t tos_rwlock_rpend_try(k_rwlock_t *rwlock); + +/** + * @brief Pend on the write-lock of a read-write lock. + * + * @attention if one writer already hold the write-lock, other writer CANNOT hold the write-lock any more. + * and no readers can hold the read-lock. + * + * @param[in] rwlock the read-write lock. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_WAITING_WRITERS_TO_MANY too many writers are waiting for the write-lock + */ +__API__ k_err_t tos_rwlock_wpend_timed(k_rwlock_t *rwlock, k_tick_t timeout); + +/** + * @brief Pend on the write-lock of a read-write lock. + * + * @attention if one writer already hold the write-lock, other writer CANNOT hold the write-lock any more. + * and no readers can hold the read-lock. + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_WAITING_WRITERS_TO_MANY too many writers are waiting for the write-lock + */ +__API__ k_err_t tos_rwlock_wpend(k_rwlock_t *rwlock); + +/** + * @brief Pend on the write-lock of a read-write lock. + * + * @attention Try means just take a look, if can obtain the write-lock, then we obtain it; otherwise, just return with no-waiting. + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_IS_READING the read-write lock is hold by other reader[s](is reading). + * @retval #K_ERR_RWLOCK_IS_WRITTING the read-write lock is hold by another writter(is writting). + */ +__API__ k_err_t tos_rwlock_wpend_try(k_rwlock_t *rwlock); + +/** + * @brief Post the read-lock of a read-write lock. + * + * @attention + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_NOT_READING the read-lock is not held by reader[s]. + */ +__API__ k_err_t tos_rwlock_rpost(k_rwlock_t *rwlock); + +/** + * @brief Post the write-lock of a read-write lock. + * + * @attention + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_NOT_WRITTING the write-lock is not held by a writter. + */ +__API__ k_err_t tos_rwlock_wpost(k_rwlock_t *rwlock); + +/** + * @brief Post the read&write-lock of a read-write lock. + * + * @attention + * + * @param[in] rwlock the read-write lock. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + * @retval #K_ERR_RWLOCK_NOT_TAKEN the read-write lock is neither held by reader[s] nor held by a writter. + */ +__API__ k_err_t tos_rwlock_post(k_rwlock_t *rwlock); + +#endif + +__CDECLS_END + +#endif /* _TOS_RWLOCK_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_sched.h b/TencentOS_Tiny/kernel/core/include/tos_sched.h new file mode 100644 index 0000000..090c569 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_sched.h @@ -0,0 +1,56 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_SCHED_H_ +#define _TOS_SCHED_H_ + +__CDECLS_BEGIN + +#define K_PRIO_TBL_SIZE ((TOS_CFG_TASK_PRIO_MAX + 31) / 32) +#define K_PRIO_TBL_SLOT_SIZE (8 * sizeof(uint32_t)) + +#define K_PRIO_NDX(prio) ((prio) >> 5u) /* prio / 32u */ +#define K_PRIO_BIT(prio) ((uint32_t)1u << (K_PRIO_TBL_SLOT_SIZE - 1u - ((prio) & (K_PRIO_TBL_SLOT_SIZE - 1u)))) + +typedef struct readyqueue_st { + k_list_t task_list_head[TOS_CFG_TASK_PRIO_MAX]; + uint32_t prio_mask[K_PRIO_TBL_SIZE]; + k_prio_t highest_prio; +} readyqueue_t; + +__KNL__ void readyqueue_init(void); + +__KNL__ int readyqueue_is_prio_onlyone(k_prio_t prio); + +__KNL__ k_task_t *readyqueue_first_task_get(k_prio_t prio); + +__KNL__ k_task_t *readyqueue_highest_ready_task_get(void); + +__KNL__ void readyqueue_add_head(k_task_t *task); + +__KNL__ void readyqueue_add_tail(k_task_t *task); + +__KNL__ void readyqueue_add(k_task_t *task); + +__KNL__ void readyqueue_remove(k_task_t *task); + +__KNL__ void readyqueue_move_head_to_tail(k_prio_t prio); + +__CDECLS_END + +#endif /* _TOS_SCHED_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_sem.h b/TencentOS_Tiny/kernel/core/include/tos_sem.h new file mode 100644 index 0000000..feefb57 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_sem.h @@ -0,0 +1,155 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_SEM_H_ +#define _TOS_SEM_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_SEM_EN > 0u + +typedef struct k_sem_st { + knl_obj_t knl_obj; + + pend_obj_t pend_obj; + k_sem_cnt_t count; + k_sem_cnt_t count_max; +} k_sem_t; + +/** + * @brief Create a semaphore with a limitation of maximum count. + * create a semaphore with a limitation of maximum count. + * + * @attention None + * + * @param[in] sem pointer to the handler of the semaphore. + * @param[in] init_count initial count of the semaphore. + * @param[in] max_count maximum count of the semaphore. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_create_max(k_sem_t *sem, k_sem_cnt_t init_count, k_sem_cnt_t max_count); + +/** + * @brief Create a semaphore. + * create a semaphore. + * + * @attention None + * + * @param[in] sem pointer to the handler of the semaphore. + * @param[in] init_count initial count of the semaphore. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_create(k_sem_t *sem, k_sem_cnt_t init_count); + +/** + * @brief Create a dynamic semaphore with a limitation of maximum count. + * create a dynamic semaphore with a limitation of maximum count. + * + * @attention None + * + * @param[in] sem pointer to the pointer of the semaphore. + * @param[in] init_count initial count of the semaphore. + * @param[in] max_count maximum count of the semaphore. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_create_max_dyn(k_sem_t **sem, k_sem_cnt_t init_count, k_sem_cnt_t max_count); + +/** + * @brief Create a dynamic semaphore. + * create a dynamic semaphore. + * + * @attention None + * + * @param[in] sem pointer to the pointer of the semaphore. + * @param[in] init_count initial count of the semaphore. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_create_dyn(k_sem_t **sem, k_sem_cnt_t init_count); + +/** + * @brief Destroy a semaphore. + * destroy a semaphore. + * + * @attention None + * + * @param[in] semaphore pointer to the handler of the semaphore. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_destroy(k_sem_t *sem); + +/** + * @brief Pend a semaphore. + * pend a semaphore. + * + * @attention None + * + * @param[in] sem pointer to the handler of the semaphore. + * @param[in] timeout how much time(in k_tick_t) we would like to wait. + * + * @return errcode + * @retval #K_ERR_PEND_NOWAIT we get nothing, and we don't wanna wait. + * @retval #K_ERR_PEND_SCHED_LOCKED we can wait, but scheduler is locked. + * @retval #K_ERR_PEND_TIMEOUT the time we wait is up, we get nothing. + * @retval #K_ERR_PEND_DESTROY the semaphore we are pending is destroyed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_pend(k_sem_t *sem, k_tick_t timeout); + +/** + * @brief Post a semaphore. + * post a semaphore and wakeup one pending task. + * + * @attention when tos_sem_post return successfully, only one task who are waitting for the semaphore will be woken up. + * + * @param[in] sem pointer to the handler of the semaphore. + * + * @return errcode + * @retval #K_ERR_SEM_OVERFLOW we are nesting post a semaphore too much. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_post(k_sem_t *sem); + +/** + * @brief Post a semaphore. + * post a semaphore and wakeup all the pending task. + * + * @attention when tos_sem_post_all return successfully, all of the tasks who are waitting for the semaphore will be woken up. + * + * @param[in] sem pointer to the handler of the semaphore. + * + * @return errcode + * @retval #K_ERR_SEM_OVERFLOW we are nesting post a semaphore too much. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sem_post_all(k_sem_t *sem); + +#endif + +__CDECLS_END + +#endif /* _TOS_SEM_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_slist.h b/TencentOS_Tiny/kernel/core/include/tos_slist.h new file mode 100644 index 0000000..b47f6db --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_slist.h @@ -0,0 +1,189 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_SLIST_H_ +#define _TOS_SLIST_H_ + +__CDECLS_BEGIN + +typedef struct k_slist_node_st { + struct k_slist_node_st *next; +} k_slist_t; + +#define TOS_SLIST_NODE(dummy) \ + { K_NULL } + +#define TOS_SLIST_DEFINE(slist) \ + k_slist_t slist = { K_NULL } + +#define TOS_SLIST_ENTRY(node, type, field) \ + TOS_CONTAINER_OF_FIELD(node, type, field) + +#define TOS_SLIST_FIRST_ENTRY(slist, type, field) \ + TOS_SLIST_ENTRY((slist)->next, type, field) + +#define TOS_SLIST_FIRST_ENTRY_OR_NULL(slist, type, field) \ + (tos_slist_empty(slist) ? K_NULL : TOS_SLIST_FIRST_ENTRY(slist, type, field)) + +#define TOS_SLIST_FOR_EACH(curr, slist) \ + for (curr = (slist)->next; curr; curr = curr->next) + +#define TOS_SLIST_FOR_EACH_SAFE(curr, next, slist) \ + for (curr = (slist)->next, next = curr->next; curr; \ + curr = next, next = curr->next) + +#define TOS_SLIST_FOR_EACH_ENTRY(entry, type, field, slist) \ + for (entry = TOS_SLIST_ENTRY((slist)->next, type, field); \ + &entry->field; \ + entry = TOS_SLIST_ENTRY(entry->field.next, type, field)) + +#define TOS_SLIST_FOR_EACH_ENTRY_SAFE(entry, tmp, type, field, slist) \ + for (entry = TOS_SLIST_ENTRY((slist)->next, type, field), \ + tmp = TOS_SLIST_ENTRY(entry->field.next, type, field); \ + &entry->field; \ + entry = tmp, tmp = TOS_SLIST_ENTRY(entry->field.next, type, field)) + +__API__ __STATIC_INLINE__ void tos_slist_init(k_slist_t *slist) +{ + slist->next = K_NULL; +} + +__API__ __STATIC_INLINE__ k_slist_t *tos_slist_head(k_slist_t *slist) +{ + return slist->next; +} + +__API__ __STATIC_INLINE__ k_slist_t *tos_slist_tail(k_slist_t *slist) +{ + if (!slist->next) { + return K_NULL; + } + + while (slist->next) { + slist = slist->next; + } + + return slist; +} + +__API__ __STATIC_INLINE__ void tos_slist_add_head(k_slist_t *node, k_slist_t *slist) +{ + node->next = slist->next; + slist->next = node; +} + +__API__ __STATIC_INLINE__ void tos_slist_add_tail(k_slist_t *node, k_slist_t *slist) +{ + node->next = K_NULL; + + while (slist->next) { + slist = slist->next; + } + + tos_slist_add_head(node, slist); +} + +__API__ __STATIC_INLINE__ void tos_slist_insert(k_slist_t *next_node, k_slist_t *new_node, k_slist_t *slist) +{ + if (!next_node) { + tos_slist_add_tail(new_node, slist); + return; + } + + while (slist->next) { + if (slist->next == next_node) { + slist->next = new_node; + new_node->next = next_node; + } + + slist = slist->next; + } +} + +__API__ __STATIC_INLINE__ k_slist_t *tos_slist_del_head(k_slist_t *slist) +{ + k_slist_t *head; + + if (!slist->next) { + return K_NULL; + } + + head = slist->next; + slist->next = head->next; + head->next = K_NULL; + + return head; +} + +__API__ __STATIC_INLINE__ k_slist_t *tos_slist_del_tail(k_slist_t *slist) +{ + while (slist->next) { + if (!slist->next->next) { + return tos_slist_del_head(slist); + } + + slist = slist->next; + } + + return K_NULL; +} + +__API__ __STATIC_INLINE__ void tos_slist_del(k_slist_t *node, k_slist_t *slist) +{ + while (slist->next) { + if (slist->next == node) { + slist->next = node->next; + break; + } + + slist = slist->next; + } +} + +__API__ __STATIC_INLINE__ int tos_slist_length(k_slist_t *slist) +{ + int len = 0; + k_slist_t *iter; + + TOS_SLIST_FOR_EACH(iter, slist) { + ++len; + } + + return len; +} + +__API__ __STATIC_INLINE__ int tos_slist_contains(k_slist_t *node, k_slist_t *slist) +{ + while (slist->next) { + if (slist->next == node) { + return K_TRUE; + } + + slist = slist->next; + } + + return K_FALSE; +} +__API__ __STATIC_INLINE__ int tos_slist_empty(k_slist_t *slist) +{ + return !slist->next; +} + +__CDECLS_END + +#endif /* _TOS_SLIST_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_stopwatch.h b/TencentOS_Tiny/kernel/core/include/tos_stopwatch.h new file mode 100644 index 0000000..ec762a2 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_stopwatch.h @@ -0,0 +1,139 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_STOPWATCH_H_ +#define _TOS_STOPWATCH_H_ + +__CDECLS_BEGIN + +typedef struct k_stopwatch_st { + knl_obj_t knl_obj; + + k_tick_t until; +} k_stopwatch_t; + +/** + * @brief Create a stopwatch. + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_stopwatch_create(k_stopwatch_t *stopwatch); + +/** + * @brief Destroy a stopwatch. + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_stopwatch_destroy(k_stopwatch_t *stopwatch); + +/** + * @brief Count down for a certain tick. + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * @param[in] tick tick to count down. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_stopwatch_countdown(k_stopwatch_t *stopwatch, k_tick_t tick); + +/** + * @brief Count down for a certain time(in millisecond). + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * @param[in] millisec time(in millisecond) to count down. + * + * @return errcode + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_stopwatch_countdown_ms(k_stopwatch_t *stopwatch, k_time_t millisec); + +/** + * @brief Delay for a certain tick. + * + * @attention the stopwatch delay is a "busy" delay without give up of CPU(compared to tos_task_delay) + * + * @param[in] tick tick to delay. + * + * @return None + */ +__API__ void tos_stopwatch_delay(k_tick_t tick); + +/** + * @brief Delay for a certain time(in millisecond). + * + * @attention the stopwatch delay is a "busy" delay without give up of CPU(compared to tos_task_delay) + * + * @param[in] millisec time(in millisecond) to delay. + * + * @return None + */ +__API__ void tos_stopwatch_delay_ms(k_time_t millisec); + +/** + * @brief How much time remain of the stopwatch(in tick). + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * + * @return ticks remain + */ +__API__ k_tick_t tos_stopwatch_remain(k_stopwatch_t *stopwatch); + +/** + * @brief How much time remain of the stopwatch(in millisecond). + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * + * @return milliseconds remain + */ +__API__ k_time_t tos_stopwatch_remain_ms(k_stopwatch_t *stopwatch); + +/** + * @brief Whether the stopwatch is expired. + * + * @attention + * + * @param[in] stopwatch the stopwatch. + * + * @return whether the stopwatch is expired + * @retval #K_TRUE the stopwatch is expired. + * @retval #K_FALSE the stopwatch is no expired. + */ +__API__ int tos_stopwatch_is_expired(k_stopwatch_t *stopwatch); + +__CDECLS_END + +#endif /* _TOS_STOPWATCH_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_sys.h b/TencentOS_Tiny/kernel/core/include/tos_sys.h new file mode 100644 index 0000000..6dbbe3a --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_sys.h @@ -0,0 +1,227 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_SYS_H_ +#define _TOS_SYS_H_ + +__CDECLS_BEGIN + +#define K_NESTING_LIMIT_IRQ (k_nesting_t)250u +#define K_NESTING_LIMIT_SCHED_LOCK (k_nesting_t)250u + +typedef enum knl_state_en { + KNL_STATE_STOPPED, + KNL_STATE_RUNNING, +} knl_state_t; + +// some kind of magic number, mainly for identifing whether the object is initialized, or whether user pass the correct parameter. +typedef enum knl_obj_type_en { + KNL_OBJ_TYPE_NONE = 0x0000, + + KNL_OBJ_TYPE_BINARY_HEAP = 0xDAD0, + KNL_OBJ_TYPE_BITMAP = 0xDAD1, + KNL_OBJ_TYPE_CHAR_FIFO = 0xDAD2, + KNL_OBJ_TYPE_MMBLK_POOL = 0xDAD3, + KNL_OBJ_TYPE_MSG_QUEUE = 0xDAD4, + KNL_OBJ_TYPE_PRIORITY_QUEUE = 0xDAD5, + KNL_OBJ_TYPE_RING_QUEUE = 0xDAD6, + KNL_OBJ_TYPE_STOPWATCH = 0xDAD7, + KNL_OBJ_TYPE_TASK = 0xDAD8, + KNL_OBJ_TYPE_TIMER = 0xDAD9, + + // ipc object + KNL_OBJ_TYPE_BARRIER = 0x0BEE, + KNL_OBJ_TYPE_COMPLETION = 0x1BEE, + KNL_OBJ_TYPE_COUNTDOWNLATCH = 0x2BEE, + KNL_OBJ_TYPE_EVENT = 0x3BEE, + KNL_OBJ_TYPE_MAIL_QUEUE = 0x4BEE, + KNL_OBJ_TYPE_MESSAGE_QUEUE = 0x5BEE, + KNL_OBJ_TYPE_MUTEX = 0x6BEE, + KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE = 0x7BEE, + KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE = 0x8BEE, + KNL_OBJ_TYPE_RWLOCK = 0x9BEE, + KNL_OBJ_TYPE_SEMAPHORE = 0xABEE, +} knl_obj_type_t; + +typedef enum knl_obj_alloc_type_en { + KNL_OBJ_ALLOC_TYPE_NONE, + KNL_OBJ_ALLOC_TYPE_STATIC, + KNL_OBJ_ALLOC_TYPE_DYNAMIC, +} knl_obj_alloc_type_t; + +typedef struct knl_object_st { + knl_obj_alloc_type_t alloc_type; /* is dynamic allocated(using tos_mmheap) or static memory? */ +#if TOS_CFG_OBJECT_VERIFY_EN > 0u + knl_obj_type_t type; +#endif +} knl_obj_t; + +/** + * @brief Initialize the kernel. + * initialize the tos tiny kernel. + * + * @attention None + * + * @param None + * + * @return errcode + * @retval Non-#K_ERR_NONE return failed. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_knl_init(void); + +/** + * @brief Start the kernel. + * get the kernel start to run, which means start the multitask scheduling. + * + * @attention None + * + * @param None + * + * @return errcode + * @retval #K_ERR_KNL_RUNNING the kernel is already running. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_knl_start(void); + +/** + * @brief Get the kernel state. + * whether the kernel is running. + * + * @attention None + * + * @param None + * + * @return whether the kernel is running. + * @retval Non-0 the kernel is running. + * @retval 0 the kernel is not running. + */ +__API__ int tos_knl_is_running(void); + +/** + * @brief Kernel enter the interrupt. + * this function should be called in the entrance of a interrupt handler. + * + * @attention None + * + * @param None + * + * @return None + */ +__API__ void tos_knl_irq_enter(void); + +/** + * @brief Kernel exit the interrupt. + * this function should be called in the exit of a interrupt handler. + * + * @attention None + * + * @param None + * + * @return None + */ +__API__ void tos_knl_irq_leave(void); + +/** + * @brief Lock the scheduler. + * prevent the kernel from performing task schedule. + * + * @attention None + * + * @param None + * + * @return errcode + * @retval K_ERR_KNL_NOT_RUNNING the kernel is not running. + * @retval K_ERR_LOCK_NESTING_OVERFLOW the schedule lock nesting is overflow. + * @retval K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_knl_sched_lock(void); + +/** + * @brief Unlock the scheduler. + * re-enable the task schedule. + * + * @attention None + * + * @param None + * + * @return errcode + * @retval K_ERR_KNL_NOT_RUNNING the kernel is not running. + * @retval K_ERR_SCHED_NOT_LOCKED the scheduler is not locked. + * @retval K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_knl_sched_unlock(void); + +#if TOS_CFG_TICKLESS_EN > 0u +__KNL__ k_tick_t knl_next_expires_get(void); +#endif + +__KNL__ void knl_sched(void); +__KNL__ int knl_is_sched_locked(void); +__KNL__ int knl_is_inirq(void); +__KNL__ int knl_is_idle(k_task_t *task); +__KNL__ int knl_is_self(k_task_t *task); +__KNL__ k_err_t knl_idle_init(void); + +#if TOS_CFG_OBJECT_VERIFY_EN > 0u + +__KNL__ __STATIC_INLINE__ int knl_object_verify(knl_obj_t *knl_obj, knl_obj_type_t type) +{ + return knl_obj->type == type; +} + +__KNL__ __STATIC_INLINE__ void knl_object_init(knl_obj_t *knl_obj, knl_obj_type_t type) +{ + knl_obj->type = type; +} + +__KNL__ __STATIC_INLINE__ void knl_object_deinit(knl_obj_t *knl_obj) +{ + knl_obj->type = KNL_OBJ_TYPE_NONE; +} + +#endif + +__KNL__ __STATIC_INLINE__ void knl_object_alloc_reset(knl_obj_t *knl_obj) +{ + knl_obj->alloc_type = KNL_OBJ_ALLOC_TYPE_NONE; +} + +__KNL__ __STATIC_INLINE__ void knl_object_alloc_set_dynamic(knl_obj_t *knl_obj) +{ + knl_obj->alloc_type = KNL_OBJ_ALLOC_TYPE_DYNAMIC; +} + +__KNL__ __STATIC_INLINE__ void knl_object_alloc_set_static(knl_obj_t *knl_obj) +{ + knl_obj->alloc_type = KNL_OBJ_ALLOC_TYPE_STATIC; +} + +__KNL__ __STATIC_INLINE__ int knl_object_alloc_is_dynamic(knl_obj_t *knl_obj) +{ + return knl_obj->alloc_type == KNL_OBJ_ALLOC_TYPE_DYNAMIC; +} + +__KNL__ __STATIC_INLINE__ int knl_object_alloc_is_static(knl_obj_t *knl_obj) +{ + return knl_obj->alloc_type == KNL_OBJ_ALLOC_TYPE_STATIC; +} + +__CDECLS_END + +#endif /* _TOS_SYS_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_task.h b/TencentOS_Tiny/kernel/core/include/tos_task.h new file mode 100644 index 0000000..db7b48e --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_task.h @@ -0,0 +1,445 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_TASK_H_ +#define _TOS_TASK_H_ + +__CDECLS_BEGIN + +#define K_TASK_NAME_LEN_MAX (15u) +#define K_TASK_NAME_MAX (K_TASK_NAME_LEN_MAX + 1) +#define K_TASK_STK_SIZE_MIN (sizeof(cpu_context_t)) + +// task state is just a flag, indicating which manager list we are in. + +// ready to schedule +// a task's pend_list is in readyqueue +#define K_TASK_STATE_READY (k_task_state_t)0x0000 + +// delayed, or pend for a timeout +// a task's tick_list is in k_tick_list +#define K_TASK_STATE_SLEEP (k_task_state_t)0x0001 + +// pend for something +// a task's pend_list is in some pend object's list +#define K_TASK_STATE_PEND (k_task_state_t)0x0002 + +// suspended +#define K_TASK_STATE_SUSPENDED (k_task_state_t)0x0004 + +// deleted +#define K_TASK_STATE_DELETED (k_task_state_t)0x0008 + +// actually we don't really need those TASK_STATE below, if you understand the task state deeply, the code can be much more elegant. + +// we are pending, also we are waitting for a timeout(eg. tos_sem_pend with a valid timeout, not TOS_TIME_FOREVER) +// both a task's tick_list and pend_list is not empty +#define K_TASK_STATE_PENDTIMEOUT (k_task_state_t)(K_TASK_STATE_PEND | K_TASK_STATE_SLEEP) + +// suspended when sleeping +#define K_TASK_STATE_SLEEP_SUSPENDED (k_task_state_t)(K_TASK_STATE_SLEEP | K_TASK_STATE_SUSPENDED) + +// suspended when pending +#define K_TASK_STATE_PEND_SUSPENDED (k_task_state_t)(K_TASK_STATE_PEND | K_TASK_STATE_SUSPENDED) + +// suspended when pendtimeout +#define K_TASK_STATE_PENDTIMEOUT_SUSPENDED (k_task_state_t)(K_TASK_STATE_PENDTIMEOUT | K_TASK_STATE_SUSPENDED) + + +// if you configure TOS_CFG_TASK_PRIO_MAX as 10, means the priority for kernel is (0 ... 9] +// the priority 9(TOS_CFG_TASK_PRIO_MAX - 1) is only for idle, so avaliable priority for you is (0 ... 8] +#define K_TASK_PRIO_IDLE (k_prio_t)(TOS_CFG_TASK_PRIO_MAX - (k_prio_t)1u) +#define K_TASK_PRIO_INVALID (k_prio_t)(TOS_CFG_TASK_PRIO_MAX) + +typedef void (*k_task_entry_t)(void *arg); + +typedef void (*k_task_walker_t)(k_task_t *task); + +/** + * task control block + */ +struct k_task_st { + k_stack_t *sp; /**< task stack pointer. This lady always comes first, we count on her in port_s.S for context switch. */ + + knl_obj_t knl_obj; /**< just for verification, test whether current object is really a task. */ + + char name[K_TASK_NAME_MAX]; /**< task name */ + k_task_entry_t entry; /**< task entry */ + void *arg; /**< argument for task entry */ + k_task_state_t state; /**< just state */ + k_prio_t prio; /**< just priority */ + + k_stack_t *stk_base; /**< task stack base address */ + size_t stk_size; /**< stack size of the task */ + +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + k_list_t dead_list; /**< when a dynamic allocated task destroyed, we hook the task's dead_list to the k_dead_task_list */ +#endif + + k_list_t stat_list; /**< list for hooking us to the k_stat_list */ + + k_tick_t tick_expires; /**< if we are in k_tick_list, how much time will we wait for? */ + + k_list_t tick_list; /**< list for hooking us to the k_tick_list */ + k_list_t pend_list; /**< when we are ready, our pend_list is in readyqueue; when pend, in a certain pend object's list. */ + +#if TOS_CFG_MUTEX_EN > 0u + k_list_t mutex_own_list; /**< the list hold all the mutex we own. + When we die(tos_task_destroy), we have an obligation to wakeup all the task pending for those mutexs we own; + if not, those pending tasks may never get a chance to wakeup. */ + k_prio_t prio_pending; /*< when tos_task_prio_change called, we may be just the owner of a mutex. + to avoid PRIORITY INVERSION, must make sure our priority is higher than any one who is pending for + the mutex we hold. So, if the prio_new of tos_task_prio_change is not appropriate + (may against the principle of PRIORITY INVERSION), we just mark the prio_new here, do the real priority + change in the right time(mutex_old_owner_release) later. */ +#endif + + pend_obj_t *pending_obj; /**< if we are pending, which pend object's list we are in? */ + pend_state_t pend_state; /**< why we wakeup from a pend */ + +#if TOS_CFG_ROUND_ROBIN_EN > 0u + k_timeslice_t timeslice_reload; /**< if current time slice is used up, use time_slice_reload to reload our time slice */ + k_timeslice_t timeslice; /**< how much time slice left for us? */ +#endif + +#if (TOS_CFG_MESSAGE_QUEUE_EN > 0u) || (TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN > 0u) + void *msg; /**< if we pend a message queue successfully, our msg will be set by the message queue poster */ +#endif + +#if (TOS_CFG_MAIL_QUEUE_EN > 0u) || (TOS_CFG_PRIORITY_MAIL_QUEUE_EN > 0u) + void *mail; /**< if we pend a mail queue successfully, our mail and mail_size will be set by the message queue poster */ + size_t mail_size; +#endif + +#if TOS_CFG_EVENT_EN > 0u + k_opt_t opt_event_pend; /**< if we are pending an event, what's the option for the pending(TOS_OPT_EVENT_PEND_*)? */ + k_event_flag_t flag_expect; /**< if we are pending an event, what event flag are we pending for ? */ + k_event_flag_t *flag_match; /**< if we pend an event successfully, flag_match will be set by the event poster, and will be returned + by tos_event_pend to the caller */ +#endif +}; + +/** + * @brief Create a task. + * create a task. + * + * @attention None + * + * @param[in] task pointer to the handler of the task. + * @param[in] name name of the task. + * @param[in] entry running entry of the task. + * @param[in] arg argument for the entry of the task. + * @param[in] prio priority of the task. + * @param[in] stk_base stack base address of the task. + * @param[in] stk_size stack size of the task. + * @param[in] timeslice time slice of the task. + * + * @return errcode + * @retval #K_ERR_TASK_STK_SIZE_INVALID stack size is invalid. + * @retval #K_ERR_TASK_PRIO_INVALID priority is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_create(k_task_t *task, + char *name, + k_task_entry_t entry, + void *arg, + k_prio_t prio, + k_stack_t *stk_base, + size_t stk_size, + k_timeslice_t timeslice); + +/** + * @brief Destroy a task. + * delete a task. + * + * @attention None + * + * @param[in] task pointer to the handler of the task to be deleted. + * + * @return errcode + * @retval #K_ERR_TASK_DESTROY_IDLE attempt to destroy idle task. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_destroy(k_task_t *task); + +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + +/** + * @brief Create a task with a dynamic allocated task handler and stack. + * create a task with a dynamic allocated task handler and stack. + * + * @param[out] task dynamic allocated task handler. + * @param[in] name name of the task. + * @param[in] entry running entry of the task. + * @param[in] arg argument for the entry of the task. + * @param[in] prio priority of the task. + * @param[in] stk_size stack size of the task. + * @param[in] timeslice time slice of the task. + * + * @return errcode + * @retval #K_ERR_TASK_STK_SIZE_INVALID stack size is invalid. + * @retval #K_ERR_TASK_PRIO_INVALID priority is invalid. + * @retval #K_ERR_TASK_OUT_OF_MEMORY out of memory(insufficient heap memory). + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_create_dyn(k_task_t **task, + char *name, + k_task_entry_t entry, + void *arg, + k_prio_t prio, + size_t stk_size, + k_timeslice_t timeslice); + +#endif + +/** + * @brief Delay current task for ticks. + * Delay for a specified amount of ticks. + * + * @attention None + * + * @param[in] delay amount of ticks to delay. + * + * @return errcode + * @retval #K_ERR_DELAY_ZERO delay is zero. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_delay(k_tick_t delay); + +/** + * @brief Resume task from delay. + * Resume a delayed task from delay. + * + * @attention None + * + * @param[in] task the pointer to the handler of the task. + * + * @return errcode + * @retval #K_ERR_TASK_NOT_DELAY task is not delayed. + * @retval #K_ERR_TASK_SUSPENDED task is suspended. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_delay_abort(k_task_t *task); + +/** + * @brief Suspend a task. + * Bring a task to sleep. + * + * @attention None + * + * @param[in] task pointer to the handler of the task to be resume. + * + * @return errcode + * @retval #K_ERR_TASK_SUSPEND_IDLE attempt to suspend idle task. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_suspend(k_task_t *task); + +/** + * @brief Resume a task. + * Bring a task to run. + * + * @attention None + * + * @param[in] task pointer to the handler of the task to be resume. + * + * @return errcode + * @retval #K_ERR_TASK_RESUME_SELF attempt to resume self-task. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_resume(k_task_t *task); + +/** + * @brief Change task priority. + * Change a priority of the task. + * + * @attention None + * + * @param[in] task pointer to the handler of the task to be resume. + * @param[in] prio_new new priority. + * + * @return errcode + * @retval #K_ERR_TASK_PRIO_INVALID new priority is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_task_prio_change(k_task_t *task, k_prio_t prio_new); + +/** + * @brief Quit schedule this time. + * Quit the cpu this time. + * + * @attention None + * + * @param None + * + * @return None + */ +__API__ void tos_task_yield(void); + +/** + * @brief Get current running task. + * Get current running task. + * + * @attention if kernel is not running, you'll get K_NULL + * + * @param None + * + * @return current running task handler + */ +__API__ k_task_t *tos_task_curr_task_get(void); + + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + +/** + * @brief Get the maximum stack draught depth of a task. + * + * @attention None + * + * @param[in] task pointer to the handler of the task. + * @param[out] depth task stack draught depth. + * + * @return errcode + * @retval #K_ERR_NONE get depth successfully. + * @retval #K_ERR_TASK_STK_OVERFLOW task stack is overflow. + */ +__API__ k_err_t tos_task_stack_draught_depth(k_task_t *task, int *depth); + +#endif + +/** + * @brief Walk through all the tasks in the statistic list. + * + * @attention None + * + * @param[in] walker a function involved when meeting each tasks in the list. + * + * @return None + */ +__API__ void tos_task_walkthru(k_task_walker_t walker); + +/** + * @brief A debug API for display all tasks information. + * + * @attention None + * + * @param None + * + * @return None + */ +__DEBUG__ void tos_task_info_display(void); + +__KNL__ void task_free_all(void); + +__KNL__ __STATIC_INLINE__ int task_state_is_ready(k_task_t *task) +{ + return task->state == K_TASK_STATE_READY; +} + +__KNL__ __STATIC_INLINE__ int task_state_is_sleeping(k_task_t *task) +{ + return task->state & K_TASK_STATE_SLEEP; +} + +__KNL__ __STATIC_INLINE__ int task_state_is_pending(k_task_t *task) +{ + return task->state & K_TASK_STATE_PEND; +} + +__KNL__ __STATIC_INLINE__ int task_state_is_suspended(k_task_t *task) +{ + return task->state & K_TASK_STATE_SUSPENDED; +} + +__KNL__ __STATIC_INLINE__ void task_state_reset_pending(k_task_t *task) +{ + task->state &= ~K_TASK_STATE_PEND; +} + +__KNL__ __STATIC_INLINE__ void task_state_reset_sleeping(k_task_t *task) +{ + task->state &= ~K_TASK_STATE_SLEEP; +} + +__KNL__ __STATIC_INLINE__ void task_state_reset_suspended(k_task_t *task) +{ + task->state &= ~K_TASK_STATE_SUSPENDED; +} + +__KNL__ __STATIC_INLINE__ void task_state_set_suspended(k_task_t *task) +{ + task->state |= K_TASK_STATE_SUSPENDED; +} + +__KNL__ __STATIC_INLINE__ void task_state_set_pend(k_task_t *task) +{ + task->state |= K_TASK_STATE_PEND; +} + +__KNL__ __STATIC_INLINE__ void task_state_set_ready(k_task_t *task) +{ + task->state = K_TASK_STATE_READY; +} + +__KNL__ __STATIC_INLINE__ void task_state_set_deleted(k_task_t *task) +{ + task->state = K_TASK_STATE_DELETED; +} + +__KNL__ __STATIC_INLINE__ void task_state_set_sleeping(k_task_t *task) +{ + task->state |= K_TASK_STATE_SLEEP; +} + +__DEBUG__ __STATIC_INLINE__ void task_default_walker(k_task_t *task) +{ + char *state_str = "ABNORMAL"; + + state_str = state_str; + tos_kprintln("tsk name: %s", task->name); + + if (tos_task_curr_task_get() == task) { + state_str = "RUNNING"; + } else if (task->state == K_TASK_STATE_PENDTIMEOUT_SUSPENDED) { + state_str = "PENDTIMEOUT_SUSPENDED"; + } else if (task->state == K_TASK_STATE_PEND_SUSPENDED) { + state_str = "PEND_SUSPENDED"; + } else if (task->state == K_TASK_STATE_SLEEP_SUSPENDED) { + state_str = "SLEEP_SUSPENDED"; + } else if (task->state == K_TASK_STATE_PENDTIMEOUT) { + state_str = "PENDTIMEOUT"; + } else if (task->state == K_TASK_STATE_SUSPENDED) { + state_str = "SUSPENDED"; + } else if (task->state == K_TASK_STATE_PEND) { + state_str = "PEND"; + } else if (task->state == K_TASK_STATE_SLEEP) { + state_str = "SLEEP"; + } else if (task->state == K_TASK_STATE_READY) { + state_str = "READY"; + } + tos_kprintln("tsk stat: %s", state_str); + + tos_kprintln("stk size: %d", task->stk_size); + tos_kprintln("stk base: 0x%p", task->stk_base); + tos_kprintln("stk top : 0x%p", task->stk_base + task->stk_size); + tos_kprintf("\n"); +} + +__CDECLS_END + +#endif /* _TOS_TASK_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_tick.h b/TencentOS_Tiny/kernel/core/include/tos_tick.h new file mode 100644 index 0000000..a1e3bec --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_tick.h @@ -0,0 +1,48 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_TICK_H_ +#define _TOS_TICK_H_ + +__CDECLS_BEGIN + +/** + * @brief Systick interrupt handler. + * systick interrupt handler. + * + * @attention called from the systick interrupt entrance. + * + * @param None + * + * @return None + */ +__API__ void tos_tick_handler(void); + +__KNL__ void tick_update(k_tick_t tick); + +__KNL__ void tick_list_add(k_task_t *task, k_tick_t timeout); + +__KNL__ void tick_list_remove(k_task_t *task); + +#if TOS_CFG_TICKLESS_EN > 0u +__KNL__ k_tick_t tick_next_expires_get(void); +#endif + +__CDECLS_END + +#endif /* _TOS_TICK_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_time.h b/TencentOS_Tiny/kernel/core/include/tos_time.h new file mode 100644 index 0000000..f0cc2a5 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_time.h @@ -0,0 +1,114 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_TIME_H_ +#define _TOS_TIME_H_ + +__CDECLS_BEGIN + +// if you wanna pend for something forever, use TOS_TIME_FOREVER +#define TOS_TIME_FOREVER (k_tick_t)(-1) +// if you don't wanna wait when you pend nothing, use TOS_TIME_NOWAIT +#define TOS_TIME_NOWAIT (k_tick_t)0u + +// those two are not for you, for kernel only. +#define K_TIME_MILLISEC_PER_SEC 1000u +#define K_TIME_MAX (k_tick_t)(TOS_TIME_FOREVER - 1) + +/** + * @brief Get system tick. + * Get the number of ticks since boot. + * + * @attention None + * + * @param None + * + * @return tick count since boot + */ +__API__ k_tick_t tos_systick_get(void); + +/** + * @brief Set system tick. + * Set the number of ticks. + * + * @attention None + * + * @param tick systick count to set + * + * @return None + */ +__API__ void tos_systick_set(k_tick_t tick); + +/** + * @brief Convert ticks to milliseconds. + * Convert tick to millisecond. + * + * @attention None + * + * @param[in] tick tick to convert. + * + * @return milliseconds equals to the ticks. + */ +__API__ k_time_t tos_tick2millisec(k_tick_t tick); + +/** + * @brief Convert milliseconds to ticks. + * Convert milliseconds to ticks. + * + * @attention None + * + * @param[in] millisec millisecond to convert. + * + * @return ticks equals to the millisecond. + */ +__API__ k_tick_t tos_millisec2tick(k_time_t millisec); + +/** + * @brief Sleep current task. + * Sleep for a specified amount of milliseconds. + * + * @attention None + * + * @param[in] millisec amount of milliseconds to delay. + * + * @return errcode + * @retval #K_ERR_DELAY_ZERO millisec is zero. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sleep_ms(k_time_t millisec); + +/** + * @brief Sleep current task. + * Sleep for a specified amount of time. + * + * @attention None + * + * @param[in] hour amount of hours. + * @param[in] minute amount of minutes. + * @param[in] second amount of seconds. + * @param[in] millisec amount of milliseconds. + * + * @return errcode + * @retval #K_ERR_DELAY_ZERO time is zero. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_sleep_hmsm(k_time_t hour, k_time_t minute, k_time_t second, k_time_t millisec); + +__CDECLS_END + +#endif /* _TOS_TIME_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_timer.h b/TencentOS_Tiny/kernel/core/include/tos_timer.h new file mode 100644 index 0000000..5ad3b3a --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_timer.h @@ -0,0 +1,193 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_TIMER_H_ +#define _TOS_TIMER_H_ + +__CDECLS_BEGIN + +#if TOS_CFG_TIMER_EN > 0u + +// if we just want the timer to run only once, this option should be passed to tos_timer_create. +#define TOS_OPT_TIMER_ONESHOT (k_opt_t)(0x0001u) + +// if we want the timer run periodically, this option should be passed to tos_timer_create. +#define TOS_OPT_TIMER_PERIODIC (k_opt_t)(0x0002u) + +typedef enum timer_change_type_en { + TIMER_CHANGE_TYPE_DELAY, + TIMER_CHANGE_TYPE_PERIOD, +} timer_change_type_t; + +/** + * state for timer + */ +typedef enum timer_state_en { + TIMER_STATE_UNUSED, /**< the timer has been destroyed */ + TIMER_STATE_STOPPED, /**< the timer has been created but not been started, or just be stopped(tos_timer_stop) */ + TIMER_STATE_RUNNING, /**< the timer has been created and been started */ + TIMER_STATE_COMPLETED /**< the timer has finished its expires, it can only happen when the timer's opt is TOS_OPT_TIMER_ONESHOT */ +} timer_state_t; + +// callback function type for a timer +typedef void (*k_timer_callback_t)(void *arg); + +/** + * timer control block + */ +typedef struct k_timer_st { + knl_obj_t knl_obj; /**< just for verification, test whether current object is really a timer */ + + k_timer_callback_t cb; /**< callback when time is up */ + void *cb_arg; /**< argument for callback */ + k_list_t list; /**< list for hooking us to the k_tick_list */ + k_tick_t expires; /**< how much time left until time expires */ + k_tick_t delay; /**< how much time from now to begin the first run of the timer */ + k_tick_t period; /**< if the time expires, how much time after should we begin the next round */ + k_opt_t opt; /**< option for the timer, see TOS_OPT_TIMER_* */ + timer_state_t state; /**< state for the timer, see TIMER_STATE_* */ +} k_timer_t; + +typedef struct timer_control_st { + k_tick_t next_expires; + k_list_t list; +} timer_ctl_t; + +/** + * @brief Create a timer. + * Create a timer. + * + * @attention I dont't think a timer need a name. If you do, help yourself. + * + * @param[in] tmr pointer to the handler of the timer. + * @param[in] delay time interval for a timer to run. + * @param[in] period period for a timer to restart to run. + * @param[in] callback callback function called when the timer expires. + * @param[in] cb_arg argument for the callback. + * @param[in] opt option for the function call. + * + * @return errcode + * @retval #K_ERR_TIMER_INVALID_PERIOD period is invalid. + * @retval #K_ERR_TIMER_INVALID_DELAY delay is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_timer_create(k_timer_t *tmr, k_tick_t delay, k_tick_t period, + k_timer_callback_t callback, void *cb_arg, k_opt_t opt); + +/** + * @brief Delete a timer. + * Delete the timer. + * + * @attention None + * + * @param[in] tmr pointer to the handler of the timer. + * + * @return errcode + * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_timer_destroy(k_timer_t *tmr); + +/** + * @brief Start a timer. + * Start the timer to run. + * + * @attention None + * + * @param[in] tmr pointer to the handler of the timer. + * + * @return errcode + * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. + * @retval #K_ERR_TIMER_INVALID_STATE state of the timer is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_timer_start(k_timer_t *tmr); + +/** + * @brief Stop a timer. + * Stop the timer from running. + * + * @attention None + * + * @param[in] tmr pointer to the handler of the timer. + * + * @return errcode + * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. + * @retval #K_ERR_TIMER_STOPPED the timer is already stoppped. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_timer_stop(k_timer_t *tmr); + +/** + * @brief Change a timer's delay. + * + * @attention None + * + * @param[in] tmr pointer to the handler of the timer. + * @param[in] delay new delay of the timer. + * + * @return errcode + * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. + * @retval #K_ERR_TIMER_RUNNING the timer is running. + * @retval #K_ERR_TIMER_INVALID_DELAY the delay is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_timer_delay_change(k_timer_t *tmr, k_tick_t delay); + +/** + * @brief Change a timer's period. + * + * @attention None + * + * @param[in] tmr pointer to the handler of the timer. + * @param[in] period new period of the timer. + * + * @return errcode + * @retval #K_ERR_TIMER_INACTIVE the timer is not active yet. + * @retval #K_ERR_TIMER_RUNNING the timer is running. + * @retval #K_ERR_TIMER_INVALID_PERIOD the period is invalid. + * @retval #K_ERR_NONE return successfully. + */ +__API__ k_err_t tos_timer_period_change(k_timer_t *tmr, k_tick_t period); + + +#if TOS_CFG_TIMER_AS_PROC > 0u + +/** + * @brief Timer update function. + * When enable timer as a process function not a task, this will be the function entry. + * + * @attention None + * + * @param None + * + * @return None + */ +__KNL__ void timer_update(void); + +#endif + +__KNL__ k_err_t timer_init(void); + +__KNL__ k_tick_t timer_next_expires_get(void); + +#endif + +__CDECLS_END + +#endif /* _TOS_TIMER_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/include/tos_version.h b/TencentOS_Tiny/kernel/core/include/tos_version.h new file mode 100644 index 0000000..2b7d353 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/include/tos_version.h @@ -0,0 +1,32 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_VERSION_H_ +#define _TOS_VERSION_H_ + +// the format of the tencentos-tiny version is major.minor.patch +// major is updated for major changes that will need user code changes +// minor is updated for minor changes/bug fixes that may need user code changes +// patch is updated for patch changes/bug fixes that should not need user code changes + +#define TOS_VERSION_MAJOR 0x02 +#define TOS_VERSION_MINOR 0x04 +#define TOS_VERSION_PATCH 0x05 +#define TOS_VERSION "2.4.5" + +#endif /* _TOS_VERSION_H_ */ + diff --git a/TencentOS_Tiny/kernel/core/tos_barrier.c b/TencentOS_Tiny/kernel/core/tos_barrier.c new file mode 100644 index 0000000..f0933f2 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_barrier.c @@ -0,0 +1,109 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_BARRIER_EN > 0 + +__API__ k_err_t tos_barrier_create(k_barrier_t *barrier, k_barrier_cnt_t count) +{ + TOS_PTR_SANITY_CHECK(barrier); + + if (count == 0u) { + return K_ERR_BARRIER_COUNT_INVALID; + } + + barrier->count = count; + pend_object_init(&barrier->pend_obj); + TOS_OBJ_INIT(barrier, KNL_OBJ_TYPE_BARRIER); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_barrier_destroy(k_barrier_t *barrier) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(barrier); + TOS_OBJ_VERIFY(barrier, KNL_OBJ_TYPE_BARRIER); + + TOS_CPU_INT_DISABLE(); + + pend_wakeup_all(&barrier->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&barrier->pend_obj); + + TOS_OBJ_DEINIT(barrier); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_barrier_pend(k_barrier_t *barrier) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(barrier); + TOS_OBJ_VERIFY(barrier, KNL_OBJ_TYPE_BARRIER); + + TOS_CPU_INT_DISABLE(); + + if (barrier->count == 0u) { + TOS_CPU_INT_ENABLE(); + return K_ERR_BARRIER_OVERFLOW; + } + + if (barrier->count == (k_barrier_cnt_t)1u) { + barrier->count = (k_barrier_cnt_t)0u; + pend_wakeup_all(&barrier->pend_obj, PEND_STATE_POST); + + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + --barrier->count; + pend_task_block(k_curr_task, &barrier->pend_obj, TOS_TIME_FOREVER); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return pend_state2errno(k_curr_task->pend_state); +} + +__API__ k_err_t tos_barrier_reset(k_barrier_t *barrier, k_barrier_cnt_t count) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(barrier); + TOS_OBJ_VERIFY(barrier, KNL_OBJ_TYPE_BARRIER); + + TOS_CPU_INT_DISABLE(); + barrier->count = count; + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +#endif /* TOS_CFG_BARRIER_EN */ diff --git a/TencentOS_Tiny/kernel/core/tos_binary_heap.c b/TencentOS_Tiny/kernel/core/tos_binary_heap.c new file mode 100644 index 0000000..4c4e6a2 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_binary_heap.c @@ -0,0 +1,296 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC_INLINE__ void bin_heap_item_copy_to(k_bin_heap_t *bin_heap, void *item_out, size_t *item_size) +{ + memcpy(item_out, BIN_HEAP_FIRST_ITEM(bin_heap), bin_heap->item_size); + if (item_size) { + *item_size = bin_heap->item_size; + } +} + +__STATIC_INLINE__ void bin_heap_item_copy_from(k_bin_heap_t *bin_heap, void *item_in) +{ + memcpy(BIN_HEAP_LAST_ITEM(bin_heap), item_in, bin_heap->item_size); +} + +__STATIC_INLINE__ void bin_heap_item_increase(k_bin_heap_t *bin_heap) +{ + ++bin_heap->total; +} + +__STATIC_INLINE__ void bin_heap_item_decrease(k_bin_heap_t *bin_heap) +{ + --bin_heap->total; +} + +__STATIC__ void bin_heap_do_percolate_up(k_bin_heap_t *bin_heap, uint16_t hole, void *item_backup) +{ + k_bin_heap_cmp cmp; + size_t item_size; + uint16_t parent, top; + void *hole_item, *parent_item; + + top = 0u; + parent = BIN_HEAP_PARENT(hole); + cmp = bin_heap->cmp; + item_size = bin_heap->item_size; + + hole_item = BIN_HEAP_THE_ITEM(bin_heap, hole); + parent_item = BIN_HEAP_THE_ITEM(bin_heap, parent); + + while (hole > top && cmp(item_backup, parent_item)) { + memcpy(hole_item, parent_item, item_size); + hole = parent; + parent = BIN_HEAP_PARENT(hole); + hole_item = BIN_HEAP_THE_ITEM(bin_heap, hole); + parent_item = BIN_HEAP_THE_ITEM(bin_heap, parent); + } + hole_item = BIN_HEAP_THE_ITEM(bin_heap, hole); + memcpy(hole_item, item_backup, item_size); +} + +__STATIC__ void bin_heap_percolate_up(k_bin_heap_t *bin_heap, void *item_backup) +{ + bin_heap_do_percolate_up(bin_heap, bin_heap->total, item_backup); +} + +__STATIC__ void bin_heap_percolate_down(k_bin_heap_t *bin_heap) +{ + k_bin_heap_cmp cmp; + size_t item_size; + uint16_t lchild, rchild, the_child, hole; + void *hole_item, *rchild_item, *lchild_item, *the_child_item; + + hole = 0u; + rchild = BIN_HEAP_RCHILD(hole); + lchild = BIN_HEAP_LSIBLING(rchild); + the_child = rchild; + cmp = bin_heap->cmp; + item_size = bin_heap->item_size; + + hole_item = BIN_HEAP_THE_ITEM(bin_heap, hole); + rchild_item = BIN_HEAP_THE_ITEM(bin_heap, rchild); + lchild_item = BIN_HEAP_THE_ITEM(bin_heap, lchild); + + while (the_child < bin_heap->total) { + if (cmp(lchild_item, rchild_item)) { + the_child = lchild; + } + the_child_item = BIN_HEAP_THE_ITEM(bin_heap, the_child); + memcpy(hole_item, the_child_item, item_size); + + hole = the_child; + the_child = BIN_HEAP_RCHILD(the_child); + rchild = the_child; + lchild = BIN_HEAP_LSIBLING(rchild); + + hole_item = BIN_HEAP_THE_ITEM(bin_heap, hole); + rchild_item = BIN_HEAP_THE_ITEM(bin_heap, rchild); + lchild_item = BIN_HEAP_THE_ITEM(bin_heap, lchild); + } + + if (the_child == bin_heap->total) { + memcpy(hole_item, lchild_item, item_size); + hole = lchild; + hole_item = BIN_HEAP_THE_ITEM(bin_heap, hole); + } + bin_heap_do_percolate_up(bin_heap, hole, BIN_HEAP_LAST_ITEM(bin_heap)); +} + +__API__ k_err_t tos_bin_heap_create(k_bin_heap_t *bin_heap, void *pool, size_t item_cnt, size_t item_size, k_bin_heap_cmp cmp) +{ + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_PTR_SANITY_CHECK(pool); + TOS_PTR_SANITY_CHECK(cmp); + + bin_heap->total = 0; + bin_heap->cmp = cmp; + bin_heap->item_size = item_size; + bin_heap->item_cnt = item_cnt; + bin_heap->pool = (uint8_t *)pool; + + TOS_OBJ_INIT(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + knl_object_alloc_set_static(&bin_heap->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bin_heap_destroy(k_bin_heap_t *bin_heap) +{ + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_OBJ_VERIFY(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + + if (!knl_object_alloc_is_static(&bin_heap->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + bin_heap->total = 0; + bin_heap->cmp = K_NULL; + bin_heap->item_size = 0; + bin_heap->item_cnt = 0; + bin_heap->pool = K_NULL; + + TOS_OBJ_DEINIT(bin_heap); + knl_object_alloc_reset(&bin_heap->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bin_heap_create_dyn(k_bin_heap_t *bin_heap, size_t item_cnt, size_t item_size, k_bin_heap_cmp cmp) +{ + void *pool; + + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_PTR_SANITY_CHECK(cmp); + + pool = tos_mmheap_alloc(item_cnt * item_size); + if (!pool) { + return K_ERR_OUT_OF_MEMORY; + } + + bin_heap->total = 0; + bin_heap->cmp = cmp; + bin_heap->item_size = item_size; + bin_heap->item_cnt = item_cnt; + bin_heap->pool = (uint8_t *)pool; + + TOS_OBJ_INIT(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + knl_object_alloc_set_dynamic(&bin_heap->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bin_heap_destroy_dyn(k_bin_heap_t *bin_heap) +{ + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_OBJ_VERIFY(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + + if (!knl_object_alloc_is_dynamic(&bin_heap->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + tos_mmheap_free(bin_heap->pool); + + bin_heap->total = 0; + bin_heap->cmp = K_NULL; + bin_heap->item_size = 0; + bin_heap->item_cnt = 0; + bin_heap->pool = K_NULL; + + TOS_OBJ_DEINIT(bin_heap); + knl_object_alloc_reset(&bin_heap->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bin_heap_push(k_bin_heap_t *bin_heap, void *item, size_t item_size) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_PTR_SANITY_CHECK(item); + TOS_OBJ_VERIFY(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + + if (item_size != bin_heap->item_size) { + return K_ERR_BIN_HEAP_ITEM_SIZE_NOT_MATCH; + } + + if (tos_bin_heap_is_full(bin_heap)) { + return K_ERR_BIN_HEAP_FULL; + } + + TOS_CPU_INT_DISABLE(); + + bin_heap_item_copy_from(bin_heap, item); + bin_heap_percolate_up(bin_heap, item); + bin_heap_item_increase(bin_heap); + + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__API__ k_err_t tos_bin_heap_pop(k_bin_heap_t *bin_heap, void *item, size_t *item_size) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_PTR_SANITY_CHECK(item); + TOS_OBJ_VERIFY(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + + TOS_CPU_INT_DISABLE(); + + if (tos_bin_heap_is_empty(bin_heap)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_BIN_HEAP_EMPTY; + } + + bin_heap_item_copy_to(bin_heap, item, item_size); + bin_heap_item_decrease(bin_heap); + bin_heap_percolate_down(bin_heap); + + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bin_heap_flush(k_bin_heap_t *bin_heap) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(bin_heap); + TOS_OBJ_VERIFY(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP); + + TOS_CPU_INT_DISABLE(); + bin_heap->total = 0; + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +__API__ int tos_bin_heap_is_empty(k_bin_heap_t *bin_heap) +{ + TOS_CPU_CPSR_ALLOC(); + int is_empty = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(bin_heap, K_FALSE); + TOS_OBJ_VERIFY_RC(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_empty = (bin_heap->total == 0); + TOS_CPU_INT_ENABLE(); + + return is_empty; +} + +__API__ int tos_bin_heap_is_full(k_bin_heap_t *bin_heap) +{ + TOS_CPU_CPSR_ALLOC(); + int is_full = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(bin_heap, K_FALSE); + TOS_OBJ_VERIFY_RC(bin_heap, KNL_OBJ_TYPE_BINARY_HEAP, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_full = (bin_heap->total == bin_heap->item_cnt ? K_TRUE : K_FALSE); + TOS_CPU_INT_ENABLE(); + + return is_full; +} + diff --git a/TencentOS_Tiny/kernel/core/tos_bitmap.c b/TencentOS_Tiny/kernel/core/tos_bitmap.c new file mode 100644 index 0000000..c9f5957 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_bitmap.c @@ -0,0 +1,143 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ k_err_t tos_bitmap_create_empty(k_bitmap_t *bitmap, k_bmtbl_t *bitmap_tbl, uint32_t bit_max) +{ + int i = 0; + + TOS_PTR_SANITY_CHECK(bitmap); + + bitmap->bitmap_tbl = bitmap_tbl; + bitmap->bit_max = bit_max; + bitmap->bit_ndx_max = K_BITMAP_TBL_SIZE(bit_max); + + for (i = 0; i < bitmap->bit_ndx_max; ++i) { + /* all bits are 0 */ + bitmap_tbl[i] = 0; + } + TOS_OBJ_INIT(bitmap, KNL_OBJ_TYPE_BITMAP); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bitmap_create_full(k_bitmap_t *bitmap, k_bmtbl_t *bitmap_tbl, uint32_t bit_max) +{ + int i = 0; + + TOS_PTR_SANITY_CHECK(bitmap); + + bitmap->bitmap_tbl = bitmap_tbl; + bitmap->bit_max = bit_max; + bitmap->bit_ndx_max = K_BITMAP_TBL_SIZE(bit_max); + + for (i = 0; i < bitmap->bit_ndx_max; ++i) { + /* all bits are 1 */ + bitmap_tbl[i] = ~0; + } + TOS_OBJ_INIT(bitmap, KNL_OBJ_TYPE_BITMAP); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bitmap_destroy(k_bitmap_t *bitmap) +{ + TOS_PTR_SANITY_CHECK(bitmap); + TOS_OBJ_VERIFY(bitmap, KNL_OBJ_TYPE_BITMAP); + + TOS_OBJ_DEINIT(bitmap); + return K_ERR_NONE; +} + +__API__ k_err_t tos_bitmap_set(k_bitmap_t *bitmap, uint32_t bit) +{ + TOS_PTR_SANITY_CHECK(bitmap); + TOS_OBJ_VERIFY(bitmap, KNL_OBJ_TYPE_BITMAP); + + if (bit > bitmap->bit_max) { + return K_ERR_BITMAP_EXCEED; + } + + bitmap->bitmap_tbl[K_BITMAP_NDX(bit)] |= K_BITMAP_BIT(bit); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_bitmap_reset(k_bitmap_t *bitmap, uint32_t bit) +{ + TOS_PTR_SANITY_CHECK(bitmap); + TOS_OBJ_VERIFY(bitmap, KNL_OBJ_TYPE_BITMAP); + + if (bit > bitmap->bit_max) { + return K_ERR_BITMAP_EXCEED; + } + + bitmap->bitmap_tbl[K_BITMAP_NDX(bit)] &= ~K_BITMAP_BIT(bit); + + return K_ERR_NONE; +} + +__API__ int tos_bitmap_is_set(k_bitmap_t *bitmap, uint32_t bit) +{ + TOS_PTR_SANITY_CHECK_RC(bitmap, K_FALSE); + TOS_OBJ_VERIFY_RC(bitmap, KNL_OBJ_TYPE_BITMAP, K_FALSE); + + if (bit > bitmap->bit_max) { + return K_FALSE; + } + + return (bitmap->bitmap_tbl[K_BITMAP_NDX(bit)] & K_BITMAP_BIT(bit)) ? K_TRUE : K_FALSE; +} + +__API__ int tos_bitmap_is_reset(k_bitmap_t *bitmap, uint32_t bit) +{ + TOS_PTR_SANITY_CHECK_RC(bitmap, K_FALSE); + TOS_OBJ_VERIFY_RC(bitmap, KNL_OBJ_TYPE_BITMAP, K_FALSE); + + if (bit > bitmap->bit_max) { + return K_FALSE; + } + + return tos_bitmap_is_set(bitmap, bit) ? K_FALSE : K_TRUE; +} + +__API__ int tos_bitmap_lsb(k_bitmap_t *bitmap) +{ + int lsb = 0, i = 0; + k_bmtbl_t *bitmap_tbl; + + TOS_PTR_SANITY_CHECK_RC(bitmap, -1); + TOS_OBJ_VERIFY_RC(bitmap, KNL_OBJ_TYPE_BITMAP, -1); + + bitmap_tbl = bitmap->bitmap_tbl; + + for (i = 0; i < bitmap->bit_ndx_max - 1; ++i) { + if (*bitmap_tbl == 0) { + lsb += K_BITMAP_SLOT_SIZE; + ++bitmap_tbl; + } + } + + lsb += tos_cpu_clz(*bitmap_tbl); + if (lsb > bitmap->bit_max) { + return bitmap->bit_max + 1; + } + + return lsb; +} + diff --git a/TencentOS_Tiny/kernel/core/tos_char_fifo.c b/TencentOS_Tiny/kernel/core/tos_char_fifo.c new file mode 100644 index 0000000..7dc3bc4 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_char_fifo.c @@ -0,0 +1,185 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ k_err_t tos_chr_fifo_create(k_chr_fifo_t *chr_fifo, void *buffer, size_t size) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(chr_fifo); + TOS_PTR_SANITY_CHECK(buffer); + + err = tos_ring_q_create(&chr_fifo->ring_q, buffer, size, sizeof(uint8_t)); + if (err != K_ERR_NONE) { + return err; + } + + TOS_OBJ_INIT(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + knl_object_alloc_set_static(&chr_fifo->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_chr_fifo_destroy(k_chr_fifo_t *chr_fifo) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(chr_fifo); + TOS_OBJ_VERIFY(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + + if (!knl_object_alloc_is_static(&chr_fifo->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + err = tos_ring_q_destroy(&chr_fifo->ring_q); + if (err != K_ERR_NONE) { + return err; + } + + TOS_OBJ_DEINIT(chr_fifo); + knl_object_alloc_reset(&chr_fifo->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_chr_fifo_create_dyn(k_chr_fifo_t *chr_fifo, size_t fifo_size) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(chr_fifo); + + err = tos_ring_q_create_dyn(&chr_fifo->ring_q, fifo_size, sizeof(uint8_t)); + if (err != K_ERR_NONE) { + return err; + } + + TOS_OBJ_INIT(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + knl_object_alloc_set_dynamic(&chr_fifo->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_chr_fifo_destroy_dyn(k_chr_fifo_t *chr_fifo) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(chr_fifo); + TOS_OBJ_VERIFY(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + + if (!knl_object_alloc_is_dynamic(&chr_fifo->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + err = tos_ring_q_destroy_dyn(&chr_fifo->ring_q); + if (err != K_ERR_NONE) { + return err; + } + + TOS_OBJ_DEINIT(chr_fifo); + knl_object_alloc_reset(&chr_fifo->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_chr_fifo_push(k_chr_fifo_t *chr_fifo, uint8_t data) +{ + TOS_PTR_SANITY_CHECK(chr_fifo); + TOS_OBJ_VERIFY(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + + return tos_ring_q_enqueue(&chr_fifo->ring_q, &data, sizeof(uint8_t)); +} + +__API__ int tos_chr_fifo_push_stream(k_chr_fifo_t *chr_fifo, uint8_t *stream, size_t size) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + int i = 0; + + TOS_PTR_SANITY_CHECK_RC(chr_fifo, 0); + TOS_OBJ_VERIFY_RC(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO, 0); + + TOS_CPU_INT_DISABLE(); + + while (i < size) { + err = tos_ring_q_enqueue(&chr_fifo->ring_q, &stream[i], sizeof(uint8_t)); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return i; + } + ++i; + } + + TOS_CPU_INT_ENABLE(); + return i; +} + +__API__ k_err_t tos_chr_fifo_pop(k_chr_fifo_t *chr_fifo, uint8_t *out) +{ + TOS_PTR_SANITY_CHECK(chr_fifo); + TOS_OBJ_VERIFY(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + + return tos_ring_q_dequeue(&chr_fifo->ring_q, (void *)out, K_NULL); +} + +__API__ int tos_chr_fifo_pop_stream(k_chr_fifo_t *chr_fifo, uint8_t *buffer, size_t size) +{ + TOS_CPU_CPSR_ALLOC(); + int i = 0; + uint8_t data; + + TOS_PTR_SANITY_CHECK_RC(chr_fifo, 0); + TOS_OBJ_VERIFY_RC(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO, 0); + + TOS_CPU_INT_DISABLE(); + + while (i < size) { + if (tos_ring_q_dequeue(&chr_fifo->ring_q, &data, K_NULL) != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return i; + } + buffer[i++] = data; + } + + TOS_CPU_INT_ENABLE(); + return i; +} + +__API__ k_err_t tos_chr_fifo_flush(k_chr_fifo_t *chr_fifo) +{ + TOS_PTR_SANITY_CHECK(chr_fifo); + TOS_OBJ_VERIFY(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO); + + return tos_ring_q_flush(&chr_fifo->ring_q); +} + +__API__ int tos_chr_fifo_is_empty(k_chr_fifo_t *chr_fifo) +{ + TOS_PTR_SANITY_CHECK_RC(chr_fifo, K_FALSE); + TOS_OBJ_VERIFY_RC(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO, K_FALSE); + + return tos_ring_q_is_empty(&chr_fifo->ring_q); +} + +__API__ int tos_chr_fifo_is_full(k_chr_fifo_t *chr_fifo) +{ + TOS_PTR_SANITY_CHECK_RC(chr_fifo, K_FALSE); + TOS_OBJ_VERIFY_RC(chr_fifo, KNL_OBJ_TYPE_CHAR_FIFO, K_FALSE); + + return tos_ring_q_is_full(&chr_fifo->ring_q); +} + diff --git a/TencentOS_Tiny/kernel/core/tos_completion.c b/TencentOS_Tiny/kernel/core/tos_completion.c new file mode 100644 index 0000000..6564227 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_completion.c @@ -0,0 +1,160 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_COMPLETION_EN > 0 + +__API__ k_err_t tos_completion_create(k_completion_t *completion) +{ + TOS_PTR_SANITY_CHECK(completion); + + completion->done = (completion_done_t)0u; + pend_object_init(&completion->pend_obj); + TOS_OBJ_INIT(completion, KNL_OBJ_TYPE_COMPLETION); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_completion_destroy(k_completion_t *completion) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(completion); + TOS_OBJ_VERIFY(completion, KNL_OBJ_TYPE_COMPLETION); + + TOS_CPU_INT_DISABLE(); + + pend_wakeup_all(&completion->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&completion->pend_obj); + + TOS_OBJ_DEINIT(completion); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_completion_pend_timed(k_completion_t *completion, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(completion); + TOS_OBJ_VERIFY(completion, KNL_OBJ_TYPE_COMPLETION); + + TOS_CPU_INT_DISABLE(); + + if (completion->done > (completion_done_t)0u) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { // no wait, return immediately + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + pend_task_block(k_curr_task, &completion->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return pend_state2errno(k_curr_task->pend_state); +} + +__API__ k_err_t tos_completion_pend(k_completion_t *completion) +{ + return tos_completion_pend_timed(completion, TOS_TIME_FOREVER); +} + +__STATIC__ k_err_t completion_do_post(k_completion_t *completion, opt_post_t opt) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(completion); + TOS_OBJ_VERIFY(completion, KNL_OBJ_TYPE_COMPLETION); + + TOS_CPU_INT_DISABLE(); + + if (completion->done == (completion_done_t)-1) { + TOS_CPU_INT_ENABLE(); + return K_ERR_COMPLETION_OVERFLOW; + } + + ++completion->done; + + if (pend_is_nopending(&completion->pend_obj)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + pend_wakeup(&completion->pend_obj, PEND_STATE_POST, opt); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_completion_post(k_completion_t *completion) +{ + return completion_do_post(completion, OPT_POST_ONE); +} + +__API__ k_err_t tos_completion_post_all(k_completion_t *completion) +{ + return completion_do_post(completion, OPT_POST_ALL); +} + +__API__ k_err_t tos_completion_reset(k_completion_t *completion) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(completion); + TOS_OBJ_VERIFY(completion, KNL_OBJ_TYPE_COMPLETION); + + TOS_CPU_INT_DISABLE(); + completion->done = (completion_done_t)0u; + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +__API__ int tos_completion_is_done(k_completion_t *completion) +{ + TOS_CPU_CPSR_ALLOC(); + int is_done = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(completion, K_FALSE); + TOS_OBJ_VERIFY_RC(completion, KNL_OBJ_TYPE_COMPLETION, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_done = (completion->done > (completion_done_t)0u ? K_TRUE : K_FALSE); + TOS_CPU_INT_ENABLE(); + + return is_done; +} + +#endif /* TOS_CFG_COMPLETION_EN */ diff --git a/TencentOS_Tiny/kernel/core/tos_countdownlatch.c b/TencentOS_Tiny/kernel/core/tos_countdownlatch.c new file mode 100644 index 0000000..cdb0186 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_countdownlatch.c @@ -0,0 +1,135 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_COUNTDOWNLATCH_EN > 0 + +__API__ k_err_t tos_countdownlatch_create(k_countdownlatch_t *countdownlatch, k_countdownlatch_cnt_t count) +{ + TOS_PTR_SANITY_CHECK(countdownlatch); + + countdownlatch->count = count; + pend_object_init(&countdownlatch->pend_obj); + TOS_OBJ_INIT(countdownlatch, KNL_OBJ_TYPE_COUNTDOWNLATCH); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_countdownlatch_destroy(k_countdownlatch_t *countdownlatch) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(countdownlatch); + TOS_OBJ_VERIFY(countdownlatch, KNL_OBJ_TYPE_COUNTDOWNLATCH); + + TOS_CPU_INT_DISABLE(); + + pend_wakeup_all(&countdownlatch->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&countdownlatch->pend_obj); + + TOS_OBJ_DEINIT(countdownlatch); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_countdownlatch_pend_timed(k_countdownlatch_t *countdownlatch, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(countdownlatch); + TOS_OBJ_VERIFY(countdownlatch, KNL_OBJ_TYPE_COUNTDOWNLATCH); + + TOS_CPU_INT_DISABLE(); + + if (countdownlatch->count == (k_countdownlatch_cnt_t)0u) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { // no wait, return immediately + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + pend_task_block(k_curr_task, &countdownlatch->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return pend_state2errno(k_curr_task->pend_state); +} + +__API__ k_err_t tos_countdownlatch_pend(k_countdownlatch_t *countdownlatch) +{ + return tos_countdownlatch_pend_timed(countdownlatch, TOS_TIME_FOREVER); +} + +__API__ k_err_t tos_countdownlatch_post(k_countdownlatch_t *countdownlatch) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(countdownlatch); + TOS_OBJ_VERIFY(countdownlatch, KNL_OBJ_TYPE_COUNTDOWNLATCH); + + TOS_CPU_INT_DISABLE(); + + if (countdownlatch->count == (k_countdownlatch_cnt_t)0) { + TOS_CPU_INT_ENABLE(); + return K_ERR_COUNTDOWNLATCH_OVERFLOW; + } + + --countdownlatch->count; + + if (countdownlatch->count > (k_countdownlatch_cnt_t)0) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + pend_wakeup_one(&countdownlatch->pend_obj, PEND_STATE_POST); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_countdownlatch_reset(k_countdownlatch_t *countdownlatch, k_countdownlatch_cnt_t count) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(countdownlatch); + TOS_OBJ_VERIFY(countdownlatch, KNL_OBJ_TYPE_COUNTDOWNLATCH); + + TOS_CPU_INT_DISABLE(); + countdownlatch->count = count; + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +#endif /* TOS_CFG_COUNTDOWNLATCH_EN */ diff --git a/TencentOS_Tiny/kernel/core/tos_event.c b/TencentOS_Tiny/kernel/core/tos_event.c new file mode 100644 index 0000000..145fbba --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_event.c @@ -0,0 +1,170 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_EVENT_EN > 0 + +__API__ k_err_t tos_event_create(k_event_t *event, k_event_flag_t init_flag) +{ + TOS_PTR_SANITY_CHECK(event); + + event->flag = init_flag; + pend_object_init(&event->pend_obj); + TOS_OBJ_INIT(event, KNL_OBJ_TYPE_EVENT); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_event_destroy(k_event_t *event) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(event); + TOS_OBJ_VERIFY(event, KNL_OBJ_TYPE_EVENT); + + TOS_CPU_INT_DISABLE(); + + pend_wakeup_all(&event->pend_obj, PEND_STATE_DESTROY); + + event->flag = (k_event_flag_t)0u; + + pend_object_deinit(&event->pend_obj); + + TOS_OBJ_DEINIT(event); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__STATIC__ int event_is_match(k_event_flag_t event, k_event_flag_t flag_expect, k_event_flag_t *flag_match, k_opt_t opt_pend) +{ + if (opt_pend & TOS_OPT_EVENT_PEND_ALL) { + if ((event & flag_expect) == flag_expect) { + *flag_match = flag_expect; + return K_TRUE; + } + } else if (opt_pend & TOS_OPT_EVENT_PEND_ANY) { + if (event & flag_expect) { + *flag_match = event & flag_expect; + return K_TRUE; + } + } + return K_FALSE; +} + +__API__ k_err_t tos_event_pend(k_event_t *event, k_event_flag_t flag_expect, k_event_flag_t *flag_match, k_tick_t timeout, k_opt_t opt_pend) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(event); + TOS_PTR_SANITY_CHECK(flag_match); + TOS_OBJ_VERIFY(event, KNL_OBJ_TYPE_EVENT); + + if (!(opt_pend & TOS_OPT_EVENT_PEND_ALL) && !(opt_pend & TOS_OPT_EVENT_PEND_ANY)) { + return K_ERR_EVENT_PEND_OPT_INVALID; + } + + if ((opt_pend & TOS_OPT_EVENT_PEND_ALL) && (opt_pend & TOS_OPT_EVENT_PEND_ANY)) { + return K_ERR_EVENT_PEND_OPT_INVALID; + } + + TOS_CPU_INT_DISABLE(); + + if (event_is_match(event->flag, flag_expect, flag_match, opt_pend)) { + if (opt_pend & TOS_OPT_EVENT_PEND_CLR) { // destroy the bridge after get across the river + event->flag = (k_event_flag_t)0u; + } + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + k_curr_task->flag_expect = flag_expect; + k_curr_task->flag_match = flag_match; + k_curr_task->opt_event_pend = opt_pend; + + pend_task_block(k_curr_task, &event->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + k_curr_task->flag_expect = (k_event_flag_t)0u; + k_curr_task->flag_match = (k_event_flag_t *)K_NULL; + k_curr_task->opt_event_pend = (k_opt_t)0u; + + return pend_state2errno(k_curr_task->pend_state); +} + +__STATIC__ k_err_t event_do_post(k_event_t *event, k_event_flag_t flag, opt_event_post_t opt_post) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *task, *tmp; + + TOS_PTR_SANITY_CHECK(event); + TOS_OBJ_VERIFY(event, KNL_OBJ_TYPE_EVENT); + + if (opt_post == OPT_EVENT_POST_KEP) { + event->flag |= flag; + } else { + event->flag = flag; + } + + TOS_CPU_INT_DISABLE(); + + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, pend_list, &event->pend_obj.list) { + if (event_is_match(event->flag, task->flag_expect, task->flag_match, task->opt_event_pend)) { + pend_task_wakeup(task, PEND_STATE_POST); + + // if anyone pending the event has set the TOS_OPT_EVENT_PEND_CLR, then no wakeup for the others pendig for the event. + if (task->opt_event_pend & TOS_OPT_EVENT_PEND_CLR) { + event->flag = (k_event_flag_t)0u; + break; + } + } + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_event_post(k_event_t *event, k_event_flag_t flag) +{ + return event_do_post(event, flag, OPT_EVENT_POST_CLR); +} + +__API__ k_err_t tos_event_post_keep(k_event_t *event, k_event_flag_t flag) +{ + return event_do_post(event, flag, OPT_EVENT_POST_KEP); +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_global.c b/TencentOS_Tiny/kernel/core/tos_global.c new file mode 100644 index 0000000..e80eb15 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_global.c @@ -0,0 +1,87 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include + +k_nesting_t k_irq_nest_cnt = (k_nesting_t)0; +k_nesting_t k_sched_lock_nest_cnt = (k_nesting_t)0; +knl_state_t k_knl_state = KNL_STATE_STOPPED; + +readyqueue_t k_rdyq; + +k_tick_t k_tick_count = (k_tick_t)0u; +k_task_t *k_curr_task = K_NULL; +k_task_t *k_next_task = K_NULL; + +k_task_t k_idle_task; +k_stack_t k_idle_task_stk[TOS_CFG_IDLE_TASK_STK_SIZE]; +k_stack_t *const k_idle_task_stk_addr = &k_idle_task_stk[0]; +size_t const k_idle_task_stk_size = TOS_CFG_IDLE_TASK_STK_SIZE; + +k_tick_t k_cpu_tick_per_second = TOS_CFG_CPU_TICK_PER_SECOND; + +k_cycle_t k_cpu_cycle_per_tick = (k_cycle_t)0u; + +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u +TOS_LIST_DEFINE(k_dead_task_list); +#endif + +TOS_LIST_DEFINE(k_stat_list); + +TOS_LIST_DEFINE(k_tick_list); + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +k_fault_log_writer_t k_fault_log_writer = fault_default_log_writer; +#endif + +#if TOS_CFG_MMHEAP_EN > 0u +#if TOS_CFG_MMHEAP_DEFAULT_POOL_EN > 0u +uint8_t k_mmheap_default_pool[TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE] __ALIGNED__(4); +#endif +k_mmheap_ctl_t k_mmheap_ctl; +#endif + +#if TOS_CFG_ROUND_ROBIN_EN > 0u +k_timeslice_t k_robin_default_timeslice = TOS_CFG_CPU_TICK_PER_SECOND / 10; +#endif + +#if TOS_CFG_TIMER_EN > 0u +timer_ctl_t k_timer_ctl = { TOS_TIME_FOREVER, TOS_LIST_NODE(k_timer_ctl.list) }; + +#if TOS_CFG_TIMER_AS_PROC == 0u +k_task_t k_timer_task; +k_stack_t k_timer_task_stk[TOS_CFG_TIMER_TASK_STK_SIZE]; +k_prio_t const k_timer_task_prio = TOS_CFG_TIMER_TASK_PRIO; +k_stack_t *const k_timer_task_stk_addr = &k_timer_task_stk[0]; +size_t const k_timer_task_stk_size = TOS_CFG_TIMER_TASK_STK_SIZE; +#endif /* TOS_CFG_TIMER_AS_PROC == 0u */ + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u +pm_device_ctl_t k_pm_device_ctl = { 0u }; + +/* default idle power manager mode is SLEEP */ +idle_pwrmgr_mode_t k_idle_pwr_mgr_mode = IDLE_POWER_MANAGER_MODE_SLEEP; + +k_cpu_lpwr_mode_t k_cpu_lpwr_mode = TOS_LOW_POWER_MODE_NONE; +#endif + +#if TOS_CFG_TICKLESS_EN > 0u +k_tickless_wkup_alarm_t *k_tickless_wkup_alarm[__LOW_POWER_MODE_DUMMY] = { K_NULL }; +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_mail_queue.c b/TencentOS_Tiny/kernel/core/tos_mail_queue.c new file mode 100644 index 0000000..033d9b4 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_mail_queue.c @@ -0,0 +1,233 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_MAIL_QUEUE_EN > 0u + +__API__ k_err_t tos_mail_q_create(k_mail_q_t *mail_q, void *pool, size_t mail_cnt, size_t mail_size) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(mail_q); + + err = tos_ring_q_create(&mail_q->ring_q, pool, mail_cnt, mail_size); + if (err != K_ERR_NONE) { + return err; + } + + pend_object_init(&mail_q->pend_obj); + + TOS_OBJ_INIT(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + knl_object_alloc_set_static(&mail_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mail_q_destroy(k_mail_q_t *mail_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(mail_q); + TOS_OBJ_VERIFY(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + + if (!knl_object_alloc_is_static(&mail_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_ring_q_destroy(&mail_q->ring_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&mail_q->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&mail_q->pend_obj); + + TOS_OBJ_DEINIT(mail_q); + knl_object_alloc_reset(&mail_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mail_q_create_dyn(k_mail_q_t *mail_q, size_t mail_cnt, size_t mail_size) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(mail_q); + + err = tos_ring_q_create_dyn(&mail_q->ring_q, mail_cnt, mail_size); + if (err != K_ERR_NONE) { + return err; + } + + pend_object_init(&mail_q->pend_obj); + + TOS_OBJ_INIT(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + knl_object_alloc_set_dynamic(&mail_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mail_q_destroy_dyn(k_mail_q_t *mail_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(mail_q); + TOS_OBJ_VERIFY(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + + if (!knl_object_alloc_is_dynamic(&mail_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_ring_q_destroy_dyn(&mail_q->ring_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&mail_q->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&mail_q->pend_obj); + + TOS_OBJ_DEINIT(mail_q); + knl_object_alloc_reset(&mail_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mail_q_flush(k_mail_q_t *mail_q) +{ + TOS_PTR_SANITY_CHECK(mail_q); + TOS_OBJ_VERIFY(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + + return tos_ring_q_flush(&mail_q->ring_q); +} + +__API__ k_err_t tos_mail_q_pend(k_mail_q_t *mail_q, void *mail_buf, size_t *mail_size, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mail_q); + TOS_PTR_SANITY_CHECK(mail_buf); + TOS_OBJ_VERIFY(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (tos_ring_q_dequeue(&mail_q->ring_q, mail_buf, mail_size) == K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { + *mail_size = 0; + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + k_curr_task->mail = mail_buf; + pend_task_block(k_curr_task, &mail_q->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + err = pend_state2errno(k_curr_task->pend_state); + if (err == K_ERR_NONE) { + *mail_size = k_curr_task->mail_size; + k_curr_task->mail = K_NULL; + k_curr_task->mail_size = 0; + } + + return err; +} + +__STATIC__ void mail_task_recv(k_task_t *task, void *mail_buf, size_t mail_size) +{ + memcpy(task->mail, mail_buf, mail_size); + task->mail_size = mail_size; + pend_task_wakeup(task, PEND_STATE_POST); +} + +__STATIC__ k_err_t mail_q_do_post(k_mail_q_t *mail_q, void *mail_buf, size_t mail_size, opt_post_t opt) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + k_task_t *task, *tmp; + + TOS_PTR_SANITY_CHECK(mail_q); + TOS_PTR_SANITY_CHECK(mail_buf); + TOS_OBJ_VERIFY(mail_q, KNL_OBJ_TYPE_MAIL_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (pend_is_nopending(&mail_q->pend_obj)) { + err = tos_ring_q_enqueue(&mail_q->ring_q, mail_buf, mail_size); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (opt == OPT_POST_ONE) { + mail_task_recv(TOS_LIST_FIRST_ENTRY(&mail_q->pend_obj.list, k_task_t, pend_list), + mail_buf, mail_size); + } else { // OPT_POST_ALL + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, pend_list, &mail_q->pend_obj.list) { + mail_task_recv(task, mail_buf, mail_size); + } + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mail_q_post(k_mail_q_t *mail_q, void *mail_buf, size_t mail_size) +{ + return mail_q_do_post(mail_q, mail_buf, mail_size, OPT_POST_ONE); +} + +__API__ k_err_t tos_mail_q_post_all(k_mail_q_t *mail_q, void *mail_buf, size_t mail_size) +{ + return mail_q_do_post(mail_q, mail_buf, mail_size, OPT_POST_ALL); +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_message_queue.c b/TencentOS_Tiny/kernel/core/tos_message_queue.c new file mode 100644 index 0000000..0f3cee2 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_message_queue.c @@ -0,0 +1,229 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_MESSAGE_QUEUE_EN > 0u + +__API__ k_err_t tos_msg_q_create(k_msg_q_t *msg_q, void *pool, size_t msg_cnt) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(msg_q); + TOS_PTR_SANITY_CHECK(pool); + + err = tos_ring_q_create(&msg_q->ring_q, pool, msg_cnt, sizeof(void *)); + if (err != K_ERR_NONE) { + return err; + } + + pend_object_init(&msg_q->pend_obj); + + TOS_OBJ_INIT(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + knl_object_alloc_set_static(&msg_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_msg_q_destroy(k_msg_q_t *msg_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(msg_q); + TOS_OBJ_VERIFY(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + + if (!knl_object_alloc_is_static(&msg_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_ring_q_destroy(&msg_q->ring_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&msg_q->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&msg_q->pend_obj); + + TOS_OBJ_DEINIT(msg_q); + knl_object_alloc_reset(&msg_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_msg_q_create_dyn(k_msg_q_t *msg_q, size_t msg_cnt) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(msg_q); + + err = tos_ring_q_create_dyn(&msg_q->ring_q, msg_cnt, sizeof(void *)); + if (err != K_ERR_NONE) { + return err; + } + + pend_object_init(&msg_q->pend_obj); + + TOS_OBJ_INIT(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + knl_object_alloc_set_dynamic(&msg_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_msg_q_destroy_dyn(k_msg_q_t *msg_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(msg_q); + TOS_OBJ_VERIFY(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + + if (!knl_object_alloc_is_dynamic(&msg_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_ring_q_destroy_dyn(&msg_q->ring_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&msg_q->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&msg_q->pend_obj); + + TOS_OBJ_DEINIT(msg_q); + knl_object_alloc_reset(&msg_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_msg_q_flush(k_msg_q_t *msg_q) +{ + TOS_PTR_SANITY_CHECK(msg_q); + TOS_OBJ_VERIFY(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + + return tos_ring_q_flush(&msg_q->ring_q); +} + +__API__ k_err_t tos_msg_q_pend(k_msg_q_t *msg_q, void **msg_ptr, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(msg_q); + TOS_PTR_SANITY_CHECK(msg_ptr); + TOS_OBJ_VERIFY(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (tos_ring_q_dequeue(&msg_q->ring_q, msg_ptr, K_NULL) == K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { + *msg_ptr = K_NULL; + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + pend_task_block(k_curr_task, &msg_q->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + err = pend_state2errno(k_curr_task->pend_state); + if (err == K_ERR_NONE) { + *msg_ptr = k_curr_task->msg; + k_curr_task->msg = K_NULL; + } + + return err; +} + +__STATIC__ void msg_q_task_recv(k_task_t *task, void *msg_ptr) +{ + task->msg = msg_ptr; + pend_task_wakeup(task, PEND_STATE_POST); +} + +__STATIC__ k_err_t msg_q_do_post(k_msg_q_t *msg_q, void *msg_ptr, opt_post_t opt) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + k_task_t *task, *tmp; + + TOS_PTR_SANITY_CHECK(msg_q); + TOS_OBJ_VERIFY(msg_q, KNL_OBJ_TYPE_MESSAGE_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (pend_is_nopending(&msg_q->pend_obj)) { + err = tos_ring_q_enqueue(&msg_q->ring_q, &msg_ptr, sizeof(void*)); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (opt == OPT_POST_ONE) { + msg_q_task_recv(TOS_LIST_FIRST_ENTRY(&msg_q->pend_obj.list, k_task_t, pend_list), msg_ptr); + } else { // OPT_POST_ALL + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, pend_list, &msg_q->pend_obj.list) { + msg_q_task_recv(task, msg_ptr); + } + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_msg_q_post(k_msg_q_t *msg_q, void *msg_ptr) +{ + return msg_q_do_post(msg_q, msg_ptr, OPT_POST_ONE); +} + +__API__ k_err_t tos_msg_q_post_all(k_msg_q_t *msg_q, void *msg_ptr) +{ + return msg_q_do_post(msg_q, msg_ptr, OPT_POST_ALL); +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_mmblk.c b/TencentOS_Tiny/kernel/core/tos_mmblk.c new file mode 100644 index 0000000..dd7d3e8 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_mmblk.c @@ -0,0 +1,198 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ k_err_t tos_mmblk_pool_create(k_mmblk_pool_t *mbp, void *pool_start, size_t blk_num, size_t blk_size) +{ + uint32_t i; + void *blk_curr, *blk_next; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(pool_start); + + if (((cpu_addr_t)pool_start & K_MMBLK_ALIGN_MASK) != 0u) { + return K_ERR_MMBLK_INVALID_POOL_ADDR; + } + + if ((blk_size & K_MMBLK_ALIGN_MASK) != 0u) { + return K_ERR_MMBLK_INVALID_BLK_SIZE; + } + + blk_curr = pool_start; + blk_next = K_MMBLK_NEXT_BLK(blk_curr, blk_size); + + for (i = 0; i < blk_num - 1u; ++i) { + *(void **)blk_curr = blk_next; + blk_curr = blk_next; + blk_next = K_MMBLK_NEXT_BLK(blk_next, blk_size); + } + *(void **)blk_curr = K_NULL; + + mbp->pool_start = pool_start; + mbp->free_list = pool_start; + mbp->blk_free = blk_num; + mbp->blk_max = blk_num; + mbp->blk_size = blk_size; + + TOS_OBJ_INIT(mbp, KNL_OBJ_TYPE_MMBLK_POOL); + + knl_object_alloc_set_static(&mbp->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mmblk_pool_destroy(k_mmblk_pool_t *mbp) +{ + TOS_PTR_SANITY_CHECK(mbp); + TOS_OBJ_VERIFY(mbp, KNL_OBJ_TYPE_MMBLK_POOL); + +#if TOS_CFG_MMHEAP_EN > 0u + if (!knl_object_alloc_is_static(&mbp->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } +#endif + + mbp->pool_start = K_NULL; + mbp->free_list = K_NULL; + mbp->blk_free = 0; + mbp->blk_max = 0; + mbp->blk_size = 0; + + TOS_OBJ_DEINIT(mbp); + + return K_ERR_NONE; +} + +#if TOS_CFG_MMHEAP_EN > 0u + +__API__ k_err_t tos_mmblk_pool_create_dyn(k_mmblk_pool_t **mbp, size_t blk_num, size_t blk_size) +{ + uint32_t i; + void *pool_start; + k_mmblk_pool_t *the_mbp; + void *blk_curr, *blk_next; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mbp); + + if ((blk_size & K_MMBLK_ALIGN_MASK) != 0u) { + return K_ERR_MMBLK_INVALID_BLK_SIZE; + } + + the_mbp = tos_mmheap_calloc(1, sizeof(k_mmblk_pool_t)); + if (!the_mbp) { + return K_ERR_MMBLK_OUT_OF_MEMORY; + } + + pool_start = tos_mmheap_alloc(blk_num * blk_size); + if (!pool_start) { + return K_ERR_MMBLK_POOL_OUT_OF_MEMORY; + } + + blk_curr = pool_start; + blk_next = K_MMBLK_NEXT_BLK(blk_curr, blk_size); + + for (i = 0; i < blk_num - 1u; ++i) { + *(void **)blk_curr = blk_next; + blk_curr = blk_next; + blk_next = K_MMBLK_NEXT_BLK(blk_next, blk_size); + } + + *(void **)blk_curr = K_NULL; + + the_mbp->pool_start = pool_start; + the_mbp->free_list = pool_start; + the_mbp->blk_free = blk_num; + the_mbp->blk_max = blk_num; + the_mbp->blk_size = blk_size; + + TOS_OBJ_INIT(the_mbp, KNL_OBJ_TYPE_MMBLK_POOL); + + knl_object_alloc_set_dynamic(&the_mbp->knl_obj); + + *mbp = the_mbp; + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mmblk_pool_destroy_dyn(k_mmblk_pool_t *mbp) +{ + TOS_PTR_SANITY_CHECK(mbp); + TOS_OBJ_VERIFY(mbp, KNL_OBJ_TYPE_MMBLK_POOL); + + if (!knl_object_alloc_is_dynamic(&mbp->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + tos_mmheap_free(mbp->pool_start); + + mbp->pool_start = K_NULL; + mbp->free_list = K_NULL; + mbp->blk_free = 0; + mbp->blk_max = 0; + mbp->blk_size = 0; + + TOS_OBJ_DEINIT(mbp); + tos_mmheap_free(mbp); + + return K_ERR_NONE; +} + +#endif + +__API__ k_err_t tos_mmblk_alloc(k_mmblk_pool_t *mbp, void **blk) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(mbp); + TOS_OBJ_VERIFY(mbp, KNL_OBJ_TYPE_MMBLK_POOL); + + TOS_CPU_INT_DISABLE(); + if (mbp->blk_free == 0) { + TOS_CPU_INT_ENABLE(); + *blk = K_NULL; + return K_ERR_MMBLK_POOL_EMPTY; + } + *blk = mbp->free_list; + mbp->free_list = *(void **)mbp->free_list; + --mbp->blk_free; + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__API__ k_err_t tos_mmblk_free(k_mmblk_pool_t *mbp, void *blk) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(mbp); + TOS_PTR_SANITY_CHECK(blk); + TOS_OBJ_VERIFY(mbp, KNL_OBJ_TYPE_MMBLK_POOL); + + TOS_CPU_INT_DISABLE(); + if (mbp->blk_free >= mbp->blk_max) { + TOS_CPU_INT_ENABLE(); + return K_ERR_MMBLK_POOL_FULL; + } + + *(void **)blk = mbp->free_list; + mbp->free_list = blk; + ++mbp->blk_free; + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + diff --git a/TencentOS_Tiny/kernel/core/tos_mmheap.c b/TencentOS_Tiny/kernel/core/tos_mmheap.c new file mode 100644 index 0000000..a3f1b4d --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_mmheap.c @@ -0,0 +1,825 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +/* +** Two Level Segregated Fit memory allocator, version 3.1. +** Written by Matthew Conte +** http://tlsf.baisoku.org +** +** Based on the original documentation by Miguel Masmano: +** http://www.gii.upv.es/tlsf/main/docs +** +** This implementation was written to the specification +** of the document, therefore no GPL restrictions apply. +** +** Copyright (c) 2006-2016, Matthew Conte +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted provided that the following conditions are met: +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** * Neither the name of the copyright holder nor the +** names of its contributors may be used to endorse or promote products +** derived from this software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL MATTHEW CONTE BE LIABLE FOR ANY +** DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +** ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "tos_k.h" + +#if TOS_CFG_MMHEAP_EN > 0u + +#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u) +__STATIC__ int generic_fls(uint32_t x) +{ + int r = 32; + if (!x) + return 0; + + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} +#else +__STATIC__ int generic_fls(uint32_t x) +{ + return 32 - tos_cpu_clz(x); +} +#endif + +__STATIC__ int __ffs(uint32_t word) +{ + return generic_fls(word & (~word + 1)) - 1; +} + +__STATIC__ int __fls(uint32_t word) +{ + return generic_fls(word) - 1; +} + +/* +** TLSF utility functions. In most cases, these are direct translations of +** the documentation found in the white paper. +*/ +__STATIC__ void mapping_insert(size_t size, int *fli, int *sli) +{ + int fl, sl; + + if (size < K_MMHEAP_SMALL_BLOCK_SIZE) { + /* Store small blocks in first list. */ + fl = 0; + sl = (int)size / (K_MMHEAP_SMALL_BLOCK_SIZE / K_MMHEAP_SL_INDEX_COUNT); + } else { + fl = __fls(size); + sl = ((int)size >> (fl - K_MMHEAP_SL_INDEX_COUNT_LOG2)) ^ (1 << K_MMHEAP_SL_INDEX_COUNT_LOG2); + fl -= (K_MMHEAP_FL_INDEX_SHIFT - 1); + } + *fli = fl; + *sli = sl; +} + +/* This version rounds up to the next block size (for allocations) */ +__STATIC__ void mapping_search(size_t size, int *fli, int *sli) +{ + size_t round; + + if (size >= K_MMHEAP_SMALL_BLOCK_SIZE) { + round = (1 << (__fls(size) - K_MMHEAP_SL_INDEX_COUNT_LOG2)) - 1; + size += round; + } + mapping_insert(size, fli, sli); +} + +__STATIC_INLINE__ size_t blk_size(const mmheap_blk_t *blk) +{ + return blk->size & K_MMHEAP_BLOCK_SIZE_MASK; +} + +__STATIC_INLINE__ int blk_is_last(const mmheap_blk_t* blk) +{ + return blk_size(blk) == 0; +} + +__STATIC_INLINE__ void blk_set_size(mmheap_blk_t *blk, size_t size) +{ + blk->size = size | (blk->size & K_MMHEAP_BLOCK_STATE_MASK); +} + +__STATIC_INLINE__ int blk_is_free(const mmheap_blk_t *blk) +{ + return blk->size & K_MMHEAP_BLOCK_CURR_FREE; +} + +__STATIC_INLINE__ void blk_set_free(mmheap_blk_t *blk) +{ + blk->size |= K_MMHEAP_BLOCK_CURR_FREE; +} + +__STATIC_INLINE__ void blk_set_used(mmheap_blk_t *blk) +{ + blk->size &= ~K_MMHEAP_BLOCK_CURR_FREE; +} + +__STATIC_INLINE__ int blk_is_prev_free(const mmheap_blk_t *blk) +{ + return blk->size & K_MMHEAP_BLOCK_PREV_FREE; +} + +__STATIC_INLINE__ void blk_set_prev_free(mmheap_blk_t *blk) +{ + blk->size |= K_MMHEAP_BLOCK_PREV_FREE; +} + +__STATIC__ void blk_set_prev_used(mmheap_blk_t *blk) +{ + blk->size &= ~K_MMHEAP_BLOCK_PREV_FREE; +} + +__STATIC_INLINE__ mmheap_blk_t *blk_from_ptr(const void *ptr) +{ + return (mmheap_blk_t *)((cpu_addr_t)ptr - K_MMHEAP_BLK_START_OFFSET); +} + +__STATIC_INLINE__ void *blk_to_ptr(const mmheap_blk_t *blk) +{ + return (void *)((cpu_addr_t)blk + K_MMHEAP_BLK_START_OFFSET); +} + +/* Return location of next block after block of given size. */ +__STATIC_INLINE__ mmheap_blk_t *offset_to_blk(const void *ptr, int diff) +{ + return (mmheap_blk_t *)((cpu_addr_t)ptr + diff); +} + +/* Return location of previous block. */ +__STATIC_INLINE__ mmheap_blk_t *blk_prev(const mmheap_blk_t *blk) +{ + return blk->prev_phys_blk; +} + +/* Return location of next existing block. */ +__STATIC__ mmheap_blk_t *blk_next(const mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = offset_to_blk(blk_to_ptr(blk), blk_size(blk) - K_MMHEAP_BLK_HEADER_OVERHEAD); + return next_blk; +} + +/* Link a new block with its physical neighbor, return the neighbor. */ +__STATIC__ mmheap_blk_t *blk_link_next(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = blk_next(blk); + next_blk->prev_phys_blk = blk; + return next_blk; +} + +__STATIC__ void blk_mark_as_free(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + /* Link the block to the next block, first. */ + next_blk = blk_link_next(blk); + blk_set_prev_free(next_blk); + blk_set_free(blk); +} + +__STATIC__ void blk_mark_as_used(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = blk_next(blk); + blk_set_prev_used(next_blk); + blk_set_used(blk); +} + +__STATIC_INLINE__ size_t align_up(size_t x, size_t align) +{ + return (x + (align - 1)) & ~(align - 1); +} + +__STATIC_INLINE__ size_t align_down(size_t x, size_t align) +{ + return x - (x & (align - 1)); +} + +__STATIC_INLINE__ void *align_ptr(const void *ptr, size_t align) +{ + return (void *)(((cpu_addr_t)ptr + (align -1)) & ~(align -1)); +} + +/* Insert a free block into the free block list. */ +__STATIC__ void insert_free_block(mmheap_blk_t *blk, int fl, int sl) +{ + mmheap_blk_t *curr; + + curr = k_mmheap_ctl.blocks[fl][sl]; + blk->next_free = curr; + blk->prev_free = &k_mmheap_ctl.block_null; + curr->prev_free = blk; + + /* + ** Insert the new block at the head of the list, and mark the first- + ** and second-level bitmaps appropriately. + */ + k_mmheap_ctl.blocks[fl][sl] = blk; + k_mmheap_ctl.fl_bitmap |= (1 << fl); + k_mmheap_ctl.sl_bitmap[fl] |= (1 << sl); +} + +/* Remove a free block from the free list.*/ +__STATIC__ void remove_free_block(mmheap_blk_t *blk, int fl, int sl) +{ + mmheap_blk_t *prev_blk; + mmheap_blk_t *next_blk; + + prev_blk = blk->prev_free; + next_blk = blk->next_free; + next_blk->prev_free = prev_blk; + prev_blk->next_free = next_blk; + + /* If this block is the head of the free list, set new head. */ + if (k_mmheap_ctl.blocks[fl][sl] == blk) { + k_mmheap_ctl.blocks[fl][sl] = next_blk; + + /* If the new head is null, clear the bitmap. */ + if (next_blk == &k_mmheap_ctl.block_null) { + k_mmheap_ctl.sl_bitmap[fl] &= ~(1 << sl); + + /* If the second bitmap is now empty, clear the fl bitmap. */ + if (!k_mmheap_ctl.sl_bitmap[fl]) { + k_mmheap_ctl.fl_bitmap &= ~(1 << fl); + } + } + } +} + +/* Remove a given block from the free list. */ +__STATIC__ void blk_remove(mmheap_blk_t *blk) +{ + int fl, sl; + + mapping_insert(blk_size(blk), &fl, &sl); + remove_free_block(blk, fl, sl); +} + +/* Insert a given block into the free list. */ +__STATIC__ void blk_insert(mmheap_blk_t *blk) +{ + int fl, sl; + + mapping_insert(blk_size(blk), &fl, &sl); + insert_free_block(blk, fl, sl); +} + +__STATIC__ int blk_can_split(mmheap_blk_t *blk, size_t size) +{ + return blk_size(blk) >= sizeof(mmheap_blk_t) + size; +} + +/* Split a block into two, the second of which is free. */ +__STATIC__ mmheap_blk_t *blk_split(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining; + size_t remain_size; + + /* Calculate the amount of space left in the remaining block. */ + remaining = offset_to_blk(blk_to_ptr(blk), size - K_MMHEAP_BLK_HEADER_OVERHEAD); + remain_size = blk_size(blk) - (size + K_MMHEAP_BLK_HEADER_OVERHEAD); + + blk_set_size(remaining, remain_size); + + blk_set_size(blk, size); + blk_mark_as_free(remaining); + + return remaining; +} + +/* Absorb a free block's storage into an adjacent previous free block. */ +__STATIC__ mmheap_blk_t *blk_absorb(mmheap_blk_t *prev_blk, mmheap_blk_t *blk) +{ + prev_blk->size += blk_size(blk) + K_MMHEAP_BLK_HEADER_OVERHEAD; + blk_link_next(prev_blk); + return prev_blk; +} + +/* Merge a just-freed block with an adjacent previous free block. */ +__STATIC__ mmheap_blk_t *blk_merge_prev(mmheap_blk_t *blk) +{ + mmheap_blk_t *prev_blk; + + if (blk_is_prev_free(blk)) { + prev_blk = blk_prev(blk); + blk_remove(prev_blk); + blk = blk_absorb(prev_blk, blk); + } + + return blk; +} + +/* Merge a just-freed block with an adjacent free block. */ +__STATIC__ mmheap_blk_t *blk_merge_next(mmheap_blk_t *blk) +{ + mmheap_blk_t *next_blk; + + next_blk = blk_next(blk); + if (blk_is_free(next_blk)) { + blk_remove(next_blk); + blk = blk_absorb(blk, next_blk); + } + + return blk; +} + +/* Trim any trailing block space off the end of a block, return to pool. */ +__STATIC__ void blk_trim_free(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining_blk; + + if (blk_can_split(blk, size)) { + remaining_blk = blk_split(blk, size); + blk_link_next(blk); + blk_set_prev_free(remaining_blk); + blk_insert(remaining_blk); + } +} + +/* Trim any trailing block space off the end of a used block, return to pool. */ +__STATIC__ void blk_trim_used(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining_blk; + + if (blk_can_split(blk, size)) { + /* If the next block is free, we must coalesce. */ + remaining_blk = blk_split(blk, size); + blk_set_prev_used(remaining_blk); + + remaining_blk = blk_merge_next(remaining_blk); + blk_insert(remaining_blk); + } +} + +__STATIC__ mmheap_blk_t *blk_trim_free_leading(mmheap_blk_t *blk, size_t size) +{ + mmheap_blk_t *remaining_blk; + + remaining_blk = blk; + if (blk_can_split(blk, size)) { + /* We want the 2nd block. */ + remaining_blk = blk_split(blk, size - K_MMHEAP_BLK_HEADER_OVERHEAD); + blk_set_prev_free(remaining_blk); + + blk_link_next(blk); + blk_insert(blk); + } + + return remaining_blk; +} + +__STATIC__ mmheap_blk_t *blk_search_suitable(int *fli, int *sli) +{ + int fl, sl; + uint32_t sl_map, fl_map; + + fl = *fli; + sl = *sli; + + /* + ** First, search for a block in the list associated with the given + ** fl/sl index. + */ + sl_map = k_mmheap_ctl.sl_bitmap[fl] & (~0U << sl); + if (!sl_map) { + /* No block exists. Search in the next largest first-level list. */ + fl_map = k_mmheap_ctl.fl_bitmap & (~0U << (fl + 1)); + if (!fl_map) { + /* No free blocks available, memory has been exhausted. */ + return 0; + } + + fl = __ffs(fl_map); + *fli = fl; + sl_map = k_mmheap_ctl.sl_bitmap[fl]; + } + sl = __ffs(sl_map); + *sli = sl; + + /* Return the first block in the free list. */ + return k_mmheap_ctl.blocks[fl][sl]; +} + +__STATIC__ mmheap_blk_t *blk_locate_free(size_t size) +{ + int fl = 0, sl = 0; + mmheap_blk_t *blk = K_NULL; + + if (!size) { + return K_NULL; + } + + mapping_search(size, &fl, &sl); + + /* + ** mapping_search can futz with the size, so for excessively large sizes it can sometimes wind up + ** with indices that are off the end of the block array. + ** So, we protect against that here, since this is the only callsite of mapping_search. + ** Note that we don't need to check sl, since it comes from a modulo operation that guarantees it's always in range. + */ + if (fl < K_MMHEAP_FL_INDEX_COUNT) { + blk = blk_search_suitable(&fl, &sl); + } + + if (blk) { + remove_free_block(blk, fl, sl); + } + + return blk; +} + +/* +** Adjust an allocation size to be aligned to word size, and no smaller +** than internal minimum. +*/ +__STATIC__ size_t adjust_request_size(size_t size, size_t align) +{ + size_t adjust_size = 0; + + if (!size) { + return 0; + } + + adjust_size = align_up(size, align); + if (!adjust_size || adjust_size > K_MMHEAP_BLK_SIZE_MAX) { + return 0; + } + + /* aligned sized must not exceed block_size_max or we'll go out of bounds on sl_bitmap */ + return adjust_size > K_MMHEAP_BLK_SIZE_MIN ? adjust_size : K_MMHEAP_BLK_SIZE_MIN; +} + +__STATIC__ void *blk_prepare_used(mmheap_blk_t *blk, size_t size) +{ + if (!blk) { + return K_NULL; + } + blk_trim_free(blk, size); + blk_mark_as_used(blk); + return blk_to_ptr(blk); +} + +__STATIC_INLINE__ int mmheap_pool_is_full(void) +{ + return k_mmheap_ctl.pool_cnt == K_MMHEAP_POOL_MAX; +} + +__STATIC__ int mmheap_pool_is_exist(void *pool_start) +{ + int i = 0; + + for (i = 0; i < k_mmheap_ctl.pool_cnt; ++i) { + if (k_mmheap_ctl.pool_start[i] == pool_start) { + return K_TRUE; + } + } + return K_FALSE; +} + +__STATIC_INLINE__ void mmheap_pool_record(void *pool_start) +{ + k_mmheap_ctl.pool_start[k_mmheap_ctl.pool_cnt++] = pool_start; +} + +__STATIC__ void mmheap_pool_unrecord(void *pool_start) +{ + int i = 0; + + for (i = 0; i < k_mmheap_ctl.pool_cnt; ++i) { + if (k_mmheap_ctl.pool_start[i] == pool_start) { + break; + } + } + if (i != k_mmheap_ctl.pool_cnt - 1) { + k_mmheap_ctl.pool_start[i] = k_mmheap_ctl.pool_start[k_mmheap_ctl.pool_cnt - 1]; + } + --k_mmheap_ctl.pool_cnt; +} + +__STATIC__ void mmheap_ctl_init(void) +{ + int i, j; + + k_mmheap_ctl.pool_cnt = 0u; + for (i = 0; i < K_MMHEAP_POOL_MAX; ++i) { + k_mmheap_ctl.pool_start[i] = (void *)K_NULL; + } + + k_mmheap_ctl.block_null.next_free = &k_mmheap_ctl.block_null; + k_mmheap_ctl.block_null.prev_free = &k_mmheap_ctl.block_null; + + k_mmheap_ctl.fl_bitmap = 0; + for (i = 0; i < K_MMHEAP_FL_INDEX_COUNT; ++i) { + k_mmheap_ctl.sl_bitmap[i] = 0; + for (j = 0; j < K_MMHEAP_SL_INDEX_COUNT; ++j) { + k_mmheap_ctl.blocks[i][j] = &k_mmheap_ctl.block_null; + } + } +} + +__KNL__ k_err_t mmheap_init(void) +{ + mmheap_ctl_init(); + return K_ERR_NONE; +} + +__KNL__ k_err_t mmheap_init_with_pool(void *pool_start, size_t pool_size) +{ + mmheap_ctl_init(); + + return tos_mmheap_pool_add(pool_start, pool_size); +} + +__API__ void *tos_mmheap_alloc(size_t size) +{ + size_t adjust_size; + mmheap_blk_t *blk; + + if (size > K_MMHEAP_BLK_SIZE_MAX) { + return K_NULL; + } + + adjust_size = adjust_request_size(size, K_MMHEAP_ALIGN_SIZE); + blk = blk_locate_free(adjust_size); + if (!blk) { + return K_NULL; + } + + return blk_prepare_used(blk, adjust_size); +} + +__API__ void *tos_mmheap_calloc(size_t num, size_t size) +{ + void *ptr; + + ptr = tos_mmheap_alloc(num * size); + if (ptr) { + memset(ptr, 0, num * size); + } + + return ptr; +} + +__API__ void *tos_mmheap_aligned_alloc(size_t size, size_t align) +{ + mmheap_blk_t *blk; + void *ptr, *aligned, *next_aligned; + size_t adjust_size, aligned_size; + size_t gap_minimum, size_with_gap, gap, gap_remain, offset; + + adjust_size = adjust_request_size(size, K_MMHEAP_ALIGN_SIZE); + gap_minimum = sizeof(mmheap_blk_t); + size_with_gap = adjust_request_size(adjust_size + align + gap_minimum, align); + aligned_size = (adjust_size && align > K_MMHEAP_ALIGN_SIZE) ? size_with_gap : adjust_size; + + blk = blk_locate_free(aligned_size); + if (!blk) { + return K_NULL; + } + + ptr = blk_to_ptr(blk); + aligned = align_ptr(ptr, align); + gap = (size_t)((cpu_addr_t)aligned - (cpu_addr_t)ptr); + + if (gap && gap < gap_minimum) { + gap_remain = gap_minimum - gap; + offset = gap_remain > align ? gap_remain : align; + next_aligned = (void *)((cpu_data_t)aligned + offset); + + aligned = align_ptr(next_aligned, align); + gap = (size_t)((cpu_addr_t)aligned - (cpu_addr_t)ptr); + } + + if (gap) { + blk = blk_trim_free_leading(blk, gap); + } + + return blk_prepare_used(blk, adjust_size); +} + +__API__ void tos_mmheap_free(void *ptr) +{ + mmheap_blk_t *blk; + + if (!ptr) { + return; + } + + blk = blk_from_ptr(ptr); + blk_mark_as_free(blk); + blk = blk_merge_prev(blk); + blk = blk_merge_next(blk); + blk_insert(blk); +} + +__API__ void *tos_mmheap_realloc(void *ptr, size_t size) +{ + void *p = 0; + mmheap_blk_t *curr_blk, *next_blk; + size_t curr_size, combined_size, adjust_size, min_size; + + if (ptr && size == 0) { + tos_mmheap_free(ptr); + return K_NULL; + } + + if (!ptr) { + return tos_mmheap_alloc(size); + } + + curr_blk = blk_from_ptr(ptr); + next_blk = blk_next(curr_blk); + + curr_size = blk_size(curr_blk); + combined_size = curr_size + blk_size(next_blk) + K_MMHEAP_BLK_HEADER_OVERHEAD; + adjust_size = adjust_request_size(size, K_MMHEAP_ALIGN_SIZE); + + if (adjust_size > curr_size && (!blk_is_free(next_blk) || adjust_size > combined_size)) { + p = tos_mmheap_alloc(size); + if (p) { + min_size = curr_size < size ? curr_size : size; + memcpy(p, ptr, min_size); + tos_mmheap_free(ptr); + } + } else { + if (adjust_size > curr_size) { + blk_merge_next(curr_blk); + blk_mark_as_used(curr_blk); + } + + blk_trim_used(curr_blk, adjust_size); + p = ptr; + } + + return p; +} + +__API__ k_err_t tos_mmheap_pool_add(void *pool_start, size_t pool_size) +{ + mmheap_blk_t *curr_blk; + mmheap_blk_t *next_blk; + size_t size_aligned; + + if (mmheap_pool_is_full()) { + return K_ERR_MMHEAP_POOL_OVERFLOW; + } + + if (mmheap_pool_is_exist(pool_start)) { + return K_ERR_MMHEAP_POOL_ALREADY_EXIST; + } + + size_aligned = align_down(pool_size - 2 * K_MMHEAP_BLK_HEADER_OVERHEAD, K_MMHEAP_ALIGN_SIZE); + + if (((cpu_addr_t)pool_start % K_MMHEAP_ALIGN_SIZE) != 0u) { + return K_ERR_MMHEAP_INVALID_POOL_ADDR; + } + + if (size_aligned < K_MMHEAP_BLK_SIZE_MIN || + size_aligned > K_MMHEAP_BLK_SIZE_MAX) { + return K_ERR_MMHEAP_INVALID_POOL_SIZE; + } + + /* + ** Create the main free block. Offset the start of the block slightly + ** so that the prev_phys_block field falls outside of the pool - + ** it will never be used. + */ + curr_blk = offset_to_blk(pool_start, -K_MMHEAP_BLK_HEADER_OVERHEAD); + blk_set_size(curr_blk, size_aligned); + blk_set_free(curr_blk); + blk_set_prev_used(curr_blk); + blk_insert(curr_blk); + + /* Split the block to create a zero-size sentinel block. */ + next_blk = blk_link_next(curr_blk); + blk_set_size(next_blk, 0); + blk_set_used(next_blk); + blk_set_prev_free(next_blk); + + mmheap_pool_record(pool_start); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mmheap_pool_rmv(void *pool_start) +{ + int fl = 0, sl = 0; + mmheap_blk_t *blk; + + TOS_PTR_SANITY_CHECK(pool_start); + + if (!mmheap_pool_is_exist(pool_start)) { + return K_ERR_MMHEAP_POOL_NOT_EXIST; + } + + blk = offset_to_blk(pool_start, -K_MMHEAP_BLK_HEADER_OVERHEAD); + mapping_insert(blk_size(blk), &fl, &sl); + remove_free_block(blk, fl, sl); + + mmheap_pool_unrecord(pool_start); + return K_ERR_NONE; +} + +__API__ k_err_t tos_mmheap_pool_check(void *pool_start, k_mmheap_info_t *info) +{ + mmheap_blk_t* blk; + + TOS_PTR_SANITY_CHECK(pool_start); + TOS_PTR_SANITY_CHECK(info); + + memset(info, 0, sizeof(k_mmheap_info_t)); + + blk = offset_to_blk(pool_start, -K_MMHEAP_BLK_HEADER_OVERHEAD); + + while (blk && !blk_is_last(blk)) { + if (blk_is_free(blk)) { + info->free += blk_size(blk); + } else { + info->used += blk_size(blk); + } + blk = blk_next(blk); + } + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mmheap_check(k_mmheap_info_t *info) +{ + int i; + k_err_t err; + k_mmheap_info_t pool_info; + + TOS_PTR_SANITY_CHECK(info); + + memset(info, 0, sizeof(k_mmheap_info_t)); + + for (i = 0; i < k_mmheap_ctl.pool_cnt; ++i) { + err = tos_mmheap_pool_check(k_mmheap_ctl.pool_start[i], &pool_info); + if (err != K_ERR_NONE) { + return err; + } + + info->free += pool_info.free; + info->used += pool_info.used; + } + + return K_ERR_NONE; +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_mutex.c b/TencentOS_Tiny/kernel/core/tos_mutex.c new file mode 100644 index 0000000..e19085f --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_mutex.c @@ -0,0 +1,242 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_MUTEX_EN > 0u + +__STATIC_INLINE__ void mutex_old_owner_release(k_mutex_t *mutex) +{ + k_task_t *owner; + + owner = mutex->owner; + + tos_list_del(&mutex->owner_anchor); + mutex->owner = K_NULL; + mutex->pend_nesting = (k_nesting_t)0u; + + // the right time comes! let's do it! + if (owner->prio_pending != K_TASK_PRIO_INVALID) { + tos_task_prio_change(owner, owner->prio_pending); + owner->prio_pending = K_TASK_PRIO_INVALID; + } else if (owner->prio != mutex->owner_orig_prio) { + tos_task_prio_change(owner, mutex->owner_orig_prio); + mutex->owner_orig_prio = K_TASK_PRIO_INVALID; + } +} + +__STATIC_INLINE__ void mutex_fresh_owner_mark(k_mutex_t *mutex, k_task_t *task) +{ + mutex->owner = task; + mutex->owner_orig_prio = task->prio; + mutex->pend_nesting = (k_nesting_t)1u; + + tos_list_add(&mutex->owner_anchor, &task->mutex_own_list); +} + +__STATIC_INLINE__ void mutex_new_owner_mark(k_mutex_t *mutex, k_task_t *task) +{ + k_prio_t highest_pending_prio; + + mutex_fresh_owner_mark(mutex, task); + + // we own the mutex now, make sure our priority is higher than any one in the pend list. + highest_pending_prio = pend_highest_pending_prio_get(&mutex->pend_obj); + if (task->prio > highest_pending_prio) { + tos_task_prio_change(task, highest_pending_prio); + } +} + +__KNL__ void mutex_release(k_mutex_t *mutex) +{ + mutex_old_owner_release(mutex); + pend_wakeup_all(&mutex->pend_obj, PEND_STATE_OWNER_DIE); +} + +__API__ k_err_t tos_mutex_create(k_mutex_t *mutex) +{ + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mutex); + + pend_object_init(&mutex->pend_obj); + mutex->pend_nesting = (k_nesting_t)0u; + mutex->owner = K_NULL; + mutex->owner_orig_prio = K_TASK_PRIO_INVALID; + tos_list_init(&mutex->owner_anchor); + + TOS_OBJ_INIT(mutex, KNL_OBJ_TYPE_MUTEX); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mutex_create_dyn(k_mutex_t **mutex) +{ + k_mutex_t *the_mutex; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mutex); + + the_mutex = tos_mmheap_calloc(1, sizeof(k_mutex_t)); + if (!the_mutex) { + return K_ERR_MUTEX_OUT_OF_MEMORY; + } + + pend_object_init(&the_mutex->pend_obj); + the_mutex->pend_nesting = (k_nesting_t)0u; + the_mutex->owner = K_NULL; + the_mutex->owner_orig_prio = K_TASK_PRIO_INVALID; + tos_list_init(&the_mutex->owner_anchor); + TOS_OBJ_INIT(the_mutex, KNL_OBJ_TYPE_MUTEX); + + knl_object_alloc_set_dynamic(&the_mutex->knl_obj); + + *mutex = the_mutex; + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mutex_destroy(k_mutex_t *mutex) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mutex); + TOS_OBJ_VERIFY(mutex, KNL_OBJ_TYPE_MUTEX); + + TOS_CPU_INT_DISABLE(); + + pend_wakeup_all(&mutex->pend_obj, PEND_STATE_DESTROY); + + if (mutex->owner) { + mutex_old_owner_release(mutex); + } + + pend_object_deinit(&mutex->pend_obj); + + if (knl_object_alloc_is_dynamic(&mutex->knl_obj)) { + TOS_OBJ_DEINIT(mutex); + tos_mmheap_free(mutex); + } else { + TOS_OBJ_DEINIT(mutex); + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_mutex_pend_timed(k_mutex_t *mutex, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mutex); + TOS_OBJ_VERIFY(mutex, KNL_OBJ_TYPE_MUTEX); + + TOS_CPU_INT_DISABLE(); + if (mutex->pend_nesting == (k_nesting_t)0u) { // first come + mutex_fresh_owner_mark(mutex, k_curr_task); + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (knl_is_self(mutex->owner)) { // come again + if (mutex->pend_nesting == (k_nesting_t)-1) { + TOS_CPU_INT_ENABLE(); + return K_ERR_MUTEX_NESTING_OVERFLOW; + } + ++mutex->pend_nesting; + TOS_CPU_INT_ENABLE(); + return K_ERR_MUTEX_NESTING; + } + + if (timeout == TOS_TIME_NOWAIT) { // no wait, return immediately + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + if (mutex->owner->prio > k_curr_task->prio) { + // PRIORITY INVERSION: + // we are declaring a mutex, which's owner has a lower(numerically bigger) priority. + // make owner the same priority with us. + tos_task_prio_change(mutex->owner, k_curr_task->prio); + } + + pend_task_block(k_curr_task, &mutex->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return pend_state2errno(k_curr_task->pend_state); +} + +__API__ k_err_t tos_mutex_pend(k_mutex_t *mutex) +{ + return tos_mutex_pend_timed(mutex, TOS_TIME_FOREVER); +} + +__API__ k_err_t tos_mutex_post(k_mutex_t *mutex) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *pending_task; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(mutex); + TOS_OBJ_VERIFY(mutex, KNL_OBJ_TYPE_MUTEX); + + TOS_CPU_INT_DISABLE(); + if (!knl_is_self(mutex->owner)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_MUTEX_NOT_OWNER; + } + + --mutex->pend_nesting; + if (mutex->pend_nesting > (k_nesting_t)0u) { + TOS_CPU_INT_ENABLE(); + return K_ERR_MUTEX_NESTING; + } + + mutex_old_owner_release(mutex); + + if (pend_is_nopending(&mutex->pend_obj)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + /* must do the mutex owner switch right here + if the pender don't get a chance to schedule, the poster(old owner) may obtain the mutex immediately again + but the pender already get ready(already in the critical section). + we switch the owner right here to avoid the old owner obtain the mutex again + */ + pending_task = pend_highest_pending_task_get(&mutex->pend_obj); + mutex_new_owner_mark(mutex, pending_task); + + pend_wakeup_one(&mutex->pend_obj, PEND_STATE_POST); + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_pend.c b/TencentOS_Tiny/kernel/core/tos_pend.c new file mode 100644 index 0000000..9cf4d2c --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_pend.c @@ -0,0 +1,152 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC__ void pend_list_add(k_task_t *task, pend_obj_t *pend_obj) +{ + k_task_t *iter; + + /* keep priority in descending order, the boss(task with highest priority, + numerically smallest) always comes first + */ + TOS_LIST_FOR_EACH_ENTRY(iter, k_task_t, pend_list, &pend_obj->list) { + if (task->prio < iter->prio) { + break; + } + } + tos_list_add_tail(&task->pend_list, &iter->pend_list); + + // remember me, you may use me someday + task->pending_obj = pend_obj; + task_state_set_pend(task); +} + +__KNL__ k_prio_t pend_highest_pending_prio_get(pend_obj_t *object) +{ + k_task_t *task; + + // we keep the task priority in descending order, so the first one is just fine. + task = TOS_LIST_FIRST_ENTRY_OR_NULL(&object->list, k_task_t, pend_list); + return task ? task->prio : K_TASK_PRIO_INVALID; +} + +__KNL__ k_task_t *pend_highest_pending_task_get(pend_obj_t *object) +{ + return TOS_LIST_FIRST_ENTRY(&object->list, k_task_t, pend_list); +} + +__KNL__ void pend_list_remove(k_task_t *task) +{ + tos_list_del(&task->pend_list); + + task->pending_obj = (pend_obj_t *)K_NULL; + task_state_reset_pending(task); +} + +__KNL__ void pend_object_init(pend_obj_t *object) +{ + tos_list_init(&object->list); +} + +__KNL__ void pend_object_deinit(pend_obj_t *object) +{ + tos_list_init(&object->list); +} + +__KNL__ int pend_is_nopending(pend_obj_t *object) +{ + return tos_list_empty(&object->list); +} + +__KNL__ void pend_list_adjust(k_task_t *task) +{ + // we may be the boss, so re-enter the pend list + tos_list_del(&task->pend_list); + // the "someday" comes + pend_list_add(task, task->pending_obj); +} + +__KNL__ k_err_t pend_state2errno(pend_state_t state) +{ + if (state == PEND_STATE_POST) { + return K_ERR_NONE; + } else if (state == PEND_STATE_TIMEOUT) { + return K_ERR_PEND_TIMEOUT; + } else if (state == PEND_STATE_DESTROY) { + return K_ERR_PEND_DESTROY; + } else if (state == PEND_STATE_OWNER_DIE) { + return K_ERR_PEND_OWNER_DIE; + } else { + return K_ERR_PEND_ABNORMAL; + } +} + +__KNL__ void pend_task_wakeup(k_task_t *task, pend_state_t state) +{ + if (task_state_is_pending(task)) { + // mark why we wakeup + task->pend_state = state; + pend_list_remove(task); + } + + if (task_state_is_sleeping(task)) { + tick_list_remove(task); + } + + if (task_state_is_suspended(task)) { + return; + } + + readyqueue_add(task); +} + +__KNL__ void pend_task_block(k_task_t *task, pend_obj_t *object, k_tick_t timeout) +{ + readyqueue_remove(task); + + task->pend_state = PEND_STATE_NONE; + pend_list_add(task, object); + + if (timeout != TOS_TIME_FOREVER) { + tick_list_add(task, timeout); + } +} + +__KNL__ void pend_wakeup_one(pend_obj_t *object, pend_state_t state) +{ + pend_task_wakeup(TOS_LIST_FIRST_ENTRY(&object->list, k_task_t, pend_list), state); +} + +__KNL__ void pend_wakeup_all(pend_obj_t *object, pend_state_t state) +{ + k_task_t *task, *tmp; + + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, pend_list, &object->list) { + pend_task_wakeup(task, state); + } +} + +__KNL__ void pend_wakeup(pend_obj_t *object, pend_state_t state, opt_post_t opt) +{ + if (opt == OPT_POST_ONE) { + pend_wakeup_one(object, state); + } else { + pend_wakeup_all(object, state); + } +} + diff --git a/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.c b/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.c new file mode 100644 index 0000000..cba5ecc --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.c @@ -0,0 +1,244 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_PRIORITY_MAIL_QUEUE_EN > 0u + +__API__ k_err_t tos_prio_mail_q_create(k_prio_mail_q_t *prio_mail_q, void *pool, size_t mail_cnt, size_t mail_size) +{ + k_err_t err; + void *prio_q_mgr_array = K_NULL; + + TOS_PTR_SANITY_CHECK(prio_mail_q); + + prio_q_mgr_array = tos_mmheap_alloc(TOS_PRIO_Q_MGR_ARRAY_SIZE(mail_cnt)); + if (!prio_q_mgr_array) { + return K_ERR_OUT_OF_MEMORY; + } + + err = tos_prio_q_create(&prio_mail_q->prio_q, prio_q_mgr_array, pool, mail_cnt, mail_size); + if (err != K_ERR_NONE) { + tos_mmheap_free(prio_q_mgr_array); + return err; + } + + prio_mail_q->prio_q_mgr_array = prio_q_mgr_array; + pend_object_init(&prio_mail_q->pend_obj); + + TOS_OBJ_INIT(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + knl_object_alloc_set_static(&prio_mail_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_mail_q_destroy(k_prio_mail_q_t *prio_mail_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(prio_mail_q); + TOS_OBJ_VERIFY(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + + if (!knl_object_alloc_is_static(&prio_mail_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_prio_q_destroy(&prio_mail_q->prio_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&prio_mail_q->pend_obj, PEND_STATE_DESTROY); + + tos_mmheap_free(prio_mail_q->prio_q_mgr_array); + prio_mail_q->prio_q_mgr_array = K_NULL; + + pend_object_deinit(&prio_mail_q->pend_obj); + + TOS_OBJ_DEINIT(prio_mail_q); + knl_object_alloc_reset(&prio_mail_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_mail_q_create_dyn(k_prio_mail_q_t *prio_mail_q, size_t mail_cnt, size_t mail_size) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(prio_mail_q); + + err = tos_prio_q_create_dyn(&prio_mail_q->prio_q, mail_cnt, mail_size); + if (err != K_ERR_NONE) { + return err; + } + + pend_object_init(&prio_mail_q->pend_obj); + + TOS_OBJ_INIT(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + knl_object_alloc_set_dynamic(&prio_mail_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_mail_q_destroy_dyn(k_prio_mail_q_t *prio_mail_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(prio_mail_q); + TOS_OBJ_VERIFY(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + + if (!knl_object_alloc_is_dynamic(&prio_mail_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_prio_q_destroy_dyn(&prio_mail_q->prio_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&prio_mail_q->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&prio_mail_q->pend_obj); + + TOS_OBJ_DEINIT(prio_mail_q); + knl_object_alloc_reset(&prio_mail_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_mail_q_flush(k_prio_mail_q_t *prio_mail_q) +{ + TOS_PTR_SANITY_CHECK(prio_mail_q); + TOS_OBJ_VERIFY(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + + return tos_prio_q_flush(&prio_mail_q->prio_q); +} + +__API__ k_err_t tos_prio_mail_q_pend(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t *mail_size, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(prio_mail_q); + TOS_PTR_SANITY_CHECK(mail_buf); + TOS_OBJ_VERIFY(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (tos_prio_q_dequeue(&prio_mail_q->prio_q, mail_buf, mail_size, K_NULL) == K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { + *mail_size = 0; + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + k_curr_task->mail = mail_buf; + pend_task_block(k_curr_task, &prio_mail_q->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + err = pend_state2errno(k_curr_task->pend_state); + if (err == K_ERR_NONE) { + *mail_size = k_curr_task->mail_size; + k_curr_task->mail = K_NULL; + k_curr_task->mail_size = 0; + } + + return err; +} + +__STATIC__ void prio_mail_task_recv(k_task_t *task, void *mail_buf, size_t mail_size) +{ + memcpy(task->mail, mail_buf, mail_size); + task->mail_size = mail_size; + pend_task_wakeup(task, PEND_STATE_POST); +} + +__STATIC__ k_err_t prio_mail_q_do_post(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t mail_size, k_prio_t prio, opt_post_t opt) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + k_task_t *task, *tmp; + + TOS_PTR_SANITY_CHECK(prio_mail_q); + TOS_PTR_SANITY_CHECK(mail_buf); + TOS_OBJ_VERIFY(prio_mail_q, KNL_OBJ_TYPE_PRIORITY_MAIL_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (pend_is_nopending(&prio_mail_q->pend_obj)) { + err = tos_prio_q_enqueue(&prio_mail_q->prio_q, mail_buf, mail_size, prio); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (opt == OPT_POST_ONE) { + prio_mail_task_recv(TOS_LIST_FIRST_ENTRY(&prio_mail_q->pend_obj.list, k_task_t, pend_list), + mail_buf, mail_size); + } else { // OPT_POST_ALL + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, pend_list, &prio_mail_q->pend_obj.list) { + prio_mail_task_recv(task, mail_buf, mail_size); + } + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_mail_q_post(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t mail_size, k_prio_t prio) +{ + return prio_mail_q_do_post(prio_mail_q, mail_buf, mail_size, prio, OPT_POST_ONE); +} + +__API__ k_err_t tos_prio_mail_q_post_all(k_prio_mail_q_t *prio_mail_q, void *mail_buf, size_t mail_size, k_prio_t prio) +{ + return prio_mail_q_do_post(prio_mail_q, mail_buf, mail_size, prio, OPT_POST_ALL); +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_priority_message_queue.c b/TencentOS_Tiny/kernel/core/tos_priority_message_queue.c new file mode 100644 index 0000000..07925f0 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_priority_message_queue.c @@ -0,0 +1,242 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN > 0u + +__API__ k_err_t tos_prio_msg_q_create(k_prio_msg_q_t *prio_msg_q, void *pool, size_t msg_cnt) +{ + k_err_t err; + void *prio_q_mgr_array = K_NULL; + + TOS_PTR_SANITY_CHECK(prio_msg_q); + + prio_q_mgr_array = tos_mmheap_alloc(TOS_PRIO_Q_MGR_ARRAY_SIZE(msg_cnt)); + if (!prio_q_mgr_array) { + return K_ERR_OUT_OF_MEMORY; + } + + err = tos_prio_q_create(&prio_msg_q->prio_q, prio_q_mgr_array, pool, msg_cnt, sizeof(void *)); + if (err != K_ERR_NONE) { + tos_mmheap_free(prio_q_mgr_array); + return err; + } + + prio_msg_q->prio_q_mgr_array = prio_q_mgr_array; + pend_object_init(&prio_msg_q->pend_obj); + + TOS_OBJ_INIT(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + knl_object_alloc_set_static(&prio_msg_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_msg_q_destroy(k_prio_msg_q_t *prio_msg_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(prio_msg_q); + TOS_OBJ_VERIFY(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + + if (!knl_object_alloc_is_static(&prio_msg_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_prio_q_destroy(&prio_msg_q->prio_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&prio_msg_q->pend_obj, PEND_STATE_DESTROY); + + tos_mmheap_free(prio_msg_q->prio_q_mgr_array); + prio_msg_q->prio_q_mgr_array = K_NULL; + + pend_object_deinit(&prio_msg_q->pend_obj); + + TOS_OBJ_DEINIT(prio_msg_q); + knl_object_alloc_reset(&prio_msg_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_msg_q_create_dyn(k_prio_msg_q_t *prio_msg_q, size_t msg_cnt) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(prio_msg_q); + + err = tos_prio_q_create_dyn(&prio_msg_q->prio_q, msg_cnt, sizeof(void *)); + if (err != K_ERR_NONE) { + return err; + } + + pend_object_init(&prio_msg_q->pend_obj); + + TOS_OBJ_INIT(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + knl_object_alloc_set_dynamic(&prio_msg_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_msg_q_destroy_dyn(k_prio_msg_q_t *prio_msg_q) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_PTR_SANITY_CHECK(prio_msg_q); + TOS_OBJ_VERIFY(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + + if (!knl_object_alloc_is_dynamic(&prio_msg_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + TOS_CPU_INT_DISABLE(); + + err = tos_prio_q_destroy_dyn(&prio_msg_q->prio_q); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + + pend_wakeup_all(&prio_msg_q->pend_obj, PEND_STATE_DESTROY); + + tos_mmheap_free(prio_msg_q->prio_q_mgr_array); + prio_msg_q->prio_q_mgr_array = K_NULL; + + pend_object_deinit(&prio_msg_q->pend_obj); + + TOS_OBJ_DEINIT(prio_msg_q); + knl_object_alloc_reset(&prio_msg_q->knl_obj); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_msg_q_flush(k_prio_msg_q_t *prio_msg_q) +{ + TOS_PTR_SANITY_CHECK(prio_msg_q); + TOS_OBJ_VERIFY(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + + return tos_prio_q_flush(&prio_msg_q->prio_q); +} + +__API__ k_err_t tos_prio_msg_q_pend(k_prio_msg_q_t *prio_msg_q, void **msg_ptr, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(prio_msg_q); + TOS_PTR_SANITY_CHECK(msg_ptr); + TOS_OBJ_VERIFY(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (tos_prio_q_dequeue(&prio_msg_q->prio_q, msg_ptr, K_NULL, K_NULL) == K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { + *msg_ptr = K_NULL; + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + pend_task_block(k_curr_task, &prio_msg_q->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + err = pend_state2errno(k_curr_task->pend_state); + if (err == K_ERR_NONE) { + *msg_ptr = k_curr_task->msg; + k_curr_task->msg = K_NULL; + } + + return err; +} + +__STATIC__ void prio_msg_q_task_recv(k_task_t *task, void *msg_ptr) +{ + task->msg = msg_ptr; + pend_task_wakeup(task, PEND_STATE_POST); +} + +__STATIC__ k_err_t prio_msg_q_do_post(k_prio_msg_q_t *prio_msg_q, void *msg_ptr, k_prio_t prio, opt_post_t opt) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t err; + k_task_t *task, *tmp; + + TOS_PTR_SANITY_CHECK(prio_msg_q); + TOS_OBJ_VERIFY(prio_msg_q, KNL_OBJ_TYPE_PRIORITY_MESSAGE_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (pend_is_nopending(&prio_msg_q->pend_obj)) { + err = tos_prio_q_enqueue(&prio_msg_q->prio_q, &msg_ptr, sizeof(void *), prio); + if (err != K_ERR_NONE) { + TOS_CPU_INT_ENABLE(); + return err; + } + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (opt == OPT_POST_ONE) { + prio_msg_q_task_recv(TOS_LIST_FIRST_ENTRY(&prio_msg_q->pend_obj.list, k_task_t, pend_list), msg_ptr); + } else { // OPT_POST_ALL + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, pend_list, &prio_msg_q->pend_obj.list) { + prio_msg_q_task_recv(task, msg_ptr); + } + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_msg_q_post(k_prio_msg_q_t *prio_msg_q, void *msg_ptr, k_prio_t prio) +{ + return prio_msg_q_do_post(prio_msg_q, msg_ptr, prio, OPT_POST_ONE); +} + +__API__ k_err_t tos_prio_msg_q_post_all(k_prio_msg_q_t *prio_msg_q, void *msg_ptr, k_prio_t prio) +{ + return prio_msg_q_do_post(prio_msg_q, msg_ptr, prio, OPT_POST_ALL); +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_priority_queue.c b/TencentOS_Tiny/kernel/core/tos_priority_queue.c new file mode 100644 index 0000000..e6dc6b6 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_priority_queue.c @@ -0,0 +1,377 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC_INLINE__ void prio_q_item_copy_to(k_prio_q_t *prio_q, void *item_out, size_t *item_size, prio_q_slot_t slot) +{ + memcpy(item_out, PRIO_Q_THE_ITEM(prio_q, slot), prio_q->item_size); + if (item_size) { + *item_size = prio_q->item_size; + } +} + +__STATIC_INLINE__ void prio_q_item_copy_from(k_prio_q_t *prio_q, void *item_in, prio_q_slot_t slot) +{ + memcpy(PRIO_Q_THE_ITEM(prio_q, slot), item_in, prio_q->item_size); +} + +__STATIC_INLINE__ void prio_q_item_increase(k_prio_q_t *prio_q) +{ + ++prio_q->total; +} + +__STATIC_INLINE__ void prio_q_item_decrease(k_prio_q_t *prio_q) +{ + --prio_q->total; +} + +__STATIC__ void prio_q_pool_mgr_init(prio_q_pool_mgr_t *pool_mgr, prio_q_pool_mgr_ent_t *pool_mgr_ent_array, size_t item_cnt) +{ + prio_q_slot_t i; + + pool_mgr->first_free = (prio_q_slot_t)0u; + pool_mgr->pool_mgr_ent_array = pool_mgr_ent_array; + + for (i = 0; i < item_cnt; ++i) { + pool_mgr_ent_array[i].next = i + 1; + } + pool_mgr_ent_array[item_cnt - 1].next = PRIO_Q_POOL_SLOT_INVALID; +} + +__STATIC__ void prio_q_pool_mgr_reset(prio_q_pool_mgr_t *pool_mgr, size_t item_cnt) +{ + prio_q_slot_t i; + prio_q_pool_mgr_ent_t *pool_mgr_ent_array; + + pool_mgr->first_free = (prio_q_slot_t)0u; + pool_mgr_ent_array = pool_mgr->pool_mgr_ent_array; + + for (i = 0; i < item_cnt; ++i) { + pool_mgr_ent_array[i].next = i + 1; + } + pool_mgr_ent_array[item_cnt - 1].next = PRIO_Q_POOL_SLOT_INVALID; +} + +__STATIC__ void prio_q_pool_mgr_deinit(prio_q_pool_mgr_t *pool_mgr) +{ + pool_mgr->first_free = (prio_q_slot_t)0u; + pool_mgr->pool_mgr_ent_array = K_NULL; +} + +__STATIC__ int prio_q_mgr_entry_cmp(void *first, void *second) +{ + prio_q_prio_mgr_ent_t *first_entry, *second_entry; + + first_entry = (prio_q_prio_mgr_ent_t *)first; + second_entry = (prio_q_prio_mgr_ent_t *)second; + + // numerically bigger, actually smaller, we build a minimal binary heap here + if (first_entry->priority < second_entry->priority) { + return K_TRUE; + } + return K_FALSE; +} + +__STATIC__ void prio_q_prio_mgr_init(prio_q_prio_mgr_t *prio_mgr, prio_q_prio_mgr_ent_t *prio_mgr_ent_pool, size_t item_cnt) +{ + prio_mgr->prio_mgr_ent_pool = prio_mgr_ent_pool; + tos_bin_heap_create(&prio_mgr->prio_mgr_bin_heap, prio_mgr_ent_pool, item_cnt, sizeof(prio_q_prio_mgr_ent_t), prio_q_mgr_entry_cmp); +} + +__STATIC__ void prio_q_prio_mgr_reset(prio_q_prio_mgr_t *prio_mgr) +{ + tos_bin_heap_flush(&prio_mgr->prio_mgr_bin_heap); +} + +__STATIC__ void prio_q_prio_mgr_deinit(prio_q_prio_mgr_t *prio_mgr) +{ + prio_mgr->prio_mgr_ent_pool = K_NULL; + tos_bin_heap_destroy(&prio_mgr->prio_mgr_bin_heap); +} + +__STATIC__ prio_q_slot_t prio_q_pool_mgr_slot_alloc(prio_q_pool_mgr_t *pool_mgr) +{ + prio_q_slot_t fresh; + prio_q_pool_mgr_ent_t *first_free; + + if (pool_mgr->first_free == PRIO_Q_POOL_SLOT_INVALID) { + return PRIO_Q_POOL_SLOT_INVALID; + } + + fresh = pool_mgr->first_free; + first_free = &pool_mgr->pool_mgr_ent_array[pool_mgr->first_free]; + pool_mgr->first_free = first_free->next; + + return fresh; +} + +__STATIC__ void prio_q_pool_mgr_slot_free(prio_q_pool_mgr_t *pool_mgr, prio_q_slot_t slot) +{ + prio_q_pool_mgr_ent_t *slot_entry; + + slot_entry = &pool_mgr->pool_mgr_ent_array[slot]; + slot_entry->next = pool_mgr->first_free; + pool_mgr->first_free = slot; +} + +__STATIC__ void prio_q_prio_mgr_slot_enqueue(prio_q_prio_mgr_t *prio_mgr, prio_q_slot_t slot, k_prio_t prio) +{ + k_err_t err; + prio_q_prio_mgr_ent_t prio_mgr_entry; + + prio_mgr_entry.priority = prio; + prio_mgr_entry.slot = slot; + + err = tos_bin_heap_push(&prio_mgr->prio_mgr_bin_heap, &prio_mgr_entry, sizeof(prio_q_prio_mgr_ent_t)); + TOS_ASSERT(err == K_ERR_NONE); +} + +__STATIC__ prio_q_slot_t prio_q_prio_mgr_slot_dequeue(prio_q_prio_mgr_t *prio_mgr, k_prio_t *prio) +{ + k_err_t err; + size_t dummy; + prio_q_prio_mgr_ent_t prio_mgr_entry; + + err = tos_bin_heap_pop(&prio_mgr->prio_mgr_bin_heap, &prio_mgr_entry, &dummy); + TOS_ASSERT(err == K_ERR_NONE); + TOS_ASSERT(dummy == sizeof(prio_q_prio_mgr_ent_t)); + + if (prio) { + *prio = prio_mgr_entry.priority; + } + + return prio_mgr_entry.slot; +} + +__API__ k_err_t tos_prio_q_create(k_prio_q_t *prio_q, void *mgr_array, void *pool, size_t item_cnt, size_t item_size) +{ + prio_q_pool_mgr_ent_t *pool_mgr_ent_array; + prio_q_prio_mgr_ent_t *prio_mgr_ent_pool; + + TOS_PTR_SANITY_CHECK(prio_q); + TOS_PTR_SANITY_CHECK(mgr_array); + TOS_PTR_SANITY_CHECK(pool); + + pool_mgr_ent_array = (prio_q_pool_mgr_ent_t *)mgr_array; + prio_mgr_ent_pool = (prio_q_prio_mgr_ent_t *)((uint8_t *)mgr_array + PRIO_Q_POOL_MGR_ENT_ARRAY_SIZE(item_cnt)); + + prio_q_pool_mgr_init(&prio_q->pool_mgr, pool_mgr_ent_array, item_cnt); + prio_q_prio_mgr_init(&prio_q->prio_mgr, prio_mgr_ent_pool, item_cnt); + + prio_q->total = 0; + prio_q->item_size = item_size; + prio_q->item_cnt = item_cnt; + prio_q->mgr_pool = (uint8_t *)mgr_array; + prio_q->data_pool = (uint8_t *)pool; + + TOS_OBJ_INIT(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE); + knl_object_alloc_set_static(&prio_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_q_destroy(k_prio_q_t *prio_q) +{ + TOS_PTR_SANITY_CHECK(prio_q); + TOS_OBJ_VERIFY(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE); + + if (!knl_object_alloc_is_static(&prio_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + prio_q_pool_mgr_deinit(&prio_q->pool_mgr); + prio_q_prio_mgr_deinit(&prio_q->prio_mgr); + + prio_q->total = 0; + prio_q->item_size = 0; + prio_q->item_cnt = 0; + prio_q->mgr_pool = K_NULL; + prio_q->data_pool = K_NULL; + + TOS_OBJ_DEINIT(prio_q); + knl_object_alloc_reset(&prio_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_q_create_dyn(k_prio_q_t *prio_q, size_t item_cnt, size_t item_size) +{ + k_err_t err; + void *mgr_pool, *data_pool; + + TOS_PTR_SANITY_CHECK(prio_q); + + mgr_pool = tos_mmheap_alloc(TOS_PRIO_Q_MGR_ARRAY_SIZE(item_cnt)); + if (!mgr_pool) { + return K_ERR_OUT_OF_MEMORY; + } + + data_pool = tos_mmheap_alloc(item_cnt * item_size); + if (!data_pool) { + tos_mmheap_free(mgr_pool); + return K_ERR_OUT_OF_MEMORY; + } + + err = tos_prio_q_create(prio_q, mgr_pool, data_pool, item_cnt, item_size); + if (err != K_ERR_NONE) { + tos_mmheap_free(data_pool); + tos_mmheap_free(mgr_pool); + } + + knl_object_alloc_set_dynamic(&prio_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_q_destroy_dyn(k_prio_q_t *prio_q) +{ + TOS_PTR_SANITY_CHECK(prio_q); + TOS_OBJ_VERIFY(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE); + + if (!knl_object_alloc_is_dynamic(&prio_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + prio_q_pool_mgr_deinit(&prio_q->pool_mgr); + prio_q_prio_mgr_deinit(&prio_q->prio_mgr); + + tos_mmheap_free(prio_q->mgr_pool); + tos_mmheap_free(prio_q->data_pool); + + prio_q->total = 0; + prio_q->item_size = 0; + prio_q->item_cnt = 0; + prio_q->mgr_pool = K_NULL; + prio_q->data_pool = K_NULL; + + TOS_OBJ_DEINIT(prio_q); + knl_object_alloc_reset(&prio_q->knl_obj); + + return K_ERR_NONE; +} + +__STATIC__ void prio_q_do_enqueue(k_prio_q_t *prio_q, void *item, prio_q_slot_t slot, k_prio_t prio) +{ + prio_q_item_copy_from(prio_q, item, slot); + prio_q_prio_mgr_slot_enqueue(&prio_q->prio_mgr, slot, prio); + prio_q_item_increase(prio_q); +} + +__API__ k_err_t tos_prio_q_enqueue(k_prio_q_t *prio_q, void *item, size_t item_size, k_prio_t prio) +{ + TOS_CPU_CPSR_ALLOC(); + prio_q_slot_t the_slot; + + TOS_PTR_SANITY_CHECK(prio_q); + TOS_PTR_SANITY_CHECK(item); + TOS_OBJ_VERIFY(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE); + + if (item_size != prio_q->item_size) { + return K_ERR_PRIO_Q_ITEM_SIZE_NOT_MATCH; + } + + if (tos_prio_q_is_full(prio_q)) { + return K_ERR_PRIO_Q_FULL; + } + + TOS_CPU_INT_DISABLE(); + + the_slot = prio_q_pool_mgr_slot_alloc(&prio_q->pool_mgr); + TOS_ASSERT(the_slot != PRIO_Q_POOL_SLOT_INVALID); + prio_q_do_enqueue(prio_q, item, the_slot, prio); + + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__STATIC__ void prio_q_do_dequeue(k_prio_q_t *prio_q, void *item, size_t *item_size, prio_q_slot_t slot) +{ + prio_q_pool_mgr_slot_free(&prio_q->pool_mgr, slot); + prio_q_item_copy_to(prio_q, item, item_size, slot); + prio_q_item_decrease(prio_q); +} + +__API__ k_err_t tos_prio_q_dequeue(k_prio_q_t *prio_q, void *item, size_t *item_size, k_prio_t *prio) +{ + TOS_CPU_CPSR_ALLOC(); + prio_q_slot_t the_slot; + + TOS_PTR_SANITY_CHECK(prio_q); + TOS_PTR_SANITY_CHECK(item); + TOS_OBJ_VERIFY(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE); + + if (tos_prio_q_is_empty(prio_q)) { + return K_ERR_PRIO_Q_EMPTY; + } + + TOS_CPU_INT_DISABLE(); + + the_slot = prio_q_prio_mgr_slot_dequeue(&prio_q->prio_mgr, prio); + prio_q_do_dequeue(prio_q, item, item_size, the_slot); + + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__API__ k_err_t tos_prio_q_flush(k_prio_q_t *prio_q) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(prio_q); + TOS_OBJ_VERIFY(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE); + + TOS_CPU_INT_DISABLE(); + + prio_q_pool_mgr_reset(&prio_q->pool_mgr, prio_q->item_cnt); + prio_q_prio_mgr_reset(&prio_q->prio_mgr); + prio_q->total = 0; + + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__API__ int tos_prio_q_is_empty(k_prio_q_t *prio_q) +{ + TOS_CPU_CPSR_ALLOC(); + int is_empty = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(prio_q, K_FALSE); + TOS_OBJ_VERIFY_RC(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_empty = (prio_q->total == 0); + TOS_CPU_INT_ENABLE(); + + return is_empty; +} + +__API__ int tos_prio_q_is_full(k_prio_q_t *prio_q) +{ + TOS_CPU_CPSR_ALLOC(); + int is_full = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(prio_q, K_FALSE); + TOS_OBJ_VERIFY_RC(prio_q, KNL_OBJ_TYPE_PRIORITY_QUEUE, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_full = (prio_q->total == prio_q->item_cnt); + TOS_CPU_INT_ENABLE(); + + return is_full; +} + diff --git a/TencentOS_Tiny/kernel/core/tos_ring_queue.c b/TencentOS_Tiny/kernel/core/tos_ring_queue.c new file mode 100644 index 0000000..fd3f8b7 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_ring_queue.c @@ -0,0 +1,233 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC_INLINE__ void ring_q_item_copy_to(k_ring_q_t *ring_q, void *item_out, size_t *item_size) +{ + memcpy(item_out, RING_HEAD_ITEM(ring_q), ring_q->item_size); + if (item_size) { + *item_size = ring_q->item_size; + } +} + +__STATIC_INLINE__ void ring_q_item_copy_from(k_ring_q_t *ring_q, void *item_in) +{ + memcpy(RING_TAIL_ITEM(ring_q), item_in, ring_q->item_size); +} + +__STATIC_INLINE__ void ring_q_item_increase(k_ring_q_t *ring_q) +{ + ring_q->tail = RING_NEXT(ring_q, ring_q->tail); + ++ring_q->total; +} + +__STATIC_INLINE__ void ring_q_item_decrease(k_ring_q_t *ring_q) +{ + ring_q->head = RING_NEXT(ring_q, ring_q->head); + --ring_q->total; +} + + __API__ k_err_t tos_ring_q_create(k_ring_q_t *ring_q, void *pool, size_t item_cnt, size_t item_size) +{ + TOS_PTR_SANITY_CHECK(ring_q); + TOS_PTR_SANITY_CHECK(pool); + + ring_q->head = 0u; + ring_q->tail = 0u; + ring_q->total = 0; + + ring_q->pool = (uint8_t *)pool; + ring_q->item_size = item_size; + ring_q->item_cnt = item_cnt; + + TOS_OBJ_INIT(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + knl_object_alloc_set_static(&ring_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_ring_q_destroy(k_ring_q_t *ring_q) +{ + TOS_PTR_SANITY_CHECK(ring_q); + TOS_OBJ_VERIFY(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + + if (!knl_object_alloc_is_static(&ring_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + ring_q->head = 0u; + ring_q->tail = 0u; + ring_q->total = 0; + + ring_q->pool = K_NULL; + ring_q->item_size = 0u; + ring_q->item_cnt = 0u; + + TOS_OBJ_DEINIT(ring_q); + knl_object_alloc_reset(&ring_q->knl_obj); + + return K_ERR_NONE; +} + + __API__ k_err_t tos_ring_q_create_dyn(k_ring_q_t *ring_q, size_t item_cnt, size_t item_size) +{ + void *pool; + + TOS_PTR_SANITY_CHECK(ring_q); + + pool = tos_mmheap_alloc(item_cnt * item_size); + if (!pool) { + return K_ERR_OUT_OF_MEMORY; + } + + ring_q->head = 0u; + ring_q->tail = 0u; + ring_q->total = 0; + + ring_q->pool = (uint8_t *)pool; + ring_q->item_size = item_size; + ring_q->item_cnt = item_cnt; + + TOS_OBJ_INIT(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + knl_object_alloc_set_dynamic(&ring_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_ring_q_destroy_dyn(k_ring_q_t *ring_q) +{ + TOS_PTR_SANITY_CHECK(ring_q); + TOS_OBJ_VERIFY(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + + if (!knl_object_alloc_is_dynamic(&ring_q->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } + + tos_mmheap_free(ring_q->pool); + + ring_q->head = 0u; + ring_q->tail = 0u; + ring_q->total = 0; + + ring_q->pool = K_NULL; + ring_q->item_size = 0u; + ring_q->item_cnt = 0u; + + TOS_OBJ_DEINIT(ring_q); + knl_object_alloc_reset(&ring_q->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_ring_q_enqueue(k_ring_q_t *ring_q, void *item, size_t item_size) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(ring_q); + TOS_PTR_SANITY_CHECK(item); + TOS_OBJ_VERIFY(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + + if (item_size != ring_q->item_size) { + return K_ERR_RING_Q_ITEM_SIZE_NOT_MATCH; + } + + TOS_CPU_INT_DISABLE(); + + if (tos_ring_q_is_full(ring_q)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_RING_Q_FULL; + } + + ring_q_item_copy_from(ring_q, item); + ring_q_item_increase(ring_q); + + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__API__ k_err_t tos_ring_q_dequeue(k_ring_q_t *ring_q, void *item, size_t *item_size) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(ring_q); + TOS_PTR_SANITY_CHECK(item); + TOS_OBJ_VERIFY(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + + TOS_CPU_INT_DISABLE(); + + if (tos_ring_q_is_empty(ring_q)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_RING_Q_EMPTY; + } + + ring_q_item_copy_to(ring_q, item, item_size); + ring_q_item_decrease(ring_q); + + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_ring_q_flush(k_ring_q_t *ring_q) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(ring_q); + TOS_OBJ_VERIFY(ring_q, KNL_OBJ_TYPE_RING_QUEUE); + + TOS_CPU_INT_DISABLE(); + + ring_q->head = 0u; + ring_q->tail = 0u; + ring_q->total = 0; + + TOS_CPU_INT_ENABLE(); + + return K_ERR_NONE; +} + +__API__ int tos_ring_q_is_empty(k_ring_q_t *ring_q) +{ + TOS_CPU_CPSR_ALLOC(); + int is_empty = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(ring_q, K_FALSE); + TOS_OBJ_VERIFY_RC(ring_q, KNL_OBJ_TYPE_RING_QUEUE, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_empty = (ring_q->total == 0 ? K_TRUE : K_FALSE); + TOS_CPU_INT_ENABLE(); + + return is_empty; +} + +__API__ int tos_ring_q_is_full(k_ring_q_t *ring_q) +{ + TOS_CPU_CPSR_ALLOC(); + int is_full = K_FALSE; + + TOS_PTR_SANITY_CHECK_RC(ring_q, K_FALSE); + TOS_OBJ_VERIFY_RC(ring_q, KNL_OBJ_TYPE_RING_QUEUE, K_FALSE); + + TOS_CPU_INT_DISABLE(); + is_full = (ring_q->total == ring_q->item_cnt ? K_TRUE : K_FALSE); + TOS_CPU_INT_ENABLE(); + + return is_full; +} + diff --git a/TencentOS_Tiny/kernel/core/tos_robin.c b/TencentOS_Tiny/kernel/core/tos_robin.c new file mode 100644 index 0000000..3ec31c4 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_robin.c @@ -0,0 +1,105 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_ROUND_ROBIN_EN > 0u + +__API__ void tos_robin_default_timeslice_config(k_timeslice_t default_timeslice) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_CPU_INT_DISABLE(); + + if (default_timeslice > (k_timeslice_t)0u) { + k_robin_default_timeslice = default_timeslice; + } else { + k_robin_default_timeslice = TOS_CFG_CPU_TICK_PER_SECOND / 10; + } + + TOS_CPU_INT_ENABLE(); +} + +__API__ void tos_robin_timeslice_set(k_task_t *task, k_timeslice_t timeslice) +{ + TOS_CPU_CPSR_ALLOC(); + + if (!task) { + task = k_curr_task; + } + + TOS_CPU_INT_DISABLE(); + + if (timeslice == (k_timeslice_t)0u) { + task->timeslice_reload = k_robin_default_timeslice; + } else { + task->timeslice_reload = timeslice; + } + + if (task->timeslice_reload > task->timeslice) { + task->timeslice = task->timeslice_reload; + } + TOS_CPU_INT_ENABLE(); +} + +__KNL__ void robin_sched(k_prio_t prio) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *task; + + TOS_CPU_INT_DISABLE(); + + task = readyqueue_first_task_get(prio); + if (!task || knl_is_idle(task)) { + TOS_CPU_INT_ENABLE(); + return; + } + + if (readyqueue_is_prio_onlyone(prio)) { + TOS_CPU_INT_ENABLE(); + return; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return; + } + + if (task->timeslice > (k_timeslice_t)0u) { + --task->timeslice; + } + + if (task->timeslice > (k_timeslice_t)0u) { + TOS_CPU_INT_ENABLE(); + return; + } + + readyqueue_move_head_to_tail(k_curr_task->prio); + + task = readyqueue_first_task_get(prio); + if (task->timeslice_reload == (k_timeslice_t)0u) { + task->timeslice = k_robin_default_timeslice; + } else { + task->timeslice = task->timeslice_reload; + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_rwlock.c b/TencentOS_Tiny/kernel/core/tos_rwlock.c new file mode 100644 index 0000000..48cb663 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_rwlock.c @@ -0,0 +1,327 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if (TOS_CFG_SEM_EN > 0u) && (TOS_CFG_MUTEX_EN > 0u) + +__API__ k_err_t tos_rwlock_create(k_rwlock_t *rwlock) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(rwlock); + + err = tos_sem_create(&rwlock->signal, 0u); + if (err != K_ERR_NONE) { + return err; + } + + err = tos_mutex_create(&rwlock->lock); + if (err != K_ERR_NONE) { + tos_sem_destroy(&rwlock->signal); + return err; + } + + rwlock->n_readers = (rw_cnt_t)0u; + rwlock->n_writers = (rw_cnt_t)0u; + rwlock->is_writting = K_FALSE; + TOS_OBJ_INIT(rwlock, KNL_OBJ_TYPE_RWLOCK); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_rwlock_destroy(k_rwlock_t *rwlock) +{ + k_err_t err0, err1; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + err0 = tos_sem_destroy(&rwlock->signal); + err1 = tos_mutex_destroy(&rwlock->lock); + + rwlock->n_readers = (rw_cnt_t)0u; + rwlock->n_writers = (rw_cnt_t)0u; + rwlock->is_writting = K_FALSE; + TOS_OBJ_DEINIT(rwlock); + + if (err0 != K_ERR_NONE) { + return err0; + } + + return err1; +} + +__API__ k_err_t tos_rwlock_rpend_timed(k_rwlock_t *rwlock, k_tick_t timeout) +{ + k_err_t err; + k_stopwatch_t stopwatch; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + if (timeout != TOS_TIME_FOREVER) { + tos_stopwatch_create(&stopwatch); + tos_stopwatch_countdown(&stopwatch, timeout); + } + + err = tos_mutex_pend_timed(&rwlock->lock, timeout); + if (err != K_ERR_NONE) { + return err; + } + + if (rwlock->n_readers == (rw_cnt_t)-1) { + /* number of reader reachs limit */ + return K_ERR_RWLOCK_READERS_TO_MANY; + } + + if (rwlock->n_writers == 0u && !rwlock->is_writting) { + /* no writer is now holding or waiting to hold the lock */ + ++rwlock->n_readers; + tos_mutex_post(&rwlock->lock); + return K_ERR_NONE; + } + + if (timeout != TOS_TIME_FOREVER) { + timeout = tos_stopwatch_remain(&stopwatch); + if (timeout == 0u) { + timeout = 1u; + } + } + + while (rwlock->n_writers > 0u || rwlock->is_writting) { + /* util no one is writting or waiting to hold the lock */ + err = tos_sem_pend(&rwlock->signal, timeout); + if (err != K_ERR_NONE) { + break; + } + + if (timeout != TOS_TIME_FOREVER) { + timeout = tos_stopwatch_remain(&stopwatch); + if (timeout == 0u) { + err = K_ERR_PEND_TIMEOUT; + break; + } + } + } + + tos_mutex_post(&rwlock->lock); + return err; +} + +__API__ k_err_t tos_rwlock_rpend(k_rwlock_t *rwlock) +{ + return tos_rwlock_rpend_timed(rwlock, TOS_TIME_FOREVER); +} + +__API__ k_err_t tos_rwlock_rpend_try(k_rwlock_t *rwlock) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + err = tos_mutex_pend_timed(&rwlock->lock, TOS_TIME_NOWAIT); + if (err != K_ERR_NONE) { + return err; + } + + if (rwlock->n_readers == (rw_cnt_t)-1) { + /* number of reader reachs limit */ + return K_ERR_RWLOCK_READERS_TO_MANY; + } + + if (rwlock->n_writers == 0u && !rwlock->is_writting) { + /* no writer is holding or waiting to hold the lock */ + ++rwlock->n_readers; + tos_mutex_post(&rwlock->lock); + return K_ERR_NONE; + } + + /* the rwlock is held by other writters */ + tos_mutex_post(&rwlock->lock); + return K_ERR_RWLOCK_IS_WRITTING; +} + +__API__ k_err_t tos_rwlock_wpend_timed(k_rwlock_t *rwlock, k_tick_t timeout) +{ + k_err_t err; + k_stopwatch_t stopwatch; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + if (timeout != TOS_TIME_FOREVER) { + tos_stopwatch_create(&stopwatch); + tos_stopwatch_countdown(&stopwatch, timeout); + } + + err = tos_mutex_pend_timed(&rwlock->lock, timeout); + if (err != K_ERR_NONE) { + return err; + } + + if (rwlock->n_writers == (rw_cnt_t)-1) { + /* number of waitting writer reachs limit */ + return K_ERR_RWLOCK_WAITING_WRITERS_TO_MANY; + } + + ++rwlock->n_writers; + + if (timeout != TOS_TIME_FOREVER) { + timeout = tos_stopwatch_remain(&stopwatch); + if (timeout == 0u) { + timeout = 1u; + } + } + + while (rwlock->n_readers > 0u || rwlock->is_writting) { + /* until no one is writting or reading */ + err = tos_sem_pend(&rwlock->signal, timeout); + if (err != K_ERR_NONE) { + break; + } + + if (timeout != TOS_TIME_FOREVER) { + timeout = tos_stopwatch_remain(&stopwatch); + if (timeout == 0u) { + err = K_ERR_PEND_TIMEOUT; + break; + } + } + } + + if (err == K_ERR_NONE) { + /* we hold the wlock now */ + rwlock->is_writting = K_TRUE; + } else { + tos_sem_post_all(&rwlock->signal); + } + + --rwlock->n_writers; + + tos_mutex_post(&rwlock->lock); + return err; +} + +__API__ k_err_t tos_rwlock_wpend(k_rwlock_t *rwlock) +{ + return tos_rwlock_wpend_timed(rwlock, TOS_TIME_FOREVER); +} + +__API__ k_err_t tos_rwlock_wpend_try(k_rwlock_t *rwlock) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + err = tos_mutex_pend_timed(&rwlock->lock, TOS_TIME_NOWAIT); + if (err != K_ERR_NONE) { + return err; + } + + if (rwlock->n_readers > 0u) { + err = K_ERR_RWLOCK_IS_READING; + } else if (rwlock->is_writting) { + err = K_ERR_RWLOCK_IS_WRITTING; + } else { + rwlock->is_writting = K_TRUE; + } + + tos_mutex_post(&rwlock->lock); + return err; +} + +__API__ k_err_t tos_rwlock_rpost(k_rwlock_t *rwlock) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + err = tos_mutex_pend(&rwlock->lock); + if (err != K_ERR_NONE) { + return err; + } + + if (rwlock->n_readers == 0u) { + err = K_ERR_RWLOCK_NOT_READING; + } else { + --rwlock->n_readers; + if (rwlock->n_readers == 0u) { + err = tos_sem_post_all(&rwlock->signal); + } + } + + tos_mutex_post(&rwlock->lock); + return err; +} + +__API__ k_err_t tos_rwlock_wpost(k_rwlock_t *rwlock) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + err = tos_mutex_pend(&rwlock->lock); + if (err != K_ERR_NONE) { + return err; + } + + if (!rwlock->is_writting) { + err = K_ERR_RWLOCK_NOT_WRITTING; + } else { + rwlock->is_writting = K_FALSE; + err = tos_sem_post_all(&rwlock->signal); + } + + tos_mutex_post(&rwlock->lock); + return err; +} + +__API__ k_err_t tos_rwlock_post(k_rwlock_t *rwlock) +{ + k_err_t err; + + TOS_PTR_SANITY_CHECK(rwlock); + TOS_OBJ_VERIFY(rwlock, KNL_OBJ_TYPE_RWLOCK); + + err = tos_mutex_pend(&rwlock->lock); + if (err != K_ERR_NONE) { + return err; + } + + if (rwlock->n_readers > 0u) { + --rwlock->n_readers; + if (rwlock->n_readers == 0u) { + err = tos_sem_post_all(&rwlock->signal); + } + } else if (rwlock->is_writting) { + rwlock->is_writting = K_FALSE; + err = tos_sem_post_all(&rwlock->signal); + } else { + err = K_ERR_RWLOCK_NOT_TAKEN; + } + + tos_mutex_post(&rwlock->lock); + return err; +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_sched.c b/TencentOS_Tiny/kernel/core/tos_sched.c new file mode 100644 index 0000000..b6ea129 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_sched.c @@ -0,0 +1,172 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC__ k_prio_t readyqueue_prio_highest_get(void) +{ + uint32_t *tbl; + k_prio_t prio; + + prio = 0; + tbl = &k_rdyq.prio_mask[0]; + + while (*tbl == 0) { + prio += K_PRIO_TBL_SLOT_SIZE; + ++tbl; + } + prio += tos_cpu_clz(*tbl); + return prio; +} + +__STATIC_INLINE__ void readyqueue_prio_insert(k_prio_t prio) +{ + k_rdyq.prio_mask[K_PRIO_NDX(prio)] |= K_PRIO_BIT(prio); +} + +__STATIC_INLINE__ void readyqueue_prio_remove(k_prio_t prio) +{ + k_rdyq.prio_mask[K_PRIO_NDX(prio)] &= ~K_PRIO_BIT(prio); +} + +__STATIC_INLINE__ void readyqueue_prio_mark(k_prio_t prio) +{ + readyqueue_prio_insert(prio); + + if (prio < k_rdyq.highest_prio) { + k_rdyq.highest_prio = prio; + } +} + +/** + * when this function involved, must be at least one task in the task list of the certain priority + */ +__KNL__ int readyqueue_is_prio_onlyone(k_prio_t prio) +{ + k_list_t *task_list; + k_task_t *task; + + task_list = &k_rdyq.task_list_head[prio]; + task = TOS_LIST_FIRST_ENTRY(task_list, k_task_t, pend_list); + return task->pend_list.next == task_list; +} + +__KNL__ k_task_t *readyqueue_first_task_get(k_prio_t prio) +{ + k_list_t *task_list; + + task_list = &k_rdyq.task_list_head[prio]; + return TOS_LIST_FIRST_ENTRY_OR_NULL(task_list, k_task_t, pend_list); +} + +__KNL__ k_task_t *readyqueue_highest_ready_task_get(void) +{ + k_list_t *task_list; + + task_list = &k_rdyq.task_list_head[k_rdyq.highest_prio]; + return TOS_LIST_FIRST_ENTRY(task_list, k_task_t, pend_list); +} + +__KNL__ void readyqueue_init(void) +{ + uint8_t i; + + k_rdyq.highest_prio = TOS_CFG_TASK_PRIO_MAX; + + for (i = 0; i < TOS_CFG_TASK_PRIO_MAX; ++i) { + tos_list_init(&k_rdyq.task_list_head[i]); + } + + for (i = 0; i < K_PRIO_TBL_SIZE; ++i) { + k_rdyq.prio_mask[i] = 0; + } +} + +__KNL__ void readyqueue_add_head(k_task_t *task) +{ + k_prio_t task_prio; + k_list_t *task_list; + + task_prio = task->prio; + task_list = &k_rdyq.task_list_head[task_prio]; + + if (tos_list_empty(task_list)) { + readyqueue_prio_mark(task_prio); + } + + tos_list_add(&task->pend_list, task_list); +} + +__KNL__ void readyqueue_add_tail(k_task_t *task) +{ + k_prio_t task_prio; + k_list_t *task_list; + + task_prio = task->prio; + task_list = &k_rdyq.task_list_head[task_prio]; + + if (tos_list_empty(task_list)) { + readyqueue_prio_mark(task_prio); + } + + tos_list_add_tail(&task->pend_list, task_list); +} + +__KNL__ void readyqueue_add(k_task_t *task) +{ + if (task->prio == k_curr_task->prio) { + readyqueue_add_tail(task); + } else { + readyqueue_add_head(task); + } +} + +__KNL__ void readyqueue_remove(k_task_t *task) +{ + k_prio_t task_prio; + k_list_t *task_list; + + // protect the idle task. + if (knl_is_idle(task)) { + return; + } + + task_prio = task->prio; + task_list = &k_rdyq.task_list_head[task_prio]; + + tos_list_del(&task->pend_list); + + if (tos_list_empty(task_list)) { + readyqueue_prio_remove(task_prio); + } + + if (task_prio == k_rdyq.highest_prio) { + k_rdyq.highest_prio = readyqueue_prio_highest_get(); + } +} + +__KNL__ void readyqueue_move_head_to_tail(k_prio_t prio) +{ + k_list_t *task_list; + + task_list = &k_rdyq.task_list_head[prio]; + + if (!tos_list_empty(task_list)) { + tos_list_move_tail(task_list->next, task_list); + } +} + diff --git a/TencentOS_Tiny/kernel/core/tos_sem.c b/TencentOS_Tiny/kernel/core/tos_sem.c new file mode 100644 index 0000000..2970fe9 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_sem.c @@ -0,0 +1,179 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_SEM_EN > 0u + +__API__ k_err_t tos_sem_create_max(k_sem_t *sem, k_sem_cnt_t init_count, k_sem_cnt_t max_count) +{ + TOS_PTR_SANITY_CHECK(sem); + + if (unlikely(init_count > max_count)) { + init_count = max_count; + } + + sem->count = init_count; + sem->count_max = max_count; + + pend_object_init(&sem->pend_obj); + TOS_OBJ_INIT(sem, KNL_OBJ_TYPE_SEMAPHORE); + + knl_object_alloc_set_static(&sem->knl_obj); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_sem_create(k_sem_t *sem, k_sem_cnt_t init_count) +{ + return tos_sem_create_max(sem, init_count, (k_sem_cnt_t)-1); +} + +__API__ k_err_t tos_sem_create_max_dyn(k_sem_t **sem, k_sem_cnt_t init_count, k_sem_cnt_t max_count) +{ + k_sem_t *the_sem; + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(sem); + + if (unlikely(init_count > max_count)) { + init_count = max_count; + } + + the_sem = tos_mmheap_calloc(1, sizeof(k_sem_t)); + if (!the_sem) { + return K_ERR_SEM_OUT_OF_MEMORY; + } + + the_sem->count = init_count; + the_sem->count_max = max_count; + + pend_object_init(&the_sem->pend_obj); + TOS_OBJ_INIT(the_sem, KNL_OBJ_TYPE_SEMAPHORE); + + knl_object_alloc_set_dynamic(&the_sem->knl_obj); + + *sem = the_sem; + + return K_ERR_NONE; +} + +__API__ k_err_t tos_sem_create_dyn(k_sem_t **sem, k_sem_cnt_t init_count) +{ + return tos_sem_create_max_dyn(sem, init_count, (k_sem_cnt_t)-1); +} + +__API__ k_err_t tos_sem_destroy(k_sem_t *sem) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(sem); + TOS_OBJ_VERIFY(sem, KNL_OBJ_TYPE_SEMAPHORE); + + TOS_CPU_INT_DISABLE(); + + pend_wakeup_all(&sem->pend_obj, PEND_STATE_DESTROY); + + pend_object_deinit(&sem->pend_obj); + + if (knl_object_alloc_is_dynamic(&sem->knl_obj)) { + TOS_OBJ_DEINIT(sem); + tos_mmheap_free(sem); + } else { + TOS_OBJ_DEINIT(sem); + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__STATIC__ k_err_t sem_do_post(k_sem_t *sem, opt_post_t opt) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(sem); + TOS_OBJ_VERIFY(sem, KNL_OBJ_TYPE_SEMAPHORE); + + TOS_CPU_INT_DISABLE(); + + if (sem->count == sem->count_max) { + TOS_CPU_INT_ENABLE(); + return K_ERR_SEM_OVERFLOW; + } + + if (pend_is_nopending(&sem->pend_obj)) { + ++sem->count; + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + pend_wakeup(&sem->pend_obj, PEND_STATE_POST, opt); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_sem_post(k_sem_t *sem) +{ + return sem_do_post(sem, OPT_POST_ONE); +} + +__API__ k_err_t tos_sem_post_all(k_sem_t *sem) +{ + return sem_do_post(sem, OPT_POST_ALL); +} + +__API__ k_err_t tos_sem_pend(k_sem_t *sem, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(sem); + TOS_OBJ_VERIFY(sem, KNL_OBJ_TYPE_SEMAPHORE); + + TOS_CPU_INT_DISABLE(); + + if (sem->count > (k_sem_cnt_t)0u) { + --sem->count; + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; + } + + if (timeout == TOS_TIME_NOWAIT) { // no wait, return immediately + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_NOWAIT; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return K_ERR_PEND_SCHED_LOCKED; + } + + pend_task_block(k_curr_task, &sem->pend_obj, timeout); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return pend_state2errno(k_curr_task->pend_state); +} + +#endif // TOS_CFG_SEM_EN + diff --git a/TencentOS_Tiny/kernel/core/tos_stopwatch.c b/TencentOS_Tiny/kernel/core/tos_stopwatch.c new file mode 100644 index 0000000..24a09bc --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_stopwatch.c @@ -0,0 +1,123 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ k_err_t tos_stopwatch_create(k_stopwatch_t *stopwatch) +{ + TOS_PTR_SANITY_CHECK(stopwatch); + + stopwatch->until = 0u; + TOS_OBJ_INIT(stopwatch, KNL_OBJ_TYPE_STOPWATCH); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_stopwatch_destroy(k_stopwatch_t *stopwatch) +{ + TOS_PTR_SANITY_CHECK(stopwatch); + TOS_OBJ_VERIFY(stopwatch, KNL_OBJ_TYPE_STOPWATCH); + + stopwatch->until = 0u; + TOS_OBJ_DEINIT(stopwatch); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_stopwatch_countdown(k_stopwatch_t *stopwatch, k_tick_t tick) +{ + k_tick_t now; + + TOS_PTR_SANITY_CHECK(stopwatch); + TOS_OBJ_VERIFY(stopwatch, KNL_OBJ_TYPE_STOPWATCH); + + now = tos_systick_get(); + stopwatch->until = now + tick; + + return K_ERR_NONE; +} + +__API__ k_err_t tos_stopwatch_countdown_ms(k_stopwatch_t *stopwatch, k_time_t millisec) +{ + k_tick_t tick; + + TOS_PTR_SANITY_CHECK(stopwatch); + TOS_OBJ_VERIFY(stopwatch, KNL_OBJ_TYPE_STOPWATCH); + + tick = tos_millisec2tick(millisec); + return tos_stopwatch_countdown(stopwatch, tick); +} + +__API__ void tos_stopwatch_delay(k_tick_t tick) +{ + k_tick_t now; + + now = tos_systick_get(); + while ((tos_systick_get() - now) < tick) { + ; + } +} + +__API__ void tos_stopwatch_delay_ms(k_time_t millisec) +{ + k_tick_t tick; + + tick = tos_millisec2tick(millisec); + tos_stopwatch_delay(tick); +} + +__API__ k_tick_t tos_stopwatch_remain(k_stopwatch_t *stopwatch) +{ + k_tick_t now; + + TOS_PTR_SANITY_CHECK_RC(stopwatch, (k_tick_t)-1); + TOS_OBJ_VERIFY_RC(stopwatch, KNL_OBJ_TYPE_STOPWATCH, (k_tick_t)-1); + + if (tos_stopwatch_is_expired(stopwatch)) { + return (k_tick_t)0u; + } + + now = tos_systick_get(); + return stopwatch->until - now; +} + +__API__ k_time_t tos_stopwatch_remain_ms(k_stopwatch_t *stopwatch) +{ + k_tick_t now; + + TOS_PTR_SANITY_CHECK_RC(stopwatch, (k_time_t)-1); + TOS_OBJ_VERIFY_RC(stopwatch, KNL_OBJ_TYPE_STOPWATCH, (k_time_t)-1); + + if (tos_stopwatch_is_expired(stopwatch)) { + return (k_tick_t)0u; + } + + now = tos_systick_get(); + return (k_time_t)(((stopwatch->until) - now + TOS_CFG_CPU_TICK_PER_SECOND - 1) / TOS_CFG_CPU_TICK_PER_SECOND); +} + +__API__ int tos_stopwatch_is_expired(k_stopwatch_t *stopwatch) +{ + k_tick_t now; + + TOS_PTR_SANITY_CHECK_RC(stopwatch, K_FALSE); + TOS_OBJ_VERIFY_RC(stopwatch, KNL_OBJ_TYPE_STOPWATCH, K_FALSE); + + now = tos_systick_get(); + return now >= stopwatch->until ? K_TRUE : K_FALSE; +} + diff --git a/TencentOS_Tiny/kernel/core/tos_sys.c b/TencentOS_Tiny/kernel/core/tos_sys.c new file mode 100644 index 0000000..f5c7ed9 --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_sys.c @@ -0,0 +1,274 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ k_err_t tos_knl_init(void) +{ + k_err_t err; + + cpu_init(); + + readyqueue_init(); + +#if TOS_CFG_MMHEAP_EN > 0 +#if TOS_CFG_MMHEAP_DEFAULT_POOL_EN > 0u + err = mmheap_init_with_pool(k_mmheap_default_pool, TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE); +#else + err = mmheap_init(); +#endif + if (err != K_ERR_NONE) { + return err; + } +#endif + + err = knl_idle_init(); + if (err != K_ERR_NONE) { + return err; + } + +#if TOS_CFG_TIMER_EN > 0 + err = timer_init(); + if (err != K_ERR_NONE) { + return err; + } +#endif + +#if TOS_CFG_PWR_MGR_EN > 0U + pm_init(); +#endif + +#if TOS_CFG_TICKLESS_EN > 0u + tickless_init(); +#endif + + return K_ERR_NONE; +} + +__API__ void tos_knl_irq_enter(void) +{ + if (!tos_knl_is_running()) { + return; + } + + if (unlikely(k_irq_nest_cnt >= K_NESTING_LIMIT_IRQ)) { + return; + } + + ++k_irq_nest_cnt; +} + +__API__ void tos_knl_irq_leave(void) +{ + TOS_CPU_CPSR_ALLOC(); + + if (!tos_knl_is_running()) { + return; + } + + TOS_CPU_INT_DISABLE(); + if (!knl_is_inirq()) { + TOS_CPU_INT_ENABLE(); + return; + } + + --k_irq_nest_cnt; + + if (knl_is_inirq()) { + TOS_CPU_INT_ENABLE(); + return; + } + + if (knl_is_sched_locked()) { + TOS_CPU_INT_ENABLE(); + return; + } + + k_next_task = readyqueue_highest_ready_task_get(); + if (knl_is_self(k_next_task)) { + TOS_CPU_INT_ENABLE(); + return; + } + + cpu_irq_context_switch(); + TOS_CPU_INT_ENABLE(); +} + +__API__ k_err_t tos_knl_sched_lock(void) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + + if (!tos_knl_is_running()) { + return K_ERR_KNL_NOT_RUNNING; + } + + if (k_sched_lock_nest_cnt >= K_NESTING_LIMIT_SCHED_LOCK) { + return K_ERR_LOCK_NESTING_OVERFLOW; + } + + TOS_CPU_INT_DISABLE(); + ++k_sched_lock_nest_cnt; + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} + +__API__ k_err_t tos_knl_sched_unlock(void) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + + if (!tos_knl_is_running()) { + return K_ERR_KNL_NOT_RUNNING; + } + + if (!knl_is_sched_locked()) { + return K_ERR_SCHED_NOT_LOCKED; + } + + TOS_CPU_INT_DISABLE(); + --k_sched_lock_nest_cnt; + TOS_CPU_INT_ENABLE(); + + knl_sched(); + return K_ERR_NONE; +} + +__API__ k_err_t tos_knl_start(void) +{ + if (unlikely(tos_knl_is_running())) { + return K_ERR_KNL_RUNNING; + } + + k_next_task = readyqueue_highest_ready_task_get(); + k_curr_task = k_next_task; + k_knl_state = KNL_STATE_RUNNING; + +// printf("start\r\n"); + cpu_sched_start(); + + return K_ERR_NONE; +} + +__API__ int tos_knl_is_running(void) +{ + return k_knl_state == KNL_STATE_RUNNING; +} + +#if TOS_CFG_TICKLESS_EN > 0u + +/** + * @brief Get the remain ticks of the first oncoming task. + * + * @return The remian ticks of the first oncoming task to be scheduled. + */ +__KNL__ k_tick_t knl_next_expires_get(void) +{ + k_tick_t tick_next_expires; +#if TOS_CFG_TIMER_EN > 0u + k_tick_t timer_next_expires; +#endif + + tick_next_expires = tick_next_expires_get(); + +#if TOS_CFG_TIMER_EN > 0u + timer_next_expires = timer_next_expires_get(); +#endif + +#if TOS_CFG_TIMER_EN > 0u + return tick_next_expires < timer_next_expires ? tick_next_expires : timer_next_expires; +#else + return tick_next_expires; +#endif +} + +#endif + +__KNL__ void knl_sched(void) +{ + TOS_CPU_CPSR_ALLOC(); + + if (unlikely(!tos_knl_is_running())) { + return; + } + + if (knl_is_inirq()) { + return; + } + + if (knl_is_sched_locked()) { + return; + } + + TOS_CPU_INT_DISABLE(); + k_next_task = readyqueue_highest_ready_task_get(); + if (knl_is_self(k_next_task)) { + TOS_CPU_INT_ENABLE(); + return; + } + + cpu_context_switch(); + TOS_CPU_INT_ENABLE(); +} + +__KNL__ int knl_is_sched_locked(void) +{ + return k_sched_lock_nest_cnt > 0u; +} + +__KNL__ int knl_is_inirq(void) +{ + return k_irq_nest_cnt > 0u; +} + +__KNL__ int knl_is_idle(k_task_t *task) +{ + return task == &k_idle_task; +} + +__KNL__ int knl_is_self(k_task_t *task) +{ + return task == k_curr_task; +} + +__STATIC__ void knl_idle_entry(void *arg) +{ + arg = arg; // make compiler happy + + while (K_TRUE) { +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + task_free_all(); +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + pm_power_manager(); +#endif + } +} + +__KNL__ k_err_t knl_idle_init(void) +{ + return tos_task_create(&k_idle_task, "idle", + knl_idle_entry, K_NULL, + K_TASK_PRIO_IDLE, + k_idle_task_stk_addr, + k_idle_task_stk_size, + 0); +} + diff --git a/TencentOS_Tiny/kernel/core/tos_task.c b/TencentOS_Tiny/kernel/core/tos_task.c new file mode 100644 index 0000000..496de2c --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_task.c @@ -0,0 +1,585 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC_INLINE__ void task_reset(k_task_t *task) +{ +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + knl_object_alloc_reset(&task->knl_obj); + + tos_list_init(&task->dead_list); +#endif + tos_list_init(&task->stat_list); + tos_list_init(&task->tick_list); + tos_list_init(&task->pend_list); + +#if TOS_CFG_MUTEX_EN > 0u + tos_list_init(&task->mutex_own_list); + task->prio_pending = K_TASK_PRIO_INVALID; +#endif + + task->pend_state = PEND_STATE_NONE; + task->pending_obj = (pend_obj_t *)K_NULL; + +#if TOS_CFG_MESSAGE_QUEUE_EN > 0u + task->msg = K_NULL; +#endif + +#if TOS_CFG_MAIL_QUEUE_EN > 0u + task->mail = K_NULL; + task->mail_size = 0; +#endif + + TOS_OBJ_DEINIT(task); +} + +__STATIC__ void task_exit(void) +{ + tos_task_destroy(K_NULL); +} + +#if TOS_CFG_MUTEX_EN > 0u +__STATIC__ k_prio_t task_highest_pending_prio_get(k_task_t *task) +{ + k_mutex_t *mutex; + k_prio_t prio, highest_prio_pending = K_TASK_PRIO_INVALID; + + TOS_LIST_FOR_EACH_ENTRY(mutex, k_mutex_t, owner_anchor, &task->mutex_own_list) { + prio = pend_highest_pending_prio_get(&mutex->pend_obj); + if (prio < highest_prio_pending) { + highest_prio_pending = prio; + } + } + + return highest_prio_pending; +} + +__STATIC__ void task_mutex_release(k_task_t *task) +{ + k_mutex_t *mutex, *tmp; + + TOS_LIST_FOR_EACH_ENTRY_SAFE(mutex, tmp, k_mutex_t, owner_anchor, &task->mutex_own_list) { + mutex_release(mutex); + } +} +#endif + +__API__ k_err_t tos_task_create(k_task_t *task, + char *name, + k_task_entry_t entry, + void *arg, + k_prio_t prio, + k_stack_t *stk_base, + size_t stk_size, + k_timeslice_t timeslice) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + + TOS_PTR_SANITY_CHECK(task); + TOS_PTR_SANITY_CHECK(entry); + TOS_PTR_SANITY_CHECK(stk_base); + + /* try to re-create a task, kind of dangerous */ + TOS_OBJ_TEST_RC(task, KNL_OBJ_TYPE_TASK, K_ERR_TASK_ALREADY_CREATED); + + if (unlikely(stk_size < K_TASK_STK_SIZE_MIN)) { + return K_ERR_TASK_STK_SIZE_INVALID; + } + + if (unlikely(prio == K_TASK_PRIO_IDLE && !knl_is_idle(task))) { + return K_ERR_TASK_PRIO_INVALID; + } + + if (unlikely(prio > K_TASK_PRIO_IDLE)) { + return K_ERR_TASK_PRIO_INVALID; + } + + task_reset(task); + tos_list_add(&task->stat_list, &k_stat_list); + + TOS_OBJ_INIT(task, KNL_OBJ_TYPE_TASK); +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + knl_object_alloc_set_static(&task->knl_obj); +#endif + + task->sp = cpu_task_stk_init((void *)entry, arg, (void *)task_exit, stk_base, stk_size); + task->entry = entry; + task->arg = arg; + task->prio = prio; + task->stk_base = stk_base; + task->stk_size = stk_size; + strncpy(task->name, name, K_TASK_NAME_LEN_MAX); + +#if TOS_CFG_ROUND_ROBIN_EN > 0u + task->timeslice_reload = timeslice; + + if (timeslice == (k_timeslice_t)0u) { + task->timeslice = k_robin_default_timeslice; + } else { + task->timeslice = timeslice; + } +#endif + + TOS_CPU_INT_DISABLE(); + task_state_set_ready(task); + readyqueue_add_tail(task); + TOS_CPU_INT_ENABLE(); + + if (tos_knl_is_running()) { + knl_sched(); + } + + return K_ERR_NONE; +} + +__STATIC__ k_err_t task_do_destroy(k_task_t *task) +{ + TOS_CPU_CPSR_ALLOC(); + + if (knl_is_idle(task)) { + return K_ERR_TASK_DESTROY_IDLE; + } + + TOS_CPU_INT_DISABLE(); + +#if TOS_CFG_MUTEX_EN > 0u + // when we die, wakeup all the people in this land. + if (!tos_list_empty(&task->mutex_own_list)) { + task_mutex_release(task); + } +#endif + + if (task_state_is_ready(task)) { // that's simple, good kid + readyqueue_remove(task); + } + if (task_state_is_sleeping(task)) { + tick_list_remove(task); + } + if (task_state_is_pending(task)) { + pend_list_remove(task); + } + + tos_list_del(&task->stat_list); + task_reset(task); + + task_state_set_deleted(task); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__STATIC__ k_err_t task_destroy_static(k_task_t *task) +{ +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + if (!knl_object_alloc_is_static(&task->knl_obj)) { + return K_ERR_OBJ_INVALID_ALLOC_TYPE; + } +#endif + + return task_do_destroy(task); +} + +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + +__STATIC__ void task_free(k_task_t *task) +{ + tos_mmheap_free(task->stk_base); + tos_mmheap_free(task); +} + +__KNL__ void task_free_all(void) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *task, *tmp; + + TOS_CPU_INT_DISABLE(); + + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, dead_list, &k_dead_task_list) { + tos_list_del(&task->dead_list); + task_free(task); + } + + TOS_CPU_INT_ENABLE(); +} + +__API__ k_err_t tos_task_create_dyn(k_task_t **task, + char *name, + k_task_entry_t entry, + void *arg, + k_prio_t prio, + size_t stk_size, + k_timeslice_t timeslice) +{ + k_err_t err; + k_task_t *the_task; + k_stack_t *stk_base; + + TOS_IN_IRQ_CHECK(); + + TOS_PTR_SANITY_CHECK(task); + TOS_PTR_SANITY_CHECK(entry); + + if (unlikely(stk_size < sizeof(cpu_context_t))) { + return K_ERR_TASK_STK_SIZE_INVALID; + } + + if (unlikely(prio == K_TASK_PRIO_IDLE)) { + return K_ERR_TASK_PRIO_INVALID; + } + + if (unlikely(prio > K_TASK_PRIO_IDLE)) { + return K_ERR_TASK_PRIO_INVALID; + } + + the_task = tos_mmheap_calloc(1, sizeof(k_task_t)); + if (!the_task) { + return K_ERR_TASK_OUT_OF_MEMORY; + } + + stk_base = tos_mmheap_alloc(stk_size); + if (!stk_base) { + tos_mmheap_free(the_task); + return K_ERR_TASK_OUT_OF_MEMORY; + } + + the_task->stk_base = stk_base; + err = tos_task_create(the_task, name, entry, arg, prio, stk_base, stk_size, timeslice); + if (err != K_ERR_NONE) { + task_free(the_task); + return err; + } + + knl_object_alloc_set_dynamic(&the_task->knl_obj); + + *task = the_task; + + return K_ERR_NONE; +} + +__STATIC__ k_err_t task_destroy_dyn(k_task_t *task) +{ + k_err_t err; + + tos_knl_sched_lock(); + + err = task_do_destroy(task); + if (err != K_ERR_NONE) { + tos_knl_sched_unlock(); + return err; + } + + if (knl_is_self(task)) { // we are destroying ourself + // in this situation, we cannot just free ourself's task stack because we are using it + // we count on the idle task to free the memory + tos_list_add(&task->dead_list, &k_dead_task_list); + } else { + task_free(task); + } + + tos_knl_sched_unlock(); + + return K_ERR_NONE; +} + +#endif + +__API__ k_err_t tos_task_destroy(k_task_t *task) +{ + TOS_IN_IRQ_CHECK(); + + if (unlikely(!task)) { + task = k_curr_task; + } + + TOS_OBJ_VERIFY(task, KNL_OBJ_TYPE_TASK); + + if (knl_is_self(task) && knl_is_sched_locked()) { + return K_ERR_SCHED_LOCKED; + } + +#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u + if (knl_object_alloc_is_dynamic(&task->knl_obj)) { + return task_destroy_dyn(task); + } +#endif + + return task_destroy_static(task); +} + +__API__ void tos_task_yield(void) +{ + TOS_CPU_CPSR_ALLOC(); + + if (knl_is_inirq()) { + return; + } + + TOS_CPU_INT_DISABLE(); + + readyqueue_remove(k_curr_task); + readyqueue_add_tail(k_curr_task); + + TOS_CPU_INT_ENABLE(); + knl_sched(); +} + +__API__ k_err_t tos_task_prio_change(k_task_t *task, k_prio_t prio_new) +{ + TOS_CPU_CPSR_ALLOC(); +#if TOS_CFG_MUTEX_EN > 0u + k_prio_t highest_pending_prio; +#endif + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(task); + TOS_OBJ_VERIFY(task, KNL_OBJ_TYPE_TASK); + + if (unlikely(prio_new >= K_TASK_PRIO_IDLE)) { + return K_ERR_TASK_PRIO_INVALID; + } + + TOS_CPU_INT_DISABLE(); + + if (task->prio == prio_new) { // just kidding + TOS_CPU_INT_ENABLE(); + knl_sched(); + return K_ERR_NONE; + } + +#if TOS_CFG_MUTEX_EN > 0u + if (!tos_list_empty(&task->mutex_own_list)) { + highest_pending_prio = task_highest_pending_prio_get(task); + if (prio_new > highest_pending_prio) { + task->prio_pending = prio_new; + prio_new = highest_pending_prio; + } + } +#endif + + if (task_state_is_pending(task)) { + task->prio = prio_new; + pend_list_adjust(task); + } else if (task_state_is_sleeping(task)) { + task->prio = prio_new; + } else if (task_state_is_ready(task)) { // good kid + readyqueue_remove(task); + + /* ATTENTION: + must do the prio assignment after readyqueue_remove + otherwise the k_rdyq.highest_prio refresh in readyqueue_remove will be wrong. + */ + task->prio = prio_new; + if (knl_is_self(task)) { + readyqueue_add_head(task); + } else { + readyqueue_add_tail(task); + } + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_task_suspend(k_task_t *task) +{ + TOS_CPU_CPSR_ALLOC(); + + if (unlikely(!task)) { + task = k_curr_task; + } + + TOS_OBJ_VERIFY(task, KNL_OBJ_TYPE_TASK); + + if (knl_is_idle(task)) { + return K_ERR_TASK_SUSPEND_IDLE; + } + + if (unlikely(knl_is_self(task)) && knl_is_sched_locked()) { // if not you, who? + return K_ERR_SCHED_LOCKED; + } + + TOS_CPU_INT_DISABLE(); + + if (task_state_is_ready(task)) { // kill the good kid + readyqueue_remove(task); + } + task_state_set_suspended(task); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_task_resume(k_task_t *task) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_PTR_SANITY_CHECK(task); + TOS_OBJ_VERIFY(task, KNL_OBJ_TYPE_TASK); + + if (unlikely(knl_is_self(task))) { + return K_ERR_TASK_RESUME_SELF; + } + + TOS_CPU_INT_DISABLE(); + + if (!task_state_is_suspended(task)) { + TOS_CPU_INT_ENABLE(); + knl_sched(); + return K_ERR_NONE; + } + + task_state_reset_suspended(task); + if (task_state_is_ready(task)) { // we are good kid now + readyqueue_add(task); + } + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_task_delay(k_tick_t delay) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + + if (knl_is_sched_locked()) { + return K_ERR_SCHED_LOCKED; + } + + if (unlikely(delay == (k_tick_t)0u)) { + tos_task_yield(); + return K_ERR_NONE; + } + + if (unlikely(delay == TOS_TIME_FOREVER)) { + // if you wanna delay your task forever, why don't just suspend? + return K_ERR_DELAY_FOREVER; + } + + TOS_CPU_INT_DISABLE(); + + tick_list_add(k_curr_task, delay); + readyqueue_remove(k_curr_task); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_task_delay_abort(k_task_t *task) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_IN_IRQ_CHECK(); + TOS_PTR_SANITY_CHECK(task); + TOS_OBJ_VERIFY(task, KNL_OBJ_TYPE_TASK); + + TOS_CPU_INT_DISABLE(); + + if (knl_is_self(task) || !task_state_is_sleeping(task)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_TASK_NOT_DELAY; + } + + if (task_state_is_suspended(task)) { + TOS_CPU_INT_ENABLE(); + return K_ERR_TASK_SUSPENDED; + } + + tick_list_remove(task); + readyqueue_add(task); + + TOS_CPU_INT_ENABLE(); + knl_sched(); + + return K_ERR_NONE; +} + +__API__ k_task_t *tos_task_curr_task_get(void) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *curr_task = K_NULL; + + TOS_CPU_INT_DISABLE(); + if (likely(tos_knl_is_running())) { + curr_task = k_curr_task; + } + TOS_CPU_INT_ENABLE(); + + return curr_task; +} + +__API__ void tos_task_walkthru(k_task_walker_t walker) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *task; + + if (!walker) { + return; + } + + TOS_CPU_INT_DISABLE(); + + TOS_LIST_FOR_EACH_ENTRY(task, k_task_t, stat_list, &k_stat_list) { + walker(task); + } + + TOS_CPU_INT_ENABLE(); +} + +__DEBUG__ void tos_task_info_display(void) +{ + tos_task_walkthru(task_default_walker); +} + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + +__API__ k_err_t tos_task_stack_draught_depth(k_task_t *task, int *depth) +{ + TOS_CPU_CPSR_ALLOC(); + k_err_t rc; + + TOS_PTR_SANITY_CHECK(depth); + + if (unlikely(!task)) { + task = k_curr_task; + } + + TOS_OBJ_VERIFY(task, KNL_OBJ_TYPE_TASK); + + TOS_CPU_INT_DISABLE(); + rc = cpu_task_stack_draught_depth(task->stk_base, task->stk_size, depth); + TOS_CPU_INT_ENABLE(); + + return rc; +} + +#endif + diff --git a/TencentOS_Tiny/kernel/core/tos_tick.c b/TencentOS_Tiny/kernel/core/tos_tick.c new file mode 100644 index 0000000..8fb4bfc --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_tick.c @@ -0,0 +1,149 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC__ void tick_task_place(k_task_t *task, k_tick_t timeout) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *curr_task = K_NULL; + k_tick_t curr_expires, prev_expires = (k_tick_t)0u; + + TOS_CPU_INT_DISABLE(); + + task->tick_expires = timeout; + + TOS_LIST_FOR_EACH_ENTRY(curr_task, k_task_t, tick_list, &k_tick_list) { + curr_expires = prev_expires + curr_task->tick_expires; + + if (task->tick_expires < curr_expires) { + break; + } + if (task->tick_expires == curr_expires && + task->prio < curr_task->prio) { + break; + } + prev_expires = curr_expires; + } + task->tick_expires -= prev_expires; + if (&curr_task->tick_list != &k_tick_list) { + curr_task->tick_expires -= task->tick_expires; + } + tos_list_add_tail(&task->tick_list, &curr_task->tick_list); + + TOS_CPU_INT_ENABLE(); +} + +__STATIC__ void tick_task_takeoff(k_task_t *task) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *next; + + TOS_CPU_INT_DISABLE(); + + next = TOS_LIST_FIRST_ENTRY_OR_NULL(&task->tick_list, k_task_t, tick_list); + if (next && task->tick_list.next != &k_tick_list) { // not the only one + if (next->tick_expires <= K_TIME_MAX - task->tick_expires) { + next->tick_expires += task->tick_expires; + } else { + next->tick_expires = K_TIME_MAX; + } + } + + tos_list_del(&task->tick_list); + + TOS_CPU_INT_ENABLE(); +} + +__KNL__ void tick_list_add(k_task_t *task, k_tick_t timeout) +{ + tick_task_place(task, timeout); + task_state_set_sleeping(task); +} + +__KNL__ void tick_list_remove(k_task_t *task) +{ + tick_task_takeoff(task); + task_state_reset_sleeping(task); +} + +__KNL__ void tick_update(k_tick_t tick) +{ + TOS_CPU_CPSR_ALLOC(); + k_task_t *first, *task, *tmp; + + TOS_CPU_INT_DISABLE(); + k_tick_count += tick; + + if (tos_list_empty(&k_tick_list)) { + TOS_CPU_INT_ENABLE(); + return; + } + + first = TOS_LIST_FIRST_ENTRY(&k_tick_list, k_task_t, tick_list); + if (first->tick_expires <= tick) { + first->tick_expires = (k_tick_t)0u; + } else { + first->tick_expires -= tick; + TOS_CPU_INT_ENABLE(); + return; + } + + TOS_LIST_FOR_EACH_ENTRY_SAFE(task, tmp, k_task_t, tick_list, &k_tick_list) { + if (task->tick_expires > (k_tick_t)0u) { + break; + } + + // we are pending for something, but tick's up, no longer waitting + pend_task_wakeup(task, PEND_STATE_TIMEOUT); + } + + TOS_CPU_INT_ENABLE(); +} + +__KNL__ k_tick_t tick_next_expires_get(void) +{ + TOS_CPU_CPSR_ALLOC(); + k_tick_t next_expires; + k_task_t *first; + + TOS_CPU_INT_DISABLE(); + + first = TOS_LIST_FIRST_ENTRY_OR_NULL(&k_tick_list, k_task_t, tick_list); + next_expires = first ? first->tick_expires : TOS_TIME_FOREVER; + + TOS_CPU_INT_ENABLE(); + return next_expires; +} + +__API__ void tos_tick_handler(void) +{ + if (unlikely(!tos_knl_is_running())) { + return; + } + + tick_update((k_tick_t)1u); + +#if TOS_CFG_TIMER_EN > 0u && TOS_CFG_TIMER_AS_PROC > 0u + timer_update(); +#endif + +#if TOS_CFG_ROUND_ROBIN_EN > 0u + robin_sched(k_curr_task->prio); +#endif +} + diff --git a/TencentOS_Tiny/kernel/core/tos_time.c b/TencentOS_Tiny/kernel/core/tos_time.c new file mode 100644 index 0000000..bbf180c --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_time.c @@ -0,0 +1,66 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ k_tick_t tos_systick_get(void) +{ + TOS_CPU_CPSR_ALLOC(); + k_tick_t tick; + + TOS_CPU_INT_DISABLE(); + tick = k_tick_count; + TOS_CPU_INT_ENABLE(); + return tick; +} + +__API__ void tos_systick_set(k_tick_t tick) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_CPU_INT_DISABLE(); + k_tick_count = tick; + TOS_CPU_INT_ENABLE(); +} + +__API__ k_time_t tos_tick2millisec(k_tick_t tick) +{ + return (k_time_t)(tick * (K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_TICK_PER_SECOND)); +} + +__API__ k_tick_t tos_millisec2tick(k_time_t ms) +{ + return (k_tick_t)(ms * (TOS_CFG_CPU_TICK_PER_SECOND / K_TIME_MILLISEC_PER_SEC)); +} + +__API__ k_err_t tos_sleep_ms(k_time_t ms) +{ + return tos_task_delay(tos_millisec2tick(ms)); +} + +__STATIC_INLINE__ k_tick_t time_hmsm2tick(k_time_t hour, k_time_t minute, k_time_t second, k_time_t millisec) +{ + return ((k_tick_t)hour * (k_tick_t)3600u + (k_tick_t)minute * (k_tick_t)60u + + (k_tick_t)second) * TOS_CFG_CPU_TICK_PER_SECOND + + (TOS_CFG_CPU_TICK_PER_SECOND * ((k_tick_t)millisec + (k_tick_t)500u / TOS_CFG_CPU_TICK_PER_SECOND)) / (k_tick_t)1000u; +} + +__API__ k_err_t tos_sleep_hmsm(k_time_t hour, k_time_t minute, k_time_t second, k_time_t millisec) +{ + return tos_task_delay(time_hmsm2tick(hour, minute, second, millisec)); +} + diff --git a/TencentOS_Tiny/kernel/core/tos_timer.c b/TencentOS_Tiny/kernel/core/tos_timer.c new file mode 100644 index 0000000..4e71f9c --- /dev/null +++ b/TencentOS_Tiny/kernel/core/tos_timer.c @@ -0,0 +1,367 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_TIMER_EN > 0u + +__STATIC__ void timer_place(k_timer_t *tmr) +{ + TOS_CPU_CPSR_ALLOC(); + k_timer_t *iter = K_NULL; + + TOS_CPU_INT_DISABLE(); + + tmr->expires += k_tick_count; + + TOS_LIST_FOR_EACH_ENTRY(iter, k_timer_t, list, &k_timer_ctl.list) { + if (tmr->expires < iter->expires) { + break; + } + } + tos_list_add_tail(&tmr->list, &iter->list); + + if (k_timer_ctl.list.next == &tmr->list) { + // we are the first guy now + k_timer_ctl.next_expires = tmr->expires; + +#if TOS_CFG_TIMER_AS_PROC == 0u + if (task_state_is_sleeping(&k_timer_task)) { + tos_task_delay_abort(&k_timer_task); + } +#endif + } + +#if TOS_CFG_TIMER_AS_PROC == 0u + if (task_state_is_suspended(&k_timer_task)) { + tos_task_resume(&k_timer_task); + } +#endif + + TOS_CPU_INT_ENABLE(); +} + +__STATIC__ void timer_takeoff(k_timer_t *tmr) +{ + TOS_CPU_CPSR_ALLOC(); + k_timer_t *first, *next; + + TOS_CPU_INT_DISABLE(); + + first = TOS_LIST_FIRST_ENTRY(&k_timer_ctl.list, k_timer_t, list); + + tos_list_del(&tmr->list); + + if (first == tmr) { + // if the first guy removed, we need to refresh k_timer_ctl.next_expires + next = TOS_LIST_FIRST_ENTRY_OR_NULL(&tmr->list, k_timer_t, list); + if (!next) { + // the only guy removed + k_timer_ctl.next_expires = TOS_TIME_FOREVER; + } else { + k_timer_ctl.next_expires = next->expires; + } + } + + TOS_CPU_INT_ENABLE(); +} + +__STATIC_INLINE__ void timer_reset(k_timer_t *tmr) +{ + tmr->state = TIMER_STATE_UNUSED; + tmr->delay = (k_tick_t)0u; + tmr->expires = (k_tick_t)0u; + tmr->period = (k_tick_t)0u; + tmr->opt = (k_opt_t)0u; + tmr->cb = K_NULL; + tmr->cb_arg = K_NULL; + tos_list_init(&tmr->list); + + TOS_OBJ_DEINIT(tmr); +} + +__API__ k_err_t tos_timer_create(k_timer_t *tmr, + k_tick_t delay, + k_tick_t period, + k_timer_callback_t callback, + void *cb_arg, + k_opt_t opt) +{ + TOS_PTR_SANITY_CHECK(tmr); + TOS_PTR_SANITY_CHECK(callback); + + if (opt == TOS_OPT_TIMER_PERIODIC && period == (k_tick_t)0u) { + return K_ERR_TIMER_INVALID_PERIOD; + } + + if (opt == TOS_OPT_TIMER_ONESHOT && delay == (k_tick_t)0u) { + // if you create a oneshot timer and delay 0 to trigger, why don't just call the timer_callback? + return K_ERR_TIMER_INVALID_DELAY; + } + + if (opt != TOS_OPT_TIMER_ONESHOT && opt != TOS_OPT_TIMER_PERIODIC) { + return K_ERR_TIMER_INVALID_OPT; + } + + if (delay == TOS_TIME_FOREVER) { + return K_ERR_TIMER_DELAY_FOREVER; + } + + if (period == TOS_TIME_FOREVER) { + return K_ERR_TIMER_PERIOD_FOREVER; + } + + tmr->state = TIMER_STATE_STOPPED; + tmr->delay = delay; + tmr->expires = (k_tick_t)0u; + tmr->period = period; + tmr->opt = opt; + tmr->cb = callback; + tmr->cb_arg = cb_arg; + tos_list_init(&tmr->list); + + TOS_OBJ_INIT(tmr, KNL_OBJ_TYPE_TIMER); + + return K_ERR_NONE; +} + +__API__ k_err_t tos_timer_destroy(k_timer_t *tmr) +{ + TOS_PTR_SANITY_CHECK(tmr); + TOS_OBJ_VERIFY(tmr, KNL_OBJ_TYPE_TIMER); + + if (tmr->state == TIMER_STATE_UNUSED) { + return K_ERR_TIMER_INACTIVE; + } + + if (tmr->state == TIMER_STATE_RUNNING) { + timer_takeoff(tmr); + } + + timer_reset(tmr); + return K_ERR_NONE; +} + +__API__ k_err_t tos_timer_start(k_timer_t *tmr) +{ + TOS_PTR_SANITY_CHECK(tmr); + TOS_OBJ_VERIFY(tmr, KNL_OBJ_TYPE_TIMER); + + if (tmr->state == TIMER_STATE_UNUSED) { + return K_ERR_TIMER_INACTIVE; + } + + if (tmr->state == TIMER_STATE_RUNNING) { + timer_takeoff(tmr); + tmr->expires = tmr->delay; + timer_place(tmr); + return K_ERR_NONE; + } + + if (tmr->state == TIMER_STATE_STOPPED || + tmr->state == TIMER_STATE_COMPLETED) { + tmr->state = TIMER_STATE_RUNNING; + if (tmr->delay == (k_tick_t)0u) { + tmr->expires = tmr->period; + } else { + tmr->expires = tmr->delay; + } + timer_place(tmr); + return K_ERR_NONE; + } + + return K_ERR_TIMER_INVALID_STATE; +} + +__API__ k_err_t tos_timer_stop(k_timer_t *tmr) +{ + TOS_PTR_SANITY_CHECK(tmr); + TOS_OBJ_VERIFY(tmr, KNL_OBJ_TYPE_TIMER); + + if (tmr->state == TIMER_STATE_UNUSED) { + return K_ERR_TIMER_INACTIVE; + } + + if (tmr->state == TIMER_STATE_COMPLETED || + tmr->state == TIMER_STATE_STOPPED) { + return K_ERR_TIMER_STOPPED; + } + + if (tmr->state == TIMER_STATE_RUNNING) { + tmr->state = TIMER_STATE_STOPPED; + timer_takeoff(tmr); + } + + return K_ERR_NONE; +} + +__STATIC__ k_err_t timer_change(k_timer_t *tmr, k_tick_t new_val, timer_change_type_t change_type) +{ + TOS_PTR_SANITY_CHECK(tmr); + TOS_OBJ_VERIFY(tmr, KNL_OBJ_TYPE_TIMER); + + if (tmr->state == TIMER_STATE_UNUSED) { + return K_ERR_TIMER_INACTIVE; + } + + if (tmr->state == TIMER_STATE_RUNNING) { + return K_ERR_TIMER_RUNNING; + } + + if (tmr->opt == TOS_OPT_TIMER_ONESHOT && + change_type == TIMER_CHANGE_TYPE_DELAY && + new_val == (k_tick_t)0u) { + return K_ERR_TIMER_INVALID_DELAY; + } + + if (tmr->opt == TOS_OPT_TIMER_PERIODIC && + change_type == TIMER_CHANGE_TYPE_PERIOD && + new_val == (k_tick_t)0u) { + return K_ERR_TIMER_INVALID_PERIOD; + } + + if (change_type == TIMER_CHANGE_TYPE_DELAY) { + tmr->delay = new_val; + } else { + tmr->period = new_val; + } + + return K_ERR_NONE; +} + +__API__ k_err_t tos_timer_delay_change(k_timer_t *tmr, k_tick_t delay) +{ + return timer_change(tmr, delay, TIMER_CHANGE_TYPE_DELAY); +} + +__API__ k_err_t tos_timer_period_change(k_timer_t *tmr, k_tick_t period) +{ + return timer_change(tmr, period, TIMER_CHANGE_TYPE_PERIOD); +} + +__KNL__ k_tick_t timer_next_expires_get(void) +{ + TOS_CPU_CPSR_ALLOC(); + k_tick_t next_expires; + + TOS_CPU_INT_DISABLE(); + + if (k_timer_ctl.next_expires == TOS_TIME_FOREVER) { + next_expires = TOS_TIME_FOREVER; + } else if (k_timer_ctl.next_expires <= k_tick_count) { + next_expires = (k_tick_t)0u; + } else { + next_expires = k_timer_ctl.next_expires - k_tick_count; + } + + TOS_CPU_INT_ENABLE(); + return next_expires; +} + +#if TOS_CFG_TIMER_AS_PROC > 0u + +__KNL__ void timer_update(void) +{ + k_timer_t *tmr, *tmp; + + if (k_timer_ctl.next_expires > k_tick_count) { // not yet + return; + } + + tos_knl_sched_lock(); + + TOS_LIST_FOR_EACH_ENTRY_SAFE(tmr, tmp, k_timer_t, list, &k_timer_ctl.list) { + if (tmr->expires > k_tick_count) { + break; + } + + // time's up + timer_takeoff(tmr); + + if (tmr->opt == TOS_OPT_TIMER_PERIODIC) { + tmr->expires = tmr->period; + timer_place(tmr); + } else { + tmr->state = TIMER_STATE_COMPLETED; + } + + (*tmr->cb)(tmr->cb_arg); + } + + tos_knl_sched_unlock(); +} + +#else /* TOS_CFG_TIMER_AS_PROC > 0u */ + +__STATIC__ void timer_task_entry(void *arg) +{ + k_timer_t *tmr, *tmp; + k_tick_t next_expires; + + arg = arg; // make compiler happy + while (K_TRUE) { + next_expires = timer_next_expires_get(); + if (next_expires == TOS_TIME_FOREVER) { + tos_task_suspend(K_NULL); + } else if (next_expires > (k_tick_t)0u) { + tos_task_delay(next_expires); + } + + tos_knl_sched_lock(); + + TOS_LIST_FOR_EACH_ENTRY_SAFE(tmr, tmp, k_timer_t, list, &k_timer_ctl.list) { + if (tmr->expires > k_tick_count) { // not yet + break; + } + + // time's up + timer_takeoff(tmr); + + if (tmr->opt == TOS_OPT_TIMER_PERIODIC) { + tmr->expires = tmr->period; + timer_place(tmr); + } else { + tmr->state = TIMER_STATE_COMPLETED; + } + + (*tmr->cb)(tmr->cb_arg); + } + + tos_knl_sched_unlock(); + } +} + +#endif + +__KNL__ k_err_t timer_init(void) +{ +#if TOS_CFG_TIMER_AS_PROC > 0u + return K_ERR_NONE; +#else + return tos_task_create(&k_timer_task, + "timer", + timer_task_entry, + K_NULL, + k_timer_task_prio, + k_timer_task_stk_addr, + k_timer_task_stk_size, + 0); +#endif +} + +#endif + diff --git a/TencentOS_Tiny/kernel/hal/include/tos_hal.h b/TencentOS_Tiny/kernel/hal/include/tos_hal.h new file mode 100644 index 0000000..bf4250d --- /dev/null +++ b/TencentOS_Tiny/kernel/hal/include/tos_hal.h @@ -0,0 +1,26 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_HAL_H_ +#define _TOS_HAL_H_ + +#include "tos_k.h" +#include "tos_hal_sd.h" +#include "tos_hal_uart.h" + +#endif + diff --git a/TencentOS_Tiny/kernel/hal/include/tos_hal_sd.h b/TencentOS_Tiny/kernel/hal/include/tos_hal_sd.h new file mode 100644 index 0000000..e48eacd --- /dev/null +++ b/TencentOS_Tiny/kernel/hal/include/tos_hal_sd.h @@ -0,0 +1,66 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_HAL_SD_H_ +#define _TOS_HAL_SD_H_ + +typedef enum hal_sd_state_en { + HAL_SD_STAT_RESET, /*< not yet initialized or disabled */ + HAL_SD_STAT_READY, /*< initialized and ready for use */ + HAL_SD_STAT_TIMEOUT, /*< timeout state */ + HAL_SD_STAT_BUSY, /*< process ongoing */ + HAL_SD_STAT_PROGRAMMING, /*< programming state */ + HAL_SD_STAT_RECEIVING, /*< receinving state */ + HAL_SD_STAT_TRANSFER, /*< transfert state */ + HAL_SD_STAT_ERROR, /*< error state */ +} hal_sd_state_t; + +typedef struct hal_sd_info_st { + uint32_t card_type; /*< card type */ + uint32_t card_version; /*< card version */ + uint32_t class; /*< card class */ + uint32_t relative_card_addr; /*< relative card address */ + uint32_t blk_num; /*< card capacity in blocks */ + uint32_t blk_size; /*< one block size in bytes */ + uint32_t logical_blk_num; /*< card logical capacity in blocks */ + uint32_t logical_blk_size; /*< logical block size in bytes */ +} hal_sd_info_t; + +typedef struct hal_sd_st { + void *private_sd; +} hal_sd_t; + +__API__ int tos_hal_sd_init(hal_sd_t *sd); + +__API__ int tos_hal_sd_read(hal_sd_t *sd, uint8_t *buf, uint32_t blk_addr, uint32_t blk_num, uint32_t timeout); + +__API__ int tos_hal_sd_write(hal_sd_t *sd, const uint8_t *buf, uint32_t blk_addr, uint32_t blk_num, uint32_t timeout); + +__API__ int tos_hal_sd_read_dma(hal_sd_t *sd, uint8_t *buf, uint32_t blk_addr, uint32_t blk_num); + +__API__ int tos_hal_sd_write_dma(hal_sd_t *sd, const uint8_t *buf, uint32_t blk_addr, uint32_t blk_num); + +__API__ int tos_hal_sd_erase(hal_sd_t *sd, uint32_t blk_add_start, uint32_t blk_addr_end); + +__API__ int tos_hal_sd_info_get(hal_sd_t *sd, hal_sd_info_t *info); + +__API__ int tos_hal_sd_state_get(hal_sd_t *sd, hal_sd_state_t *state); + +__API__ int tos_hal_sd_deinit(hal_sd_t *sd); + +#endif + diff --git a/TencentOS_Tiny/kernel/hal/include/tos_hal_uart.h b/TencentOS_Tiny/kernel/hal/include/tos_hal_uart.h new file mode 100644 index 0000000..8a688ec --- /dev/null +++ b/TencentOS_Tiny/kernel/hal/include/tos_hal_uart.h @@ -0,0 +1,45 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_HAL_UART_H_ +#define _TOS_HAL_UART_H_ + +typedef enum hal_uart_port_en { + HAL_UART_PORT_0 = 0, + HAL_UART_PORT_1, + HAL_UART_PORT_2, + HAL_UART_PORT_3, + HAL_UART_PORT_4, + HAL_UART_PORT_5, + HAL_UART_PORT_6, +} hal_uart_port_t; + +typedef struct hal_uart_st { + hal_uart_port_t port; + void *private_uart; +} hal_uart_t; + +__API__ int tos_hal_uart_init(hal_uart_t *uart, hal_uart_port_t port); + +__API__ int tos_hal_uart_write(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout); + +__API__ int tos_hal_uart_read(hal_uart_t *uart, const uint8_t *buf, size_t size, uint32_t timeout); + +__API__ int tos_hal_uart_deinit(hal_uart_t *uart); + +#endif + diff --git a/TencentOS_Tiny/kernel/pm/include/tos_pm.h b/TencentOS_Tiny/kernel/pm/include/tos_pm.h new file mode 100644 index 0000000..c4ae722 --- /dev/null +++ b/TencentOS_Tiny/kernel/pm/include/tos_pm.h @@ -0,0 +1,103 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_PM_H_ +#define _TOS_PM_H_ + +#if TOS_CFG_PWR_MGR_EN > 0u + +#define K_PM_DEVICE_MAX_COUNT 10u + +typedef enum idle_power_manager_mode_en { + IDLE_POWER_MANAGER_MODE_SLEEP, + IDLE_POWER_MANAGER_MODE_TICKLESS, +} idle_pwrmgr_mode_t; + +/* + Low-power mode summary +|-------------------------------------------------------------------------------------------------------------------| +| Mode name | Entry | Wakeup | Effect on 1.8V | Effect on VDD | Voltage regulator | +| | | | domain clocks | domain clocks | | +|----------------|------------------|--------------------|--------------------|-----------------|-------------------| +| Sleep | WFI | Any interrupt | CPU clock OFF | | | +| (Sleep now or |------------------|--------------------| no effect on other | None | ON | +| Sleep-on-exit) | WFE | Wakeup event | clocks or analog | | | +| | | | clock sources | | | +|----------------|------------------|--------------------|--------------------|-----------------|-------------------| +| | | | | | ON or in | +| Stop | PDDS and LPDS | Any EXTI line | | | low-power mode | +| | bits + SLEEPDEEP | (configured in the | | | (depends on Power | +| | bit + WFI or WFE | EXTI registers | | | control register | +| | | | | | (PWR_CR) | +|----------------|------------------|--------------------| All 1.8V domain | HSI and HSE |-------------------| +| | | WKUP pin rising | clocks OFF | oscillators OFF | | +| Standby | PDDS bit + | edge, RTC alarm, | | | | +| | SLEEPDEEP bit + | external reset in | | | OFF | +| | WFI or WFE | NRST pin, | | | | +| | | IWDG reset | | | | +| | | | | | | +|-------------------------------------------------------------------------------------------------------------------| + */ +typedef enum k_cpu_low_power_mode_en { + TOS_LOW_POWER_MODE_NONE = 0, /* if set to NONE, disable low power mode */ + TOS_LOW_POWER_MODE_SLEEP, /* wakeup source: systick/tim/rtc */ + TOS_LOW_POWER_MODE_STOP, /* wakeup source: rtc wakeup/alarm */ + TOS_LOW_POWER_MODE_STANDBY, /* wakeup source: rtc alarm */ + __LOW_POWER_MODE_DUMMY, +} k_cpu_lpwr_mode_t; + +typedef struct k_pm_device_st { + char *name; + + int (*init)(void); + int (*suspend)(void); + int (*resume)(void); +} k_pm_device_t; + +typedef struct pm_device_control_st { + uint8_t count; + k_pm_device_t *mgr[K_PM_DEVICE_MAX_COUNT]; +} pm_device_ctl_t; + +#if TOS_CFG_TICKLESS_EN > 0u +__API__ k_err_t tos_pm_cpu_lpwr_mode_set(k_cpu_lpwr_mode_t cpu_lpwr_mode); +#endif + +__API__ k_err_t tos_pm_device_register(k_pm_device_t *device); + +__KNL__ void pm_init(void); + +__KNL__ void pm_cpu_lpwr_mode_enter(k_cpu_lpwr_mode_t lpwr_mode); + +__KNL__ k_cpu_lpwr_mode_t pm_cpu_lpwr_mode_get(void); + +__KNL__ void pm_idle_pwr_mgr_mode_set(idle_pwrmgr_mode_t idle_pwrmgr_mode); + +__KNL__ int pm_idle_pwr_mgr_mode_is_sleep(void); + +__KNL__ int pm_idle_pwr_mgr_mode_is_tickless(void); + +__KNL__ void pm_power_manager(void); + +__KNL__ int pm_device_suspend(void); + +__KNL__ int pm_device_resume(void); + +#endif /* TOS_CFG_PWR_MGR_EN */ + +#endif /* _TOS_PM_H_ */ + diff --git a/TencentOS_Tiny/kernel/pm/include/tos_tickless.h b/TencentOS_Tiny/kernel/pm/include/tos_tickless.h new file mode 100644 index 0000000..d9bc2f8 --- /dev/null +++ b/TencentOS_Tiny/kernel/pm/include/tos_tickless.h @@ -0,0 +1,45 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_TICKLESS_H_ +#define _TOS_TICKLESS_H_ + +#if TOS_CFG_TICKLESS_EN > 0u + +typedef struct k_tickless_wakeup_alarm_st { + int (*init)(void); + int (*setup)(k_time_t millisecond); + int (*dismiss)(void); + k_time_t (*max_delay)(void); /* in millisecond */ +} k_tickless_wkup_alarm_t; + +__API__ void tos_tickless_wkup_alarm_install(k_cpu_lpwr_mode_t mode, k_tickless_wkup_alarm_t *wkup_alarm); + +__API__ k_err_t tos_tickless_wkup_alarm_init(k_cpu_lpwr_mode_t mode); + +__HOOK__ int tos_bsp_tickless_setup(void); + +__KNL__ int tickless_wkup_alarm_is_installed(k_cpu_lpwr_mode_t mode); + +__KNL__ void tickless_init(void); + +__KNL__ void tickless_proc(void); + +#endif /* TOS_CFG_TICKLESS_EN */ + +#endif /* _TOS_TICKLESS_H_ */ + diff --git a/TencentOS_Tiny/kernel/pm/tos_pm.c b/TencentOS_Tiny/kernel/pm/tos_pm.c new file mode 100644 index 0000000..66420d5 --- /dev/null +++ b/TencentOS_Tiny/kernel/pm/tos_pm.c @@ -0,0 +1,162 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_PWR_MGR_EN > 0u + +#if TOS_CFG_TICKLESS_EN > 0u +__API__ k_err_t tos_pm_cpu_lpwr_mode_set(k_cpu_lpwr_mode_t cpu_lpwr_mode) +{ + TOS_CPU_CPSR_ALLOC(); + + if (cpu_lpwr_mode != TOS_LOW_POWER_MODE_NONE && + !tickless_wkup_alarm_is_installed(cpu_lpwr_mode)) { + return K_ERR_PM_WKUP_SOURCE_NOT_INSTALL; + } + + TOS_CPU_INT_DISABLE(); + k_cpu_lpwr_mode = cpu_lpwr_mode; + TOS_CPU_INT_ENABLE(); + return K_ERR_NONE; +} +#endif + +__STATIC__ int pm_device_is_registered(k_pm_device_t *device) +{ + uint8_t i = 0; + + for (i = 0; i < k_pm_device_ctl.count; ++i) { + if (strcmp(k_pm_device_ctl.mgr[i]->name, device->name) == 0) { + return 1; + } + } + return 0; +} + +__API__ k_err_t tos_pm_device_register(k_pm_device_t *device) +{ + TOS_PTR_SANITY_CHECK(device); + + if (pm_device_is_registered(device)) { + return K_ERR_PM_DEVICE_ALREADY_REG; + } + + if (k_pm_device_ctl.count >= K_PM_DEVICE_MAX_COUNT) { + return K_ERR_PM_DEVICE_OVERFLOW; + } + + k_pm_device_ctl.mgr[k_pm_device_ctl.count++] = device; + + return K_ERR_NONE; +} + +__KNL__ void pm_init(void) +{ + memset(&k_pm_device_ctl, 0, sizeof(k_pm_device_ctl)); + k_pm_device_ctl.count = 0u; +} + +__STATIC_INLINE__ void pm_cpu_sleep_mode_enter(void) +{ + cpu_sleep_mode_enter(); +} + +__STATIC_INLINE__ void pm_cpu_stop_mode_enter(void) +{ + cpu_stop_mode_enter(); +} + +__STATIC_INLINE__ void pm_cpu_standby_mode_enter(void) +{ + cpu_standby_mode_enter(); +} + +__KNL__ void pm_cpu_lpwr_mode_enter(k_cpu_lpwr_mode_t lpwr_mode) +{ + if (TOS_LOW_POWER_MODE_SLEEP == lpwr_mode) { + pm_cpu_sleep_mode_enter(); + } else if (TOS_LOW_POWER_MODE_STOP == lpwr_mode) { + pm_device_suspend(); + pm_cpu_stop_mode_enter(); + pm_device_resume(); + } else if (TOS_LOW_POWER_MODE_STANDBY == lpwr_mode) { + pm_device_suspend(); + pm_cpu_standby_mode_enter(); + pm_device_resume(); + } +} + +__KNL__ k_cpu_lpwr_mode_t pm_cpu_lpwr_mode_get(void) +{ + return k_cpu_lpwr_mode; +} + +__KNL__ void pm_idle_pwr_mgr_mode_set(idle_pwrmgr_mode_t idle_pwrmgr_mode) +{ + k_idle_pwr_mgr_mode = idle_pwrmgr_mode; +} + +__KNL__ int pm_idle_pwr_mgr_mode_is_sleep(void) +{ + return k_idle_pwr_mgr_mode == IDLE_POWER_MANAGER_MODE_SLEEP; +} + +__KNL__ int pm_idle_pwr_mgr_mode_is_tickless(void) +{ + return k_idle_pwr_mgr_mode == IDLE_POWER_MANAGER_MODE_TICKLESS; +} + +__KNL__ void pm_power_manager(void) +{ + if (pm_idle_pwr_mgr_mode_is_sleep()) { + pm_cpu_sleep_mode_enter(); + } + +#if TOS_CFG_TICKLESS_EN > 0u + else if (pm_idle_pwr_mgr_mode_is_tickless()) { + tickless_proc(); + } +#endif +} + +__KNL__ int pm_device_suspend(void) +{ + uint8_t i = 0; + + for (i = 0; i < k_pm_device_ctl.count; ++i) { + if (*k_pm_device_ctl.mgr[i]->suspend) { + (*k_pm_device_ctl.mgr[i]->suspend)(); + } + } + return 0; +} + +__KNL__ int pm_device_resume(void) +{ + uint8_t i = 0; + + for (i = 0; i < k_pm_device_ctl.count; ++i) { + if (*k_pm_device_ctl.mgr[i]->resume) { + (*k_pm_device_ctl.mgr[i]->resume)(); + } + } + return 0; +} + +#endif + diff --git a/TencentOS_Tiny/kernel/pm/tos_tickless.c b/TencentOS_Tiny/kernel/pm/tos_tickless.c new file mode 100644 index 0000000..4446eac --- /dev/null +++ b/TencentOS_Tiny/kernel/pm/tos_tickless.c @@ -0,0 +1,175 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_TICKLESS_EN > 0u + +__API__ void tos_tickless_wkup_alarm_install(k_cpu_lpwr_mode_t mode, k_tickless_wkup_alarm_t *wkup_alarm) +{ + k_tickless_wkup_alarm[mode] = wkup_alarm; +} + +__API__ k_err_t tos_tickless_wkup_alarm_init(k_cpu_lpwr_mode_t mode) +{ + if (!k_tickless_wkup_alarm[mode]) { + return K_ERR_TICKLESS_WKUP_ALARM_NOT_INSTALLED; + } + + if (!k_tickless_wkup_alarm[mode]->init) { + return K_ERR_TICKLESS_WKUP_ALARM_NO_INIT; + } + + if (k_tickless_wkup_alarm[mode]->init() != 0) { + return K_ERR_TICKLESS_WKUP_ALARM_INIT_FAILED; + } + return K_ERR_NONE; +} + +__KNL__ int tickless_wkup_alarm_is_installed(k_cpu_lpwr_mode_t mode) +{ + return k_tickless_wkup_alarm[mode] != K_NULL; +} + +__STATIC__ int tickless_wkup_alarm_setup(k_cpu_lpwr_mode_t mode, k_time_t expires) +{ + if (k_tickless_wkup_alarm[mode] && k_tickless_wkup_alarm[mode]->setup) { + return k_tickless_wkup_alarm[mode]->setup(expires); + } + return -1; +} + +__STATIC__ int tickless_wkup_alarm_dismiss(k_cpu_lpwr_mode_t mode) +{ + if (k_tickless_wkup_alarm[mode] && k_tickless_wkup_alarm[mode]->dismiss) { + return k_tickless_wkup_alarm[mode]->dismiss(); + } + return -1; +} + +__STATIC__ k_time_t tickless_wkup_alarm_max_delay(k_cpu_lpwr_mode_t mode) +{ + if (k_tickless_wkup_alarm[mode] && k_tickless_wkup_alarm[mode]->max_delay) { + return k_tickless_wkup_alarm[mode]->max_delay(); + } + return (k_time_t)0u; +} + +__STATIC__ k_time_t tickless_cpu_sleep_time_get(k_cpu_lpwr_mode_t lpwr_mode) +{ + k_tick_t next_expires; + k_time_t time_sleep_ms, max_delay_ms; + + /* the max time(in millisecond) we can sleep */ + max_delay_ms = tickless_wkup_alarm_max_delay(lpwr_mode); + + next_expires = knl_next_expires_get(); + if (next_expires == TOS_TIME_FOREVER) { + return max_delay_ms; + } + + /* how much time should we sleep(in millisecond) */ + time_sleep_ms = (k_time_t)(next_expires * K_TIME_MILLISEC_PER_SEC / k_cpu_tick_per_second); + + return time_sleep_ms > max_delay_ms ? max_delay_ms : time_sleep_ms; +} + +__STATIC__ void tickless_tick_suspend(void) +{ + cpu_systick_suspend(); + cpu_systick_pending_reset(); +} + +__STATIC__ void tickless_tick_resume(void) +{ + cpu_systick_suspend(); + cpu_systick_reset(); + cpu_systick_resume(); +} + +__STATIC__ void tickless_tick_fix(k_tick_t tick_sleep) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_CPU_INT_DISABLE(); + + /* we wakeup from SLEEP mode, fix the system's tick & timer */ + tick_update(tick_sleep); + +#if TOS_CFG_TIMER_EN > 0u && TOS_CFG_TIMER_AS_PROC > 0u + timer_update(); +#endif + + tickless_tick_resume(); + + TOS_CPU_INT_ENABLE(); +} + +__STATIC__ void tickless_enter(void) +{ + tickless_tick_suspend(); +} + +__STATIC__ void tickless_leave(k_time_t time_sleep_ms) +{ + k_tick_t tick_sleep; + + /* how many "ticks" have we sleep */ + tick_sleep = k_cpu_tick_per_second * time_sleep_ms / K_TIME_MILLISEC_PER_SEC; + + tickless_tick_fix(tick_sleep); + + knl_sched(); +} + +__KNL__ void tickless_proc(void) +{ + TOS_CPU_CPSR_ALLOC(); + k_time_t time_sleep; + k_cpu_lpwr_mode_t lpwr_mode; + + lpwr_mode = pm_cpu_lpwr_mode_get(); + if (lpwr_mode == TOS_LOW_POWER_MODE_NONE || + !tickless_wkup_alarm_is_installed(lpwr_mode)) { + return; + } + + TOS_CPU_INT_DISABLE(); + + time_sleep = tickless_cpu_sleep_time_get(lpwr_mode); /* in millisecond */ + if (unlikely(time_sleep == (k_time_t)0)) { + TOS_CPU_INT_ENABLE(); + return; + } + + tickless_enter(); + TOS_CPU_INT_ENABLE(); + tickless_wkup_alarm_setup(lpwr_mode, time_sleep); + pm_cpu_lpwr_mode_enter(lpwr_mode); + tickless_wkup_alarm_dismiss(lpwr_mode); + tickless_leave(time_sleep); +} + +__KNL__ void tickless_init(void) +{ + pm_idle_pwr_mgr_mode_set(IDLE_POWER_MANAGER_MODE_TICKLESS); + + tos_bsp_tickless_setup(); +} + +#endif + diff --git a/TencentOS_Tiny/tos_js/tos_js.c b/TencentOS_Tiny/tos_js/tos_js.c new file mode 100644 index 0000000..663ab84 --- /dev/null +++ b/TencentOS_Tiny/tos_js/tos_js.c @@ -0,0 +1,1431 @@ +// Copyright (c) 2013-2022 Cesanta Software Limited +// All rights reserved +// +// This software is dual-licensed: you can redistribute it and/or modify +// it under the terms of the GNU Affero General Public License version 3 as +// published by the Free Software Foundation. For the terms of this +// license, see http://www.fsf.org/licensing/licenses/agpl-3.0.html +// +// You are free to use this software under the terms of the GNU General +// Public License, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +// See the GNU General Public License for more details. +// +// Alternatively, you can license this software under a commercial +// license, please contact us at https://cesanta.com/contact.html + +//#if defined(__GNUC__) && !defined(JS_OPT) && !defined(ARDUINO_AVR_UNO) && \ +// !defined(ARDUINO_AVR_NANO) && !defined(ARDUINO_AVR_PRO) && \ +// !defined(__APPLE__) +//#pragma GCC optimize("O3,inline") +//#endif + +#include +#include +#include +#include +#include +#include + +#include "tos_js.h" + +#ifndef JS_EXPR_MAX +#define JS_EXPR_MAX 20 +#endif + +#ifndef JS_GC_THRESHOLD +#define JS_GC_THRESHOLD 0.75 +#endif + +typedef uint32_t jsoff_t; + +struct js { + jsoff_t css; // Max observed C stack size + jsoff_t lwm; // JS RAM low watermark: min free RAM observed + const char *code; // Currently parsed code snippet + char errmsg[33]; // Error message placeholder + uint8_t tok; // Last parsed token value + uint8_t consumed; // Indicator that last parsed token was consumed + uint8_t flags; // Execution flags, see F_* constants below +#define F_NOEXEC 1U // Parse code, but not execute +#define F_LOOP 2U // We're inside the loop +#define F_CALL 4U // We're inside a function call +#define F_BREAK 8U // Exit the loop +#define F_RETURN 16U // Return has been executed + jsoff_t clen; // Code snippet length + jsoff_t pos; // Current parsing position + jsoff_t toff; // Offset of the last parsed token + jsoff_t tlen; // Length of the last parsed token + jsoff_t nogc; // Entity offset to exclude from GC + jsval_t tval; // Holds last parsed numeric or string literal value + jsval_t scope; // Current scope + uint8_t *mem; // Available JS memory + jsoff_t size; // Memory size + jsoff_t brk; // Current mem usage boundary + jsoff_t gct; // GC threshold. If brk > gct, trigger GC + jsoff_t maxcss; // Maximum allowed C stack size usage + void *cstk; // C stack pointer at the beginning of js_eval() +}; + +// A JS memory stores diffenent entities: objects, properties, strings +// All entities are packed to the beginning of a buffer. +// The `brk` marks the end of the used memory: +// +// | entity1 | entity2| .... |entityN| unused memory | +// |---------|--------|------|-------|------------------------------| +// js.mem js.brk js.size +// +// Each entity is 4-byte aligned, therefore 2 LSB bits store entity type. +// Object: 8 bytes: offset of the first property, offset of the upper obj +// Property: 8 bytes + val: 4 byte next prop, 4 byte key offs, N byte value +// String: 4xN bytes: 4 byte len << 2, 4byte-aligned 0-terminated data +// +// If C functions are imported, they use the upper part of memory as stack for +// passing params. Each argument is pushed to the top of the memory as jsval_t, +// and js.size is decreased by sizeof(jsval_t), i.e. 8 bytes. When function +// returns, js.size is restored back. So js.size is used as a stack pointer. + +// clang-format off +enum { + TOK_ERR, TOK_EOF, TOK_IDENTIFIER, TOK_NUMBER, TOK_STRING, TOK_SEMICOLON, + TOK_LPAREN, TOK_RPAREN, TOK_LBRACE, TOK_RBRACE, + // Keyword tokens + TOK_BREAK = 50, TOK_CASE, TOK_CATCH, TOK_CLASS, TOK_CONST, TOK_CONTINUE, + TOK_DEFAULT, TOK_DELETE, TOK_DO, TOK_ELSE, TOK_FINALLY, TOK_FOR, TOK_FUNC, + TOK_IF, TOK_IN, TOK_INSTANCEOF, TOK_LET, TOK_NEW, TOK_RETURN, TOK_SWITCH, + TOK_THIS, TOK_THROW, TOK_TRY, TOK_VAR, TOK_VOID, TOK_WHILE, TOK_WITH, + TOK_YIELD, TOK_UNDEF, TOK_NULL, TOK_TRUE, TOK_FALSE, + // JS Operator tokens + TOK_DOT = 100, TOK_CALL, TOK_POSTINC, TOK_POSTDEC, TOK_NOT, TOK_TILDA, // 100 + TOK_TYPEOF, TOK_UPLUS, TOK_UMINUS, TOK_EXP, TOK_MUL, TOK_DIV, TOK_REM, // 106 + TOK_PLUS, TOK_MINUS, TOK_SHL, TOK_SHR, TOK_ZSHR, TOK_LT, TOK_LE, TOK_GT, // 113 + TOK_GE, TOK_EQ, TOK_NE, TOK_AND, TOK_XOR, TOK_OR, TOK_LAND, TOK_LOR, // 121 + TOK_COLON, TOK_Q, TOK_ASSIGN, TOK_PLUS_ASSIGN, TOK_MINUS_ASSIGN, + TOK_MUL_ASSIGN, TOK_DIV_ASSIGN, TOK_REM_ASSIGN, TOK_SHL_ASSIGN, + TOK_SHR_ASSIGN, TOK_ZSHR_ASSIGN, TOK_AND_ASSIGN, TOK_XOR_ASSIGN, + TOK_OR_ASSIGN, TOK_COMMA, +}; + +enum { + // IMPORTANT: T_OBJ, T_PROP, T_STR must go first. That is required by the + // memory layout functions: memory entity types are encoded in the 2 bits, + // thus type values must be 0,1,2,3 + T_OBJ, T_PROP, T_STR, T_UNDEF, T_NULL, T_NUM, T_BOOL, T_FUNC, T_CODEREF, + T_CFUNC, T_ERR +}; + +static const char *typestr(uint8_t t) { + const char *names[] = { "object", "prop", "string", "undefined", "null", + "number", "boolean", "function", "coderef", + "cfunc", "err", "nan" }; + return (t < sizeof(names) / sizeof(names[0])) ? names[t] : "??"; +} + +// Pack JS values into uin64_t, double nan, per IEEE 754 +// 64bit "double": 1 bit sign, 11 bits exponent, 52 bits mantissa +// +// seeeeeee|eeeemmmm|mmmmmmmm|mmmmmmmm|mmmmmmmm|mmmmmmmm|mmmmmmmm|mmmmmmmm +// 11111111|11110000|00000000|00000000|00000000|00000000|00000000|00000000 inf +// 11111111|11111000|00000000|00000000|00000000|00000000|00000000|00000000 qnan +// +// 11111111|1111tttt|vvvvvvvv|vvvvvvvv|vvvvvvvv|vvvvvvvv|vvvvvvvv|vvvvvvvv +// NaN marker |type| 48-bit placeholder for values: pointers, strings +// +// On 64-bit platforms, pointers are really 48 bit only, so they can fit, +// provided they are sign extended +static jsval_t tov(double d) { union { double d; jsval_t v; } u = {d}; return u.v; } +static double tod(jsval_t v) { union { jsval_t v; double d; } u = {v}; return u.d; } +static jsval_t mkval(uint8_t type, uint64_t data) { return ((jsval_t) 0x7ff0U << 48U) | ((jsval_t) (type) << 48) | (data & 0xffffffffffffUL); } +static bool is_nan(jsval_t v) { return (v >> 52U) == 0x7ffU; } +static uint8_t vtype(jsval_t v) { return is_nan(v) ? ((v >> 48U) & 15U) : (uint8_t) T_NUM; } +static size_t vdata(jsval_t v) { return (size_t) (v & ~((jsval_t) 0x7fffUL << 48U)); } +static jsval_t mkcoderef(jsval_t off, jsoff_t len) { return mkval(T_CODEREF, (off & 0xffffffU) | ((jsval_t)(len & 0xffffffU) << 24U)); } +static jsoff_t coderefoff(jsval_t v) { return v & 0xffffffU; } +static jsoff_t codereflen(jsval_t v) { return (v >> 24U) & 0xffffffU; } + +static uint8_t unhex(uint8_t c) { return (c >= '0' && c <= '9') ? (uint8_t) (c - '0') : (c >= 'a' && c <= 'f') ? (uint8_t) (c - 'W') : (c >= 'A' && c <= 'F') ? (uint8_t) (c - '7') : 0; } +static bool is_space(int c) { return c == ' ' || c == '\r' || c == '\n' || c == '\t' || c == '\f' || c == '\v'; } +static bool is_digit(int c) { return c >= '0' && c <= '9'; } +static bool is_xdigit(int c) { return is_digit(c) || (c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F'); } +static bool is_alpha(int c) { return (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z'); } +static bool is_ident_begin(int c) { return c == '_' || c == '$' || is_alpha(c); } +static bool is_ident_continue(int c) { return c == '_' || c == '$' || is_alpha(c) || is_digit(c); } +static bool is_err(jsval_t v) { return vtype(v) == T_ERR; } +static bool is_unary(uint8_t tok) { return tok >= TOK_POSTINC && tok <= TOK_UMINUS; } +static bool is_assign(uint8_t tok) { return (tok >= TOK_ASSIGN && tok <= TOK_OR_ASSIGN); } +static void saveoff(struct js *js, jsoff_t off, jsoff_t val) { memcpy(&js->mem[off], &val, sizeof(val)); } +static void saveval(struct js *js, jsoff_t off, jsval_t val) { memcpy(&js->mem[off], &val, sizeof(val)); } +static jsoff_t loadoff(struct js *js, jsoff_t off) { jsoff_t v = 0; assert(js->brk <= js->size); memcpy(&v, &js->mem[off], sizeof(v)); return v; } +static jsoff_t offtolen(jsoff_t off) { return (off >> 2) - 1; } +static jsoff_t vstrlen(struct js *js, jsval_t v) { return offtolen(loadoff(js, (jsoff_t) vdata(v))); } +static jsval_t loadval(struct js *js, jsoff_t off) { jsval_t v = 0; memcpy(&v, &js->mem[off], sizeof(v)); return v; } +static jsval_t upper(struct js *js, jsval_t scope) { return mkval(T_OBJ, loadoff(js, (jsoff_t) (vdata(scope) + sizeof(jsoff_t)))); } +static jsoff_t align32(jsoff_t v) { return ((v + 3) >> 2) << 2; } + +#define CHECKV(_v) do { if (is_err(_v)) { res = (_v); goto done; } } while (0) +#define EXPECT(_tok, _e) do { if (next(js) != _tok) { _e; return js_mkerr(js, "parse error"); }; js->consumed = 1; } while (0) +// clang-format on + +// Forward declarations of the private functions +static size_t tostr(struct js *js, jsval_t value, char *buf, size_t len); +static jsval_t js_expr(struct js *js); +static jsval_t js_stmt(struct js *js); +static jsval_t do_op(struct js *, uint8_t op, jsval_t l, jsval_t r); + +static void setlwm(struct js *js) { + jsoff_t n = 0, css = 0; + if (js->brk < js->size) n = js->size - js->brk; + if (js->lwm > n) js->lwm = n; + if ((char *) js->cstk > (char *) &n) + css = (jsoff_t) ((char *) js->cstk - (char *) &n); + if (css > js->css) js->css = css; +} + +// Copy src to dst, make no overflows, 0-terminate. Return bytes copied +static size_t cpy(char *dst, size_t dstlen, const char *src, size_t srclen) { + size_t i = 0; + for (i = 0; i < dstlen && i < srclen && src[i] != 0; i++) dst[i] = src[i]; + if (dstlen > 0) dst[i < dstlen ? i : dstlen - 1] = '\0'; + return i; +} + +// Stringify JS object +static size_t strobj(struct js *js, jsval_t obj, char *buf, size_t len) { + size_t n = cpy(buf, len, "{", 1); + jsoff_t next = loadoff(js, (jsoff_t) vdata(obj)) & ~3U; // First prop offset + while (next < js->brk && next != 0) { // Iterate over props + jsoff_t koff = loadoff(js, next + (jsoff_t) sizeof(next)); + jsval_t val = loadval(js, next + (jsoff_t) (sizeof(next) + sizeof(koff))); + // printf("PROP %u, koff %u\n", next & ~3, koff); + n += cpy(buf + n, len - n, ",", n == 1 ? 0 : 1); + n += tostr(js, mkval(T_STR, koff), buf + n, len - n); + n += cpy(buf + n, len - n, ":", 1); + n += tostr(js, val, buf + n, len - n); + next = loadoff(js, next) & ~3U; // Load next prop offset + } + return n + cpy(buf + n, len - n, "}", 1); +} + +// Stringify numeric JS value +static size_t strnum(jsval_t value, char *buf, size_t len) { + double dv = tod(value), iv; + const char *fmt = modf(dv, &iv) == 0.0 ? "%.17g" : "%g"; + return (size_t) sprintf(buf, fmt, dv); +} + +// Return mem offset and length of the JS string +static jsoff_t vstr(struct js *js, jsval_t value, jsoff_t *len) { + jsoff_t off = (jsoff_t) vdata(value); + if (len) *len = offtolen(loadoff(js, off)); + return (jsoff_t) (off + sizeof(off)); +} + +// Stringify string JS value +static size_t strstring(struct js *js, jsval_t value, char *buf, size_t len) { + jsoff_t slen, off = vstr(js, value, &slen); + size_t n = 0; + n += cpy(buf + n, len - n, "\"", 1); + n += cpy(buf + n, len - n, (char *) &js->mem[off], slen); + n += cpy(buf + n, len - n, "\"", 1); + return n; +} + +// Stringify JS function +static size_t strfunc(struct js *js, jsval_t value, char *buf, size_t len) { + jsoff_t sn, off = vstr(js, value, &sn); + size_t n = cpy(buf, len, "function", 8); + return n + cpy(buf + n, len - n, (char *) &js->mem[off], sn); +} + +jsval_t js_mkerr(struct js *js, const char *xx, ...) { + va_list ap; + size_t n = cpy(js->errmsg, sizeof(js->errmsg), "ERROR: ", 7); + va_start(ap, xx); + vsnprintf(js->errmsg + n, sizeof(js->errmsg) - n, xx, ap); + va_end(ap); + js->errmsg[sizeof(js->errmsg) - 1] = '\0'; + js->pos = js->clen, js->tok = TOK_EOF, js->consumed = 0; // Jump to the end + return mkval(T_ERR, 0); +} + +// Stringify JS value into the given buffer +static size_t tostr(struct js *js, jsval_t value, char *buf, size_t len) { + switch (vtype(value)) { // clang-format off + case T_UNDEF: return cpy(buf, len, "undefined", 9); + case T_NULL: return cpy(buf, len, "null", 4); + case T_BOOL: return cpy(buf, len, vdata(value) & 1 ? "true" : "false", vdata(value) & 1 ? 4 : 5); + case T_OBJ: return strobj(js, value, buf, len); + case T_STR: return strstring(js, value, buf, len); + case T_NUM: return strnum(value, buf, len); + case T_FUNC: return strfunc(js, value, buf, len); + case T_CFUNC: return (size_t) snprintf(buf, len, "\"c_func_0x%lx\"", (unsigned long) vdata(value)); + case T_PROP: return (size_t) snprintf(buf, len, "PROP@%lu", (unsigned long) vdata(value)); + default: return (size_t) snprintf(buf, len, "VTYPE%d", vtype(value)); + } // clang-format on +} + +// Stringify JS value into a free JS memory block +const char *js_str(struct js *js, jsval_t value) { + // Leave jsoff_t placeholder between js->brk and a stringify buffer, + // in case if next step is convert it into a JS variable + char *buf = (char *) &js->mem[js->brk + sizeof(jsoff_t)]; + size_t len, available = js->size - js->brk - sizeof(jsoff_t); + if (is_err(value)) return js->errmsg; + if (js->brk + sizeof(jsoff_t) >= js->size) return ""; + len = tostr(js, value, buf, available); + js_mkstr(js, NULL, len); + return buf; +} + +static bool js_truthy(struct js *js, jsval_t v) { + uint8_t t = vtype(v); + return (t == T_BOOL && vdata(v) != 0) || (t == T_NUM && tod(v) != 0.0) || + (t == T_OBJ || t == T_FUNC) || (t == T_STR && vstrlen(js, v) > 0); +} + +static jsoff_t js_alloc(struct js *js, size_t size) { + jsoff_t ofs = js->brk; + size = align32((jsoff_t) size); // 4-byte align, (n + k - 1) / k * k + if (js->brk + size > js->size) return ~(jsoff_t) 0; + js->brk += (jsoff_t) size; + return ofs; +} + +static jsval_t mkentity(struct js *js, jsoff_t b, const void *buf, size_t len) { + jsoff_t ofs = js_alloc(js, len + sizeof(b)); + if (ofs == (jsoff_t) ~0) return js_mkerr(js, "oom"); + memcpy(&js->mem[ofs], &b, sizeof(b)); + // Using memmove - in case we're stringifying data from the free JS mem + if (buf != NULL) memmove(&js->mem[ofs + sizeof(b)], buf, len); + if ((b & 3) == T_STR) js->mem[ofs + sizeof(b) + len - 1] = 0; // 0-terminate + // printf("MKE: %u @ %u type %d\n", js->brk - ofs, ofs, b & 3); + return mkval(b & 3, ofs); +} + +jsval_t js_mkstr(struct js *js, const void *ptr, size_t len) { + jsoff_t n = (jsoff_t) (len + 1); + // printf("MKSTR %u %u\n", n, js->brk); + return mkentity(js, (jsoff_t) ((n << 2) | T_STR), ptr, n); +} + +static jsval_t mkobj(struct js *js, jsoff_t parent) { + return mkentity(js, 0 | T_OBJ, &parent, sizeof(parent)); +} + +static jsval_t setprop(struct js *js, jsval_t obj, jsval_t k, jsval_t v) { + jsoff_t koff = (jsoff_t) vdata(k); // Key offset + jsoff_t b, head = (jsoff_t) vdata(obj); // Property list head + char buf[sizeof(koff) + sizeof(v)]; // Property memory layout + memcpy(&b, &js->mem[head], sizeof(b)); // Load current 1st prop offset + memcpy(buf, &koff, sizeof(koff)); // Initialize prop data: copy key + memcpy(buf + sizeof(koff), &v, sizeof(v)); // Copy value + jsoff_t brk = js->brk | T_OBJ; // New prop offset + memcpy(&js->mem[head], &brk, sizeof(brk)); // Repoint head to the new prop + // printf("PROP: %u -> %u\n", b, brk); + return mkentity(js, (b & ~3U) | T_PROP, buf, sizeof(buf)); // Create new prop +} + +// Return T_OBJ/T_PROP/T_STR entity size based on the first word in memory +static inline jsoff_t esize(jsoff_t w) { + switch (w & 3U) { // clang-format off + case T_OBJ: return (jsoff_t) (sizeof(jsoff_t) + sizeof(jsoff_t)); + case T_PROP: return (jsoff_t) (sizeof(jsoff_t) + sizeof(jsoff_t) + sizeof(jsval_t)); + case T_STR: return (jsoff_t) (sizeof(jsoff_t) + align32(w >> 2U)); + default: return (jsoff_t) ~0U; + } // clang-format on +} + +static bool is_mem_entity(uint8_t t) { + return t == T_OBJ || t == T_PROP || t == T_STR || t == T_FUNC; +} + +#define GCMASK ~(((jsoff_t) ~0) >> 1) // Entity deletion marker +static void js_fixup_offsets(struct js *js, jsoff_t start, jsoff_t size) { + for (jsoff_t n, v, off = 0; off < js->brk; off += n) { // start from 0! + v = loadoff(js, off); + n = esize(v & ~GCMASK); + if (v & GCMASK) continue; // To be deleted, don't bother + if ((v & 3) != T_OBJ && (v & 3) != T_PROP) continue; + if (v > start) saveoff(js, off, v - size); + if ((v & 3) == T_OBJ) { + jsoff_t u = loadoff(js, (jsoff_t) (off + sizeof(jsoff_t))); + if (u > start) saveoff(js, (jsoff_t) (off + sizeof(jsoff_t)), u - size); + } + if ((v & 3) == T_PROP) { + jsoff_t koff = loadoff(js, (jsoff_t) (off + sizeof(off))); + if (koff > start) saveoff(js, (jsoff_t) (off + sizeof(off)), koff - size); + jsval_t val = loadval(js, (jsoff_t) (off + sizeof(off) + sizeof(off))); + if (is_mem_entity(vtype(val)) && vdata(val) > start) { + saveval(js, (jsoff_t) (off + sizeof(off) + sizeof(off)), + mkval(vtype(val), (unsigned long) (vdata(val) - size))); + } + } + } + // Fixup js->scope + jsoff_t off = (jsoff_t) vdata(js->scope); + if (off > start) js->scope = mkval(T_OBJ, off - size); + if (js->nogc >= start) js->nogc -= size; + // Fixup code that we're executing now, if required + if (js->code > (char *) js->mem && js->code - (char *) js->mem < js->size && + js->code - (char *) js->mem > start) { + js->code -= size; + // printf("GC-ing code under us!! %ld\n", js->code - (char *) js->mem); + } + // printf("FIXEDOFF %u %u\n", start, size); +} + +static void js_delete_marked_entities(struct js *js) { + for (jsoff_t n, v, off = 0; off < js->brk; off += n) { + v = loadoff(js, off); + n = esize(v & ~GCMASK); + if (v & GCMASK) { // This entity is marked for deletion, remove it + // printf("DEL: %4u %d %x\n", off, v & 3, n); + // assert(off + n <= js->brk); + js_fixup_offsets(js, off, n); + memmove(&js->mem[off], &js->mem[off + n], js->brk - off - n); + js->brk -= n; // Shrink brk boundary by the size of deleted entity + n = 0; // We shifted data, next iteration stay on this offset + } + } +} + +static void js_mark_all_entities_for_deletion(struct js *js) { + for (jsoff_t v, off = 0; off < js->brk; off += esize(v)) { + v = loadoff(js, off); + saveoff(js, off, v | GCMASK); + } +} + +static jsoff_t js_unmark_entity(struct js *js, jsoff_t off) { + jsoff_t v = loadoff(js, off); + if (v & GCMASK) { + saveoff(js, off, v & ~GCMASK); + // printf("UNMARK %5u %d\n", off, v & 3); + if ((v & 3) == T_OBJ) js_unmark_entity(js, v & ~(GCMASK | 3)); + if ((v & 3) == T_PROP) { + js_unmark_entity(js, v & ~(GCMASK | 3)); // Unmark next prop + js_unmark_entity(js, loadoff(js, (jsoff_t) (off + sizeof(off)))); // key + jsval_t val = loadval(js, (jsoff_t) (off + sizeof(off) + sizeof(off))); + if (is_mem_entity(vtype(val))) js_unmark_entity(js, (jsoff_t) vdata(val)); + } + } + return v & ~(GCMASK | 3U); +} + +static void js_unmark_used_entities(struct js *js) { + jsval_t scope = js->scope; + do { + js_unmark_entity(js, (jsoff_t) vdata(scope)); + scope = upper(js, scope); + } while (vdata(scope) != 0); // When global scope is GC-ed, stop + if (js->nogc) js_unmark_entity(js, js->nogc); + // printf("UNMARK: nogc %u\n", js->nogc); + // js_dump(js); +} + +void js_gc(struct js *js) { + // printf("================== GC %u\n", js->nogc); + setlwm(js); + if (js->nogc == (jsoff_t) ~0) return; // ~0 is a special case: GC Is disabled + js_mark_all_entities_for_deletion(js); + js_unmark_used_entities(js); + js_delete_marked_entities(js); +} + +// Skip whitespaces and comments +static jsoff_t skiptonext(const char *code, jsoff_t len, jsoff_t n) { + // printf("SKIP: [%.*s]\n", len - n, &code[n]); + while (n < len) { + if (is_space(code[n])) { + n++; + } else if (n + 1 < len && code[n] == '/' && code[n + 1] == '/') { + for (n += 2; n < len && code[n] != '\n';) n++; + } else if (n + 3 < len && code[n] == '/' && code[n + 1] == '*') { + for (n += 4; n < len && (code[n - 2] != '*' || code[n - 1] != '/');) n++; + } else { + break; + } + } + return n; +} + +static bool streq(const char *buf, size_t len, const char *p, size_t n) { + return n == len && memcmp(buf, p, len) == 0; +} + +static uint8_t parsekeyword(const char *buf, size_t len) { + switch (buf[0]) { // clang-format off + case 'b': if (streq("break", 5, buf, len)) return TOK_BREAK; break; + case 'c': if (streq("class", 5, buf, len)) return TOK_CLASS; if (streq("case", 4, buf, len)) return TOK_CASE; if (streq("catch", 5, buf, len)) return TOK_CATCH; if (streq("const", 5, buf, len)) return TOK_CONST; if (streq("continue", 8, buf, len)) return TOK_CONTINUE; break; + case 'd': if (streq("do", 2, buf, len)) return TOK_DO; if (streq("default", 7, buf, len)) return TOK_DEFAULT; break; // if (streq("delete", 6, buf, len)) return TOK_DELETE; break; + case 'e': if (streq("else", 4, buf, len)) return TOK_ELSE; break; + case 'f': if (streq("for", 3, buf, len)) return TOK_FOR; if (streq("function", 8, buf, len)) return TOK_FUNC; if (streq("finally", 7, buf, len)) return TOK_FINALLY; if (streq("false", 5, buf, len)) return TOK_FALSE; break; + case 'i': if (streq("if", 2, buf, len)) return TOK_IF; if (streq("in", 2, buf, len)) return TOK_IN; if (streq("instanceof", 10, buf, len)) return TOK_INSTANCEOF; break; + case 'l': if (streq("let", 3, buf, len)) return TOK_LET; break; + case 'n': if (streq("new", 3, buf, len)) return TOK_NEW; if (streq("null", 4, buf, len)) return TOK_NULL; break; + case 'r': if (streq("return", 6, buf, len)) return TOK_RETURN; break; + case 's': if (streq("switch", 6, buf, len)) return TOK_SWITCH; break; + case 't': if (streq("try", 3, buf, len)) return TOK_TRY; if (streq("this", 4, buf, len)) return TOK_THIS; if (streq("throw", 5, buf, len)) return TOK_THROW; if (streq("true", 4, buf, len)) return TOK_TRUE; if (streq("typeof", 6, buf, len)) return TOK_TYPEOF; break; + case 'u': if (streq("undefined", 9, buf, len)) return TOK_UNDEF; break; + case 'v': if (streq("var", 3, buf, len)) return TOK_VAR; if (streq("void", 4, buf, len)) return TOK_VOID; break; + case 'w': if (streq("while", 5, buf, len)) return TOK_WHILE; if (streq("with", 4, buf, len)) return TOK_WITH; break; + case 'y': if (streq("yield", 5, buf, len)) return TOK_YIELD; break; + } // clang-format on + return TOK_IDENTIFIER; +} + +static uint8_t parseident(const char *buf, jsoff_t len, jsoff_t *tlen) { + if (is_ident_begin(buf[0])) { + while (*tlen < len && is_ident_continue(buf[*tlen])) (*tlen)++; + return parsekeyword(buf, *tlen); + } + return TOK_ERR; +} + +static uint8_t next(struct js *js) { + if (js->consumed == 0) return js->tok; + js->consumed = 0; + js->tok = TOK_ERR; + js->toff = js->pos = skiptonext(js->code, js->clen, js->pos); + js->tlen = 0; + const char *buf = js->code + js->toff; + // clang-format off + if (js->toff >= js->clen) { js->tok = TOK_EOF; return js->tok; } +#define TOK(T, LEN) { js->tok = T; js->tlen = (LEN); break; } +#define LOOK(OFS, CH) js->toff + OFS < js->clen && buf[OFS] == CH + switch (buf[0]) { + case '?': TOK(TOK_Q, 1); + case ':': TOK(TOK_COLON, 1); + case '(': TOK(TOK_LPAREN, 1); + case ')': TOK(TOK_RPAREN, 1); + case '{': TOK(TOK_LBRACE, 1); + case '}': TOK(TOK_RBRACE, 1); + case ';': TOK(TOK_SEMICOLON, 1); + case ',': TOK(TOK_COMMA, 1); + case '!': if (LOOK(1, '=') && LOOK(2, '=')) TOK(TOK_NE, 3); TOK(TOK_NOT, 1); + case '.': TOK(TOK_DOT, 1); + case '~': TOK(TOK_TILDA, 1); + case '-': if (LOOK(1, '-')) TOK(TOK_POSTDEC, 2); if (LOOK(1, '=')) TOK(TOK_MINUS_ASSIGN, 2); TOK(TOK_MINUS, 1); + case '+': if (LOOK(1, '+')) TOK(TOK_POSTINC, 2); if (LOOK(1, '=')) TOK(TOK_PLUS_ASSIGN, 2); TOK(TOK_PLUS, 1); + case '*': if (LOOK(1, '*')) TOK(TOK_EXP, 2); if (LOOK(1, '=')) TOK(TOK_MUL_ASSIGN, 2); TOK(TOK_MUL, 1); + case '/': if (LOOK(1, '=')) TOK(TOK_DIV_ASSIGN, 2); TOK(TOK_DIV, 1); + case '%': if (LOOK(1, '=')) TOK(TOK_REM_ASSIGN, 2); TOK(TOK_REM, 1); + case '&': if (LOOK(1, '&')) TOK(TOK_LAND, 2); if (LOOK(1, '=')) TOK(TOK_AND_ASSIGN, 2); TOK(TOK_AND, 1); + case '|': if (LOOK(1, '|')) TOK(TOK_LOR, 2); if (LOOK(1, '=')) TOK(TOK_OR_ASSIGN, 2); TOK(TOK_OR, 1); + case '=': if (LOOK(1, '=') && LOOK(2, '=')) TOK(TOK_EQ, 3); TOK(TOK_ASSIGN, 1); + case '<': if (LOOK(1, '<') && LOOK(2, '=')) TOK(TOK_SHL_ASSIGN, 3); if (LOOK(1, '<')) TOK(TOK_SHL, 2); if (LOOK(1, '=')) TOK(TOK_LE, 2); TOK(TOK_LT, 1); + case '>': if (LOOK(1, '>') && LOOK(2, '=')) TOK(TOK_SHR_ASSIGN, 3); if (LOOK(1, '>')) TOK(TOK_SHR, 2); if (LOOK(1, '=')) TOK(TOK_GE, 2); TOK(TOK_GT, 1); + case '^': if (LOOK(1, '=')) TOK(TOK_XOR_ASSIGN, 2); TOK(TOK_XOR, 1); + case '"': case '\'': + js->tlen++; + while (js->toff + js->tlen < js->clen && buf[js->tlen] != buf[0]) { + uint8_t increment = 1; + if (buf[js->tlen] == '\\') { + if (js->toff + js->tlen + 2 > js->clen) break; + increment = 2; + if (buf[js->tlen + 1] == 'x') { + if (js->toff + js->tlen + 4 > js->clen) break; + increment = 4; + } + } + js->tlen += increment; + } + if (buf[0] == buf[js->tlen]) js->tok = TOK_STRING, js->tlen++; + break; + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { + char *end; + js->tval = tov(strtod(buf, &end)); // TODO(lsm): protect against OOB access + TOK(TOK_NUMBER, (jsoff_t) (end - buf)); + } + default: js->tok = parseident(buf, js->clen - js->toff, &js->tlen); break; + } // clang-format on + js->pos = js->toff + js->tlen; + // printf("NEXT: %d %d [%.*s]\n", js->tok, js->pos, (int) js->tlen, buf); + return js->tok; +} + +static inline uint8_t lookahead(struct js *js) { + uint8_t old = js->tok, tok = 0; + jsoff_t pos = js->pos; + js->consumed = 1; + tok = next(js); + js->pos = pos, js->tok = old; + return tok; +} + +static void mkscope(struct js *js) { + assert((js->flags & F_NOEXEC) == 0); + jsoff_t prev = (jsoff_t) vdata(js->scope); + js->scope = mkobj(js, prev); + // printf("ENTER SCOPE %u, prev %u\n", (jsoff_t) vdata(js->scope), prev); +} + +static void delscope(struct js *js) { + js->scope = upper(js, js->scope); + // printf("EXIT SCOPE %u\n", (jsoff_t) vdata(js->scope)); +} + +static jsval_t js_block(struct js *js, bool create_scope) { + jsval_t res = js_mkundef(); + if (create_scope) mkscope(js); // Enter new scope + js->consumed = 1; + // jsoff_t pos = js->pos; + while (next(js) != TOK_EOF && next(js) != TOK_RBRACE && !is_err(res)) { + uint8_t t = js->tok; + res = js_stmt(js); + if (!is_err(res) && t != TOK_LBRACE && t != TOK_IF && t != TOK_WHILE && + js->tok != TOK_SEMICOLON) { + res = js_mkerr(js, "; expected"); + break; + } + } + // printf("BLOCKEND %s\n", js_str(js, res)); + if (create_scope) delscope(js); // Exit scope + return res; +} + +// Seach for property in a single object +static jsoff_t lkp(struct js *js, jsval_t obj, const char *buf, size_t len) { + jsoff_t off = loadoff(js, (jsoff_t) vdata(obj)) & ~3U; // Load first prop off + // printf("LKP: %lu %u [%.*s]\n", vdata(obj), off, (int) len, buf); + while (off < js->brk && off != 0) { // Iterate over props + jsoff_t koff = loadoff(js, (jsoff_t) (off + sizeof(off))); + jsoff_t klen = (loadoff(js, koff) >> 2) - 1; + const char *p = (char *) &js->mem[koff + sizeof(koff)]; + // printf(" %u %u[%.*s]\n", off, (int) klen, (int) klen, p); + if (streq(buf, len, p, klen)) return off; // Found ! + off = loadoff(js, off) & ~3U; // Load next prop offset + } + return 0; // Not found +} + +// Lookup variable in the scope chain +static jsval_t lookup(struct js *js, const char *buf, size_t len) { + if (js->flags & F_NOEXEC) return 0; + for (jsval_t scope = js->scope;;) { + jsoff_t off = lkp(js, scope, buf, len); + if (off != 0) return mkval(T_PROP, off); + if (vdata(scope) == 0) break; + scope = + mkval(T_OBJ, loadoff(js, (jsoff_t) (vdata(scope) + sizeof(jsoff_t)))); + } + return js_mkerr(js, "'%.*s' not found", (int) len, buf); +} + +static jsval_t resolveprop(struct js *js, jsval_t v) { + if (vtype(v) != T_PROP) return v; + return resolveprop(js, + loadval(js, (jsoff_t) (vdata(v) + sizeof(jsoff_t) * 2))); +} + +static jsval_t assign(struct js *js, jsval_t lhs, jsval_t val) { + saveval(js, (jsoff_t) ((vdata(lhs) & ~3U) + sizeof(jsoff_t) * 2), val); + return lhs; +} + +static jsval_t do_assign_op(struct js *js, uint8_t op, jsval_t l, jsval_t r) { + uint8_t m[] = {TOK_PLUS, TOK_MINUS, TOK_MUL, TOK_DIV, TOK_REM, TOK_SHL, + TOK_SHR, TOK_ZSHR, TOK_AND, TOK_XOR, TOK_OR}; + jsval_t res = do_op(js, m[op - TOK_PLUS_ASSIGN], resolveprop(js, l), r); + return assign(js, l, res); +} + +static jsval_t do_string_op(struct js *js, uint8_t op, jsval_t l, jsval_t r) { + jsoff_t n1, off1 = vstr(js, l, &n1); + jsoff_t n2, off2 = vstr(js, r, &n2); + if (op == TOK_PLUS) { + jsval_t res = js_mkstr(js, NULL, n1 + n2); + // printf("STRPLUS %u %u %u %u [%.*s] [%.*s]\n", n1, off1, n2, off2, (int) + // n1, + // &js->mem[off1], (int) n2, &js->mem[off2]); + if (vtype(res) == T_STR) { + jsoff_t n, off = vstr(js, res, &n); + memmove(&js->mem[off], &js->mem[off1], n1); + memmove(&js->mem[off + n1], &js->mem[off2], n2); + } + return res; + } else if (op == TOK_EQ) { + bool eq = n1 == n2 && memcmp(&js->mem[off1], &js->mem[off2], n1) == 0; + return mkval(T_BOOL, eq ? 1 : 0); + } else if (op == TOK_NE) { + bool eq = n1 == n2 && memcmp(&js->mem[off1], &js->mem[off2], n1) == 0; + return mkval(T_BOOL, eq ? 0 : 1); + } else { + return js_mkerr(js, "bad str op"); + } +} + +static jsval_t do_dot_op(struct js *js, jsval_t l, jsval_t r) { + const char *ptr = (char *) &js->code[coderefoff(r)]; + if (vtype(r) != T_CODEREF) return js_mkerr(js, "ident expected"); + // Handle stringvalue.length + if (vtype(l) == T_STR && streq(ptr, codereflen(r), "length", 6)) { + return tov(offtolen(loadoff(js, (jsoff_t) vdata(l)))); + } + if (vtype(l) != T_OBJ) return js_mkerr(js, "lookup in non-obj"); + jsoff_t off = lkp(js, l, ptr, codereflen(r)); + return off == 0 ? js_mkundef() : mkval(T_PROP, off); +} + +static jsval_t js_call_params(struct js *js) { + jsoff_t pos = js->pos; + uint8_t flags = js->flags; + js->flags |= F_NOEXEC; + js->consumed = 1; + for (bool comma = false; next(js) != TOK_EOF; comma = true) { + if (!comma && next(js) == TOK_RPAREN) break; + js_expr(js); + if (next(js) == TOK_RPAREN) break; + EXPECT(TOK_COMMA, js->flags = flags); + } + EXPECT(TOK_RPAREN, js->flags = flags); + js->flags = flags; + return mkcoderef(pos, js->pos - pos - js->tlen); +} + +static void reverse(jsval_t *args, int nargs) { + for (int i = 0; i < nargs / 2; i++) { + jsval_t tmp = args[i]; + args[i] = args[nargs - i - 1], args[nargs - i - 1] = tmp; + } +} + +// Call native C function +static jsval_t call_c(struct js *js, + jsval_t (*fn)(struct js *, jsval_t *, int)) { + int argc = 0; + while (js->pos < js->clen) { + if (next(js) == TOK_RPAREN) break; + jsval_t arg = resolveprop(js, js_expr(js)); + if (js->brk + sizeof(arg) > js->size) return js_mkerr(js, "call oom"); + js->size -= (jsoff_t) sizeof(arg); + memcpy(&js->mem[js->size], &arg, sizeof(arg)); + argc++; + // printf(" arg %d -> %s\n", argc, js_str(js, arg)); + if (next(js) == TOK_COMMA) js->consumed = 1; + } + reverse((jsval_t *) &js->mem[js->size], argc); + jsval_t res = fn(js, (jsval_t *) &js->mem[js->size], argc); + setlwm(js); + js->size += (jsoff_t) sizeof(jsval_t) * (jsoff_t) argc; // Restore stack + return res; +} + +// Call JS function. 'fn' looks like this: "(a,b) { return a + b; }" +static jsval_t call_js(struct js *js, const char *fn, jsoff_t fnlen) { + jsoff_t fnpos = 1; + // printf("JSCALL [%.*s] -> %.*s\n", (int) js->clen, js->code, (int) fnlen, + // fn); + // printf("JSCALL, nogc %u [%.*s]\n", js->nogc, (int) fnlen, fn); + mkscope(js); // Create function call scope + // Loop over arguments list "(a, b)" and set scope variables + while (fnpos < fnlen) { + fnpos = skiptonext(fn, fnlen, fnpos); // Skip to the identifier + if (fnpos < fnlen && fn[fnpos] == ')') break; // Closing paren? break! + jsoff_t identlen = 0; // Identifier length + uint8_t tok = parseident(&fn[fnpos], fnlen - fnpos, &identlen); + if (tok != TOK_IDENTIFIER) break; + // Here we have argument name. Calculate arg value + // printf(" [%.*s] -> %u [%.*s] -> ", (int) identlen, &fn[fnpos], js->pos, + // (int) js->clen, js->code); + js->pos = skiptonext(js->code, js->clen, js->pos); + js->consumed = 1; + jsval_t v = js->code[js->pos] == ')' ? js_mkundef() : js_expr(js); + // Set argument in the function scope + setprop(js, js->scope, js_mkstr(js, &fn[fnpos], identlen), v); + js->pos = skiptonext(js->code, js->clen, js->pos); + if (js->pos < js->clen && js->code[js->pos] == ',') js->pos++; + fnpos = skiptonext(fn, fnlen, fnpos + identlen); // Skip past identifier + if (fnpos < fnlen && fn[fnpos] == ',') fnpos++; // And skip comma + } + if (fnpos < fnlen && fn[fnpos] == ')') fnpos++; // Skip to the function body + fnpos = skiptonext(fn, fnlen, fnpos); // Up to the opening brace + if (fnpos < fnlen && fn[fnpos] == '{') fnpos++; // And skip the brace + size_t n = fnlen - fnpos - 1U; // Function code with stripped braces + // printf("flags: %d, body: %zu [%.*s]\n", js->flags, n, (int) n, &fn[fnpos]); + js->flags = F_CALL; // Mark we're in the function call + jsval_t res = js_eval(js, &fn[fnpos], n); // Call function, no GC + if (!is_err(res) && !(js->flags & F_RETURN)) res = js_mkundef(); // No return + delscope(js); // Delete call scope + // printf(" -> %d [%s], tok %d\n", js->flags, js_str(js, res), js->tok); + return res; +} + +static jsval_t do_call_op(struct js *js, jsval_t func, jsval_t args) { + if (vtype(args) != T_CODEREF) return js_mkerr(js, "bad call"); + if (vtype(func) != T_FUNC && vtype(func) != T_CFUNC) + return js_mkerr(js, "calling non-function"); + const char *code = js->code; // Save current parser state + jsoff_t clen = js->clen, pos = js->pos; // code, position and code length + js->code = &js->code[coderefoff(args)]; // Point parser to args + js->clen = codereflen(args); // Set args length + js->pos = skiptonext(js->code, js->clen, 0); // Skip to 1st arg + uint8_t tok = js->tok, flags = js->flags; // Save flags + jsoff_t nogc = js->nogc; + jsval_t res = js_mkundef(); + if (vtype(func) == T_FUNC) { + jsoff_t fnlen, fnoff = vstr(js, func, &fnlen); + js->nogc = (jsoff_t) (fnoff - sizeof(jsoff_t)); + res = call_js(js, (const char *) (&js->mem[fnoff]), fnlen); + } else { + res = call_c(js, (jsval_t(*)(struct js *, jsval_t *, int)) vdata(func)); + } + js->code = code, js->clen = clen, js->pos = pos; // Restore parser + js->flags = flags, js->tok = tok, js->nogc = nogc; + js->consumed = 1; + return res; +} + +// clang-format off +static jsval_t do_op(struct js *js, uint8_t op, jsval_t lhs, jsval_t rhs) { + if (js->flags & F_NOEXEC) return 0; + jsval_t l = resolveprop(js, lhs), r = resolveprop(js, rhs); + // printf("OP %d %d %d\n", op, vtype(lhs), vtype(r)); + setlwm(js); + if (is_err(l)) return l; + if (is_err(r)) return r; + if (is_assign(op) && vtype(lhs) != T_PROP) return js_mkerr(js, "bad lhs"); + switch (op) { + case TOK_TYPEOF: return js_mkstr(js, typestr(vtype(r)), strlen(typestr(vtype(r)))); + case TOK_CALL: return do_call_op(js, l, r); + case TOK_ASSIGN: return assign(js, lhs, r); + case TOK_POSTINC: { do_assign_op(js, TOK_PLUS_ASSIGN, lhs, tov(1)); return l; } + case TOK_POSTDEC: { do_assign_op(js, TOK_MINUS_ASSIGN, lhs, tov(1)); return l; } + case TOK_NOT: if (vtype(r) == T_BOOL) return mkval(T_BOOL, !vdata(r)); break; + } + if (is_assign(op)) return do_assign_op(js, op, lhs, r); + if (vtype(l) == T_STR && vtype(r) == T_STR) return do_string_op(js, op, l, r); + if (is_unary(op) && vtype(r) != T_NUM) return js_mkerr(js, "type mismatch"); + if (!is_unary(op) && op != TOK_DOT && (vtype(l) != T_NUM || vtype(r) != T_NUM)) return js_mkerr(js, "type mismatch"); + double a = tod(l), b = tod(r); + switch (op) { + //case TOK_EXP: return tov(pow(a, b)); + case TOK_DIV: return tod(r) == 0 ? js_mkerr(js, "div by zero") : tov(a / b); + case TOK_REM: return tov(a - b * ((double) (long) (a / b))); + case TOK_MUL: return tov(a * b); + case TOK_PLUS: return tov(a + b); + case TOK_MINUS: return tov(a - b); + case TOK_XOR: return tov((double)((long) a ^ (long) b)); + case TOK_AND: return tov((double)((long) a & (long) b)); + case TOK_OR: return tov((double)((long) a | (long) b)); + case TOK_UMINUS: return tov(-b); + case TOK_UPLUS: return r; + case TOK_TILDA: return tov((double)(~(long) b)); + case TOK_NOT: return mkval(T_BOOL, b == 0); + case TOK_SHL: return tov((double)((long) a << (long) b)); + case TOK_SHR: return tov((double)((long) a >> (long) b)); + case TOK_DOT: return do_dot_op(js, l, r); + case TOK_EQ: return mkval(T_BOOL, (long) a == (long) b); + case TOK_NE: return mkval(T_BOOL, (long) a != (long) b); + case TOK_LT: return mkval(T_BOOL, a < b); + case TOK_LE: return mkval(T_BOOL, a <= b); + case TOK_GT: return mkval(T_BOOL, a > b); + case TOK_GE: return mkval(T_BOOL, a >= b); + default: return js_mkerr(js, "unknown op %d", (int) op); // LCOV_EXCL_LINE + } +} // clang-format on + +static jsval_t js_str_literal(struct js *js) { + uint8_t *in = (uint8_t *) &js->code[js->toff]; + uint8_t *out = &js->mem[js->brk + sizeof(jsoff_t)]; + size_t n1 = 0, n2 = 0; + // printf("STR %u %lu %lu\n", js->brk, js->tlen, js->clen); + if (js->brk + sizeof(jsoff_t) + js->tlen > js->size) + return js_mkerr(js, "oom"); + while (n2++ + 2 < js->tlen) { + if (in[n2] == '\\') { + if (in[n2 + 1] == in[0]) { + out[n1++] = in[0]; + } else if (in[n2 + 1] == 'n') { + out[n1++] = '\n'; + } else if (in[n2 + 1] == 't') { + out[n1++] = '\t'; + } else if (in[n2 + 1] == 'r') { + out[n1++] = '\r'; + } else if (in[n2 + 1] == 'x' && is_xdigit(in[n2 + 2]) && + is_xdigit(in[n2 + 3])) { + out[n1++] = (uint8_t) ((unhex(in[n2 + 2]) << 4U) | unhex(in[n2 + 3])); + n2 += 2; + } else { + return js_mkerr(js, "bad str literal"); + } + n2++; + } else { + out[n1++] = ((uint8_t *) js->code)[js->toff + n2]; + } + } + return js_mkstr(js, NULL, n1); +} + +static jsval_t js_obj_literal(struct js *js) { + uint8_t exe = !(js->flags & F_NOEXEC); + // printf("OLIT1\n"); + jsval_t obj = exe ? mkobj(js, 0) : js_mkundef(); + if (is_err(obj)) return obj; + js->consumed = 1; + while (next(js) != TOK_RBRACE) { + jsval_t key = 0; + if (js->tok == TOK_IDENTIFIER) { + if (exe) key = js_mkstr(js, js->code + js->toff, js->tlen); + } else if (js->tok == TOK_STRING) { + if (exe) key = js_str_literal(js); + } else { + return js_mkerr(js, "parse error"); + } + js->consumed = 1; + EXPECT(TOK_COLON, ); + jsval_t val = js_expr(js); + if (exe) { + // printf("XXXX [%s] scope: %lu\n", js_str(js, val), vdata(js->scope)); + if (is_err(val)) return val; + if (is_err(key)) return key; + jsval_t res = setprop(js, obj, key, resolveprop(js, val)); + if (is_err(res)) return res; + } + if (next(js) == TOK_RBRACE) break; + EXPECT(TOK_COMMA, ); + } + EXPECT(TOK_RBRACE, ); + return obj; +} + +static jsval_t js_func_literal(struct js *js) { + uint8_t flags = js->flags; // Save current flags + js->consumed = 1; + EXPECT(TOK_LPAREN, js->flags = flags); + jsoff_t pos = js->pos - 1; + for (bool comma = false; next(js) != TOK_EOF; comma = true) { + if (!comma && next(js) == TOK_RPAREN) break; + EXPECT(TOK_IDENTIFIER, js->flags = flags); + if (next(js) == TOK_RPAREN) break; + EXPECT(TOK_COMMA, js->flags = flags); + } + EXPECT(TOK_RPAREN, js->flags = flags); + EXPECT(TOK_LBRACE, js->flags = flags); + js->consumed = 0; + js->flags |= F_NOEXEC; // Set no-execution flag to parse the + jsval_t res = js_block(js, false); // Skip function body - no exec + if (is_err(res)) { // But fail short on parse error + js->flags = flags; + return res; + } + js->flags = flags; // Restore flags + jsval_t str = js_mkstr(js, &js->code[pos], js->pos - pos); + js->consumed = 1; + // printf("FUNC: %u [%.*s]\n", pos, js->pos - pos, &js->code[pos]); + return mkval(T_FUNC, (unsigned long) vdata(str)); +} + +#define RTL_BINOP(_f1, _f2, _cond) \ + jsval_t res = _f1(js); \ + while (!is_err(res) && (_cond)) { \ + uint8_t op = js->tok; \ + js->consumed = 1; \ + jsval_t rhs = _f2(js); \ + if (is_err(rhs)) return rhs; \ + res = do_op(js, op, res, rhs); \ + } \ + return res; + +#define LTR_BINOP(_f, _cond) \ + jsval_t res = _f(js); \ + while (!is_err(res) && (_cond)) { \ + uint8_t op = js->tok; \ + js->consumed = 1; \ + jsval_t rhs = _f(js); \ + if (is_err(rhs)) return rhs; \ + res = do_op(js, op, res, rhs); \ + } \ + return res; + +static jsval_t js_literal(struct js *js) { + next(js); + setlwm(js); + // printf("css : %u\n", js->css); + if (js->maxcss > 0 && js->css > js->maxcss) return js_mkerr(js, "C stack"); + js->consumed = 1; + switch (js->tok) { // clang-format off + case TOK_ERR: return js_mkerr(js, "parse error"); + case TOK_NUMBER: return js->tval; + case TOK_STRING: return js_str_literal(js); + case TOK_LBRACE: return js_obj_literal(js); + case TOK_FUNC: return js_func_literal(js); + case TOK_NULL: return js_mknull(); + case TOK_UNDEF: return js_mkundef(); + case TOK_TRUE: return js_mktrue(); + case TOK_FALSE: return js_mkfalse(); + case TOK_IDENTIFIER: return mkcoderef((jsoff_t) js->toff, (jsoff_t) js->tlen); + default: return js_mkerr(js, "bad expr"); + } // clang-format on +} + +static jsval_t js_group(struct js *js) { + if (next(js) == TOK_LPAREN) { + js->consumed = 1; + jsval_t v = js_expr(js); + if (is_err(v)) return v; + if (next(js) != TOK_RPAREN) return js_mkerr(js, ") expected"); + js->consumed = 1; + return v; + } else { + return js_literal(js); + } +} + +static jsval_t js_call_dot(struct js *js) { + jsval_t res = js_group(js); + if (is_err(res)) return res; + if (vtype(res) == T_CODEREF) { + res = lookup(js, &js->code[coderefoff(res)], codereflen(res)); + } + while (next(js) == TOK_LPAREN || next(js) == TOK_DOT) { + if (js->tok == TOK_DOT) { + js->consumed = 1; + res = do_op(js, TOK_DOT, res, js_group(js)); + } else { + jsval_t params = js_call_params(js); + if (is_err(params)) return params; + res = do_op(js, TOK_CALL, res, params); + } + } + return res; +} + +static jsval_t js_postfix(struct js *js) { + jsval_t res = js_call_dot(js); + if (is_err(res)) return res; + next(js); + if (js->tok == TOK_POSTINC || js->tok == TOK_POSTDEC) { + js->consumed = 1; + res = do_op(js, js->tok, res, 0); + } + return res; +} + +static jsval_t js_unary(struct js *js) { + if (next(js) == TOK_NOT || js->tok == TOK_TILDA || js->tok == TOK_TYPEOF || + js->tok == TOK_MINUS || js->tok == TOK_PLUS) { + uint8_t t = js->tok; + if (t == TOK_MINUS) t = TOK_UMINUS; + if (t == TOK_PLUS) t = TOK_UPLUS; + js->consumed = 1; + return do_op(js, t, js_mkundef(), js_unary(js)); + } else { + return js_postfix(js); + } +} + +static jsval_t js_mul_div_rem(struct js *js) { + LTR_BINOP(js_unary, + (next(js) == TOK_MUL || js->tok == TOK_DIV || js->tok == TOK_REM)); +} + +static jsval_t js_plus_minus(struct js *js) { + LTR_BINOP(js_mul_div_rem, (next(js) == TOK_PLUS || js->tok == TOK_MINUS)); +} + +static jsval_t js_shifts(struct js *js) { + LTR_BINOP(js_plus_minus, (next(js) == TOK_SHR || next(js) == TOK_SHL || + next(js) == TOK_ZSHR)); +} + +static jsval_t js_comparison(struct js *js) { + LTR_BINOP(js_shifts, (next(js) == TOK_LT || next(js) == TOK_LE || + next(js) == TOK_GT || next(js) == TOK_GE)); +} + +static jsval_t js_equality(struct js *js) { + LTR_BINOP(js_comparison, (next(js) == TOK_EQ || next(js) == TOK_NE)); +} + +static jsval_t js_bitwise_and(struct js *js) { + LTR_BINOP(js_equality, (next(js) == TOK_AND)); +} + +static jsval_t js_bitwise_xor(struct js *js) { + LTR_BINOP(js_bitwise_and, (next(js) == TOK_XOR)); +} + +static jsval_t js_bitwise_or(struct js *js) { + LTR_BINOP(js_bitwise_xor, (next(js) == TOK_OR)); +} + +static jsval_t js_logical_and(struct js *js) { + jsval_t res = js_bitwise_or(js); + if (is_err(res)) return res; + uint8_t flags = js->flags; + while (next(js) == TOK_LAND) { + js->consumed = 1; + res = resolveprop(js, res); + if (!js_truthy(js, res)) js->flags |= F_NOEXEC; // false && ... shortcut + if (js->flags & F_NOEXEC) { + js_logical_and(js); + } else { + res = js_logical_and(js); + } + } + js->flags = flags; + return res; +} + +static jsval_t js_logical_or(struct js *js) { + jsval_t res = js_logical_and(js); + if (is_err(res)) return res; + uint8_t flags = js->flags; + while (next(js) == TOK_LOR) { + js->consumed = 1; + res = resolveprop(js, res); + if (js_truthy(js, res)) js->flags |= F_NOEXEC; // true || ... shortcut + if (js->flags & F_NOEXEC) { + js_logical_or(js); + } else { + res = js_logical_or(js); + } + } + js->flags = flags; + return res; +} + +static jsval_t js_ternary(struct js *js) { + jsval_t res = js_logical_or(js); + if (next(js) == TOK_Q) { + uint8_t flags = js->flags; + js->consumed = 1; + if (js_truthy(js, resolveprop(js, res))) { + res = js_ternary(js); + js->flags |= F_NOEXEC; + EXPECT(TOK_COLON, js->flags = flags); + js_ternary(js); + js->flags = flags; + } else { + js->flags |= F_NOEXEC; + js_ternary(js); + EXPECT(TOK_COLON, js->flags = flags); + js->flags = flags; + res = js_ternary(js); + } + } + return res; +} + +static jsval_t js_assignment(struct js *js) { + RTL_BINOP(js_ternary, js_assignment, + (next(js) == TOK_ASSIGN || js->tok == TOK_PLUS_ASSIGN || + js->tok == TOK_MINUS_ASSIGN || js->tok == TOK_MUL_ASSIGN || + js->tok == TOK_DIV_ASSIGN || js->tok == TOK_REM_ASSIGN || + js->tok == TOK_SHL_ASSIGN || js->tok == TOK_SHR_ASSIGN || + js->tok == TOK_ZSHR_ASSIGN || js->tok == TOK_AND_ASSIGN || + js->tok == TOK_XOR_ASSIGN || js->tok == TOK_OR_ASSIGN)); +} + +static jsval_t js_expr(struct js *js) { + return js_assignment(js); +} + +static jsval_t js_let(struct js *js) { + uint8_t exe = !(js->flags & F_NOEXEC); + js->consumed = 1; + for (;;) { + EXPECT(TOK_IDENTIFIER, ); + js->consumed = 0; + jsoff_t noff = js->toff, nlen = js->tlen; + char *name = (char *) &js->code[noff]; + jsval_t v = js_mkundef(); + js->consumed = 1; + if (next(js) == TOK_ASSIGN) { + js->consumed = 1; + v = js_expr(js); + if (is_err(v)) return v; // Propagate error if any + } + if (exe) { + if (lkp(js, js->scope, name, nlen) > 0) + return js_mkerr(js, "'%.*s' already declared", (int) nlen, name); + jsval_t x = + setprop(js, js->scope, js_mkstr(js, name, nlen), resolveprop(js, v)); + if (is_err(x)) return x; + } + if (next(js) == TOK_SEMICOLON || next(js) == TOK_EOF) break; // Stop + EXPECT(TOK_COMMA, ); + } + return js_mkundef(); +} + +static jsval_t js_block_or_stmt(struct js *js) { + if (next(js) == TOK_LBRACE) return js_block(js, !(js->flags & F_NOEXEC)); + jsval_t res = resolveprop(js, js_stmt(js)); + js->consumed = 0; // + return res; +} + +static jsval_t js_if(struct js *js) { + js->consumed = 1; + EXPECT(TOK_LPAREN, ); + jsval_t res = js_mkundef(), cond = resolveprop(js, js_expr(js)); + EXPECT(TOK_RPAREN, ); + bool cond_true = js_truthy(js, cond), exe = !(js->flags & F_NOEXEC); + // printf("IF COND: %s, true? %d\n", js_str(js, cond), cond_true); + if (!cond_true) js->flags |= F_NOEXEC; + jsval_t blk = js_block_or_stmt(js); + if (cond_true) res = blk; + if (exe && !cond_true) js->flags &= (uint8_t) ~F_NOEXEC; + if (lookahead(js) == TOK_ELSE) { + js->consumed = 1; + next(js); + js->consumed = 1; + if (cond_true) js->flags |= F_NOEXEC; + blk = js_block_or_stmt(js); + if (!cond_true) res = blk; + if (cond_true && exe) js->flags &= (uint8_t) ~F_NOEXEC; + } + return res; +} + +static inline bool expect(struct js *js, uint8_t tok, jsval_t *res) { + if (next(js) != tok) { + *res = js_mkerr(js, "parse error"); + return false; + } else { + js->consumed = 1; + return true; + } +} + +static inline bool is_err2(jsval_t *v, jsval_t *res) { + bool r = is_err(*v); + if (r) *res = *v; + return r; +} + +static jsval_t js_for(struct js *js) { + uint8_t flags = js->flags, exe = !(flags & F_NOEXEC); + jsval_t v, res = js_mkundef(); + jsoff_t pos1 = 0, pos2 = 0, pos3 = 0, pos4 = 0; + if (exe) mkscope(js); // Enter new scope + if (!expect(js, TOK_FOR, &res)) goto done; + if (!expect(js, TOK_LPAREN, &res)) goto done; + + if (next(js) == TOK_SEMICOLON) { // initialisation + } else if (next(js) == TOK_LET) { + v = js_let(js); + if (is_err2(&v, &res)) goto done; + } else { + v = js_expr(js); + if (is_err2(&v, &res)) goto done; + } + if (!expect(js, TOK_SEMICOLON, &res)) goto done; + js->flags |= F_NOEXEC; + pos1 = js->pos; // condition + if (next(js) != TOK_SEMICOLON) { + v = js_expr(js); + if (is_err2(&v, &res)) goto done; + } + if (!expect(js, TOK_SEMICOLON, &res)) goto done; + pos2 = js->pos; // final expr + if (next(js) != TOK_RPAREN) { + v = js_expr(js); + if (is_err2(&v, &res)) goto done; + } + if (!expect(js, TOK_RPAREN, &res)) goto done; + pos3 = js->pos; // body + v = js_block_or_stmt(js); + if (is_err2(&v, &res)) goto done; + pos4 = js->pos; // end of body + while (!(flags & F_NOEXEC)) { + js->flags = flags, js->pos = pos1, js->consumed = 1; + if (next(js) != TOK_SEMICOLON) { // Is condition specified? + v = resolveprop(js, js_expr(js)); // Yes. check condition + if (is_err2(&v, &res)) goto done; // Fail short on error + if (!js_truthy(js, v)) break; // Exit the loop if condition is false + } + js->pos = pos3, js->consumed = 1, js->flags |= F_LOOP; // Execute the + v = js_block_or_stmt(js); // loop body + if (is_err2(&v, &res)) goto done; // Fail on error + if (js->flags & F_BREAK) break; // break was executed - exit the loop! + js->flags = flags, js->pos = pos2, js->consumed = 1; // Jump to final expr + if (next(js) != TOK_RPAREN) { // Is it specified? + v = js_expr(js); // Yes. Execute it + if (is_err2(&v, &res)) goto done; // On error, fail short + } + } + js->pos = pos4, js->tok = TOK_SEMICOLON, js->consumed = 0; +done: + if (exe) delscope(js); // Exit scope + js->flags = flags; // Restore flags + return res; +} + +static jsval_t js_break(struct js *js) { + if (js->flags & F_NOEXEC) { + } else { + if (!(js->flags & F_LOOP)) return js_mkerr(js, "not in loop"); + js->flags |= F_BREAK | F_NOEXEC; + } + js->consumed = 1; + return js_mkundef(); +} + +static jsval_t js_continue(struct js *js) { + if (js->flags & F_NOEXEC) { + } else { + if (!(js->flags & F_LOOP)) return js_mkerr(js, "not in loop"); + js->flags |= F_NOEXEC; + } + js->consumed = 1; + return js_mkundef(); +} + +static jsval_t js_return(struct js *js) { + uint8_t exe = !(js->flags & F_NOEXEC); + js->consumed = 1; + if (exe && !(js->flags & F_CALL)) return js_mkerr(js, "not in func"); + if (next(js) == TOK_SEMICOLON) return js_mkundef(); + jsval_t res = resolveprop(js, js_expr(js)); + if (exe) { + js->pos = js->clen; // Shift to the end - exit the code snippet + js->flags |= F_RETURN; // Tell caller we've executed + } + return resolveprop(js, res); +} + +static jsval_t js_stmt(struct js *js) { + jsval_t res; + // jsoff_t pos = js->pos - js->tlen; + if (js->brk > js->gct) js_gc(js); + switch (next(js)) { // clang-format off + case TOK_CASE: case TOK_CATCH: case TOK_CLASS: case TOK_CONST: + case TOK_DEFAULT: case TOK_DELETE: case TOK_DO: case TOK_FINALLY: + case TOK_IN: case TOK_INSTANCEOF: case TOK_NEW: case TOK_SWITCH: + case TOK_THIS: case TOK_THROW: case TOK_TRY: case TOK_VAR: case TOK_VOID: + case TOK_WITH: case TOK_WHILE: case TOK_YIELD: + res = js_mkerr(js, "'%.*s' not implemented", (int) js->tlen, js->code + js->toff); + break; + case TOK_CONTINUE: res = js_continue(js); break; + case TOK_BREAK: res = js_break(js); break; + case TOK_LET: res = js_let(js); break; + case TOK_IF: res = js_if(js); break; + case TOK_LBRACE: res = js_block(js, !(js->flags & F_NOEXEC)); break; + case TOK_FOR: res = js_for(js); break; // 25222 -> 27660 + case TOK_RETURN: res = js_return(js); break; + default: res = resolveprop(js, js_expr(js)); break; + } + //printf("STMT [%.*s] -> %s, tok %d, flags %d\n", (int) (js->pos - pos), &js->code[pos], js_str(js, res), next(js), js->flags); + if (next(js) != TOK_SEMICOLON && next(js) != TOK_EOF && next(js) != TOK_RBRACE) return js_mkerr(js, "; expected"); + js->consumed = 1; + // clang-format on + return res; +} + +struct js *js_create(void *buf, size_t len) { + struct js *js = NULL; + if (len < sizeof(*js) + esize(T_OBJ)) return js; + memset(buf, 0, len); // Important! + js = (struct js *) buf; // struct js lives at the beginning + js->mem = (uint8_t *) (js + 1); // Then goes memory for JS data + js->size = (jsoff_t) (len - sizeof(*js)); // JS memory size + js->scope = mkobj(js, 0); // Create global scope + js->size = js->size / 8U * 8U; // Align js->size by 8 byte + js->lwm = js->size; // Initial LWM: 100% free + js->gct = js->size / 2; + return js; +} + +// clang-format off +void js_setgct(struct js *js, size_t gct) { js->gct = (jsoff_t) gct; } +void js_setmaxcss(struct js *js, size_t max) { js->maxcss = (jsoff_t) max; } +jsval_t js_mktrue(void) { return mkval(T_BOOL, 1); } +jsval_t js_mkfalse(void) { return mkval(T_BOOL, 0); } +jsval_t js_mkundef(void) { return mkval(T_UNDEF, 0); } +jsval_t js_mknull(void) { return mkval(T_NULL, 0); } +jsval_t js_mknum(double value) { return tov(value); } +jsval_t js_mkobj(struct js *js) { return mkobj(js, 0); } +jsval_t js_mkfun(jsval_t (*fn)(struct js *, jsval_t *, int)) { return mkval(T_CFUNC, (size_t) (void *) fn); } +double js_getnum(jsval_t value) { return tod(value); } +int js_getbool(jsval_t value) { return vdata(value) & 1 ? 1 : 0; } + +jsval_t js_glob(struct js *js) { (void) js; return mkval(T_OBJ, 0); } + +void js_set(struct js *js, jsval_t obj, const char *key, jsval_t val) { + if (vtype(obj) == T_OBJ) setprop(js, obj, js_mkstr(js, key, strlen(key)), val); +} + +char *js_getstr(struct js *js, jsval_t value, size_t *len) { + if (vtype(value) != T_STR) return NULL; + jsoff_t n, off = vstr(js, value, &n); + if (len != NULL) *len = n; + return (char *) &js->mem[off]; +} + +int js_type(jsval_t val) { + switch (vtype(val)) { + case T_UNDEF: return JS_UNDEF; + case T_NULL: return JS_NULL; + case T_BOOL: return vdata(val) == 0 ? JS_FALSE: JS_TRUE; + case T_STR: return JS_STR; + case T_NUM: return JS_NUM; + case T_ERR: return JS_ERR; + default: return JS_PRIV; + } +} +void js_stats(struct js *js, size_t *total, size_t *lwm, size_t *css) { + if (total) *total = js->size; + if (lwm) *lwm = js->lwm; + if (css) *css = js->css; +} +// clang-format on + +bool js_chkargs(jsval_t *args, int nargs, const char *spec) { + int i = 0, ok = 1; + for (; ok && i < nargs && spec[i]; i++) { + uint8_t t = vtype(args[i]), c = (uint8_t) spec[i]; + ok = (c == 'b' && t == T_BOOL) || (c == 'd' && t == T_NUM) || + (c == 's' && t == T_STR) || (c == 'j'); + } + if (spec[i] != '\0' || i != nargs) ok = 0; + return ok; +} +jsval_t js_run(struct js *js, const char *buf) { + return js_eval(js, buf, ~0U); +} +jsval_t js_eval(struct js *js, const char *buf, size_t len) { + // printf("EVAL: [%.*s]\n", (int) len, buf); + jsval_t res = js_mkundef(); + if (len == (size_t) ~0U || len == 0) len = strlen(buf); + js->consumed = 1; + js->tok = TOK_ERR; + js->code = buf; + js->clen = (jsoff_t) len; + js->pos = 0; + js->cstk = &res; + while (next(js) != TOK_EOF && !is_err(res)) { + res = js_stmt(js); + } + return res; +} + +//#ifdef JS_DUMP +void js_dump(struct js *js) { + jsoff_t off = 0, v; + printf("JS size %u, brk %u, lwm %u, css %u, nogc %u\n", js->size, js->brk, + js->lwm, (unsigned) js->css, js->nogc); + while (off < js->brk) { + memcpy(&v, &js->mem[off], sizeof(v)); + printf(" %5u: ", off); + if ((v & 3U) == T_OBJ) { + printf("OBJ %u %u\n", v & ~3U, + loadoff(js, (jsoff_t) (off + sizeof(off)))); + } else if ((v & 3U) == T_PROP) { + jsoff_t koff = loadoff(js, (jsoff_t) (off + sizeof(v))); + jsval_t val = loadval(js, (jsoff_t) (off + sizeof(v) + sizeof(v))); + printf("PROP next %u, koff %u vtype %d vdata %lu\n", v & ~3U, koff, + vtype(val), (unsigned long) vdata(val)); + } else if ((v & 3) == T_STR) { + jsoff_t len = offtolen(v); + printf("STR %u [%.*s]\n", len, (int) len, js->mem + off + sizeof(v)); + } else { + printf("???\n"); + break; + } + off += esize(v); + } +} +//#endif diff --git a/TencentOS_Tiny/tos_js/tos_js.h b/TencentOS_Tiny/tos_js/tos_js.h new file mode 100644 index 0000000..a8106b2 --- /dev/null +++ b/TencentOS_Tiny/tos_js/tos_js.h @@ -0,0 +1,64 @@ +// Copyright (c) 2013-2022 Cesanta Software Limited +// All rights reserved +// +// This software is dual-licensed: you can redistribute it and/or modify +// it under the terms of the GNU Affero General Public License version 3 as +// published by the Free Software Foundation. For the terms of this +// license, see http://www.fsf.org/licensing/licenses/agpl-3.0.html +// +// You are free to use this software under the terms of the GNU General +// Public License, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +// See the GNU General Public License for more details. +// +// Alternatively, you can license this software under a commercial +// license, please contact us at https://cesanta.com/contact.html + +#define JS_VERSION "3.0.0" +#pragma once + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct js; // JS engine (opaque) +typedef uint64_t jsval_t; // JS value +//typedef unsigned long long jsval_t; // JS value + +struct js *js_create(void *buf, size_t len); // Create JS instance +jsval_t js_run(struct js *, const char *); // Execute JS code +jsval_t js_eval(struct js *, const char *, size_t); // Execute JS code +jsval_t js_glob(struct js *); // Return global object +const char *js_str(struct js *, jsval_t val); // Stringify JS value +bool js_chkargs(jsval_t *, int, const char *); // Check args validity +void js_setmaxcss(struct js *, size_t); // Set max C stack size +void js_setgct(struct js *, size_t); // Set GC trigger threshold +void js_stats(struct js *, size_t *total, size_t *min, size_t *cstacksize); +void js_dump(struct js *); // Print debug info. Requires -DJS_DUMP + +// Create JS values from C values +jsval_t js_mkundef(void); // Create undefined +jsval_t js_mknull(void); // Create null, null, true, false +jsval_t js_mktrue(void); // Create true +jsval_t js_mkfalse(void); // Create false +jsval_t js_mkstr(struct js *, const void *, size_t); // Create string +jsval_t js_mknum(double); // Create number +jsval_t js_mkerr(struct js *js, const char *fmt, ...); // Create error +jsval_t js_mkfun(jsval_t (*fn)(struct js *, jsval_t *, int)); // Create func +jsval_t js_mkobj(struct js *); // Create object +void js_set(struct js *, jsval_t, const char *, jsval_t); // Set obj attr + +// Extract C values from JS values +enum { JS_UNDEF, JS_NULL, JS_TRUE, JS_FALSE, JS_STR, JS_NUM, JS_ERR, JS_PRIV }; +int js_type(jsval_t val); // Return JS value type +double js_getnum(jsval_t val); // Get number +int js_getbool(jsval_t val); // Get boolean, 0 or 1 +char *js_getstr(struct js *js, jsval_t val, size_t *len); // Get string + +#ifdef __cplusplus +} +#endif diff --git a/User/ch32v30x_conf.h b/User/ch32v30x_conf.h new file mode 100644 index 0000000..399feaf --- /dev/null +++ b/User/ch32v30x_conf.h @@ -0,0 +1,43 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_conf.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Library configuration file. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_CONF_H +#define __CH32V30x_CONF_H + +#include "ch32v30x_adc.h" +#include "ch32v30x_bkp.h" +#include "ch32v30x_can.h" +#include "ch32v30x_crc.h" +#include "ch32v30x_dac.h" +#include "ch32v30x_dbgmcu.h" +#include "ch32v30x_dma.h" +#include "ch32v30x_exti.h" +#include "ch32v30x_flash.h" +#include "ch32v30x_fsmc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_i2c.h" +#include "ch32v30x_iwdg.h" +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_rtc.h" +#include "ch32v30x_sdio.h" +#include "ch32v30x_spi.h" +#include "ch32v30x_tim.h" +#include "ch32v30x_usart.h" +#include "ch32v30x_wwdg.h" +#include "ch32v30x_it.h" +#include "ch32v30x_misc.h" + + +#endif /* __CH32V30x_CONF_H */ + + + + + diff --git a/User/ch32v30x_it.c b/User/ch32v30x_it.c new file mode 100644 index 0000000..95f8bba --- /dev/null +++ b/User/ch32v30x_it.c @@ -0,0 +1,41 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Main Interrupt Service Routines. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + + diff --git a/User/ch32v30x_it.h b/User/ch32v30x_it.h new file mode 100644 index 0000000..6475c5f --- /dev/null +++ b/User/ch32v30x_it.h @@ -0,0 +1,18 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains the headers of the interrupt handlers. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_IT_H +#define __CH32V30x_IT_H + +#include "debug.h" + + +#endif /* __CH32V30x_IT_H */ + + diff --git a/User/main.c b/User/main.c new file mode 100644 index 0000000..3f88e4d --- /dev/null +++ b/User/main.c @@ -0,0 +1,106 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : main.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Main program body. + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + *******************************************************************************/ + +/* + *@Note + GPIỌ + PA0 + + */ + +#include "debug.h" +#include "tos_k.h" +#include "tos_js.h" + +/* Global define */ + +/* Global Variable */ + +/********************************************************************* + * @fn GPIO_Toggle_INIT + * + * @brief Initializes GPIOA.0 + * + * @return none + */ +void GPIO_Toggle_INIT(void) { + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); +} + +#define TASK1_STK_SIZE 10240 +k_task_t task1; +__aligned(4) uint8_t task1_stk[TASK1_STK_SIZE]; + +#define TASK2_STK_SIZE 10240 +k_task_t task2; +__aligned(4) uint8_t task2_stk[TASK2_STK_SIZE]; + +void task1_entry(void *arg) { + while (1) + { + printf("###I am task1\r\n"); + tos_task_delay(2000); + } +} +jsval_t js_print(struct js *js, jsval_t *args, int nargs) { + for (int i = 0; i < nargs; i++) { + const char *space = i == 0 ? "" : " "; + printf("%s%s", space, js_str(js, args[i])); + } + putchar('\n'); + return js_mkundef(); +} + +char js_mem[2000]; + +void task2_entry(void *arg) { + struct js *js = js_create(js_mem, sizeof(js_mem)); + js_set(js, js_glob(js), "print", js_mkfun(js_print)); + js_run(js, "let a = 1;"); + while (1) + { +// printf("***I am task2\r\n"); + js_run(js, "a *= 2; print('res:', a);"); + tos_task_delay(1000); + } +} + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) { + USART_Printf_Init(115200); + printf("SystemClk:%d\r\n", SystemCoreClock); + + printf("Welcome to TencentOS tiny(%s)\r\n", TOS_VERSION); + tos_knl_init(); + tos_task_create(&task1, "task1", task1_entry, NULL, 3, task1_stk, + TASK1_STK_SIZE, 0); // Create task1 + tos_task_create(&task2, "task2", task2_entry, NULL, 4, task2_stk, + TASK2_STK_SIZE, 0); // Create task2 + tos_knl_start(); + + printf("should not run at here!\r\n"); + + while(1) + { + asm("nop"); + } +} diff --git a/User/system_ch32v30x.c b/User/system_ch32v30x.c new file mode 100644 index 0000000..87150ca --- /dev/null +++ b/User/system_ch32v30x.c @@ -0,0 +1,776 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer System Source File. +* For HSE = 8Mhz +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*********************************************************************************/ +#include "ch32v30x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +// #define SYSCLK_FREQ_HSE HSE_VALUE +/* #define SYSCLK_FREQ_24MHz 24000000 */ +//#define SYSCLK_FREQ_48MHz 48000000 +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +//#define SYSCLK_FREQ_96MHz 96000000 +//#define SYSCLK_FREQ_120MHz 120000000 +//#define SYSCLK_FREQ_144MHz 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */ + +#elif defined SYSCLK_FREQ_96MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /* System Clock Frequency (Core Clock) */ + +#else /* HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); + +#elif defined SYSCLK_FREQ_96MHz + static void SetSysClockTo96(void); +#elif defined SYSCLK_FREQ_120MHz + static void SetSysClockTo120(void); +#elif defined SYSCLK_FREQ_144MHz + static void SetSysClockTo144(void); + +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + +#ifdef CH32V30x_D8C + RCC->CFGR0 &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR0 &= (uint32_t)0xF0FF0000; +#endif + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#ifdef CH32V30x_D8 + if(pllmull == 17) pllmull = 18; +#else + if(pllmull == 2) pllmull = 18; + if(pllmull == 15){ + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) pllmull = 15; + if(pllmull == 17) pllmull = 16; +#endif + + if (pllsource == 0x00) + { + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#elif defined SYSCLK_FREQ_96MHz + SetSysClockTo96(); +#elif defined SYSCLK_FREQ_120MHz + SetSysClockTo120(); +#elif defined SYSCLK_FREQ_144MHz + SetSysClockTo144(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_24MHz + +/********************************************************************* + * @fn SetSysClockTo24 + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN); +#endif + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz + +/********************************************************************* + * @fn SetSysClockTo48 + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz + +/********************************************************************* + * @fn SetSysClockTo56 + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz + +/********************************************************************* + * @fn SetSysClockTo72 + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz + +/********************************************************************* + * @fn SetSysClockTo96 + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz + +/********************************************************************* + * @fn SetSysClockTo120 + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_144MHz + +/********************************************************************* + * @fn SetSysClockTo144 + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#endif diff --git a/User/system_ch32v30x.h b/User/system_ch32v30x.h new file mode 100644 index 0000000..0e0ef4e --- /dev/null +++ b/User/system_ch32v30x.h @@ -0,0 +1,30 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer System Header File. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __SYSTEM_CH32V30x_H +#define __SYSTEM_CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V30x_SYSTEM_H */ + + + diff --git a/obj/Core/core_riscv.d b/obj/Core/core_riscv.d new file mode 100644 index 0000000..25ba9bb --- /dev/null +++ b/obj/Core/core_riscv.d @@ -0,0 +1 @@ +Core/core_riscv.o: ../Core/core_riscv.c diff --git a/obj/Core/core_riscv.o b/obj/Core/core_riscv.o new file mode 100644 index 0000000..22aab02 Binary files /dev/null and b/obj/Core/core_riscv.o differ diff --git a/obj/Core/subdir.mk b/obj/Core/subdir.mk new file mode 100644 index 0000000..8d79583 --- /dev/null +++ b/obj/Core/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/core_riscv.c + +OBJS += \ +./Core/core_riscv.o + +C_DEPS += \ +./Core/core_riscv.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/%.o: ../Core/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/Debug/debug.d b/obj/Debug/debug.d new file mode 100644 index 0000000..845285b --- /dev/null +++ b/obj/Debug/debug.d @@ -0,0 +1,90 @@ +Debug/debug.o: ../Debug/debug.c ../Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +../Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Debug/debug.o b/obj/Debug/debug.o new file mode 100644 index 0000000..1e78996 Binary files /dev/null and b/obj/Debug/debug.o differ diff --git a/obj/Debug/subdir.mk b/obj/Debug/subdir.mk new file mode 100644 index 0000000..4d537d5 --- /dev/null +++ b/obj/Debug/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Debug/debug.c + +OBJS += \ +./Debug/debug.o + +C_DEPS += \ +./Debug/debug.d + + +# Each subdirectory must supply rules for building sources it contributes +Debug/%.o: ../Debug/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/JSInterpreter-TencentOS.elf b/obj/JSInterpreter-TencentOS.elf new file mode 100644 index 0000000..14f3594 Binary files /dev/null and b/obj/JSInterpreter-TencentOS.elf differ diff --git a/obj/JSInterpreter-TencentOS.hex b/obj/JSInterpreter-TencentOS.hex new file mode 100644 index 0000000..4a09b66 --- /dev/null +++ b/obj/JSInterpreter-TencentOS.hex @@ -0,0 +1,3279 @@ +:100000006F4080291300000013000000130000005F +:100010001300000013000000130000001300000094 +:100020001300000013000000130000001300000084 +:08003000130000007300100032 +:1000380000000000000000002E0400003204000050 +:1000480000000000DE410000000000000000000089 +:10005800E0410000E2410000000000000000000054 +:100068000C400000000000005C02000000000000DE +:10007800E8410000EA410000EC410000EE410000C8 +:10008800F0410000F2410000F4410000F641000098 +:10009800F8410000FA410000FC410000FE41000068 +:1000A8000042000002420000044200000642000034 +:1000B800084200000A4200000C4200000E42000004 +:1000C80010420000124200001442000016420000D4 +:1000D800184200001A4200001C4200001E420000A4 +:1000E8002042000022420000244200002642000074 +:1000F800284200002A4200002C4200002E42000044 +:100108003042000032420000344200003642000013 +:10011800384200003A4200003C4200003E420000E3 +:1001280040420000424200004442000046420000B3 +:10013800484200004A4200004C4200004E42000083 +:100148005042000052420000544200005642000053 +:10015800584200005A4200005C4200005E42000023 +:1001680060420000624200006442000066420000F3 +:10017800684200006A4200006C4200006E420000C3 +:100188007042000072420000744200007642000093 +:10019800784200007A4200007C4200007E42000063 +:1001A8008042000082420000844200008642000033 +:1001B800884200008A4200008C4200008E42000003 +:1001C80090420000924200009442000096420000D3 +:1001D8000000000000000000000000000000000017 +:1001E8000000000000000000000000000000000007 +:0801F8000000000000000000FF +:1002000083A2418503A1020011A0010082427390E4 +:100210001234924273900230A240B2414242D24222 +:100220006243F243025492542255B2554256D2567A +:100230006257F257064896482649B649464AD64A72 +:10024000664BF64B065C965C265DB65D465ED65EFA +:10025000665FF65F0961730020300100197116CAEC +:100260009302000273A04280F322003016C2F322F0 +:10027000103416C006C40EC612C81ACC1ECE22D028 +:1002800026D22AD42ED632D836DA3ADC3EDEC2C0A6 +:10029000C6C2CAC4CEC6D2C8D6CADACCDECEE2D076 +:1002A000E6D2EAD4EED6F2D8F6DAFADCFEDE8A82BC +:1002B00003A1018216C0EF30304E02419382418586 +:1002C0001383018683A3020023A0230003230300DA +:1002D00023A0620003210300924273900230824205 +:1002E00073901234A240B2414242D2426243F2437E +:1002F000025492542255B2554256D2566257F25782 +:10030000064896482649B649464AD64A664BF64BB1 +:10031000065C965C265DB65D465ED65E665FF65F01 +:10032000096173002030397101436EC619A039711B +:1003300041536AC866CA62CC5ECE19A039710153B6 +:100340005AD056D252D44ED64AD826DA22DC06DE0D +:1003500033016140828241114AC026C222C406C6CE +:100360008282B24D4101024D924C224CB24B41016E +:10037000024B924A224AB249410102499244224424 +:10038000B240410182803D432A876373C302937761 +:10039000F700BDEFADE5937606FF3D8ABA960CC334 +:1003A0004CC30CC74CC74107E36BD7FE11E28280F8 +:1003B000B306C3408A069702000096966780A6009F +:1003C0002307B700A306B7002306B700A305B700AD +:1003D0002305B700A304B7002304B700A303B700A5 +:1003E0002303B700A302B7002302B700A301B7009D +:1003F0002301B700A300B7002300B700828093F564 +:10040000F50F93968500D58D93960501D58D61B72F +:10041000939627009702000096968682E78086FAD8 +:100420009680C1171D8F3E96E374C3F8A5B773007D +:10043000203001A0EFF23FF237C400001305040B97 +:10044000EF70E06A81451305007DEF30D00DFDB7F8 +:10045000EFF2FFEDB7C4000037C90000AA8A2E8B67 +:10046000328A01449384C40A1309496DB7CB000052 +:10047000634844012945EF708056EF10A050E5B560 +:10048000A68911C0CA8993173400DA978C43D043E8 +:1004900056850504EF1000142A86CE8513854B047B +:1004A000EF70C04FF1B7EFF27FE9375500209305A9 +:1004B000007D13058534EF1000482A84EF10604D4D +:1004C0002A893705000013050545AE89EF10004C59 +:1004D000B7C600002A87AE879386060CCA854E866B +:1004E0002285EF10804BB7C500009385850C2285CF +:1004F000EF106055B7C400009385440D2285EF10BE +:10050000805481451305803EEF30F001F5B7EFF2DE +:100510009FE4716513050520EF40600DB7070020CB +:1005200083A5071E37C500001305C504EF700047FB +:10053000B7C5000037C500009385C50513054506FE +:10054000EF70C045EF30A04F0D64B70700203706AD +:100550000000B7C50000373500208148130804802B +:10056000938787250D4781461306464393854508A3 +:10057000130585A5EF30E04EB737002037060000A1 +:10058000B7C50000373500208148130804809387E1 +:1005900087B4114781461306664A9385C50813053B +:1005A00005ADEF30004CEF30C03B37C50000130500 +:1005B0004509EF70C0530100FDBFB71702409843D3 +:1005C000B706FFF841111367170098C3D8433706E1 +:1005D0000200758FD8C39843B706F7FEFD16758FD6 +:1005E00098C39843B706FCFFFD16758F98C3D84390 +:1005F000B70681FFFD16758FD8C39843B70600EC88 +:10060000FD16758F98C33707FF0098C723A607020A +:1006100002C402C69843C166558F98C3B7160240FC +:1006200005679C42F18F3EC6A24785073EC4B2478C +:1006300081E7A247E397E7FEB71702409C43139771 +:10064000E7006357070685473EC632478547631F65 +:10065000F704B7170240D843B706C1FFFD16D8C349 +:10066000D843D8C3D84313670740D8C3D843758F3E +:10067000D8C3D843B7061D00558FD8C39843B706D3 +:100680000001558F98C3984393166700E3DD06FE7B +:10069000D843B7160240719BD8C3D84313672700CD +:1006A000D8C32147DC42B18BE39EE7FE4101828043 +:1006B00002C661BF13D745019307F07F1545631547 +:1006C000F700C18113F5F5008280EFF2DFC8DD3756 +:1006D00059151335150055B138517C4D411102C6DD +:1006E0006374F700998F3EC6B247584163F3E70041 +:1006F0005CC17C5578006377F700998F184163736C +:10070000F7001CC141018280AA8701456308B50238 +:100710006307D5003307A6000307070001E785C17B +:10072000AA8501A83388A7002300E8000505F9BFC2 +:100730007D153E95230005002E85828075F9828007 +:10074000130E0002914E9306F0021303A002294FEC +:100750006364B600328582803307C5000308070052 +:1007600093071600630CC803930878FF93F8F80FFB +:1007700063F61E0363F8B7026316D802B308F500E8 +:10078000838808006390D802930726006388B70027 +:100790003307F500030707006314E7013E864DBFEA +:1007A0008507EDB793083600E3F6B8FAE314D8FAF4 +:1007B000AA9783870700E39F67F893074600E38FB4 +:1007C000B7FC030627006316660003063700E3073D +:1007D000D6FC85070507E5B7639BB600EFF2BFB708 +:1007E000B2853686EF50D0711335150079B60145C4 +:1007F0008280AA87130505FD1375F50F2547637DD4 +:10080000A7001387F7F91377F70F954663E7E6001C +:10081000938797FA13F5F70F82801387F7FB137707 +:10082000F70F0145E3EAE6FE938797FCE5B71377F8 +:1008300035008546AA87630ED700214501CF89463A +:100840007D556319D70013D527000D057199110542 +:10085000828041458280EFF21FB041112A84AE842C +:1008600032C6A53501C5324600C244C2410131B687 +:10087000EFF27FAE38517C4D411102C663F0E702C2 +:10088000B7C6000037C500009386863413860183FF +:100890009305E0091305C535EF5090603C4D1146B6 +:1008A0006800BE95EF50306832454101F9B4EFF26F +:1008B0009FAA41112E8436C6653FB24609817D1537 +:1008C00088C21305440041014DBCEFF2DFA82C495A +:1008D0002A849105713FB707F07F28C87CC871BC96 +:1008E000EFF27FA72A892E842E85B285B284D93370 +:1008F00019476315E5003335800041B41547AA87D1 +:10090000631BE500014681462285A685EF40106203 +:100910003335A000DDB70545EDD31D47E38FE7FC78 +:1009200009470145E39BE7FCA2854A859137098188 +:100930007D15F9BFEFF29FA0AA84B6893A8A0D3FD0 +:10094000BC501374C5FF637AF40219E022850DB41C +:10095000930544002685293FAA852A892685093FD3 +:10096000B04C935625001109FD164A96D2854E8546 +:10097000A53569FDA2852685D9B70144C1BFEFF22F +:10098000FF9B41112A892E84B28485492285A68540 +:100990001533631D35018325890521042146A29560 +:1009A0002800EF5050582244B244CDB72285A68586 +:1009B00041017DBA830705001307F005638BE70645 +:1009C000130740026387E70693F7F7FD9387F7FB6A +:1009D00093F7F70F6547637EF70481473E85828072 +:1009E000850404C2044263F6B402B307950083870A +:1009F0000700E38707FFE38517FF13F7F7FD1307EA +:100A0000F7FB1377F70FE37DE3FC938707FDE3F92B +:100A1000F6FC1C215D479387E7F993F7F70F636AAC +:100A2000F73431678A071307070FBA979C432A8464 +:100A30008287EFF25F921308F00593084002654346 +:100A4000A5464DB72A8637C50000A68695451305ED +:100A5000053A5933894719C1930720033E856FF042 +:100A6000DF912A8637C50000A68695451305853A8D +:100A7000A533930750037DF137C50000A686228673 +:100A800091451305053B893B9307300361F937C551 +:100A90000000A686228695451305853B353B9307C6 +:100AA00040034DFD37C50000A686228695451305F7 +:100AB000053C1D339307600355F137C50000A6863A +:100AC0002286A1451305853C013B894741D99307FF +:100AD000700369B72A8637C50000A68689451305C5 +:100AE000453DDD399307A00335F937C50000A686DB +:100AF00022869D451305853DC531894725D193073C +:100B00008003A9BF2A8637C50000A6869145130534 +:100B1000053ED931894739D19307B00381B72A8679 +:100B200037C50000A6868D451305853E75319307B0 +:100B3000D003E31505F237C50000A6862286A1453D +:100B40001305052251399307E003E31905F037C572 +:100B50000000A68622869D451305C53EB53993073C +:100B6000C003E31D05EE37C50000A6862286954525 +:100B70001305453F95318947E30205EE93071005BC +:100B8000F1BD2A8637C50000A68689451305C53FF5 +:100B9000A1319307F003E31305EC37C50000A686E7 +:100BA0002286894513050540053993070004E3179C +:100BB00005EA37C50000A6862286A94513054540EB +:100BC00021398947E30C05E89307100441BD2A86C3 +:100BD00037C50000A6868D4513050541F53E8947BA +:100BE000E30E05E69307200495BD2A8637C500006D +:100BF000A6868D4513054541C53693073004E31F8E +:100C000005E437C50000A6862286914513050547F1 +:100C1000E1368947E30405E49307F00481B52A86A9 +:100C200037C50000A6869945130585417536894765 +:100C3000E30605E29307400415B52A8637C5000090 +:100C4000A686994513050542413E8947E30805E01C +:100C50009307500421B52A8637C50000A6868D4526 +:100C600013058542953E93078004E31905DE37C5D9 +:100C70000000A686228691451305C542B13E930722 +:100C80006004E31D05DC37C50000A6862286954575 +:100C900013054543913693077004E31105DC37C50E +:100CA0000000A686228691451305C5433536930775 +:100CB0000005E31505DA37C50000A68622869945AA +:100CC00013054544113E8947E30A05D89307A0065A +:100CD00071B32A8637C50000A686A545130585474A +:100CE000E53C8947E30C05D69307E00485BB2A86DB +:100CF00037C50000A6868D451305C544F13C930712 +:100D00009004E31D05D437C50000A68622869145D0 +:100D100013050545D1348947E30205D49307A004A0 +:100D200035BB2A8637C50000A6869545130585453F +:100D300065349307B004E31305D237C50000A686D7 +:100D40002286914513050546413C8947E30805D0B5 +:100D50009307C00421B32A8637C50000A6869545AF +:100D600013058546953C8947E30A05CE9307D004D1 +:100D7000F5B18947E5B1EFF20FDE0329050304451C +:100D800050592A8423070502A30605024111CA858A +:100D90002685EFF0FF9A48D808DC232E0402636909 +:100DA00025018547A306F402054541016FF0EFDCFC +:100DB000AA94838704001307F0026384E720634941 +:100DC000F708130780026382E7146340F7041307F0 +:100DD00050026387E7206343F7021307100263831F +:100DE000E71413072002638EE72EB305A94013060C +:100DF000C4032685C136A306A402F5A81307600222 +:100E0000638FE71E13077002F9BF1307B002638CEC +:100E1000E7166346F70213079002638AE70E13078B +:100E2000A002E394E7FC0505637A25198387140083 +:100E30001307A002639DE7169307D0063DA2130790 +:100E4000D002638BE710635CF70C9307400645A064 +:100E50001307E0036383E7246342F7041307A00347 +:100E60006382E70A63CDE72C1307C0036386E71E9E +:100E70006355F70A9307150063FD271D8387140048 +:100E80001307D0036397E71C09056374251D0387C7 +:100E900024006310F71C9307A00745A81307B007A9 +:100EA0006389E7066346F7021307F003638FE702DF +:100EB0001307E005E39BE7F205056371252303872C +:100EC00014009307D003631BF7209307D0F871A891 +:100ED0001307D0076381E70463C7E7141307E0072C +:100EE000E395E7F09307900619A0930720F8A3066F +:100EF000F40285475CDC1C5C585C0345D402BA975D +:100F00005CD865B5930710F8DDB79947CDB79D4715 +:100F1000F9BFA147E9BFA547D9BF9547C9BF930707 +:100F2000F0F8F1B79307150063F527030387140062 +:100F30009307D003631FF7000905637C250103872E +:100F400024006318F7009307B007A306F4028D4747 +:100F500055B79307800661BF0505637325030387B3 +:100F600014006318F70093077006A306F40289477C +:100F700051B79307D0036315F700930750F8F5B7FF +:100F800093072007ADB70505637025030387140099 +:100F90006315F70093076006C9BF9307D003631575 +:100FA000F700930740F8D1B79307100789B71307E5 +:100FB000D0036395E700930760F845BF9307E00609 +:100FC0003DB70505637B2501038714009307D00314 +:100FD0006315F700930770F849BF9307F00601BF48 +:100FE0000505637B2501038714009307D003631570 +:100FF000F700930780F895BF93070007CDBD05055F +:1010000063702503038714006315F7009307F00747 +:10101000A9BF9307D0036315F7009307C0F8B1B7D2 +:101020009307C007E9B5050563722503838714009C +:101030001307C0076395E700930700F83DB7130750 +:10104000D0036395E7009307E0F805B79307E0073F +:1010500079BD930730F861BD13071500637C270342 +:10106000038714006311F7020905637B25010387D9 +:1010700024009307D0036315F700930790F8F1B5A8 +:1010800093073007DDB59307D0036315F700930787 +:101090007007E1BD9307600799BD13071500637CD6 +:1010A0002703038714006311F7020905637B2501F9 +:1010B000038724009307D0036315F7009307A0F874 +:1010C00069B59307400755B59307D0036315F7003B +:1010D0009307900759BD9307800711BD9307D00769 +:1010E00039B585475CDC9308C005130380075C5C59 +:1010F000838504003388F4003307F50003060800F5 +:10110000637C27036397C5001147A306E4028507A4 +:10111000D5B38546631F160193062700636ED90079 +:101120000308180089466316680011076366E90022 +:101130009146B6975CDC65BFE31FB6DAF1B726854A +:101140006C00EF70B0038D47A306F402B24728C4C9 +:101150006CC4B384974044DC79BB0347E50201E7E4 +:101160000345D5028280EFF20F9F31316FF0EFA07F +:10117000EFF2CF9C41112A84AE89EFF06FEF2A89FC +:1011800063580502284CB704008093C7F4FFB37777 +:10119000F9002C0011464E953EC4EF50C05893C53F +:1011A000C4FF93773900B375B90081EF2285C93741 +:1011B000370500801345C5FF3375A90041016FF065 +:1011C0002F9B0547E396E7FE22855D37938549000F +:1011D0002285EFF0EFE9AA852285593F2C4CA10921 +:1011E0002146CE952800EF500054A244B2452685F2 +:1011F000EFF04FCC894763F5A7009D47E31AF5FA56 +:10120000A6856DB7EFF22F920111AA892E8A2E853D +:10121000B285B6843A8932C6EFF0CFC9A547AA860F +:1012200063E9A71E31679317250013070715BA97BF +:101230009C433246828737C60000A5461306864780 +:10124000CA852685EFF04FCC05616FF08F9137C6C8 +:101250000000914613060647E5B7137A1A00631893 +:101260000A0037C600001306463F9546D1BF37C671 +:1012700000001306C6439146E1B737C60000854615 +:101280001306064DCA852685EFF00FC82A84D2853D +:101290004E85EFF0EFDD137BC5FFB7CB000037CCF9 +:1012A000000083A70906B38C8400330D8940637462 +:1012B000FB00631D0B0037C6000085461306C64DB4 +:1012C000EA856685EFF04FC42295BDBF93054B00BC +:1012D0004E85EFF0EFD983A5890593078B00AA8D82 +:1012E000BE9521462808EF5000449306F4FFB3361C +:1012F000D00013864B4DEA856685624AF24AEFF0CC +:10130000AFC02A9433078940B3868400EE85370640 +:10131000F27F4E85C53D2A94B30589408546130664 +:101320008C4D33858400EFF02FBE2A94330789401B +:10133000B3868400D28556864E85E935DA852A94AF +:101340004E85EFF0EFD2137BC5FFA1BFD2853408E5 +:101350004E85EFF0CFD537CA0000AA8A854613061E +:101360000A4ECA852685EFF02FBA03A68905E24604 +:101370002A845696B305A9402695EFF0EFB82A9433 +:10138000854613060A4EB3058940338584001DBF88 +:10139000B287B28952853008BE85EF60007601467B +:1013A00081465289EF40803819C9B7C5000093853E +:1013B000C54C4A86CE862685EF60700671B5B7C5E6 +:1013C00000009385454CF5B7D28534084E85EFF083 +:1013D0000FCE37C600002A8AA14613060622CA8508 +:1013E0002685EFF06FB203A689052A84E24652965D +:1013F00059BF37C60000D2861306464ECA852685D9 +:10140000EF60E07A91B537C60000D2861306464FEA +:10141000F5B737C6000013060650CDB7397126CA96 +:1014200032D49304C50037C6000022CC4AC82A84AF +:101430002E8936D61306062E9D4693051002268564 +:1014400006CE3EDA3AD842DC46DEEFF0EFAB93054B +:1014500010023410898D4A86269536C6EF70606F6B +:101460001C5823070402F2405CD8930700105EB4B6 +:101470006244D24442490145B705FA7F2161828026 +:10148000EFE2DFEB205193877600784D4111F19B1D +:101490002EC6A297AA84637BF700B7C50000938588 +:1014A00005382685A53F41016FE09FEC3CD1FD57F3 +:1014B000E305F4FE284DB2896C0011462295368969 +:1014C000EF506026638A0900BC4C130544004A862D +:1014D000CE853E95EF508030B24589478D89639720 +:1014E000F500BC4CA297CA97A3810700C205B707B5 +:1014F000F07F2285DD8D45BFEFE2FFE5204D79715C +:10150000AA842E94A2851146680842C636C23EC4FB +:10151000EF506021A24792460C103ED4B2471146CC +:1015200022853ED6BC5036D23ED0EF50C01FF24589 +:101530005010B146F199268593E515009137456124 +:101540006FE0BFE3EFE23FE18347F5024111858B96 +:1015500099CFB7C6000037C500009386463813867A +:1015600081839305D0221305C535EF5060133C49A4 +:101570007000914681452A843EC6193728C86CC838 +:1015800041016FE09FDFEFE21FDD41112EC62A848B +:10159000B284E136B245630EB500B7C5000093854D +:1015A000C5292285A53D88C0CCC0014541016FE019 +:1015B000DFDC85472307F4020545CDBFEFE2BFD945 +:1015C00093061600939726002E8693E527004D3D3F +:1015D0006FE0BFDAEFE29FD6AA842E892E85B2850E +:1015E000B289EFF08F8E1384C4000DE5B850FC4C27 +:1015F0009306470063F3F602A04CF117CA853694B0 +:101600004E863387E740A2862685ED3E2A868145B1 +:1016100026856D3722856FE0BFD537C400001304DF +:10162000C40ACDBFEFE23FD01C5D83298500244D65 +:101630000111BE993C5113874700BA94585DBA977F +:10164000784D91076371F710B7C500009385053891 +:10165000F13305616FE0FFD0338529010821631B59 +:10166000750D4E97182303C509006313A702B387AE +:10167000C40098A305090506CA87485C138727009C +:1016800013891700E36AA7FC22858145053FD1B77E +:1016900063178701B387C40023800701E1BF631686 +:1016A0009701B387C4008CA3F1B76316A701B38772 +:1016B000C40094A3C1B76319B707138937003387F0 +:1016C00029010823130705FD63FAEA001377F5FDE6 +:1016D0001307F7FB1377F70F6368EB04CE97D82354 +:1016E000930707FD63FAFA009377F7FD9387F7FBFB +:1016F00093F7F70F636AFB0242CE2ECC36CA32C88C +:101700003AC6EFF00F8F32472A8A120A3A85EFF075 +:101710004F8E4246336AAA00D246B387C400238064 +:101720004701E2457248B9B7B7C500009385453215 +:10173000228539BF1C44185CCA97BA979823B3878F +:10174000C40098A30DBF2A8401468147930BC005AE +:10175000130CE006930C4007130D2007930D800730 +:10176000A54A154BB546A545294801BFEFE2BFBBC9 +:1017700041112A84EFE05FF63840FD576307F71404 +:101780008144B70900803C5063EBF4022448A685ED +:101790002285EFF0FF9D938544002285EFF04F8D69 +:1017A000AA8475F52C4081C52285EFF07F9CB70A8D +:1017B0000080814493CAFAFF054B894B21A2A6857C +:1017C0002285EFF0EF8A2A89284CB3673901114648 +:1017D0002C0026953EC4EF4010754A85EFF02F850A +:1017E000AA9455B7A6852285EFF08F88AA8933750C +:1017F0005501EFF0CF832A8963D5090C014A370CD4 +:10180000F07F9D4C95A0D2852285EFF06F86AA8946 +:1018100033755501EFF0AF812A8D63C6090493F744 +:101820002900B1E363FB3401284CB38729411146F9 +:101830002C0052953EC4EF40106F93F93900639924 +:10184000090893094A00CE852285EFF06F8263FC78 +:10185000A4003C4C330525412AC411462C00338595 +:101860003701EF40506C6A9A3050E36ECAF83C483A +:1018700063F8F400B38727413CC8B707F07F7CC802 +:101880003C4063E59700B38727413CC01C44284C8B +:10189000637CF500744C3387A7406377D70063F50A +:1018A000E400B38727411CC4B38524010D8EAA959B +:1018B0002695EF40B0723C503389274123202407FE +:1018C0000149CA943C50E3EFF4F041016FE07FA975 +:1018D000E39B69F993094A00CE852285EFE05FF921 +:1018E00063FCA4003C4C330525412AC411462C005E +:1018F00033853701EF4030633C4C930D8A0021461D +:10190000BE9DEE852800EF401062A249B2454E858B +:10191000EFE05FDA63F4AB00E31795F5E3F534F538 +:1019200042053365AC00B38929412AC64EC421461D +:101930002C006E853DB7EFE21FA29307700741119F +:10194000014463FDB7022E86AE8481452A84EFE010 +:101950009FA393070407938404F93CCC64CC91467D +:1019600070008145228502C6EFF09FB17C4C28C8EB +:101970006CC8E19B7CCC5CC085837CD02285410116 +:101980006FE0BF9F0145B705F37F8280B705F97F00 +:1019900082800145B705F07F8280EFE23F9A2A847A +:1019A0002E892E85B285B289B6843A8ABE8AEFE046 +:1019B0007FD00DE12685EF60E02A2A86A685228564 +:1019C000F53EAA862E87D2875688CA854E862285FE +:1019D000EFF09FB26FE0DF99EFE25F9601110147F0 +:1019E000B707F37F3ACC3ECE1307F6FFF5572A84AC +:1019F00063F8E7002E852EC6EF60C026B2452A8622 +:101A000085472307F4023C08A30604020CC410D83F +:101A1000232A04027CD485442285EFF00FF4624926 +:101A2000F249630795004A85CE85EFE01FCA11C5CC +:101A30004A85CE8505616FE0BF932285EF0090391E +:101A40002ACC2ECED1BFEFE21F917D5671376FE0C9 +:101A5000DF92EFE25F8DBE8C8347F5021D71858BAF +:101A6000639D0778B28AAE89B28536863A8C2A8D14 +:101A7000368BEFE0DFF02A84AE846686E2856A85E5 +:101A8000EFE0FFEF2A896A852E8AEFE0FFC4228506 +:101A9000A685EFE09FC32DED4A85D285EFE0FFC21A +:101AA000631105769387D90793F7F70F2D47636383 +:101AB000F7765685DA85EFE0FFBF8547630AF5764E +:101AC000B7C50000938505206A85EFF03F953DA8D6 +:101AD000D2854A85EFE01FBEB1652A841306000354 +:101AE000938545010818EF401044AD4763E787022E +:101AF0000A049C103E94832504FD2E852EC0EF60C1 +:101B0000601682452A866A85EFF05FAB2A84AE8430 +:101B10002285A68525616FE0DF84B7C50000938527 +:101B2000C51FE1BF4A85D285EFE0DFB8A147630753 +:101B3000F500B7C500009385852079B72285A68575 +:101B4000EFE05FB7930795FF93F7D70FAA8A91C786 +:101B5000B7C500009385452185BFB70500018329DE +:101B60008D00FD153375B900220A135989018327A9 +:101B70004D0333692A01B375B9004E95832B0D03CC +:101B80002324AD002328BD0201463EC0EFE05FBB29 +:101B90008347DD02232AAD0201493EC28347FD028D +:101BA0003EC483270D043EC69D47638BFA049D44C3 +:101BB000130AF008854A03274D0383270D03636842 +:101BC000F71E83258D058327CD0513561940131A5B +:101BD0003900BE950E06AE86338545012E966115F9 +:101BE000631AD6224A866A8502942A846A85AE845C +:101BF000EFE09FAE8327CD05D297232EFD04A5AA43 +:101C0000A285268674106A85EFE07FCA83248D053D +:101C10009307C5FF2320FD04AA946A853254054B1F +:101C2000EFF05F92130A9002094C854CB70DF37FD9 +:101C3000930AC00263788B0E5A86A2852685EFE050 +:101C40003FB02A8B3389A40063768500830709009F +:101C5000638747151018B30564414A8502D8EFE041 +:101C60007FD5631F850B83278D0003264D038325B6 +:101C70000D033E853EC8EFE0BFACC247232AAD024C +:101C800023079D03AA97038707006E888147630790 +:101C900047016A85EF00E07AAA872E8803230D05A5 +:101CA00083234D054256CA856A8542CE3ECC1AC86A +:101CB0001ECAEFF0BF904243D243E2477248AA8661 +:101CC0002E871E869A856A85EFF01F8383270D0372 +:101CD00003298D0003264D03BE854A853EC8EFE0EB +:101CE0003FA6C247232AAD02637AF5002A998307EB +:101CF0000900639557010505232AAD024256A285C6 +:101D000026855A96EFE0DFA32A8BE37585F2B38729 +:101D1000A40083870700E39F57F1130B150019BF39 +:101D2000636F8B065A86A2852685EFE07FA1637BD1 +:101D30008500B387A400038707009307B0076313E8 +:101D4000F700050591471306F4FFB385A400098E3B +:101D5000A307FD026A8549312A84AE84EFE0FF962D +:101D600001E98347FD02C18B81E70144B704F37F9A +:101D70006A85EFE09FB5824723243D0123287D0338 +:101D8000232AFD02A247A307FD029247A306FD02F4 +:101D9000B2472320FD0485472307FD0295BB0307B7 +:101DA000090093079002E31FF7F6050BA5BF6A85AC +:101DB000EFF0AFBAE30795E06A85EF0080682E8602 +:101DC000AA856A85EFE0BFBB03270D068327CD05F3 +:101DD0002AD82EDA210763FCE700B7C500009385F7 +:101DE000C5226A85EFF08FE32A84AE8469B70325A4 +:101DF0008D05E117232EFD0421460C183E95EF407A +:101E000090126A850509EFF04FB5E31645DB23070D +:101E10005D0355B318415C4103A3060083A346004C +:101E200098C2DCC22320650023227500A10645BBB1 +:101E30000147B707F03F5686DA86930540086A8562 +:101E4000EF106057F1B10147B707F03F5686DA86C9 +:101E500093055008EDB74A85D285EFE0BF859947D5 +:101E60006310F50213341900B704F67F55B14A87A1 +:101E7000D2875686DA86CE856A85EF10C05379B14F +:101E80002285A685EFE01F838947AA8A631FF50C88 +:101E90004A85D285EFE01F822A8B6318550D3410D6 +:101EA000A28526866A85EFE09FA05286AA8A7410D2 +:101EB000CA856A85EFE0BF9F930710072A8A639956 +:101EC000F9042256B25781456A853E96EFF00FEF2E +:101ED0002A84AE84EFE00FFEE31C65C31418A285CC +:101EE00026866A85EFE0BF9C2A8903258D05225648 +:101EF000B30555014A95EF40700EA25703258D0595 +:101F000032563E99B30545014A95EF40300D09B16F +:101F10009307A0076391F9022256B2570144E315D3 +:101F2000F6F403258D05B30545015695EF40407D38 +:101F30001334150015BF9307B0076393F9022256B7 +:101F4000B2570145631BF60003258D05B305450116 +:101F50005695EF40E07A133515001344150029B764 +:101F6000B7C500009385852385B69387A9F993F7B4 +:101F7000F70F1947636EF7004A85D285EFE08FF3BC +:101F800095476304F502B7C50000938545242DBE2F +:101F900093074006638BF9009547E396FAFE4A855E +:101FA000D285EFE02FF1E31055FF9387C9F993F73E +:101FB000F70F6947228BA68B6367F72231678A0781 +:101FC00013078717BA979C438287014681464A8543 +:101FD000D285EF30A07511E5B7C500009385452582 +:101FE000E5B44A86D2862285A685EF30E01839BE50 +:101FF0004A86D2865A85DE85EF300018EF40004FC2 +:10200000EF4040554A86D286EF30300F2A86AE86A2 +:102010005A85DE85EF30F059D5BC4A86D2862285B6 +:10202000A685EF30900DDDB44A86D2862285A6853E +:10203000EF209021E1BC4A86D286D9BF2285A685B1 +:10204000EF40C04A2A84D2854A85EF40204A218D3C +:10205000EF40405065BC2285A685EF4020492A8488 +:10206000D2854A85EF408048618DDDB72285A685FF +:10207000EF40C0472A84D2854A85EF402047418DF2 +:10208000C1BFB70500804A84B3C4450151B44A8535 +:10209000D285EF40A0451345F5FF5DBF014681465F +:1020A0004A85D285EF30806861B52285A685EF40EC +:1020B000E0432A84D2854A85EF4040433315A4008B +:1020C00041BF2285A685EF4060422A84D2854A8599 +:1020D000EF40C0413355A440A5BF4A85D285EFE00B +:1020E0006FDDA1476307F500B7C50000938505269E +:1020F000E1BAB707000103258D00FD173377F9001A +:102100003A9509476399EA02220A93558901B36512 +:10211000BA0037C60000994613060627FD8DEFE08A +:10212000AFEB01CDA2856A85EFE08FF409817D15C3 +:10213000EF404049E1BA63870A00B7C500009385C4 +:10214000852759B2220A135789013367EA00AA8604 +:102150007D8FA28526866A85EFE0CFFD5DC52A8446 +:10216000B704F17F75B22285A685EF4020382A8416 +:10217000D2854A85EF408037098C13341400EDB1C5 +:102180002285A685EF4080362A84D2854A85EF4095 +:10219000E035098C33348000C1B922854A86D28665 +:1021A000A685EF30206A132405007DB922854A8672 +:1021B000D286A685EF3000691324150075B12285FB +:1021C0004A86D286A685EF30005D3324A00069B927 +:1021D00022854A86D286A685EF30E05B1345F5FF5F +:1021E0001354F50151B1B7C500004E866A85938539 +:1021F000C528EFF0AFA26FF07F91014481446FF0EA +:102200003F914A84D2846FF0BF900144B704F37FBA +:102210006FF01F909387B9F993F7F70F1547E361B4 +:10222000F7C631678A071307471EBA979C43828710 +:1022300093073008E39DF9C203258D0593F7CAFF84 +:10224000A10721460C183E954AD852DA5684EF4031 +:10225000804DDA846FF0DF8BEFE24F8E41112A84DC +:10226000EF10E00E2A89AE849309E007054A4A85FB +:10227000A685EFE08FC511E52285EFE01FEE63082C +:1022800035034A85A685EFE04FC409ED8349F40282 +:10229000130AF007854A2285EFE03FEC630345050A +:1022A000A30734034A85A68541016FE06F8C23079D +:1022B00044032285834AD402EF1060092AC62EC443 +:1022C000EFE0AFC0A247324711E94A86A686D6851D +:1022D0002285EFF00FF82A89AE8451BF3A89BE8477 +:1022E0004DB72686CA85230754032285EFE02FE9E0 +:1022F000AE842A89AA8526862285EFE06FDE834791 +:10230000F40201E993E71700A307F4022285A93735 +:1023100059B7858BE5FF228581372A89AE84A5BF11 +:10232000EFE2CF812A840D3F2A89AE89EFE0EFB931 +:1023300009ED8344F402130A0008854A2285EFE080 +:10234000DFE163084501A30794024A85CE856FE06B +:102350002F824E86CA85230754032285EFE02FE2A1 +:10236000AE892A89AA854E862285EFE06FD78347FA +:10237000F40201C993E71700A307F40222854D3741 +:1023800075BF858BE5FF2285613F2A89AE897DB7C0 +:10239000EFD2DFFA2A84930A2008054A130B1008AB +:1023A0002285BD3F2A892285AE89EFE01FDB6314B9 +:1023B00055074E8623074403CA8522858344F402C9 +:1023C000EFE0EFDB2E86AA852285EFE06FD121C9F1 +:1023D00022857D3F8347F4022A89228593E71700EF +:1023E000A307F402AE89EFE05FD793071008630EEE +:1023F000F500B7C50000A30794029385C52922857F +:10240000EFF0CF812A89AE8939A0230744032285C2 +:102410004137A30794024A85CE856FD07FF5834765 +:10242000F402228593E71700A307F402953722856B +:10243000EFE0BFD2E31F65FB23074403A307940229 +:1024400085B7EFD2BFEF41112A8499372A89AE842C +:1024500093093008294A854A4A85A685EFE0EFA608 +:1024600031E52285EFE07FCF630A35018347D4024F +:102470009387C70793F7F70F636AFA02230754039A +:102480002285034BD402753F2AC62EC4EFE0EFA38A +:10249000A247324711E94A86A686DA852285EFF0FF +:1024A0004FDB2A89AE844DBF3A89BE844A85A68512 +:1024B00041016FD0FFEBEFD21FE78344F502854760 +:1024C0004111AA8B85882307F502054A814C370DF7 +:1024D000F37F8549130CF0085E85EFE01FC889473C +:1024E000630AF500B7C500005E859385C529EFE056 +:1024F000FFF295A823874B035E8583AD8B0303A969 +:10250000CB0303A48B00EFE01F8793073008668B93 +:10251000EA8A631BF50023874B035E851D372A8BF0 +:10252000AE8AEFE08F9A31E199C85E85EFE0FFC295 +:1025300095476314F508014BB70AF37F3DA083A5C7 +:102540000B0503A64B056E944A87A2865E85EFE0D5 +:102550006FBE0DC1B7C50000A2864A869385852C43 +:102560005E85EFE0BFEB2A8BAE8A5A85D6854101A6 +:102570006FD03FDF03A30B0583A34B054A86A285DB +:102580005E851AC41EC6EFF06F8356862AC02EC21F +:102590005E85DA85EFE0AFBE2243B2438246124742 +:1025A000AA872E881E869A855E85EFE0FFF42A8B27 +:1025B000AE8AEFE08F9135D94DBF5E85EFE0FFB970 +:1025C000E30B35F75E85EFE05FB9E31D85F1238707 +:1025D0003B0319B7EFD23FD538517C5141112A84C2 +:1025E00063F4E700EFF08F982285EFE01FB79307C1 +:1025F000D0036308F52063E0A7069307600363E157 +:10260000A702930730036375F502A1476303F51E24 +:1026100093072003630BF5082285EFF09FE2EDA6F8 +:102620009307A00363E4A70293078003636DF50497 +:1026300014441C5C505CB7C50000BE969385852E83 +:102640002285EFE0BFDD2A89AE8451A09307C00345 +:10265000E300F5FED1B793072004630AF50A63E9A6 +:10266000A7009307F0036308F50AE373F5FC6DB761 +:10267000930740046300F534E36CF5FA9307D00444 +:10268000E3ECA7F875B78347F40213F7170015EBCF +:1026900013F7270093E717001DE3B7C500009385E4 +:1026A00005302285EFE09FD779BF8347F40213F707 +:1026B000170001EB13F7270093E7970079DFA307D3 +:1026C000F40285472307F4020149B704F37F22850A +:1026D000EFE0BFA89547630FF5322285EFE0FFA733 +:1026E00085476309F5322285EFE03FA7A5476303DD +:1026F000F532B7C50000938585312285EFE01FD202 +:102700002A89AE844A85A68541016FD09FC522855E +:10271000EFF07FDA0DBF8544230794022285EFE0B6 +:102720008FE599476307F500B7C500009385C52974 +:102730008DBF230794022285EFF0BFD02E86AA8595 +:102740002285EFE0CFA32A892285AE89EFE0FFA0A2 +:102750009D47E31BF5FC4E8623079402CA8522851C +:10276000EFE00F988347F402AA8993FA170009E56E +:1027700093E71700A307F40222851D2E2A89AE8451 +:10278000639C090063970A008347F402F99BA3073F +:10279000F4020149B704F37F034BD402832B4403B3 +:1027A000054A230744032285EFE0EFDC9307B003DB +:1027B000232A7403A3066403E31BF5F023074403F1 +:1027C0002285EFE09F99230744036388090083472C +:1027D000F40293E71700A307F4022285D12CE384C7 +:1027E00009E6E3960AEE8347F402F99BA307F40295 +:1027F000F9BD8345F402228593C5F5FF8589392CFF +:1028000099B58344F4020147B707F37F13F9140025 +:102810003AC43EC6631509002285EFE0BFD23000FE +:102820009305D0032285EFE01FD66309050E300023 +:1028300099452285EFE03FD56302050E2285EFE042 +:10284000DF919547631DF50A300095452285EFE03D +:102850009FD36305050C8347F4022285032A4403B2 +:1028600093E71700A307F402EFE03F8F9547631E3D +:10287000F50A300095452285EFE0FFD045C122855D +:10288000832A4403EFE07F8D9D476319F50A3000EA +:102890009D452285EFE03FCF51C12285032B4403A4 +:1028A000012C3000EFD03FFB35E9832B44038549F1 +:1028B000154C9D4C6310090CA3079402232A440372 +:1028C000230734032285EFE00FCB6311850983478B +:1028D000F402232A64032307340393E72700A307A2 +:1028E000F4022285F1223000EFD0FFF641CD22859F +:1028F000EFD0BFFDA30794022249B244C9BB228591 +:10290000EFE0BF8593072004631DF5002285EFF0FB +:102910009FBA3000EFD03FF4E30805F2E31C09FC56 +:10292000F9B72285EFF0FFB1EDB72285EFF07FB167 +:102930003000EFD05FF2E30E05F2CDB72285EFF065 +:102940005FB03000EFD03FF139D1C9BF2285EFF041 +:102950005FAF2E86AA852285EFE06F8230002A8D38 +:10296000AE8DEFD05FEF41F5EA856E862285EFD020 +:102970003FF731FD9547232A7403A306F40223078A +:10298000040269BF8347F402A18BEDF7A307940209 +:10299000232A5403230734032285EFE0CFBDE30D40 +:1029A00095F12285EFF0FFA93000EFD0DFEAE305D3 +:1029B00005F035BF8349F40285472307F40293F7F6 +:1029C000590091E7B7C500009385C530D9B9228574 +:1029D000EFE0AFF895470149B704F37FE309F5CE7F +:1029E0002285EFF01FA62E8693F91900AA8522856D +:1029F000EFD0FFF8639A09001C585CD88347F402B3 +:102A000093E70701A307F4022E86AA852285EFD05B +:102A10001FF715B985472307F402EDB1EFD23F91B7 +:102A20002A842E8A99C1EFE0FFB185472307F4027B +:102A30000149B709F37F854A254BA14B130CF003DD +:102A4000930CB004154D2285EFE02FF16309550575 +:102A50002285EFE08FF0630465054A85CE85EFD0CF +:102A6000DFC615ED22858344D402EFF0BFB62A8974 +:102A7000AE89EFD09FC561F9E38774FDE38584FDDE +:102A8000E38394FD8347D402E38FA7FBB7C500001F +:102A9000938585312285EFE07F982A89AE89630589 +:102AA0000A002285EFD07FE24A85CE856FD0BF8BAA +:102AB000EFD27F8A2A84EFE04FEAA147631CF5003A +:102AC0008345F402228593C5F5FF8589EFF01FF554 +:102AD0006FD0BF8A2285EFF0FFAF2E86AA852285B0 +:102AE000EFD0FFE923070402E5B7EFD2DF8301113E +:102AF0002A8CEFE08FE699476314F5040549230714 +:102B00002C036285EFF0FF932A84AE84EFD0FFBBE5 +:102B10001DE16285EFE06FE49D47630CF500B7C5EA +:102B200000009385852A6285EFE05F8F2A84AE845A +:102B300019A023072C032285A68505616FD07F820B +:102B40006285EFE08FE16285EFD01FB983278C06A5 +:102B500091CB03270C0063F7E700B7C5000093850E +:102B6000452BD1B78347DC02054423078C0221475C +:102B7000638CE7066367F70209476385E7266368A6 +:102B8000F700F5C3B7C500009385C52B69BF0D4796 +:102B90006387E7041147E397E7FE6285EFE09FA8AC +:102BA00071B71307F0046380E726636EF70013071D +:102BB000E003638DE7141307E004E395E7FC0144A9 +:102BC000B704F37F8DBF130700056382E724130763 +:102BD00010050144E398E7FAB704F67FA9BF032480 +:102BE0008C048324CC0481BF034AFC02137A1A00AC +:102BF00063100A08914670088145628502CEEFE0B5 +:102C00003F882A84AE842285A685EFD01FAC05F5C7 +:102C100085472307FC02A54B914C854A130D1008EC +:102C2000930DF0086285EFE04FD3630E750783477D +:102C3000DC0209476392E70481490149631E0A00E7 +:102C400083258C0083278C030326CC036285BE95E5 +:102C5000EFE0DF96AA892E8923075C036285EFE007 +:102C60008F916305A503B7C500009385C52965BD90 +:102C70000144B704F37F41BFE39797FF81490149BE +:102C8000E31C0AFC6285EFE0FF99E9B723075C03C8 +:102C90006285EFF00FFB2A8B63010A026285EFE089 +:102CA000CFCB631D75056285EFE02FCBA547E31CF5 +:102CB000F5FA85472307FC02BDBD2EC6EFD0FFA065 +:102CC0003246631805144E85CA85EFD01FA005E56E +:102CD0003246DA856285EFD09FCAAA872E88CE86D3 +:102CE0004A87A28526866285EFE01F81AA892E8900 +:102CF000EFD0BF9D45D54E84CA8435BD6285EFE0D7 +:102D0000CFC5E312B5F723075C0329BF62850349EA +:102D1000FC02EFE04F8699476305F500A3072C03FB +:102D200099B783294C0323078C02854A01449D44AB +:102D3000094B054A930BF0086285EFE00FC2630D63 +:102D4000550315C46285EFE04FC1E31965FD230704 +:102D50004C036285EFE02F82630095026285EFE00D +:102D6000CFBFE31D75FB23074C030544F1B7628514 +:102D7000EFE0AFBEE31895FC6285EFE00FBE9D4724 +:102D8000E31EF5F8054A23074C036285EFD0BFFE2A +:102D9000A147E315F5F88347FC0223070C028145A0 +:102DA00093E71700A307FC026285EFF03FC72A8470 +:102DB000AE84EFD09F9101C5A3072C03ADBB0326C2 +:102DC0004C0383258C00FD19A3072C0333063641E1 +:102DD000CE956285EFE08FFE2A8423074C03B7046B +:102DE000F77F91BB0324CC0383278C039354840087 +:102DF00013970401A20762044183A183B704F87FFB +:102E00005D8CD98C0DBB0144B704F47F2DB3054410 +:102E1000E1B35A84B28405B3EFD2EFD041112A8CCA +:102E2000EFE0AFB3930780066309F5048347DC0244 +:102E3000938777F993F7670FA9C36285EFF0FFCA0D +:102E40002A89AE89EFD07F882DCD4A85CE85EFD0F7 +:102E5000DF8725E16285EFE04FB08345DC0205475F +:102E60009387A5F993F7F70F6365F7042307EC023F +:102E7000814701474A86CE8605A80344DC029307B2 +:102E80002007630DF402930710076314F400130482 +:102E9000B00685472307FC026285BD3FAE872A87BF +:102EA0000146B706F37FA2856285EFE09FBA2A89C3 +:102EB000AE894A85CE8541016FD0AFCA1304C006E2 +:102EC000C9BF4A85CE85EFD0EFFEA1476313F50455 +:102ED0008347FC02858BD9EF370400017D14B3775B +:102EE0008900A20983248C001359890133E929013F +:102EF00003264C0583290C05BE9433748900228770 +:102F0000A686CE856285EFD0FFA215CD2A89B709A6 +:102F1000F17FC16A370B0001CA844E841D4AFD1A35 +:102F20007D1BB7CB00006285EFE02FA399476306B6 +:102F3000F5046285EFE06FA293074006630FF50288 +:102F40002689A28919B7638B090093854900628598 +:102F5000EFD01F92AA893706F07F55B7B7C500009A +:102F6000A6862286938545336285EFE02FCB2A899A +:102F7000AE8945B70149814969BF0347DC02930720 +:102F800040066314F70285472307FC026285EFF0D1 +:102F9000DFB5AE872A872686A2869305400662851E +:102FA000EFE03FABAA842E84BDBF8349FC02032916 +:102FB0004C03854C93E71900A307FC0285472307C0 +:102FC000FC02130DF0088147854D62853EC6EFE097 +:102FD000CF98B247630B9501A1C76285EFF06FC62A +:102FE0006285EFE08F97631345056285EFE0EF960A +:102FF00063074505A3073C039385CB296285EFE072 +:10300000EFC12A89AE894A85CE85EFD00FECE31E49 +:1030100005E24A87CE872686A2869305500641B7E9 +:103020006285EFE08F93E31A45FBC1B76285EFE05D +:10303000CF92E311A5FD2307BC03854779B703268B +:10304000CC038547A3073C033305C90003264C0383 +:1030500033796901B709F87F098E93568600B3F674 +:10306000560162062307FC0233692601B3E9D90041 +:1030700059BFEFD2AFAC41112A84EFF0FFD92A89B2 +:10308000AE849309E006054A854A4A85A685EFD0B5 +:10309000CFE339E52285EFE04F8C630A35018347A2 +:1030A000D402938717F993F7F70F636BFA0223079C +:1030B00054032285034BD402EFF01FD62AC62EC438 +:1030C000EFD0AFE0A247324711E94A86A686DA85FB +:1030D0002285EFE01F982A89AE8445BF3A89BE84D5 +:1030E0004A85A68541016FD0AFA8EFD22FA5411127 +:1030F0002A89EFF01FF8AA842E84930A1007130A76 +:103100002007054B2685A285EFD02FDC11E94A85E3 +:10311000EFE0AF848349D902630955016387490110 +:103120002685A28541016FD0AFA4230769034A8594 +:10313000EFF03FF42AC62EC4EFD02FD9A247324772 +:1031400011E92686A286CE854A85EFE09F90AA8463 +:103150002E844DBFBA843E84E1B7EFD24F9D41111A +:103160002A84EFF09FF82A89AE84130A4007930A55 +:10317000300793095007054B4A85A685EFD0EFD459 +:1031800005E12285EFD07FFD630145032285EFD065 +:10319000DFFC630C55012285EFD03FFC630735014E +:1031A0004A85A68541016FD00F9C230764032285C1 +:1031B000834BD402EFF07FF32AC62EC4EFD0EFD0BA +:1031C000A247324711E94A86A686DE852285EFE0CE +:1031D0005F882A89AE844DB73A89BE84D1B7EFD2D1 +:1031E0000F9541112A84EFF05FF72A89AE84130A04 +:1031F0006007930A7007130B800793099007854BAC +:103200004A85A685EFD06FCC0DE52285EFD0FFF47F +:10321000630645032285EFD05FF4630155032285E1 +:10322000EFD0BFF3630C65012285EFD01FF3630776 +:1032300035014A85A68541016FD0EF9223077403BB +:103240002285034CD402EFF05FF12AC62EC4EFD0E2 +:10325000CFC7A247324711E94A86A686E285228572 +:10326000EFE02FFF2A89AE8461BF3A89BE84D1B7CF +:10327000EFD2CF8C41112A84EFF07FF62A89AE84F9 +:10328000130AA0079309B007854A4A85A685EFD09F +:10329000CFC319E92285EFD05FEC630C450122858D +:1032A000EFD0BFEB630735014A85A68541016FD09A +:1032B0002F8C230754032285034BD402EFF03FF2F7 +:1032C0002AC62EC4EFD06FC0A247324711E94A8602 +:1032D000A686DA852285EFE0CFF72A89AE8475B716 +:1032E0003A89BE84D1B7EFD26F8541112A89EFF0B8 +:1032F0003FF8AA842E849309C007054A2685A28533 +:10330000EFD0AFBC11E54A85EFD03FE5630735014B +:103310002685A28541016FD0AF85230749034A85E1 +:10332000834AD902EFF0DFF42AC62EC4EFD0EFB9FA +:10333000A247324711E92686A286D6854A85EFE064 +:103340004FF1AA842E845DBFBA843E84D1B7EFC208 +:10335000FFFE41112A89EFF01FF9AA842E849309F8 +:10336000D007054A2685A285EFD02FB611E54A85FC +:10337000EFD0BFDE630735012685A28541016FC00E +:103380003FFF230749034A85834AD902EFF0BFF57F +:103390002AC62EC4EFD06FB3A247324711E9268662 +:1033A000A286D6854A85EFE0CFEAAA842E845DBF47 +:1033B000BA843E84D1B7EFC27FF8BE89B7776E6F0B +:1033C0000111938717273ECAB7777475938707371C +:1033D0003ECCE17793C7C7D7FC869307E007230F5E +:1033E000F1001C10BE9583CA05F73284B28536867B +:1033F0002A8AB6843A89EFD08FD8AE864A87CE879C +:103400002A86D6855285EFE0CFE483278A052AC431 +:103410001375C4FF21052EC621462C003E95EF30C2 +:1034200080302285A68505616FC09FF45C4111053F +:10343000F19B3E958280EFC21FF22A84EFF01FFFBE +:1034400000C16FC09FF3B7670020B76600201387E5 +:1034500007D7138606D823A807D6232207002324DC +:1034600007002326070010CF50CF232007021305A3 +:103470000706938707D7938606D8130800022322EE +:103480000702BE85014623A2D50805069105E31C67 +:1034900006FF110793870708E313A7FE8280417791 +:1034A000698FAA871305000219E3C2074145370750 +:1034B00000FF7D8F19E3A2076115370700F07D8FAC +:1034C00019E392077115370700C07D8F19E38A074A +:1034D000791563C307007D158280EFC2DFE793078C +:1034E000F00741112A8463EAA700135425400145DF +:1034F00088C100C241016FC05FE832C62EC4EFF040 +:103500001FFA9307A5FF3354F440134404026515D2 +:103510003246A245F1BFEFC21FE42A84484141115F +:1035200070002C007199EFF05FFBA246B24537673F +:10353000002093975600AE9793870702130707D78B +:103540008A07BA97C84337660020130606D808C40E +:1035500050C440C51053C0C385473395D700A1065A +:10356000498E8A0610D336975443B397B700D58F48 +:103570005CC341016FC07FE0EFC25FDC37640020B5 +:10358000832604D78D47638AF606130704D781473D +:10359000130904D763CDD704E11513773500F199EA +:1035A0009307003231E337070040938645FF5117F8 +:1035B00093071032636AD70293E515009309C5FF9C +:1035C0000CC1AA844E85EFF01FF54E85EFF0BFE6E3 +:1035D00089475CC1832704D7138717008A07CA97D6 +:1035E000C4C32328E4D681473E856FC07FD8110726 +:1035F00010436307C500850771BF93072032EDB7FD +:1036000093073032D5B7EFC21FD541112AC62EC459 +:10361000EFF07FE3A2453245EFF01FF641016FC0A6 +:10362000DFD5EFC2BFD15C4D184D0449A9495CC339 +:1036300098C3232805002306050003C98405630AEF +:103640003901CA852685EF000062238C34056FC0DE +:103650003FD24C2983C714022A84E38AB7FE268509 +:103660001925230A2401E5B7EFC2FFCE2A84EFF023 +:103670005FFB9145130544007D286FC01FD09C411E +:10368000938787FB138787046314B7002E8739A0BD +:103690000346150283C617026371D602F447130668 +:1036A0008504F0C738C574C590C2834705026CCD48 +:1036B00093E727002300F5028280BC47D1B71C4165 +:1036C0006309F500138787FB294509C703C597FDE3 +:1036D0008280294582807C4538455CC398C38347F6 +:1036E0000502232E0504F59B2300F5028280EFC21C +:1036F0009FC6784534456C4DD8C214C3EFF03FF8EF +:103700006FC0BFC7EFC23FC5834705022A84898BBC +:1037100081C72CD1EFF03FFC83470402858B81C722 +:103720002285EF00A07283470402918B99E32285E2 +:1037300015226FC09FC4EFC21FC21C41AA842E89EC +:103740008043138587FB130484FB930785046394EC +:10375000F4006FC09FC2CA85EFF0DFFA3C442285B7 +:10376000138487FBDDB793575500D10737670020D7 +:10377000130787B18A07BA971346F5FF8546B396B4 +:10378000C6009043D18E94C3834747056374F50008 +:10379000230AA7048280B7670020138787B1834775 +:1037A00047058E07BA978843130585FB82803767E4 +:1037B0000020930787B1A946238AD704130787B14E +:1037C000938607059CC3DCC3A107E39DF6FE23286F +:1037D00007048280EFC29FB62A8903451502B767A6 +:1037E0000020938487B193193500CE9498401384B8 +:1037F00087B16394E400EFF01FF7B30734019443FB +:1038000013078904D8C22324D9042326990498C312 +:103810006FC01FB6EFC29FB22A8903451502B76772 +:103820000020938487B193193500CE949840138477 +:1038300087B16394E400EFF01FF3B3073401D8437A +:1038400093068904D4C3232499042326E90414C3CA +:103850006FC01FB2EFC23FB083A741850347150277 +:1038600083C717026316F700EFF0DFFA6FC0FFB0EF +:10387000EFF05FF6E5BFEFC21FAE2A84952A25E977 +:103880007C44384403461402B76400205CC398C3E8 +:10389000138784B193173600BA979843938484B101 +:1038A0006311F70293575600D1078A07A6978546FA +:1038B0001347F6FF3397E60094431347F7FF758FDE +:1038C00098C383C744056394C702B76700200144C7 +:1038D000938787B631A0130404021374F40F910781 +:1038E000884375D9EF00700B2295238AA4046FC01A +:1038F000DFA801A003A7C1858547631BF70083C725 +:1039000081859306900F63E5F6008507238CF1848B +:10391000828003A7C18585476314F704EFC2BFA364 +:10392000EF00807983C781852A8489E7EF00807959 +:103930006FC0BFA4FD1793F7F70F238CF184FDF739 +:1039400083C74186E5F7EFF01FE523A0A18683A793 +:1039500041856314F5002285D1BFEF002078E5BFD3 +:103960008280EFC25F9F83A7C18585441305501FE6 +:10397000638D9700EFF03FE223A0A18623AAA184E4 +:1039800023AE9184EF00407601456FC01F9F03A5D1 +:10399000C1857D1513351500828003A7C185854734 +:1039A000631DF70283C7818503C74186D98F95E7D9 +:1039B000EFC27F9AEF0040702A84EFF0DFDD23A092 +:1039C000A18683A741856317F5002285EF00806FEC +:1039D0006FC0BF9AEF00C06FCDBF828003C5418624 +:1039E0003335A000828003C581853335A0008280F5 +:1039F000B77700209387879F1D8D13351500828030 +:103A000083A741853385A740133515008280EFC217 +:103A10009F9403A8418483A7018437460000B7C55B +:103A20000000377500208148254781461306268F00 +:103A3000938585501305859F2D206FC01F94EFC27D +:103A40009F91EF00606CEFF09FD6377500208D6579 +:103A5000130505A7EFF03FBB19E1EFF05FFB6FC067 +:103A6000DF91EFC2BF8D2A842E8B3289B68ABA8449 +:103A7000BE89428AEFF03FF769E91305C0445DC88B +:103A8000630A090A6388090A9307F0071305407758 +:103A900063F2470BA5476391F40A2285EFF05FF5C7 +:103AA00051CD930704043CC07CC0930784043CC4FC +:103AB0007CC4930704053CC87CC8A947230CF404C4 +:103AC00083A601811307C40223200406232E0404C5 +:103AD0002322040623240406D8C254D43746000007 +:103AE0009386018123A8E18014D85287CE861306DD +:103AF000E6C2D6854A85EF00A0643D46DA8508C057 +:103B0000A3009402232C2401232E540123223403E6 +:103B10002324440313058400EF40E015712BAA848D +:103B2000230004022285EFF0FFCE2685612BEFF003 +:103B30001FE601E96FC0DF83E3F597F61305F07622 +:103B4000D5BFEFF09FE50145F5B713050019DDB7C7 +:103B5000EFC2CFFE2A84EFF01FE99307001911EDA1 +:103B600019E003A441852285EFF09FE911E9228540 +:103B7000EFF01FE89307D07611C93E856FC04FFF65 +:103B8000EFF0DFE59307406A7DD1C5BF35233C48A0 +:103B900013090405AA89631DF9068347040281E716 +:103BA0002285EFF05FCD83470402858B99C3228580 +:103BB000712C83470402898B81C72285EFF0BFB146 +:103BC0001C5858544E855CC398C39307C4025CD4F8 +:103BD0001CD8930704043CC07CC0930784043CC4F5 +:103BE0007CC4A947230CF404A1472300F402232832 +:103BF0002405232A240523200406232E040423223B +:103C00000406232404067D29EFF03FD98147B5B788 +:103C10008443138587FEA11493078501E30FF9F60A +:103C2000EFF09FA49C4C2685938487FEF5B7EFC2E6 +:103C30008FF20145EFF0DFF16FC02FF4EFC2AFF16B +:103C4000EFF07FDA19ED8D29AA8403A54185EFF005 +:103C50009FC203A54185EFF0FFBB2685A521EFF0AC +:103C6000DFD36FC08FF1EFC26FED2A84AE89EFF022 +:103C70009FD75DE51305C04405C0A1471305F07645 +:103C800063EC3701152983471402AA8A6398370128 +:103C90001529EFF09FD001456FC08FED2448130A1E +:103CA0000405631F9A004E898347040213F7270017 +:103CB00021C3A30024032285EFF07FA35685C9BF4B +:103CC000A1142949938784016317FA00E37D39FD24 +:103CD000230C3405D1BF13854400EFF05F9EAA8703 +:103CE0006373A900CA87844C13F9F70FA114D9BFD5 +:103CF00013F7170001C7A3002403C9B7E1F3228516 +:103D0000EFF07FB72285A3002403EFF07FCF09C532 +:103D10002285EFF03FAC5DB72285EFF0BFAF79BFF2 +:103D20001305001995BFEFC26FE12A84AE84EFF04E +:103D30009FCB9307001901EDEFF05FCA9307406A2C +:103D400019E5B367940099E7EFF05FEF81473E858F +:103D50006FC00FE2FD576316F40093075006E38827 +:103D600084FE992EAA8903A54185A285268611285D +:103D700003A54185EFF03FB04E85A926EFF0FFC1C6 +:103D8000F1B7EFC24FDD41112A842EC632C42D2671 +:103D900083A78181B2452246938707FC0CDC50DC67 +:103DA0008146014713838181138E070463116E06D8 +:103DB000B388D540B3BE15013308E6403308D84177 +:103DC000232C1403232E040363016E02B385B64033 +:103DD000B3B6B600118F158F945FD05FB695B3B6AA +:103DE000D500329736978CDFD8DFF843930604046A +:103DF000F4C32320C40578C014C3E9248347040214 +:103E000093E717002300F40241016FC00FD783A886 +:103E1000870383AEC703B69833B8D800BA9E7698A6 +:103E2000E36806F96314C800E3E415F9639A150121 +:103E300063180601034F140283CE1702E36ADFF70B +:103E4000BC43C6864287938707FCB9BFEFC2AFD099 +:103E50002A849D243C40130704046388E7041387E5 +:103E600007FC21C7138781816381E704145C8328E1 +:103E7000C403F9553383D54003A6C7FF33B86500A3 +:103E800093C5F8FFB385054103A787FF63EAC50221 +:103E90006314B6006366E302BA9633B7E60046964B +:103EA000329723ACD7FE23AEE7FE7840D8C31CC3BD +:103EB000112C83470402F99B2300F4026FC0EFCB5F +:103EC0007956FD5623ACC7FE23AED7FEF9BFEFC22D +:103ED0008FC841112A842EC6C52283A7818683A656 +:103EE000C186B24533868700B337F600AE96B697E3 +:103EF00023A6F18683A7818123A4C186938481812F +:103F000063969700C12241016FC02FC703A7C7FF67 +:103F10002A8983A687FF138507FC63EFE5026314F4 +:103F2000B700636BD40280438146014723ACD7FEC0 +:103F300023AEE7FE130404FC93070504638897028D +:103F40001C5D585DD98F9DE38945EFF0AFFB3C4088 +:103F50002285138407FCCDB733848640B3B6860030 +:103F60000D8F158F23AC87FE23AEE7FE4A8559BF20 +:103F7000EFC26FBEEFF0BFA109C505458145EFF067 +:103F80001FF56FC08FBF21651305058073150530C0 +:103F9000828073100530828037F700E01C4386076B +:103FA00085831CC3828037F700E01C43B70600807E +:103FB000D58F1CC38280EFC20FBAEFF0DFFE6FC057 +:103FC000CFBBB7F700E023A0070023A2070081467C +:103FD00094C70147D8C71306F5FF90CB8146D4CBD1 +:103FE0003D4798C382801375F50FB7E700E023863D +:103FF000A7408280B7E700E041572387E740056785 +:1040000023A0E710116723A0E7108280197182FEB8 +:1040100086FC8AFA8EF892F696F49AF29EF0A2EE58 +:10402000A6ECAAEAAEE8B2E6B6E4BAE2BEE042FE28 +:1040300046FC4AFA4EF852F656F45AF25EF062EE38 +:1040400066EC6AEA6EE872E676E47AE27EE08A82FC +:1040500003A1018216C0EFF09F9319C9EFF09F8969 +:10406000B7F700E023A20700EFF09FF0EFF07F8AA0 +:1040700002417670E6705671C6713672A67216737A +:1040800086737664E6645665C6653666A666166708 +:1040900086677278E2785279C279327AA27A127B94 +:1040A000827B726CE26C526DC26D326EA26E126FC8 +:1040B000826F096173002030EFC2EFA9EFF0BFEC0F +:1040C0006FC0AFABEFC22FA9EFF0BFEC6FC0EFAA8C +:1040D000EFC26FA8EFF03FED6FC02FAAEFC2AFA7FE +:1040E000EFF07FED6FC06FA9EFC2EFA6EFC04F9169 +:1040F000EFC26FA62A841305000FEFF0DFEE2285D2 +:10410000EFF03FEC6FC06FA7EFC2EFA413870182FF +:104110001C438145F117F19B1CC3B707002003A680 +:10412000871E83A6C180B707002003A5071E492369 +:1041300023A8A184EFF0DFFBEFF0DFEB6FC0EFA36C +:104140003697719BB7E8EAAC2A8E130847F8130537 +:1041500007F885462943938808D0930E0002B3C719 +:104160006602110833EF660292078506B3E7E7019E +:10417000B3E71701232EF8FEE393D6FF8E8723269D +:10418000F7F8A167938707882324B7FA2324C7F891 +:104190002322F7F82320C7F982804177698FAA8705 +:1041A000014519E3C2074145370700FF7D8F19E339 +:1041B000A2072105370700F07D8F19E3920711054B +:1041C000370700C07D8F19E38A07090563C607001A +:1041D00099C3050582800905828001A001A001A084 +:1041E00001A001A001A001A001A001A001A001A0C7 +:1041F00001A001A001A001A001A001A001A001A0B7 +:1042000001A001A001A001A001A001A001A001A0A6 +:1042100001A001A001A001A001A001A001A001A096 +:1042200001A001A001A001A001A001A001A001A086 +:1042300001A001A001A001A001A001A001A001A076 +:1042400001A001A001A001A001A001A001A001A066 +:1042500001A001A001A001A001A001A001A001A056 +:1042600001A001A001A001A001A001A001A001A046 +:1042700001A001A001A001A001A001A001A001A036 +:1042800001A001A001A001A001A001A001A001A026 +:1042900001A001A001A001A097C1FF1F938181741B +:1042A00017C10020130101D6178500001305057FF3 +:1042B00097C5FF1F938505D51386018563FAC50051 +:1042C0008322050023A0550011059105E3EAC5FEF0 +:1042D00013850185976500209385059A6377B5005E +:1042E000232005001105E36DB5FEFD42739002BC6D +:1042F000FD4273904280B78200009382028073A0D7 +:10430000023097C2FFFF938262D393E23200739030 +:104310005230EFC08FAA97C2FFFF9382821F739023 +:104320001234730020309C4513F7070113F8F7008F +:1043300001C7D8413368E8008E2113F7F50F39C360 +:1043400018418146854E3D4F930F800293028004B1 +:10435000214E3396DE00B3F8C5006311160393981F +:10436000260033131F011343F3FF3377E300B31821 +:10437000180133E7E800639FF70550C98506E39A03 +:10438000C6FD18C11307F00F6375B70454412146E9 +:10439000854E3D4F930F800293028004414EB398A7 +:1043A000CE0033F715016392E802131726000117B8 +:1043B0003313EF001343F3FFB376D3003317E80052 +:1043C000D98E639DF701232A15010506E319C6FD61 +:1043D00054C18280E39457FA10C94DB7E39757FE52 +:1043E00023281501DDB7371702405C439146B18B96 +:1043F0006385D700A1466382D706B7177A009387F3 +:1044000007201CC1371602405C4237070020130703 +:1044100007009183BD8BBA9794231C41B3D7D70073 +:104420005CC15442A1829D8ABA969422B3D6D70029 +:1044300014C55442AD829D8A36971823B3D7E7003E +:104440005CC558423983937637001387418236978B +:104450001823B3D7E7021CC982805C4354434167E9 +:10446000C983F98E37F7FF1F0327C770BD8B8907F4 +:104470001316170163480600454601476392C702B9 +:10448000C94739A809476389E7023D476388E702BE +:1044900041476388E702454601476393C700C14728 +:1044A00085E6B746024083A60680C18A8DC6B71648 +:1044B0007A009386062025A00147D9B70547B5475E +:1044C000C5B70147BD47E9BFB7160240D4421396AE +:1044D000E600E35E06FCB7163D0093860690B387C0 +:1044E000D7021CC105D31C41858321BF99C537174D +:1044F00002401C4F5D8D08CF8280B7170240984F55 +:104500001345F5FF798D88CF8280EFB2DFE416295D +:10451000F577FD17F58FF621DA257971D58F1EA96C +:104520005625FD779387379FF58FD6212A842EC68F +:10453000D58F9625D58FB625D58F5EA55E29C20766 +:10454000C18393F7F7CFD98F5EA96808EFF0BFE971 +:10455000B747014093870780B245631AF404A25716 +:1045600056246547B387E702C206C186984163D2E5 +:104570000604060752244206B3D7E7021307400693 +:104580004186B3D6E702B3F7E70292066355060207 +:104590008E0793872703B3D7E70213F77700B36734 +:1045A000D700C207C1831EA445616FB01FDD9257BB +:1045B00045BF0A07C1B7920793872703B3D7E7021E +:1045C000BD8BD58FF9BF91C55E250967D98F5EA5D3 +:1045D00082805A25F977FD17F98FD5BF93F5F51F1E +:1045E0004EA182800A216D8D3335A0008280EFB20A +:1045F0009FD62A841165011185451105EFF01FEF43 +:10460000930700207C82371501408D473EC44C0043 +:10461000E147130505803EC6EFF0FFD022C83744BE +:104620000140B70708000C08130504803ECC02CAFD +:10463000231E0100EFF07FED854513050480EFF0A8 +:104640009FF805616FB07FD3EFB25FCFB7440140F1 +:10465000AE893289014493840480634524014A85EC +:104660006FB01FD1930500042685EFF0BFF77DD909 +:10467000B38789008385070026850504C205C181AB +:10468000EFF0DFF5D9BF138781821C43B7A6002066 +:10469000938646C73E95636BD500B7B600209386D8 +:1046A000060063E5A60008C33E858280FD57EDBF86 +:1046B000B687B2882A832E88639D061463F9C50ADB +:1046C0004167636EE61AB70700016363F6349356D9 +:1046D0008601E147178700001307C7EB36970347AA +:1046E0000700BA97130700021D8F19CB3398E50016 +:1046F000B357F500B318E60033E807013313E500BC +:1047000013D608013355C80293960801C182935706 +:1047100003013377C802B385A60242073368F70066 +:10472000637AB80046989307F5FF636418016367DE +:10473000B8303E853308B8403357C802420313539C +:1047400003013378C802B386E60242083368680082 +:10475000637BD80046989307F7FF636518017917C4 +:104760006363D8003E874205598D8145828001E60A +:104770000547B358C702416763EAE80EB70700016F +:1047800063ECF82893D68801E147178700001307E8 +:1047900067E0369783460700BE9693070002958F21 +:1047A000E5EB939E08013387154113DF080193DE83 +:1047B0000E018545935703013355E7033377E7032C +:1047C000B306D5034207D98F63FAD700C6971307FC +:1047D000F5FF63E4170163E6D7263A85958F33D753 +:1047E000E703420313530301B3F7E703B30ED70301 +:1047F000C207B3E7670063FBD701C6979306F7FFCD +:1048000063E51701791763E3D70136874205598DB0 +:10481000828063E2D504C16763E2F604B707000152 +:1048200063E4F61E13D786016148978700009387DB +:1048300067D6BA9703C70700130E00024297330EDC +:10484000EE40631A0E0C63EDB61C3335C5001345FC +:104850001500814582808145014582809307F00FD4 +:1048600063F3D71C13D786002148C1B71307F00F95 +:10487000C686E37C17F193D68800A14739B71307A2 +:10488000F00FB286E378C7E493568600A14799B546 +:10489000B398F80033D6D50013DF0801335EE60382 +:1048A0003397F500B356D500558F939E080193DEDC +:1048B0000E013313F50093550701B376E603B38772 +:1048C000CE03C206CD8E63FBF600C6961306FEFF2E +:1048D00063E4161763F2F616791EC6969D8E33D6DC +:1048E000E60393170701C183B3F6E6033385CE02CF +:1048F000139706015D8F637BA70046979307F6FF2A +:10490000636817136376A7127916469793150E01FD +:10491000098FD18D45B5B357E600B396C601DD8E3C +:1049200033D3E50013DF0601B357E303939E06017B +:1049300093DE0E013398C5013357E5003368070154 +:10494000935808013316C6013373E303B385FE029F +:104950004203B368130163FBB800B6981387F7FFEF +:1049600063EAD80C63F8B80CF917B698B388B84066 +:1049700033D7E803420813580801B3F8E803338338 +:10498000EE02C208B3E5080163FB6500B6951308A3 +:10499000F7FF63EDD50863FB65087917B695C20785 +:1049A000416FD98F1307FFFFB3F6E70093D80701D4 +:1049B000718F4182B38EE602B3856540B386C6022D +:1049C00013D80E013387E802BA96C2963386C8021E +:1049D00063F3E6007A9693D80601469663E2C50231 +:1049E0006385C5003E858145828041677D17F98ECC +:1049F000C206B3FEEE003315C501F696E374D5FE8C +:104A00001385F7FF8145828013D70601414831BDE8 +:104A100093560601C1477DB993D60801C147B5B386 +:104A20008145054582803687014801B5428785BFAB +:104A30003E86E9BDBA871DBF328E4DB579154698C1 +:104A4000D5B97915C69759BB3708100001117D18E3 +:104A50003377B80026CA3378D80093D4450113D3EE +:104A60004601131E37004EC61357D5010E08935743 +:104A7000D60193F4F47F1373F37F06CE22CC4AC899 +:104A800093D9F50193DEF6013367C701131F350093 +:104A900033E80701931F3600338E64406380D919D1 +:104AA0006356C0136304031CB70680009307F07FAE +:104AB0003368D800638FF4369307800363C0C7352B +:104AC000FD4763CDC747130500023305C541B3D782 +:104AD000CF01B316A8003399AF00DD8E3339200122 +:104AE000B357C80133E926011D8F33092F41B3376E +:104AF0002F013306F7409317860063D40724370746 +:104B000080007D173374E600630C042C2285EF10BF +:104B1000D031130785FF93070002998FB357F9002F +:104B20003316E400D18F3319E9006341972A330526 +:104B30009740130615007D47634DC73813070002E1 +:104B4000118FB356C9003319E9003397E700558F29 +:104B5000333920013369270133D6C7008144937765 +:104B6000790081CF1377F90091476308F7001307A5 +:104B70004900333927014A963A899317860063D64C +:104B8000071C138514009307F07FCE856304F5207E +:104B9000B70780FFFD17F18F9398D701135939009C +:104BA000A607B3E82801B1831375F57F9396C70074 +:104BB0005205F2406244B182FE05C98ECD8ED244C8 +:104BC0004249B2494685B68505618280631E0E0A58 +:104BD000138314001373E37F63170322B367E701A2 +:104BE000B368F801639D041A63870740638608442D +:104BF0003309FF41B307074133362F013386C740DE +:104C00009317860063D6074C3389EF41B307E8401A +:104C100033B62F013386C740F68991B76350C00F72 +:104C20006300030CB70680009307F07F3368D80059 +:104C3000638AF43A9307800363CBC713FD4763DFAE +:104C4000C73513090EFE93070002B3562801630A05 +:104C5000FE00130900043309C94133192801B3EFD9 +:104C60002F013339F0013369D90031A2B367F8015C +:104C7000638A071C9307FEFF638C07389306F07F57 +:104C80006309DE1A3E8E0DBDB30593406391042285 +:104C9000B367E701638707329387F5FF63810744B2 +:104CA0009306F07F638CD520BE859307800363CC89 +:104CB000B72AFD4763CFB73C930700028D8F3319A6 +:104CC000F700B356BF00B317FF003369D900B337FD +:104CD000F0003357B7003369F9003308E84041ACBE +:104CE000B367F801638007349307FEFF638A0720E8 +:104CF0009306F07F6308DE2E3E8E2DBF631E0E14DA +:104D00009386140093F7E67F63910734B367E70156 +:104D10006395042C6380073EB367F801638E073008 +:104D20003309FF01B3070701333FE9013386E70188 +:104D30009317860063D70700B70780FFFD177D8EA6 +:104D4000854493777900E39F07E09317D601935842 +:104D50003900B3E8F800935736001307F07F638DEE +:104D6000E404B207B18313F5F47FCE8581B53369CE +:104D7000F801333920017A99B337E9013386E70026 +:104D800093178600E3DF07FA85049307F07F6396A5 +:104D9000F418CE851305F07F8147814801BDC1EB32 +:104DA0006384083A931636009317D8018D82B3E8CE +:104DB000D700F68993573800B3E7F800F9DB81454F +:104DC0001305F07FB70708008148CDB3370680FF91 +:104DD0007D167D8E93777900998CE39507D8B5B7CA +:104DE0004A85EF10900413078501FD47E3D5E7D20C +:104DF000130685FFB317C900014905BB3369F801E4 +:104E000033392001DDB13309FF4133060741333423 +:104E10002F01330486409317840063CD0724B368C1 +:104E20008900E39308CE8147814981441DBFE398FF +:104E300008F80E059317D7010D81B3E8A700935723 +:104E400037009DBF0E059317D7010D81B3E8A7006A +:104E5000F2849357370011B73305934063820412ED +:104E6000B70680009307F07F558F630DF32E9307ED +:104E7000800363CBA720FD4763C3A72A93070002E3 +:104E8000898F3319F700B356AF00B317FF003369AA +:104E9000D900B337F0003357A7003369F9003A98C7 +:104EA0007E99B337F901338607019A84D1BDB706DD +:104EB00080009307F07F558FE319F3DE93173600D8 +:104EC0008D839318D801B3E81701F68993573800FA +:104ED000E5B5130715FE9306000233D7E700630A12 +:104EE000D600930600043386C6403396C700336964 +:104EF000C900333920013369E9000146814491B585 +:104F00003309FF01B30707013336E9013E969317D2 +:104F100086008544E3D707E28944B70780FFFD1781 +:104F2000F18F1357190013791900336927019398EA +:104F3000F70133E9280113D6170015B113090EFE46 +:104F400093070002B3562801630AFE001309000408 +:104F50003309C94133192801B3EF2F013339F00167 +:104F60003369D90059B63369E701333920013389F0 +:104F70002F41B3B72F013306F8409A84F689A5BEB6 +:104F8000B367E701638207189307F5FF6384071C83 +:104F90009306F07F6304D5123E85D1BD93070002CE +:104FA000B387C741B316F8003399FF0033D6CF015A +:104FB000D18E33392001B357C80133E926013E971A +:104FC0005DBB931736008D839318D801B3E81701A2 +:104FD000AE8493573800F68949B3EDC33369F801BD +:104FE000E31F09DC0E059317D7010D81B368F500A7 +:104FF00093573700D1B36381080E93163600931789 +:10500000D8018D82B3E8D700F6899357380091BB59 +:105010003309FF41B3070741333F2F013386E7418F +:105020008544D1BC0E059317D7010D81B368F500F7 +:10503000F2849357370015B30E059317D7010D81EE +:10504000B3E8A7009357370029BB9307F07FE382AB +:10505000F6D43309FF013336E901B3070701B297EC +:105060009398F7011359190033E9280113D6170053 +:10507000B684C1B93389EF413307E84033B62F0115 +:105080003304C740F68949B43369E7013339200155 +:1050900001BD938705FE93060002B357F700638AAC +:1050A000D50093060004B385B6403317B700336FBD +:1050B000EF003339E0013369F90055BD931736002D +:1050C0008D839318D801B3E8170193573800EDB1D9 +:1050D000B368C900E39708C68147814959B133894C +:1050E000EF41B307E84033B62F013386C740F68956 +:1050F000854411B4931636009317D8018D82B3E816 +:10510000D70093573800B1B9931636009317D801DA +:105110008D82B3E8D700AA84935738003DB993072E +:1051200005FE93060002B357F700630AD500930605 +:1051300000043385A6403317A700336FEF003339DF +:10514000E0013369F900A9BB81451305F07FB7077A +:105150000800A9BC3309FF01B30707013336F90181 +:105160003E9675B3931636009317D8018D82B3E837 +:10517000D7009357380089B1397193D7450122DCA4 +:105180004AD856D22A891394C50006DE26DA4ED6AE +:1051900052D45AD05ECE13F5F77F318093DAF50101 +:1051A000630B05109307F07F630BF514135AD901B5 +:1051B0000E0433648A00370A8000336A4401131BEB +:1051C0003900930415C00144814B13D8460113994B +:1051D000C6001378F87FB2881359C90093D9F60135 +:1051E000630E08089307F07F6300F8041357D60195 +:1051F0000E0933692701130818C0B7078000336709 +:10520000F90093183600B38404418145BD4733C883 +:105210003A0163E4871A977700009387A72F0A045F +:105220003E9410403E9602863367C90093841480F2 +:10523000631207101364240081488945C1BF130617 +:10524000F07F81470147B207F25062545206B183A2 +:105250007E08D18FB3E70701D2544259B259225A7E +:10526000925A025BF24B3A85BE85216182800148E9 +:105270001306F07FB70708000147F1B73367C9008D +:105280004DC7630809304A8532C4EF10003A224600 +:10529000130755FFF547930685FF998F3319D900FA +:1052A000B357F60033E72701B318D60026959304C9 +:1052B000353F8145A1BF336A240163030A0636C620 +:1052C00032C46306042A2285EF1020362246B246F5 +:1052D000AA84130755FF754A138B84FF330AEA40EB +:1052E00033146401335A4901336A8A00331B69015C +:1052F0001305D0C0B30495400144814BF9B5336A1E +:10530000240163180A002144014B9304F07F894B68 +:105310006DBD228A4A8B31449304F07F8D4B75B565 +:105320001144014B8144854B4DB5136414008148F1 +:105330008545E9BD136434004A878D45C1BD630AC4 +:10534000052E8547898F9306800363DDF63201467B +:1053500081470147CDBDCE868947638DF53A8D479C +:10536000E387F5F085473688E383F5FE1385F43F40 +:10537000E357A0FC93F778006396072893D638008C +:105380009317770063D80700B70700FFFD177D8FDD +:10539000138504409307E07FE3C3A7EA1316D70100 +:1053A00093179700B1833367D6001376F57F61BDFD +:1053B000D6865287DA88DE8545B763614723630D59 +:1053C000EA20DA86FD145284014B9317870013D329 +:1053D00088013363F300935E0301B357D403131FB3 +:1053E0000301135F0F0193D50601139E88003374E8 +:1053F000D4033307FF024204C18D63FBE5009A9595 +:105400001386F7FF63EE652663FCE526F9179A9588 +:10541000998D33D7D503C206C182B3F5D5033306C0 +:10542000EF02C205D58D63FBC5009A959306F7FF81 +:1054300063E6652463F4C52479179A95C20741642D +:105440005D8F9307F4FF3375F70093580701935F5F +:105450000E01B377FE00B302F502B386C540B383F5 +:10546000F80293D502013386AF021E962E9633853D +:10547000F803637376002295C168FD189355060101 +:10548000337616014206B3F81201AA95469663E6F2 +:10549000B6126382B6123306CB408D8E333BCB00FF +:1054A000338B66411385F43F630C6317B358DB03FA +:1054B00093550601337BDB03B3061F03420B33EB2B +:1054C0006501637BDB001A9B9385F8FF636D6B209E +:1054D000637BDB20F9181A9B330BDB40B356DB03ED +:1054E00042064182337BDB03330FDF02420B33661C +:1054F0006601637BE6011A969385F6FF6367661E75 +:105500006375E61FF9161A96C208B3E8D80093959A +:10551000080193D20801C181B38EF5023306E6413A +:10552000B385BF0293D60E01B387F202BE95AE9645 +:10553000B38F5F0263F4F600C167BE9FC165FD15BE +:1055400093D70601ED8EC206B3FEBE00BE9FF6964F +:10555000637FF6091A969387F8FF6369661A636892 +:10556000F619630FF61BBE8893E8180011B54A853B +:10557000EF10A00B13075501F145930405022246D5 +:10558000B246E3DAE5D4130485FF331A8900014BF0 +:1055900085B3328532C4EF10400913075501F14637 +:1055A000AA87224613050502E3D6E6CEE117331794 +:1055B000F6008148E5B9E370CBEE729B3335CB0141 +:1055C0001A95AA961305F7FF6378D30263E6B6101F +:1055D0006382D5102A87C1B5E3651BDF93551B0095 +:1055E0009316FA0113541A00CD8E7E0BF9BBE31DFE +:1055F000F6F7E38F06D6B9BFE31ED3FCE378CBFD05 +:105600002A8751BD93F7F8009146E389D7D693B71F +:10561000C8FF9386480093C717008D823E978DB3CD +:1056200081468547E34CA0FEFD58E31C05D093045A +:1056300010C085471385E441B316A70033D6F800A0 +:105640003395A800D18E3335A000C98E13F67600AD +:105650003357F70001CE93F7F60011466388C70071 +:1056600093874600B3B6D7003697BE869317870058 +:1056700063D80704054681470147F1B636877DBBED +:10568000B28779B3FD46E3D7F6FA0556098E93063D +:1056900000023356C7006388D7009387E443B317EB +:1056A000F700B3E8F800B3361001D18E13F6760098 +:1056B000814701CE93F7F60011460147E392C7FAFE +:1056C000931797001316D701B18313D73600518F64 +:1056D000014695BEE370CBF0729B3335CB011A9532 +:1056E0007917AA964DBBAE88C5BBAE8631BD931760 +:1056F0001E0033BEC70172931A96F9183E8EE31549 +:10570000F6E7E307DEC693E818009DB1BE88E30A1A +:10571000F6FF99BD36881306F07F8147014725B60D +:10572000E367DEFCBE88E310DEFE99B113D74501C6 +:10573000B7071000FD1713D846011377F77F9308BA +:10574000F07F33FEB700AA8EF58FFD81328F13787C +:10575000F87FFD82630B170105436306180163148C +:105760000701630DFE001A858280B368AE00054311 +:10577000E39B08FEE319E8FED18FF5F70543E394B8 +:10578000EEFF0143E381D5FE054371FF3365AE00B3 +:105790003333A000C9BF13D74501B7071000FD1769 +:1057A00013D846011377F77F9308F07F33F3B700E0 +:1057B0002A8EF58FFD81B28E1378F87FFD82630803 +:1057C0001703630018030DEBB368A300631408000C +:1057D0005D8E29CA638508046388D502054595ED69 +:1057E0008280B3E8C700E38008FE79558280336584 +:1057F000A30065FD630CE802631408005D8E79DE8A +:10580000E39ED5FCE34CE8FC63480701E3E867FC52 +:105810006303F302637FF30081E57D558280F5DE4B +:10582000054582800145E39B08FA82805D8E69DA36 +:105830006DBF01458280E3E3CEFB0145E372DEFBF1 +:10584000E5F1E1BF13D74501B7071000FD1713D8E5 +:1058500046011377F77F9308F07F33FEB700AA8ED7 +:10586000F58FFD81328F1378F87FFD82630E170369 +:10587000630D180129E3B368AE00631F08005D8E55 +:1058800001EE0143638C080421A8B3E8C700094373 +:10589000639608046DD305A0638408046385D5026C +:1058A00005438DCD7D531DA8B368AE0009436397B2 +:1058B0000802630AE802631408005D8E75D2E39162 +:1058C000D5FEE34FE8FC63490701E3EBC7FD630F37 +:1058D000FE0001436374FE00F1D505431A85828002 +:1058E000EDFE7D53E5BF5D8E79DACDBFE36ADFFB68 +:1058F0000143E3F5EEFFF5F175B739714AD813D9D5 +:1059000045014ED652D456D29399C50006DE22DC0C +:1059100026DA5AD05ECE1379F97F2A8A93D9C90044 +:1059200093DAF501630D090E9307F07F6306F9180A +:105930001354D5018E09B36934013704800033E470 +:10594000890093143500130919C08149814B13D77D +:105950004601139AC6001377F77FB285135ACA001F +:1059600013DBF601630B07109307F07F6303F70463 +:105970009357D6010E0A33EA4701130717C0B7073A +:105980008000B367FA00931536003A99814833C70F +:105990006A01BD463A851308190063E83617177681 +:1059A0000000130626BB8A09B29983A60900B296A5 +:1059B0008286B367CA001309F97F6399071293E9D6 +:1059C000290081458948E1B701479307F07F3704F3 +:1059D000080081443204D20731807E075D8C598CE7 +:1059E000A285F250625426854259D254B259225AA5 +:1059F000925A025BF24B216182805A853E84AE84CA +:105A0000C68B8947638DFB0E8D47E38FFBFA854775 +:105A10002A87639EFB3881470144814465BF33E494 +:105A2000A90061C036C632C4638C092A4E85EF00D6 +:105A3000D03F2246B246AA87130755FF7544938488 +:105A400087FF198CB399990033548A003364340169 +:105A5000B3149A0013D746011309D0C0139AC60095 +:105A60001377F77F3309F9408149814BB285135A87 +:105A7000CA0013DBF601E31907EEB367CA00B1C72A +:105A8000630F0A22528532C4EF00303A22462A8739 +:105A9000930655FFF547930587FF958F331ABA0094 +:105AA000B357F600B3E74701B315B6003309E94031 +:105AB0001309D9C08148E1BD33E4A90001ECA14933 +:105AC00081441309F07F894B59B593E91900814549 +:105AD000854875BD4E84AA84B1491309F07F8D4B6A +:105AE000BDB5914981440149854B95B593E939008C +:105AF000D2878D4869BD89475685E397FBF02A8791 +:105B00009307F07F01448144F1B5C16E1386FEFF17 +:105B100093D6040113DE0501F18CF18D33869502D5 +:105B20003383B6029358060133059E021A95AA984C +:105B3000B382C60363F36800F692C16F1383FFFF5D +:105B400033F5670093D30701B3F76800C2073373D7 +:105B500066003E933306950293D80801B387A602E8 +:105B6000135F0601B3849302BE94FA94B38E760257 +:105B700063F3F400FE9E416A9307FAFF935F04010A +:105B8000B376F400B3F9F4007D8EC1803384D5027E +:105B9000C209338FD401B299CE98B307DE02935E67 +:105BA0000401B385BF02AE97BE9E330EFE0363F3BE +:105BB000BE00529EC1679385F7FF33F6BE006D8C21 +:105BC0004206229693DE0E01B305D502769E3385FA +:105BD000AF0213D40501B386D302AA96A296B38F5F +:105BE000F30363F3A600BE9F41657D15B3F7A600DE +:105BF000C2076D8DAA97B3855800B3B93501FA97DE +:105C0000B2953384370133B6C500B30EC401338572 +:105C1000CE0033343401B3B7E701C18F33BECE01B8 +:105C200013D406013336C5003E943366CE009394F8 +:105C3000950032947E94B3E4640026049356750173 +:105C4000B3349000DD8193179500CD8C558CDD8C9D +:105C50009317740063DB070093D7140085889316AD +:105C6000F401DD8CD58C058042899307F93F635997 +:105C7000F00893F6740081CE93F6F4001146638821 +:105C8000C60093864400B3B496002694B684931657 +:105C9000740063D80600B70700FFFD177D8C9307DB +:105CA00009409306E07F63CFF60E93D63400931439 +:105CB000D4012604D58C318093F7F77F21BB328540 +:105CC00032C4EF00901693065501F1471307050201 +:105CD0002246E3D1D7DC6115B317A6008145F9B39D +:105CE000EF00B01413075501F14593070502224652 +:105CF000B246E3D5E5D461153314AA00814499BBBB +:105D000085469D8EB1E71309E941B3972401B3D4C9 +:105D1000D40033192401B337F000B3649900DD8C4B +:105D200093F77400B356D40081CF93F7F400114673 +:105D30006388C70093874400B3B49700A696BE84D7 +:105D40009397860063D8070485470144814459B17D +:105D500013068003E341D6CC7D46E356D6FA0556BA +:105D6000B307F640930500023356F4006387B6008C +:105D70001309E943B3172401DD8CB3349000D18CAF +:105D800093F67400014499CA93F7F40011468146D2 +:105D9000E392C7FA139496003180F6068D80D58C75 +:105DA00081470DB99307F07F0144814425B14289B1 +:105DB0006DBD370710007D1701113373B70093D8FD +:105DC0004601758F935ED60122CC26CA0E0393D46A +:105DD00045019357D5010E0706CE4AC84EC693F823 +:105DE000F87F130EF07F33E7EE0093F4F47F13D4C3 +:105DF000F50133E36700131F3500FD82931E360063 +:105E0000638FC81793C61600B38514416304D41278 +:105E10006350B018638A081AB70780005D8F638FDC +:105E2000C4579307800363C2B734FD4763C3B748C1 +:105E3000930700028D8FB3D9BE003318F700B39ECD +:105E4000FE00336838013357B700B339D0013368E7 +:105E500038013303E340B3090F41B3373F01330641 +:105E6000F3409317860063D20724370980007D1919 +:105E700033792601630E092C4A85452F130785FFC8 +:105E800093070002998FB3D7F9003316E900D18F39 +:105E9000B399E9006344972A058F13061700FD465E +:105EA00063C4C63A13070002118FB3D6C9003398F2 +:105EB000E9003397E700558F33380001B3690701D4 +:105EC00033D6C700814493F7790081CF93F6F90068 +:105ED00091476388F6009386490033B836014296AD +:105EE000B6899317860063D6071C1387140093079F +:105EF000F07F05886306F720B70780FFFD17F18F55 +:105F00001398D70193D93900A60733683801B183B4 +:105F10001377F77F9396C7005207B1827E04D98E1C +:105F2000C18EF2406244D2444249B2494285B685AC +:105F3000056182806356B00A638A0812B707800041 +:105F40005D8F6386C42D9307800363C7B718FD4731 +:105F500063D1B73C138805FE93070002B3590701CC +:105F6000638AF50093070004B385B7403317B70081 +:105F7000B3EEEE003338D0013368380195A2B36731 +:105F8000D7019385148099E393C61600630AD4045D +:105F9000D1E19387140093F7E77F6398071EB367F7 +:105FA000E3013368D701639204166381073C6315EC +:105FB0000842131835009316D3011358380033E8FC +:105FC00006019357330019A2B367D7016384071AF8 +:105FD0009387F5FF638A073A638BC523BE8591B526 +:105FE0006398051C9386140093F7E67FC1EFB367AF +:105FF000E301639F0434638C0744B367D701639361 +:1060000007460E051318D3010D813368A800935776 +:1060100033006DA8B385984063960420B367E3010D +:10602000638C07309387F5FF638807401305F07F83 +:106030006382A520BE859307800363C1B72AFD470D +:1060400063C7B73C930700028D8F3318F3003356B4 +:10605000BF00B317FF003368C800B339F0003353F3 +:10606000B3003368380133076740ADACB367D7017D +:10607000638207109387F5FF638E071E638FC52D1C +:10608000BE85D1B59307F07F638BF606FA9E33B6D3 +:10609000EE01B307E300B2971398F70193DE1E00F9 +:1060A000B369D80113D61700B68493F77900E39F3C +:1060B00007E09317D60113D839003368F800A68596 +:1060C000935736001307F07F6380E506B207B1836C +:1060D00013F7F57F05883DBD3367D7013338E000FE +:1060E000B309E801B3B7E901338667009317860067 +:1060F000E3DD07FA85049307F07F639BF4180588B6 +:106100001307F07F8147014831B5639007106300A2 +:10611000083C131836009317D7011358380033681A +:10612000F800368493573700B367F800E9DB014481 +:106130001307F07FB70708000148E9BB370680FF67 +:106140007D167D8E93F77900998CE39107D895B7EA +:106150004E85E12913078501FD47E3D3E7D21306F6 +:1061600085FFB397C900814935B33368D701333808 +:106170000001D5B1131835009317D3011358380017 +:106180003368F8009357330035BFB309DF41330953 +:10619000E34033363F013309C9409317890063CA8E +:1061A000072033E82901E31708CC8147014439BFB0 +:1061B000B385984063810414B70680009307F07F8D +:1061C0003363D3006381F8209307800363CCB72245 +:1061D000FD4763C9B72C930700028D8F3318F30076 +:1061E000B356BF00B317FF003368D800B339F000CF +:1061F0003353B300336838011A97B309D801B3B7E2 +:10620000D9013386E700C684D5B5E31208F2131826 +:1062100035009317D301135838003368F8009357AB +:10622000330019B7370580009307F07F3363A3006D +:10623000E393F8E00E061318D7010D823368C80007 +:10624000935737003684CDB505179306000233D730 +:10625000E700630AD600930600043386C6403396EF +:10626000C700B3E9C90033383001B369E80001461B +:10627000814425BDB309DF01B307E30033BFE90162 +:106280003386E701931786008544E3D007E289440B +:10629000B70780FFFD17F18F13D7190013F8190006 +:1062A000336807019399F701B3E9090113D6170081 +:1062B00019B9138805FE93070002B3590701638AD1 +:1062C000F50093070004B385B7403317B700B3EE6A +:1062D000EE003338D00133683801B5BE3363E301D3 +:1062E00033386000B3890E41B3B73E013306F7403F +:1062F000C6843684BDB6B367E30163870718938706 +:10630000F5FF638C071C9306F07F638ED50ABE856C +:1063100065BD930700028D8FB3D9BE003318F70017 +:10632000B39EFE00336838013357B700B339D0014C +:10633000336838013A936DB3131836009317D701B9 +:106340001358380033E807013684935737009DBB54 +:10635000BDCB3367D701E31C07DC0E051318D3014F +:106360000D813368A800935733007DBBE30F08E22B +:10637000131836009317D701135838003368F80004 +:1063800036849357370099B3B309DF41B307E3402D +:10639000333F3F013386E7418544E1B413183500AC +:1063A0009316D3011358380033E80601935733008E +:1063B000A5BBB389EE413306674033B93E013309CB +:1063C0002641368445BC0E061318D7010D8233686A +:1063D000C8009357370089BBB309DF41B307E340D7 +:1063E00033363F013386C7409317860063D7070AC9 +:1063F000B389EE41B3076740B3BE3E013386D74150 +:106400003684D1B43363E30133386000FDB31388BD +:1064100005FE93070002B3590301638AF500930751 +:106420000004B385B7403313B300336F6F003338C4 +:10643000E001336838017DB5B389EE41B3076740A9 +:10644000B3BE3E013386D7413684854419BC131848 +:1064500036009317D701135838003368F800935764 +:106460003700ADB1B309DF01B307E30033BFE90182 +:106470003386E70193178600E3D907C2B70780FF89 +:10648000FD177D8E854415B10E061318D7010D82B8 +:106490003368C8009357370035B133E8C900E306C5 +:1064A00008D021B1138805FE93070002B3590301F8 +:1064B000638AF50093070004B385B7403313B30034 +:1064C000336F6F003338E001336838013DB3014466 +:1064D0001307F07FB707080035BCB309DF01B30726 +:1064E000E300B3BED9013386D70169BB93D7450119 +:1064F000B70610001387F6FF93F7F77F1306E03F08 +:106500006D8FFD81635CF6001306D041635AF6007F +:10651000370500801345F5FF2E9582800145828066 +:10652000130630431D8E7D48558F635DC80093066A +:106530003041B387F640B357F7003305F040E5F13B +:106540003E8582809387D7BEB317F7003355C500C9 +:10655000C98FE5B7411106C622C426C205CD93579F +:10656000F541B3C4A7009D8C2A8426857D28930617 +:10657000E041898EA9477D8093F6F67F63CDA7021F +:106580002D47098FB3D7E4005505B207B394A40093 +:10659000B18329A00144814681478144B207D206D4 +:1065A000B1837E04D58FC18FB24022442685BE853B +:1065B0009244410182805515B397A400B207B1837C +:1065C0008144E9BF15CD411122C406C62A84B128F1 +:1065D0009306E041898EA94793F6F67F63DCA70214 +:1065E0005515B317A400B207B1830147B240224446 +:1065F000B207D206B183D58F3A85BE85410182802C +:1066000081478146B207D206B1830147D58F3A85CB +:10661000BE8582802D47098FB357E400B207130768 +:1066200055013317E400B183D1B7C167637EF5022A +:106630009307F00F1307000263ECA70097670000B1 +:10664000938747F5AA9703C507003305A7408280C3 +:106650002181976700009387E7F3AA9703C5070096 +:1066600061473305A7408280B7070001636EF500DC +:106670006181976700009387E7F1AA9703C5070038 +:1066800021473305A74082804181976700009387A7 +:1066900067F0AA9703C5070041473305A7408280EA +:1066A0009387C1829C434111328806C6AA882E87EF +:1066B000C8473686976700009387C7FD63170800B1 +:1066C000976700009387C79E3E88C686976500003F +:1066D000938545FD1920EF206066397132D436D696 +:1066E0003EDA3AD842DC46DE9387C1822E86AA85FE +:1066F0008843341006CE36C6712AF240216182806A +:1067000001476314E60001458280B307E5000507F1 +:10671000B386E50083C7070083C6F6FFE383D7FE91 +:106720003385D7408280B3C7A5008D8B3307C50062 +:1067300081E78D4763EEC700AA876370E50A83C6C9 +:10674000050085078505A38FD7FEE3EAE7FE828073 +:1067500093763500AA8791CA83C60500850785050B +:10676000A38FD7FE93F63700FDB79376C7FF138646 +:1067700006FE63F0C70683A3050083A2450083AF2E +:10678000850003AFC50083AE050103AE450103A339 +:10679000850183A8C5019385450223A0770003A83E +:1067A000C5FF23A2570023A4F70123A6E70123A8CE +:1067B000D70123AAC70123AC670023AE1701938733 +:1067C000470223AE07FF75B790419107910523AEAD +:1067D000C7FEE3EBD7FEE3E4E7F6828063F3A504AC +:1067E000B386C500637FD5029345F6FF8147FD1749 +:1067F0006393F50082803387F600034807003387F0 +:10680000C7002A9723000701DDB73387F5008346C9 +:1068100007003307F50085072300D700E317F6FECE +:1068200082808147E5BF1C46FD171CC663DA07005E +:10683000184E63C5E700A9476394F5006F208032C6 +:106840001C422E851387170018C22380B700828050 +:10685000011122CC26CA4AC84EC652C406CE2A8985 +:10686000AE893284B304D6007D5A63149400014586 +:1068700011A8834504004E864A85EFF0DFFA05042F +:10688000E31545FFF2406244D2444249B249224AEC +:1068900005618280357122CD26CB4AC94EC706CF0D +:1068A00052C556C35AC1DEDEE2DCE6DAAA89AE84FE +:1068B0003289368409C51C4D99E3EF30C04497678F +:1068C00000009387A7F8639DF40C83A4490083D745 +:1068D000C400A18BE5CB9C48F5C793070002A30435 +:1068E000F1029307000302D22305F10222C6930BA3 +:1068F0005002976A0000938AEADD054C294B4A84CE +:106900008347040099C36392770FB30C2441638ECD +:106910000C00E6864A86A6854E85EFF07FF3FD578C +:106920006306F51E9256E69636D283470400638FBF +:10693000071CFD571309140002C802CE3ECA02CC40 +:10694000A309010482D48345090015465685EF301A +:10695000705D13041900C24759E913F7070109C70D +:1069600013070002A309E10413F7870009C71307FF +:10697000B002A309E104834609001307A002638063 +:10698000E608F2474A8481462546034704009305FA +:106990001400130707FD6379E60AB5CA3ECE85A841 +:1069A00097670000938787EC6395F40083A48900C0 +:1069B00039BF97670000938767E7E39AF4F083A4F1 +:1069C000C90031B7A6854E85EF20202619D57D5503 +:1069D000FA406A44DA444A49BA492A4A9A4A0A4B6E +:1069E000F65B665CD65C0D618280050411BF3305E1 +:1069F00055413315AC00C98F3EC82289A9B732472B +:106A000093064700184336C6634907023ACE034748 +:106A100004009307E002631FF70403471400930781 +:106A2000A002631BF702B2470904138747009C4387 +:106A30003AC663C107023ECA35A83307E04093E770 +:106A400027003ACE3EC8E1B7B387670385462E8458 +:106A5000BA9725BFFD57C5B7050402CA81468147CD +:106A600025460347040093051400130707FD6378C8 +:106A7000E606F1F2834504000D4617650000130594 +:106A8000E5C5EF30304A11CD97670000938707C501 +:106A90001D8D93070004B397A700424505045D8D43 +:106AA0002AC883450400194617650000130545C32D +:106AB000130914002304B102EF30D04625C1970713 +:106AC00000009387C71E95E74247B2471377071028 +:106AD00009CF91073EC69257D2973ED20DB5B387E4 +:106AE000670385462E84BA97ADBF9D07E19BA1073A +:106AF000D5B77800970600009386C6D526860C0881 +:106B00004E856522FD572A8AE317F5FC83D7C4001A +:106B100093F70704E39D07EA12555DBD78009706D9 +:106B20000000938626D326860C084E85B927D9BF48 +:106B3000797122D44AD052CC56CA5AC806D626D227 +:106B40004ECE3A8AAE8A32843689428B01476358E8 +:106B50000600370700803344C7001307D0022380A4 +:106B6000E70093F4F8FD930760048D466388F40012 +:106B70009307500489466393F4000509DA87930864 +:106B8000C100130881004A87D6852286EF20A02FF6 +:106B900093077004AA896396F400137A1A00630AB3 +:106BA0000A0493076004338A29016397F40203C738 +:106BB000090093070003631EF700014681465685CE +:106BC000A285EFE0BFB611C5854733892741232051 +:106BD0002B0183270B003E9A014681465685A285EC +:106BE000EFE0DFB411E152C613070003B24763E2DE +:106BF0004703B2474257B2502254B38737411CC3B0 +:106C00004E8592540259F249624AD24A424B45613A +:106C100082809386170036C62380E700C1BF230019 +:106C2000C500130725009307B00263D60500B3051E +:106C3000B0409307D002A300F500A54763DAB7047C +:106C400041119307F100BE88294813033006B3E6CB +:106C500005031386F7FF93860603A38FD7FEB3C6FB +:106C60000503634DB30093860603F917A30FD6FE01 +:106C700063E917013305A74041018280B287B685D9 +:106C8000F9B7850783C6F7FF0507A30FD7FECDB772 +:106C90009307000313074500938505032301F500BF +:106CA000A301B5003305A740828019713ACE86DE74 +:106CB000A2DCA6DA2E84CAD8CED6D2D4B689DAD04F +:106CC000DECEE2CC3289D6D2E6CAEAC8EEC6AA84C3 +:106CD000EF30B00F832B05005E85EF00B078032BFB +:106CE0000400724702DC93760B102A8C034A84015D +:106CF0001C43F1CA9386470014C39C430810984371 +:106D00003AD0D8433AD298473AD4DC473ED6EF50EF +:106D1000400728C46CC4832CC40417670000130701 +:106D2000E79C832A8404032D0700832D4700939753 +:106D30001C0085836A86EE865685BE853ECEEF4072 +:106D4000F04941EDF2476A86EE865685BE85EFE052 +:106D50007FAF6354A008014681465685E685EFE083 +:106D60007FAE635605009307D002A301F404930796 +:106D70007004976A0000938AEA9763F64701976A5E +:106D80000000938A6A97137BBBFF8D472320640121 +:106D90001CC8014B4E87CA867018A2852685C12E55 +:106DA000FD5C631E95157D55F6506654D6544659C4 +:106DB000B659265A965A065BF64B664CD64C464D4B +:106DC000B64D096182809D07E19B9386870014C3BD +:106DD0009843DC4338C47CC43DBF5686E68656855E +:106DE000E685EF40B03F11CD93077004976A00002D +:106DF000938ACA90E3F947F9975A0000938A8A6CFC +:106E000059B75C407D57137DFA0D6395E7089947A4 +:106E10005CC0544013670B403C18D6853EC018C078 +:106E20009307310302C2D288130841036686268580 +:106E3000EFF01FD093077004AA8AD255631BFD00A0 +:106E4000F55763C5F5005C4063D8B708791A137A23 +:106E5000FA0F9307500663E64705FD1552861305A2 +:106E600004052EDAEFF0BFDB625785462A8BB307A5 +:106E7000A7001CC863C5E6001840058B19C3850729 +:106E80001CC883473103E38707F09307D002A301AF +:106E9000F40409B713077004E31DEDF6BDFB854745 +:106EA00085BF93076006631BFA025C40635BB0001A +:106EB0000CC881E71840058B09CF8507AE971CC821 +:106EC00009A889E718408546058B19C393862700D2 +:106ED00014C82CCC014B75B7130A7006E25763C96E +:106EE000F5001C400CC8858BEDD793871500C1BFFA +:106EF00005476344B00009470D8FBA97C9B71C40D6 +:106F000013F7074015E314485686CA8526858299EB +:106F1000E30B95E91C40898B63960724F25748449C +:106F2000E354F5E83E8549B513075006637B4719DE +:106F300028446C4401468146EFE04FFF39E985461D +:106F4000175600001306C67BCA8526858299E30C76 +:106F500095E55257E2576345F7001C40858BDDDB12 +:106F6000E2865E86CA8526858299FD57E30DF5E2A5 +:106F7000014A930AA4017D5BE257FD17E35CFAF82E +:106F800085465686CA8526858299E30E65E1050AFF +:106F9000E5B7D2576346F00685461756000013063C +:106FA0002676CA8526858299E30F95DFD2576257E8 +:106FB000D98F81E71C40858BB1DFE2865E86CA856A +:106FC00026858299FD57E300F5DE014A130BA401E3 +:106FD000FD5BD257B307F040634BFA00E25656868A +:106FE000CA8526858299FD57E316F5F26DBB854665 +:106FF0005A86CA8526858299E30775DB050AD1BFC3 +:107000003C4C625A63D347013E8A635A4001D286A0 +:107010005686CA8526858299FD57E306F5D8814CA8 +:10702000130DA401FD5D09A885466A86CA852685DB +:107030008299E30AB5D7850C032B8405D287635365 +:107040000A008147B307FB40E3C0FCFE5257E257FA +:10705000634DF7021C40858B8DEBE2575257338A04 +:10706000E7406344EB00338A6741635B4001D286AB +:1070700033866A01CA8526858299FD57E305F5D2D4 +:10708000814A130BA401FD5B15A0E2865E86CA85CA +:1070900026858299FD57E312F5FC31B385465A8661 +:1070A000CA8526858299E30075D1850A5257E25731 +:1070B000998F528763530A000147998FE3C0FAFE04 +:1070C00091BDE25605476344D700858BB5C7854619 +:1070D0005686CA85268582997D5AE30645CDE28685 +:1070E0005E86CA8526858299E30F45CB28446C4489 +:1070F00001468146EFE08FE31DC9E25613861A0070 +:10710000CA85FD1626858299E30F45C9DA861306DE +:107110000405F9B585465686CA8526858299E30415 +:1071200075C9050AE257FD17E346FAFEC5B7014ADD +:10713000930AA401FD5BFDB785465686CA85268560 +:107140008299E31595FD85B185465686CA852685C3 +:107150008299E30A65C5050A5C447257998FE34535 +:10716000FAFE6DBB014A930A94017D5BF5B7797114 +:1071700056CA9C49BA8A984522D426D24ECE52CCC1 +:1071800006D64AD05AC85EC6AA892E84B284368AE8 +:1071900063D3E700BA879CC00347340419C385074B +:1071A0009CC01C4093F7070281C79C4089079CC084 +:1071B0000329040013796900631A0900130B940171 +:1071C000FD5B5C449840998F634CF9041C408346F6 +:1071D000340493F70702B336D000A5EB130634044A +:1071E000D2854E85829AFD576303F5041C401146F3 +:1071F0009840998B544481446397C700B384E64018 +:1072000063D3040081441C4418486354F700998FE9 +:10721000BE94014969047D5B63982405014509A872 +:1072200085465A86D2854E85829A631E75017D55A4 +:10723000B250225492540259F249624AD24A424B05 +:10724000B24B456182800509ADBF3307D4001306F8 +:107250000003A301C7040347540493871600A297B1 +:107260008906A381E7049DBF85462286D2854E8587 +:10727000829AE30E65FB050945B7797122D426D2BF +:107280004AD04ECE06D652CC56CA5AC8B68983C604 +:107290008501930790063289AA842E8413863504CB +:1072A000638DF60263E2D706930780056389F618BB +:1072B00063EDD7006382062293073004638FF60ADA +:1072C000930A24042301D404D1A0930730066386D3 +:1072D000F60A93074006E395F6FE1C40084393F632 +:1072E000070893054500CDC61C410CC363D80700B1 +:1072F0001307D002B307F040A301E404975600003F +:1073000093864640294775A8930700076385F616BC +:1073100063E5D7029307E006638CF6189307F0063F +:10732000E390F6FA0C401C4313F805081385470058 +:107330006308080608C39C4395A893075007E38396 +:10734000F6FE93078007638CF61293073007E399E4 +:10735000F6F61C43D04181459386470014C383AAA7 +:1073600007005685EF30003C01C53305554148C044 +:107370005C401CC8A301040471A81C43930A2404A4 +:10738000938647009C4314C32301F4048547D5B773 +:1073900093F607041C410CC3B1DAC207C187B9B721 +:1073A00093F5050408C3C1D983D707001307F00676 +:1073B0006388E60E975600009386C6342947A301DA +:1073C00004044C400CC463C5050008406D9908C016 +:1073D00099E3B28A91CDB28AB3F5E702FD1AB69568 +:1073E00083C505002380BA00B3D5E70263F0E70C3C +:1073F000A147631EF7001C40858B91CB58401C4869 +:1074000063C7E70093070003A38FFAFEFD1A330654 +:10741000564110C84E87CA867000A2852685EFF0B7 +:107420001FD57D5A631E450B7D55B2502254925490 +:107430000259F249624AD24A424B45618280A38294 +:10744000D504975600009386E62B0C40084313F8AA +:1074500005081C411105630D080208C313F7150048 +:1074600001C793E505020CC04147B1FB0C4093F501 +:10747000F5FD0CC0A9B79C4193E707029CC1930797 +:107480008007A302F404975600009386E62875BF90 +:1074900013F8050408C3E30308FCC207C1837DBFDA +:1074A0009756000093860626214711BFAE872DB759 +:1074B00094411C43CC4913F8060813854700630622 +:1074C000080008C39C438CC301A808C393F60604B4 +:1074D0009C43F5DA2390B70023280400B28A1DBF2D +:1074E00014485686CA8526858299E30F45F31C40C9 +:1074F000898B8DE7B2474844E359F5F23E8535B7AD +:1075000085465686CA8526858299E30F65F1050A68 +:107510005C443247998FE345FAFEE9BF014A930A7A +:1075200094017D5BF5B79C451D71A2CCCEC6DAC037 +:1075300066DA86CEB28CA6CACAC8D2C4D6C25EDE0D +:1075400062DC6AD86ED61386F7FF1307C015368B38 +:10755000AA892E8481466377C700938637EA93070A +:10756000D0159CC51C40930AC401D68493E70778C4 +:107570001CC00149814D014C014A014D814B13064C +:107580009004130800708548930E00400943130EC1 +:1075900050061D4F18441DCB83A70C0083C707005E +:1075A000638BC7126368F60C9305900363E4F50AD6 +:1075B0009305100363FBB7149305D0026383B716DA +:1075C00063E3F5041307B002638DE71463060D004F +:1075D0001C4093F7F7EF1CC0FD1D854763EBB721F7 +:1075E00063ED9A1E0549F64066444A85D6444649ED +:1075F000B649264A964A064BF25B625CD25C425D13 +:10760000B25D256182809305E002638FB714930514 +:107610000003E39DB7FA0C4013F505107DC593F503 +:10762000F5F70CC0050D81C60507FD1618C41C44EE +:10763000FD171CC41C4885071CC883A74C00FD17F8 +:1076400023A2FC006356F01683A70C00850723A035 +:10765000FC0089B7130750046382E7121307600424 +:10766000638BE70E13071004E392E7F6E3901DF730 +:10767000894D65A06384C7116361FE04130740054B +:10768000638FE70C6364F7021307E004E390E7F409 +:1076900063910D0A63110D0A184093750770639C7E +:1076A00005091377F78718C0854D85A8130790053E +:1076B0006389E7041307100645BF1307E006E38953 +:1076C000E7FC6368F702130760066386E7081307A1 +:1076D0009006E39DE7EE63190906E31B0DEE1840E3 +:1076E00093750770E39A05EF1377F78718C005497C +:1076F0002DA0130740076384E70613079007E3975D +:10770000E7ECE315E9ED214909A833872D01E31FD3 +:1077100007EA18401377F7E718C02380F4008504C0 +:1077200039B7184093750708E38205EA1377F7F72E +:10773000E5B7638D6D06630519011147E318E9E8A4 +:1077400005091379F90FD1BF1307D9FF1377D70FA5 +:10775000E31E07E6F5B7E31B69E60D497DBF194750 +:10776000E316E9E61D4955BF184093750720E38FDE +:1077700005E41377F7D718C0EA8B45B7184093751F +:1077800007506388D50193750740E38105E4E3055D +:107790000DE49375072081E5330A7D41268C13772C +:1077A000F7871367071818C0014D85BF8D4DB5B712 +:1077B00083270418E6854E8536C68297B24613069F +:1077C0009004130800708548930E00400943130E7F +:1077D00050061D4FE30005DCD5BBFD148327C417FD +:1077E00083C5040066864E8582971C48FD171CC819 +:1077F000C5BB9307F9FF19476366F7028947A68D52 +:1078000063F12709330799401377F70F8D46B38744 +:10781000ED0093F7F70F63ECF60275191379F90F82 +:10782000B38424411C4013F7071045C393F7074066 +:10783000A1CFE3F99ADAFD148327C41783C50400A6 +:1078400066864E8582971C48FD171CC8DDB7FD1D56 +:107850008327C41783C50D0066864E853AC6829776 +:107860001C488D463247FD171CC855B7FD148327A9 +:10787000C41783C5040066864E8582971C48FD1791 +:107880001CC8E3E59AFEB9BB1C4883C5F4FF138905 +:10789000F4FFFD171CC8930750066382F502930797 +:1078A0005004638EF5008327C41766864E85829741 +:1078B0001C4883C5E4FF1389E4FFFD171CC8832718 +:1078C000C41766864E858297CA84032904001379FB +:1078D00009016313090C238004001C4013070040B6 +:1078E00093F70760639EE7023386AB416396AB056F +:1078F000D68501464E85EF10000718402A8AAE8AC9 +:107900009376270083270B00A9C6138747002320FF +:10791000EB009C4388C3CCC35C4485075CC4E1B1E5 +:10792000E3080AFC0146A94693051C004E85EF10AA +:10793000E01A33064541E2849307F41663E4F40049 +:107940009304E41697550000938545DE2685C12CE7 +:1079500045B7938647002320DB00118B844319CF62 +:10796000AA8556860808EF40E010D2466247F247E3 +:107970004246D4C098C490C0DCC479BF2A86AE8683 +:10798000EF40C00509C50145292C88C071B7528553 +:10799000D685EF406028D5BF0149B1B139713EDAD3 +:1079A0002ED232D436D63AD842DC46DE9387C18214 +:1079B00022CC804326CA06CEAA8411C41C4C81E77F +:1079C0002285EF2040340C4454102686228536C68A +:1079D000EFE05FECF2406244D24421618280011109 +:1079E0009387C18222CC804306CEAA8501C81C4C55 +:1079F00091E72AC62285EF200031B2451044228546 +:107A00006244F24005616F30B042011126CA4AC893 +:107A100006CE22CC4EC652C4AA842E8909C51C4D5E +:107A200099E3EF20402E9C4C804481E72685EF208F +:107A3000802D97570000938767E1631DF402C040D3 +:107A40008357C400A18BB9C71C48A9C7FD59294A4F +:107A50001C4483450900FD17A1ED1CC463D1070830 +:107A60002286A9452685EF10E00FFD576309F50230 +:107A700029453DA097570000938747DF6314F40022 +:107A800080447DBF97570000938747DAE31AF4FAE2 +:107A9000C0447DB7A2852685EF10201945D97D55B4 +:107AA000F2406244D2444249B249224A056182808E +:107AB0001CC4050963D70700184C63CBE700638932 +:107AC00045011C401387170018C02380B70049B731 +:107AD00022862685EF100009E31C35F7C9B71C4044 +:107AE0001387170018C029472380E70051B79387F1 +:107AF000C182AA8588436FF05FF113D745414111D8 +:107B00001377F77F06C6930617C04D4E2A88AE87B7 +:107B1000AE886342DE0663DD0600370700808146DB +:107B20006D8F14C258C2B2404285BE854101828029 +:107B3000370710007D173357D740B3F6E50033E31E +:107B4000A600631B03005CC2B70700802320060168 +:107B5000B3F7F8000148C1BF1347F7FF0148B377F7 +:107B6000B700232006015CC2BE864286EFE06FA408 +:107B70002A88AE874DBF130E3003E346DEFC930622 +:107B8000D7BE7D573357D700B376A700CDDE134756 +:107B9000F7FFB378A700232016014CC2AE864686B5 +:107BA000F1B7975700009387E7B888438280357113 +:107BB0003ECBA6DA36C73AC942CD46CF9387C182BB +:107BC00086DEA2DC844363DB05009307B0089CC01B +:107BD0007D55F6506654D6540D61828093078020FF +:107BE000231AF1002AC42ACC814799C19387F5FF53 +:107BF0003EC83ECE7401FD572E8426852C00231BE3 +:107C0000F10036C2EF30E07AFD576355F500930777 +:107C1000B0089CC05DDCA247238007005DBF3571C2 +:107C20003ECBB707008093C7F7FF3ECE3EC8C17773 +:107C30009387872032C536C73AC942CD46CF3ECA60 +:107C40009387C1822AC42ACC884334012E862C0013 +:107C500086DE36C2EF30E075A24723800700F6507B +:107C60000D618280AA87850703C7F7FF6DFF338503 +:107C7000A7407D158280AA8709CA850503C7F5FF3D +:107C800085077D16A38FE7FE65FB3E966393C700CD +:107C900082808507A38F07FED5BF011122CC2A87DA +:107CA0002E843A85A28532C606CEEF3020163246A3 +:107CB0002A88AE8805C651801374F47F9307B006F6 +:107CC000818F635DF000D2073707F03F01483E9790 +:107CD0004286BA86EFD07FC22A88AE88F2406244DC +:107CE0004285C6850561828035714AC92A893685F3 +:107CF00032D436C606CF22CD26CB4EC7EAD8EED632 +:107D00002E8D52C556C35AC1DEDEE2DCE6DA82C8E9 +:107D1000EF20500BAA8D084181440144EFF09FF4FD +:107D2000B246AA89EAC635469305B0021305D002C9 +:107D300013080002A548B64703C70700636BE608AF +:107D4000637F17095DC702C8364A93070003814A5B +:107D500003470A00631DF71283471A0013078005C3 +:107D60006388E70013068007130700036397C710B3 +:107D7000C24736889808D40817560000130686A113 +:107D8000EC004A85EF20001B93797500AA8A63886E +:107D9000090099476398F906050AD2C602C8A25796 +:107DA00081C7B64722571CC3C247A1CBB705008085 +:107DB000A18DFA406A4426854A49DA44BA492A4ADA +:107DC0009A4A0A4BF65B665CD65C465DB65D0D6111 +:107DD00082806309B7006304A702E31607F78507EB +:107DE000BEC691BF02C813871700BAC683C7170063 +:107DF000A1FFA257EAC602C8CDF7A2855DBF05471D +:107E00003AC8D5B7464611CA93055003A808EF30C3 +:107E10000024C6454A85EF20501BFD19914763EEAB +:107E2000370117570000130727918A09BA9983A7CA +:107E30000900BA978287E644764493FA8A00E38081 +:107E40000AF6B70700805D8C99BFF6453704F0FF4E +:107E50007D14B3F785005644E64413043443931568 +:107E6000440133E4B700D1BF3704F07FF9B7B70559 +:107E7000008013C4F5FFFD54C9B7B64793861700B9 +:107E8000B6C683C71700E38AE7FE91DB854AB64C86 +:107E9000014A814B014CA546A145A9473645034BF4 +:107EA000050013070BFD1376F70F63FDC60483A5CA +:107EB0000D004E86EF3050193DC1DA87E28D8146C4 +:107EC000014B0145130750066387E7001307500471 +:107ED00081496399E71663960D00B3E7560191DB7C +:107EE000814D364D1307B00293071D00BEC6834770 +:107EF0001D006382E70E1307D00201486393E70E6B +:107F00000548D9A863C98501B38BFB02BA9B050557 +:107F1000050CAAC661B7330AFA023A9ACDBF3645B4 +:107F200081464E95AAC683470500630D0C06014B9A +:107F3000E28D138707FD25466376E602054559B7AE +:107F4000B647850613861700B2C683C71700E389B4 +:107F5000E7FE1387F7FC2146E36AE61EB64C368B34 +:107F6000814D8146938707FD1387160085C73A9B8D +:107F70003385B6016E872148C14829466317A70299 +:107F8000850DB69DA14663CFE6022947B38BEB0270 +:107F90000147BE9BB64793861700B6C683C7170036 +:107FA000BA8641BF130700035DB793051700634608 +:107FB000E800B38BCB022E87D1B7E3CEB8FE330AED +:107FC000CA02D5BFC1460147E3C6B6FDA946330A7A +:107FD000DA023E9AC1B7014893072D00BEC6834717 +:107FE0002D00138707FD25466367E60C1307000382 +:107FF0006386E70A1387F7FC214681496364E60438 +:10800000B648138707FD2543294EB6471386170048 +:10801000B2C683C71700938507FD93F5F50F637606 +:10802000B3089569330616419389F9E1A148CE85D5 +:1080300063C6C800BA8963D3E500AE89630408004B +:10804000B309304163980D0CB3E6DA00E39906D426 +:10805000E31105DA1307E004638AE7066340F706D5 +:1080600013079004E397E7D897450000938585713F +:10807000E800EF20C03BE30E05D6B6479745000069 +:1080800093858570E800FD17BEC6EF20403A01E5F4 +:10809000B6478507BEC63704F07F11B3B6471386CF +:1080A0001700B2C683C71700A1B73307C703BA9733 +:1080B000138707FD99BFEAC6814969B71307900680 +:1080C000E384E7FA1307E006E395E7D2974500005B +:1080D0009385056CE800EF208035E30C05D0B647AA +:1080E00003C70700930780026313F702B0089745A0 +:1080F00000009385656BE800EF20603695476318B4 +:10810000F500F6453704F07FE6444D8C49B9370455 +:10811000F8FF71B1B38A694163130C006E8CC147DB +:108120006E8D63D3B701414D5E85EFE0AFC9A547C2 +:10813000AA842E8463DCB70393077DFF139737006F +:108140009747000093870778BA979043D443EFD0BE +:10815000CFFA2A845285AE84EFE0CFC62A86AE8657 +:108160002285A685EFC05F8EAA842E84BD4763CD8D +:10817000B709E3860AC2635450075947634357035C +:108180008E0A974700009387E773BE9A03A50A00FB +:1081900083A54A002686A286EFD02FF6AA842E84D5 +:1081A000FDBE130750023307B741634F5705B38D28 +:1081B000B741174900001309E97093973D00CA972A +:1081C0008843CC43B38DBA412686A2868E0DEFD06C +:1081D000CFF2CA9D03A60D0083A64D0075BFA95717 +:1081E00063C4FA02B3093B41139B3900974900006D +:1081F0009389496DDA9903A6090083A6490026856B +:10820000A285EFC07FF759BF338DAD41569D6357AF +:10821000A0119377FD0099CF174700001307876AD5 +:108220008E07BA978843CC432686A286EFD0EFEC20 +:10823000AA842E84137D0DFF63080D0A9307401353 +:1082400063D5A705014B814902C6814B93072002E4 +:108250002320F9003704F07F8144B247E38107B45B +:10826000C6454A85EF206056DE854A85EF20E055F9 +:10827000CE854A85EF206055B2454A85EF20E0540F +:10828000DA854A85EF20605419BE135D4D4026857E +:10829000A2858147014A05489748000093880860F5 +:1082A0006346A80599C3AA842E84174700001307C4 +:1082B000E75E93173A00BA978843CC433707B0FC80 +:1082C00022972686BA86EFD04FE33704F07FB37744 +:1082D000B4003707A07CAA84E366F7F63707907CE2 +:1082E000637AF7027D14FD54014ADDA813771D005F +:1082F00011CF13173A00469710435443EFD0EFDFE6 +:10830000854705489748000093884859050A135D3A +:108310001D4079B7370450032E94F9B7E3060DFCDE +:10832000330DA0419377FD0099CF17470000130745 +:1083300067598E07BA979043D4432685A285EFC02C +:10834000BFE3AA842E84135D4D40E30F0DF8FD4773 +:1083500063DDA701014B814902C6814B93072002CF +:10836000814401442320F900CDBD137A0D0163043B +:108370000A00130AA0062685A28597470000938766 +:10838000E743014793761D0081CA9043D4433EC61C +:10839000EFD0AFD6B2470547135D1D40A107E313E9 +:1083A0000DFE19C3AA842E8463050A029357440163 +:1083B00013F7F77F9307B006998F635CF0007D4752 +:1083C0006354F7221307400381446359F7203704AD +:1083D0007003014681462685A285EFD02FB53DD991 +:1083E0005E87EE866286E6854A85EF20C04B2AC608 +:1083F000E30A05E493D7FA41B3093B41B3F7F90027 +:108400003ED056CE63D30A0002CEB247014B81491B +:10841000B1073ED8B7071000FD173ED6B2474A85D0 +:10842000CC43EF20C031AA8BE30205E2B247C2552C +:108430003105904B09060A06EFE0EFAEB808D40804 +:108440002286A6854A8526CA22CCEF20D02BAAC830 +:10845000E30E05DE85454A85EF20405AAA89E307E9 +:1084600005DED64763C707180257724C338DE70005 +:108470006647B387474193066003BA97FD17930D8C +:1084800020C0998E63D6B7193387FD407D46998EFB +:108490006346E616854DB397ED003ED2814C369C7F +:1084A000B30DDD00529CEA8763D3AD01EE876353C1 +:1084B000FC00E2876358F000B38DFD40330CFC40B4 +:1084C000330DFD4082576358F002CE853E864A85C3 +:1084D000EF20C068AA89E30B05D64646AA854A85DF +:1084E000EF2080532ADAE30305D6C6454A85EF20FC +:1084F000C02DD257BEC8634FB011635A50017246A7 +:10850000DE854A85EF208065AA8BE30105D4635A96 +:108510008001DE8562864A85EF202070AA8BE30702 +:1085200005D2635AA001CE856A864A85EF20E06EA7 +:10853000AA89E30D05D0C6455E864A85EF20E07D19 +:108540002A8BE30505D0032CC500CE852326050024 +:10855000EF2080796359050C336C9C0063110C1279 +:108560009317C400639D0710B707F07FE18F3707AB +:10857000B0066376F71083274B0191E703270B01C1 +:10858000854763DEE70EDA8505464A85EF20E06819 +:10859000CE852A8BEF2040756353A00E630C0A1022 +:1085A000B707F07FE18F3707B0066345F71037074D +:1085B0007003E355F7DA0147B70750392685A285DE +:1085C0003A86BE86EFD06FB32E84C98DAA84E39914 +:1085D00005C8930720022320F90059B181177D5760 +:1085E000B317F7007D8CF5B37D57B317F700FD8CFB +:1085F000CDB37247025D330CF7409DBD930C20BE96 +:10860000B387FC40854CB39CFC0085473ED241BDFE +:10861000814CE5BFC6456E864A85EF200060AAC83A +:10862000E31D05EC25B169E9370710007D17B37725 +:10863000E40063090C046399E7047D5763000A02B0 +:10864000B707F07FE18FB706A00663E9F600D18394 +:108650009306B006B387F6403317F7006396E4023B +:10866000B707F07FFD176315F400FD57E380F4BEF4 +:10867000B705F07FE18D370410002E948144E31C90 +:108680000AF2F9BEC58F99DB63820C04B3FC8C003F +:10869000E3870CFE52862685A285630F0C02EFF05D +:1086A000CFDF2A86AE865245E245EFC0EFB9AA84F5 +:1086B0002E84F1B7B705F07FE18D3704F0FFA29566 +:1086C000370410007D144D8CFD5455BF9257B3FDF7 +:1086D0009700E3860DFA7DBFEFF02FDC2A86AE8689 +:1086E0005245E245EFD0EFEC01468146AA842E8444 +:1086F000EFD0CF8349F59DB1CE855A85EF20F00D9F +:1087000097470000938787059043D4432A8DAE8D09 +:10871000EFD04F936342A01063010C0A814D370DD7 +:10872000F03F0147B707F03FB706F07FB37CD400B6 +:10873000B706E07F639FDC166AD2370DB0FC229D3E +:108740002685EA853EDE3ADC6EDAEF20206CD258D0 +:1087500012582A86AE864685C285EFD00F9A2686A5 +:10876000EA86EFC06FAEAA843705F07F3376B50096 +:10877000B706A07C6257F2576365D60C6247930731 +:10878000F5FF6396E7005247FD57E381E7ACB70773 +:10879000F07F1384F7FFFD54C6454A85EF20E002C1 +:1087A000DE854A85EF206002CE854A85EF20E00114 +:1087B000DA854A85EF20600195B1B1E0B257E18FCB +:1087C000A1E7974700009387E7F89043D4436A8571 +:1087D000EE85EFD02F87634D050297470000938702 +:1087E000E7F69043D4436A85EE85EFD00F912A8750 +:1087F000AE87370D0080BA8D334DFD0035B7854704 +:108800006394F400E30C04B4814D370DF0BF11BF45 +:108810000147B707E03FF1BF97470000938707F391 +:108820009043D4436A85EE85EFD02F8D2A87AE879B +:108830002E8D63160C00370D0080334DBD00AA8DC0 +:10884000E5B5370450032E94E3180AF4B706F07F19 +:10885000E18EE393DCF4BE853A853A8DBE8CEFD091 +:10886000FFC8EFD03FCF2A86AE866A85E685EFD077 +:108870004FD4B2572A8DAE8DE18FC58F33EC87016F +:10888000630B0C0A97470000938747EE9043D4434D +:10889000EFC05FFBE346059C97470000938787ED99 +:1088A0009043D4436A85EE85EFC0FFEEE356A0EE19 +:1088B00045BA630D0A04B706A00663E99605974614 +:1088C0000000938626EA9042D4423A85BE853ADA81 +:1088D0003ED2EFC03FF7925752576344A0023A8509 +:1088E000BE85EF30601311E10545EFD0BFCD2A877B +:1088F000AE872E8D63160C00370D0080334DBD0002 +:10890000AA8DB705B0062E9D330D9D415245E24517 +:108910003EDA3AD2EF20804F2A86AE866E85EA850F +:10892000EFC0BFFD5246E246EFC00F92AA842E84EC +:10893000D257125711BF97470000938727E49043FF +:10894000D443EFC03FF0E35905E419BA13075006CA +:108950006387E7001307500405456397E7EE014B73 +:1089600005456FF08FD79387C1829C43945389E666 +:108970009776FF1F938606706FF00FB79387C182BB +:108980009C432E86945389E69776FF1F9386866EC6 +:10899000AA853E856FF04FB579714AD04ECE06D686 +:1089A00022D426D2AA892E899304190003C4F4FF85 +:1089B0003A8536C632C42EC23AC0EF1050402295D6 +:1089C0008347150002479245A18B2246B246C9E76C +:1089D0009307D0026314F40883C70400054393048B +:1089E0002900FDC641476392E60213070003639E18 +:1089F000E70083C704001307800593F7F70D63941E +:108A0000E70C83C71400C1468904B70800806314CB +:108A1000030093C8F8FF33FFD80201480145A54F72 +:108A2000E54EFD5233DED802138707FD63E4EF0401 +:108A3000BA8763DFD704630D58007D58636AAE00C0 +:108A40006314AE006346FF0005483385A6023E95D9 +:108A5000850483C7F4FFC9BF2689B9B79307B0025D +:108A60006305F400A2870143ADBF83C704009304EC +:108A70002900D5BF1387F7FB63E5EE00938797FCCA +:108A80004DBF1387F7F963E5EE00938797FA55B763 +:108A9000FD57631FF8009307200223A0F9004685C5 +:108AA00019EEB250225492540259F2494561828023 +:108AB000630403003305A0406DD66304080093856A +:108AC000F4FF0CC2F9BF93070003A1F2A14635BF22 +:108AD00013070003E38FE7F0A94605BF9387C18220 +:108AE0009C43985309E71777FF1F1307A7586FF0A8 +:108AF000BFEA1971A2DC86DEA6DA3284635B060067 +:108B00009307B0081CC17D55F6506654D6540961D0 +:108B100082803686930680202EC42ECC231AD10064 +:108B2000814519C09305F4FFFD572EC82ECEBA8695 +:108B30002C00231BF100AA84EF20B007FD576355DA +:108B4000F5009307B0089CC061D0A24723800700BE +:108B500065BF9387C1823687B2862E86AA858843F1 +:108B60006FF03FF9011122CC26CA4AC806CE4EC684 +:108B7000AA842E89328409C51C4D99E3EF10A018F0 +:108B800097470000938787CC631BF406C0401C4CBA +:108B90001CC48357C400A18BD9C31C48C9C31C483B +:108BA00008409379F90F1379F90F1D8D5C486347DD +:108BB000F500A2852685EF10E00235E51C44050589 +:108BC000FD171CC41C401387170018C023803701F1 +:108BD0005C486389A7008357C400858B89CBA9476C +:108BE0006317F900A2852685EF00D07F0DEDF240D6 +:108BF00062444A85D2444249B2490561828097471E +:108C000000009387A7C66314F400804449B79747D0 +:108C100000009387A7C1E31CF4F6C0448DBFA28572 +:108C2000268521202DDD7D59D9B741119387C18239 +:108C300026C2844322C44AC006C62A892E8491C40F +:108C40009C4C81E72685EF10000C97470000938726 +:108C5000E7BF631CF402C0400317C4009317070169 +:108C6000C18393F68700BDEE93F607019DEEA547FD +:108C70002320F900136707042316E4007D55B24052 +:108C80002244924402494101828097470000938721 +:108C9000E7BD6314F4008044C1B797470000938791 +:108CA000E7B8E31BF4FAC04445BF918B95C74C5815 +:108CB00091C9930744046385F5004A85EF2040433A +:108CC000232A04028357C4002322040093F7B7FD2C +:108CD0002316F4001C481CC08357C40093E7870088 +:108CE0002316F4001C4889EF8357C40013070020A3 +:108CF00093F707286386E700A2854A85EF101014D2 +:108D00008357C40013F7170005C75C4823240400E9 +:108D1000B307F0401CCC1C480145B5F38317C400D1 +:108D200013F7070829DF93E707042316F400B9B700 +:108D3000898B014791E3584818C4F1BF4111194587 +:108D400006C6EF2090200545EF30802C011122CC83 +:108D50001C49804906CE26CA4AC84EC652C456C2CD +:108D600063C187127D141318240093894501338A47 +:108D70000901130945014A9883270A0003270800BF +:108D80008507B354F7026366F706C1684E834A8EBF +:108D9000814E014FFD1811030326C3FF110E3377D7 +:108DA000160141823307970233069602769793564F +:108DB0000701B3771701B307FF4036968326CEFF2E +:108DC000935E06013376160133F71601BA97C18216 +:108DD00013D70741918EBA9613DF0641B3F71701F7 +:108DE000C206D58F232EFEFEE3776AFA832708009A +:108DF000BDCBAA8AEF10506F634905044166850414 +:108E0000CA8501457D16910903A8C9FF98419105BE +:108E1000B376C800158DB376C700AA96935707019D +:108E20001358080113D70641B3870741BA9713D5E2 +:108E30000741F18EC207D58F23AEF5FEE3753AFDEB +:108E400093172400CA9798431DC72685F2406244B1 +:108E5000D2444249B249224A924A0561828083271C +:108E6000080089E77D147118E36B09FF00C951B749 +:108E7000984309E77D14F117E36CF9FE23A88A00F3 +:108E8000E9B70145E1B775713ED85C5122C526C3EB +:108E90004AC1CEDED2DCE2D406C7D6DADAD8DED6D4 +:108EA000E6D2EAD0EECE36C23AC646CAAA842E84AC +:108EB0003289C2892E8A328C89EF4145EF10300207 +:108EC000C8D02322050023240500232005002326E3 +:108ED0000500DC508C4389CDD84385472685B39760 +:108EE000E7009CC5D8C1EF10500EDC5023A007004E +:108EF000635309048547131C190023A0F900135C70 +:108F00001C00B707F07F3377FC006314F706425765 +:108F10008967320C9387F770135CCC001CC3336CE9 +:108F20008C00E3050C32D24791EB97470000938702 +:108F3000A78F3EC039A823A00900E1B797470000DA +:108F40009387878E3EC0974700009387178E5247BE +:108F50001CC3BA402A4402459A440A49F659665A43 +:108F6000D65A465BB65B265C965C065DF64D49615B +:108F70008280014681462285E28522CE62D4EFC0FE +:108F8000EFFA05E1425785471CC3973700009387E6 +:108F900027773EC0D247D5DF9737000093875776B3 +:108FA0007DB7B800F4006286A285268513594C016E +:108FB000EF1070751379F97FAA89A64A630D09101D +:108FC000A2577245130919C09395C700B181B7071D +:108FD000F03FDD8D02DC974700009387A780904328 +:108FE000D443EFC01FDD974700009387278090434D +:108FF000D443EFC09F90973700009387A77F90439B +:10900000D443EFB07FA42A8B4A85AE8BEFD08FD4A8 +:10901000973700009387877E9043D443EFC0FF8D3E +:109020002A86AE865A85DE85EFB01FA22A8BAE8BCC +:10903000EFD0CFCB2A84014681465A85DE85EFC02A +:109040007F80635B05002285EFD0CFD05A86DE8615 +:10905000EFC0CFED11C17D140547D9473AD663E380 +:10906000870213173400974700009387A785BA97A4 +:109070009043D4437245A255EFC0CFFC6353050023 +:109080007D1402D633892A41930BF9FF014B63D635 +:109090000B00054B330B2B41814B634E0406A29B07 +:1090A00022CC814A1247A54763E5E7149547854CD2 +:1090B00063D6E7009307C7FF3EC2814C12478D4736 +:1090C000630EF71063CFE704894702C8630DF70604 +:1090D00085473EC88DA0364993070002569913076D +:1090E000294363D5E70213050004198D930729412D +:1090F0003315AC003354F400418DEFD0AFCCB7073B +:1091000010FEBE9585477D193EDCF1B53385E740FD +:109110003315A400DDB7330B8B40B30A804002CC7B +:1091200051B712479147630EF70005473AC81247F7 +:1091300095476306F70AFD573EC4FD5DC94702C661 +:1091400019A885473EC8B2476348F00A85470547D6 +:109150003EC4854D3AC603A94402114723220900A3 +:10916000930647018325490063FCD7082685EF1045 +:10917000005DDC502320A9009C433EC0B94763E654 +:10918000B71D63840C1C635E800A9377F400139709 +:109190003700935C4440973700009387A772BA97D3 +:1091A00093F60C0198430949DC4385C697360000C5 +:1091B0009386C66E90527245D452A2553AD03ED292 +:1091C000EFB09FFB0257925793FCFC002A8A2E8C2B +:1091D0000D49173D0000130D6D6C89A802C8B247F8 +:1091E000A2973EC4938D1700EE87E346B0F78547FC +:1091F0009DB7854C02C2E9BDB2473EC4BE8DA1BF3A +:1092000085052322B9000607A1BF93F61C0081CE75 +:1092100003260D0083264D003A85BE85EFC0EFED95 +:1092200005092A87AE8793DC1C40210DE39F0CFCC7 +:109230003A86BE865285E285EFB01FF42A8A2E8CCC +:1092400081A0094915CCB30C804093F7FC0013971B +:109250003700973700009387E766BA979043D44367 +:109260007245A25593DC4C40173D0000130D0D6371 +:10927000EFC0AFE82A8A2E8C8147639C0C12DDFF79 +:10928000B25763870714173700001307A74C104322 +:1092900054435285E28552D0EFC0CFDA635A0512AB +:1092A000638B0D12A2476350F00A173700001307B3 +:1092B00067558257104354433E85E285EFC0EFE384 +:1092C000A247130DF4FF2A8A2E8C050962874A856E +:1092D0003EDE52DABA8C3AD0EFD0CFA752580257BE +:1092E0003709C0FC4286BA86EFC02FE197360000EE +:1092F0009386C6519042D442528CEFB0EFF4F257AD +:109300002A8A2E99E1EF973700009387A750525889 +:1093100002579043D4434285BA85EFC09FA9528635 +:10932000CA862A8CAE8CEFC00FC7634AA054B70719 +:109330000080B3C727015286BE866285E685EFC0EE +:109340006FD0634B0552724A225CB64763C7073041 +:1093500039476344873013173400973700009387E9 +:109360006756BA9703AB070083AB4700B24763D297 +:1093700007206340B02163910D5097370000938719 +:1093800067499043D4435A85DE85EFC00FD7528694 +:10939000E286EFC04FC0814A01496357054A8247C0 +:1093A00002470504138A1700930710032300F700F0 +:1093B00045A113F71C0009CB03260D0083264D00A1 +:1093C0000509EFC08FD3854793DC1C40210D75B58F +:1093D000228DEE87E5BD228D8147CDBD9386F7FFB7 +:1093E00013963600973600009386C64DB296884293 +:1093F000CC428246B6973EDAC247E9C397370000AF +:109400009387C7342A86AE868843CC434ADE52D03F +:10941000EFB09FD602587257173900001309893EE2 +:109420004286BA86EFC0FF98024A2AD02ED2E6853D +:109430006285EFD0AF8B2ADEEFD0CF912A86AE8641 +:109440006285E685EFC0FF96F2572A8CAE8C2A869D +:10945000AE8602559255050A93870703A30FFAFEBD +:10946000EFC06FB36348A00E973700009387872E35 +:109470008843CC436286E686EFC0BF932A86AE86D9 +:1094800002559255EFC02FB16342A018D257E30C9A +:10949000FAEA032609008326490002559255EFC0D7 +:1094A000CFC503260900832649002AD02ED2628523 +:1094B000E685EFC08FC42A8CAE8C95BF5286CA86D3 +:1094C000EFC0AFC3525A02492AD02ED2E685628538 +:1094D000EFD0CF812ADEEFD0EF872A86AE86628575 +:1094E000E685EFC01F8D7257D25705091307070392 +:1094F000A30FE9FE2A8CAE8C6312F906173900001F +:109500001309C924032609008326490002559255F0 +:10951000EFB08FD32A86AE866285E685EFC0AFA70F +:109520006346A00E02569256032509008325490082 +:10953000EFC03F882A86AE866285E685EFC08FB091 +:1095400093070003E35105E00347FAFF9306FAFF90 +:109550006304F7006A8459A8368AFDB7973700007C +:109560009387472A9043D443EFC02FB92A8CAE8CFF +:10957000B1BFE287BE8C8247528C973A0000938A33 +:109580006A2813891700BE9D5A86DE866285E685A5 +:10959000EFB09FBEEFC09FF52A8DEFC0BFFB5A868C +:1095A000DE86EFC08FB52A86AE866285E685EFC07F +:1095B0005F8093070D03A30FF9FE2A86AE864A8AC1 +:1095C000639E2D07EFB04FC85A86DE862A8CAE8C7C +:1095D000EFC06F9C634BA0025A86DE866285E685EB +:1095E000EFC0CF9401E593771D0085E3CE852685F6 +:1095F000EF10A01DC25723000A00050480C3D24704 +:10960000E389079423A04701A9B2228D1307900391 +:109610008346FAFF9307FAFF639AE6008246639D4A +:10962000F60013070003050D2380E60003C70700BB +:1096300005072380E70039BF3E8AD9BF03A60A0089 +:1096400083A64A000509EFC04FAB014681462A8C2C +:10965000AE8CEFC0AF8D0DF951BF424763000710CC +:10966000924605476345D70C62579387374309E70E +:10967000264793076003998F568DDA8C854526859A +:109680003E9BBE9BEF1080372A89635E9001635C2E +:109690007001E68763D39B01DE87330BFB40B38CFD +:1096A000FC40B38BFB4063800A04C247C5CF6354C0 +:1096B000A003CA856A862685EF10404A4E86AA8591 +:1096C0002A892685EF1040352ACECE852685EF10D3 +:1096D000C00FF247BE893386AA4111C6CE852685C2 +:1096E000EF10C047AA8985452685EF102031E24753 +:1096F000AA8A635BF0063E86AA852685EF1000469F +:1097000012478547AA8A014D63C8E706014D6312D7 +:109710000A069317CC00528DA9EFB705F07F337C72 +:10972000BC0063080C04050B850B054D99A0138D37 +:10973000FDFF63CAAA01338DAA4163DE0D00B30C9D +:10974000BB41814725BFE247B30A5D41D6973ECC76 +:10975000EA8A014DDDB7DA8CEE870DB7568DDA8CCB +:10976000014925B756869DBF12478547014DE3DF66 +:10977000E7F8E247054589CF83A70A018D078A07E5 +:10978000D697C843EF10801C930700023385A7408B +:109790005E957D8951C193070002898F1147635AF5 +:1097A000F706F1473385A7402A9BAA9CAA9B6358DA +:1097B0006001CE855A862685EF102046AA89635817 +:1097C0007001D6855E862685EF102045AA8AB2579D +:1097D000B1C7D6854E85EF10205163510504CE8563 +:1097E000814629462685EF108002C2477D14AA894A +:1097F000638C0726CA85814629462685EF102001FD +:10980000A2472A896345F0081247894763D1E708D0 +:1098100029A8E38EE7F83E85710579B76345B0075F +:109820001247894763D1E7066EC4A24791EFD685F8 +:10983000814615462685EF00907DAA8AAA854E8529 +:10984000EF10804AE34DA0B4B247024A13C4F7FFB9 +:10985000014BD6852685EF005077E30909D86308C8 +:109860000B0063062B01DA852685EF001076CA858A +:109870002685EF0090759DBB814A0149F1B76A8446 +:10988000814A014929BEC2476EC46386071E6358D8 +:109890009001CA8566862685EF1020382A894A8578 +:1098A00063060D02832549002685EF0050690326D3 +:1098B00009012A8B9305C90009060A063105EFC084 +:1098C0009FE60546DA852685EF1020358247224738 +:1098D0004A8B138C1700BA973EC693771A002A89D1 +:1098E0003EC4D6854E85EFF06FC6DA852A8D930D7E +:1098F00005034E85EF10403F4A86AA8BD685268504 +:10990000EF10A0415045930CFCFF2A8A054711E651 +:10991000AA854E85EF10403D2A87D28526853AC814 +:10992000EF00B06A92474247628AB3E6E700A24777 +:10993000DD8E81EE130790036388ED04635470019C +:10994000930D1D032380BC0129B763CA0B00924706 +:10995000B3EB7701A247B3EBFB0063950B04E35332 +:10996000E0FECE8505462685EF10202BD685AA89F8 +:10997000EF1080376346A00071F513F71D0079D30F +:1099800013079003E39EEDFA930790032380FC00F6 +:10999000930690038347FAFF1307FAFF638CD708F7 +:1099A000850745A0635BE00013079003E38EEDFCA1 +:1099B00093871D002380FC0069BDB247A30FBCFF45 +:1099C00063818705CE85814629462685EF00306470 +:1099D000AA8981462946DA85268563182B01EF007E +:1099E00010632A8B2A89050CEDBDEF005062CA85F1 +:1099F0002A8B814629462685EF0070612A89E5B7C2 +:109A0000014BCE8505462685EF102021D685AA89F3 +:109A1000EF10802DE34EA0F601E593F71D00ADFB9E +:109A2000930700030347FAFF9306FAFFE313F7E2F5 +:109A3000368ACDBF82476399E70002470504930742 +:109A400010032300F70031B53A8AA9B75247973778 +:109A500000009387A7DC3EC097370000938787DC20 +:109A6000631707CE6FF0EFCEA2476346F0001247B0 +:109A70008947E3CCE7DA024AD6854E85EFF00FAD91 +:109A80008247050A930D05033307FA40A247A30F47 +:109A9000BAFFE357F7F6CE85814629462685EF00C3 +:109AA0001057AA89D1BF83D7C500011122CC26CA7D +:109AB00006CE4AC84EC613F78700AA842E8479EFD3 +:109AC000D841634DE000B841634AE0000145F240EF +:109AD0006244D2444249B2490561828058547DD7DC +:109AE00003A904009396370123A0040063DE060651 +:109AF00070488357C400918B99C75C401D8E5C5899 +:109B000099C33C401D8E5C540C508146268582973B +:109B1000FD570357C400631DF5009440F54763E902 +:109B2000D706B70740208507B3D7D700858BADC3CD +:109B30001C48232204001CC09317370163D8070078 +:109B4000FD576314F5009C4091E368C84C5823A06E +:109B50002401ADDD930744046385F5002685EF10ED +:109B60002059232A04029DB70C50014685462685BC +:109B70000297FD572A86E31EF5F69C40BDDB75472C +:109B80006385E70059476394E70423A024013DBFA0 +:109B9000136707042316E4007D5515BF83A905014B +:109BA000E38609F203A905008D8B23A03501330953 +:109BB0003941014791E3D84918C4E35920F11C54B5 +:109BC0000C50CA864E86268582976349A00083572B +:109BD000C40093E707042316F4007DBFAA99330954 +:109BE000A940E1BF9C49A5C3011122CC06CE2A841D +:109BF00011C51C4D81E72EC63922B24597370000AA +:109C00009387C7C4639CF5004C408397C5009DC7EC +:109C100022856244F24005616FF0FFE8973700004B +:109C20009387C7C46394F5000C44C5B79737000009 +:109C30009387C7BFE39BF5FC4C44C1BFF24062442D +:109C400001450561828001458280411122C406C61A +:109C50002A842316B5002317C500232005002322DC +:109C60000500232405002322050623280500232AB6 +:109C70000500232C0500214681451305C505EF602D +:109C80008FF0972700009387C7B05CD0972700001C +:109C9000938727B31CD497270000938767B75CD4BA +:109CA00097270000938727BA00D01CD8B2402244DF +:109CB0004101828097050000938505F399AA41111F +:109CC00026C2130680069384F5FFB384C4024AC0FB +:109CD0002E8922C406C693854407EF10E04B2A84E0 +:109CE00001CD2320050023222501310508C4138658 +:109CF00084068145EF602FE92285B24022449244D8 +:109D00000249410182801C4DA5E7411106C622C4CB +:109D100097070000938747FA1CD5938781849C435B +:109D20002324050423260504232805046314F500D1 +:109D300085471CCD2A84352848C022851D2808C4A3 +:109D40002285052848C4484001469145EFF0FFEFC1 +:109D500008440546A545EFF05FEF48440946C9456C +:109D6000EFF0BFEE85471CCCB24022444101828017 +:109D7000828041119387818426C284434AC006C6EB +:109D80009C4C22C42A8981E72685EFF0DFF7938473 +:109D900084048044DC40FD1763D607009C40B9CFA3 +:109DA0008440C5BF0317C40039E7C1778507232264 +:109DB00004062320040023220400232404005CC49E +:109DC00023280400232A0400232C04002146814573 +:109DD0001305C405EF602FDB232A0402232C0402A1 +:109DE00023240404232604042285B24022449244FE +:109DF0000249410182801304840671BF91454A855E +:109E0000EFF0FFEB88C049FDB1472320F900014482 +:109E1000E1BF797122D44AD052CC56CA5AC85EC624 +:109E200006D626D24ECE2A8AAE8A1304850401496C +:109E3000054BFD5B09ECB25022544A8592540259FD +:109E4000F249624AD24A424BB24B45618280044495 +:109E500083294400FD1963D409000040E1BF83D782 +:109E6000C400637BFB008397E40063877701A685CA +:109E70005285829A3369A90093848406E1BF104910 +:109E80009306450113D75540B6876356C7020A06A5 +:109E90000A07FD8936963697B9C913084700184353 +:109EA000130300023303B3403357B700636EC80097 +:109EB00098C311C391073387D740098718C96394A2 +:109EC000D700232A05008280832808009107110803 +:109ED000B398680033E7E80023AEE7FE0327C8FF26 +:109EE000E1B711078325C7FF910723AEB7FEE36AE9 +:109EF000C7FED1B7930705FD93F7F70F25476367B3 +:109F0000F70001159377F50F3E8582809307F5F9E9 +:109F100093F7F70F954663E5F600130595FBDDB75C +:109F20001307F5FB1377F70F8147E3EFE6FC130503 +:109F300095FDC9BF1D71D6C2AA8A428536C63AC2EE +:109F400086CECAC8D2C4DAC05EDE3E8B6ED63289F7 +:109F5000AE8DA2CCA6CACEC662DC66DA6AD89D25D2 +:109F6000832B05005E85EFD0FFCFB387AB0083A6C0 +:109F70000D0083C7F7FF7957158F3EC82A8A93874C +:109F80002600930600033306F700BE84850703C549 +:109F9000F7FF32C4E309D5FEEFF0DFF5631F0510CC +:109FA0005286DE852685EF10300A631D0510338C3E +:109FB000440103450C00EFF0FFF363060510E28453 +:109FC0009307000303C50400630BF500EFF09FF255 +:109FD000854793391500E28C3EC4268C21A0850468 +:109FE000D5B7050C03450C00EFF0DFF07DF9528684 +:109FF000DE856285EF10500511E9639C0C00529CD0 +:10A00000E28C03450C00EFF0FFEE5DE9014463854F +:10A010000C0033848C410A0483470C0013070005AD +:10A020006387E70013060007E28C6390C706834747 +:10A030001C001307B002638BE7081307D002638B81 +:10A04000E708930C1C00014D03C50C00EFF09FEADC +:10A050009307F5FF93F7F70FE14563E4F5089307DE +:10A0600005FF850C03C50C003ECAEFF0BFE8930561 +:10A07000F5FF93F5F50F6148D247A948637EB80410 +:10A0800063040D00B307F0403E9423A09D01638C50 +:10A090000904A247814491E39944F6406644268529 +:10A0A0004649D644B649264A964A064BF25B625C5C +:10A0B000D25C425DB25D256182808149814C31BFB5 +:10A0C000050C81B7268C01448549B9B7014D930C25 +:10A0D0002C009DBF054DE5BFB3871703AA97C11795 +:10A0E00049B7E28C5DB7B3079C40FD1781451D471A +:10A0F0006344F70A5685A125054693094501B30730 +:10A100004641AA8D4E8D8148814C3ECA63E984093F +:10A1100013054D0033053541098523209D0123A8F2 +:10A12000AD00931455006685EF005002832B0900A3 +:10A13000898C63D89B0CB3847441A6856E85EF002F +:10A1400070742A8A05C91386F4FF935656408A060E +:10A15000CE96944205473317C700758F054A19CB31 +:10A160006359CA009385E4FF6E85EF00B0710D4A14 +:10A1700011E1094AA6856E85EFF07FD0269403276A +:10A180008900635F8708EE85568581259247930491 +:10A19000300A23A0070011B78505858791BF930773 +:10A1A000FCFF3EC40346FCFFC2476309F602930767 +:10A1B00000026397F80023209D018148110D814C16 +:10A1C0000345FCFF46CCEFF0FFD2E2483D89224335 +:10A1D00033151501B3ECAC00910815A05247930755 +:10A1E000FCFF3383E700E36493FC1A855286DE8527 +:10A1F00046CE1ACCEF1040656243F2484DF91A8CF6 +:10A2000031B7014AE3DD74F7B3849B40EE852686BF +:10A210005685EF009020AA8D058C9309450185B7DE +:10A22000032749006355E40E3304874063457407F0 +:10A230000327C9008946630AD7048D46630AD704F9 +:10A240008546631BD70263998B026391EB02032758 +:10A250004900B2479304200698C30547924723A8B4 +:10A26000ED0023A0E90023A0B70105BD9385FBFF06 +:10A270006E85EF00306161FDEE855685B92392470A +:10A280009304000523A0070009BDE3170BFEC1B727 +:10A29000E31F0BFAD5B79304F4FF63180A0691C4C1 +:10A2A000A6856E85EF00105E2A8A13D754400A07F0 +:10A2B0004E9718438545B3959500F98D99C1136A5A +:10A2C0002A00A2856E85B38B8B40EFF05FBB032421 +:10A2D00049008944630B0A080327C9008946630AB9 +:10A2E000D7028D46630AD7028546631DD7001377D0 +:10A2F0002A0009CB03A70900336AEA00137A1A007F +:10A30000631E0A0093E404018DA0054A79BF8544C9 +:10A31000D1B70547330B6741E3060BFE83A90D0157 +:10A3200013874D01FD55139A290033064701144345 +:10A330006383B604850614C3894613874D0163946D +:10A34000D40883260900FD16639F760193D65B40EF +:10A350008A06369718438546B39B7601B3FBEB001C +:10A3600063830B00854493E40402924723A0B70162 +:10A37000B24780C31DB31107232E07FEE369C7FA56 +:10A3800003A78D0063C5E90283A54D0056858505A9 +:10A390007D2603A60D019385CD002A8B09060A06AA +:10A3A0003105EFC04FB8EE8556850521DA8D03A73C +:10A3B0000D019306170011070A0723A8DD006E9709 +:10A3C000854654C395BF83A60D0163DCD90085453E +:10A3D0006E85EFF0DFAA032789000504E35487F8B0 +:10A3E0005DB393FBFB018544E38F0BF65297032586 +:10A3F000C7FFA92B13070002B30B7741E34975FD93 +:10A400009DB7A1473386C7400A0693060002918E86 +:10A410005C41184111053398D70033670701B3D762 +:10A42000C700232EE5FE1CC1E364B5FE82801C41FB +:10A430006548850503C6F5FF850701E61CC105458E +:10A44000828003C707009306F7FB93F6F60F636459 +:10A45000D80013070702E30EC7FC014582805D7137 +:10A4600052DC03AA0500A6C24EDE93545A405AD8C5 +:10A470008A0486C6A2C4CAC056DA5ED662D466D240 +:10A480006AD06ECE137AFA012A8BB289B294630332 +:10A490000A00910483270B001389C4FF23AE04FE36 +:10A4A000CA8D4A840146814A814B214C930C00029B +:10A4B0001D4D83C61700138717003AC0B1CA3685F1 +:10A4C00032C63EC436C2EFF0FFA2324659E592468C +:10A4D000A24763E8DC0263D47A036378B40163467D +:10A4E000CD00EE852285EFF0DFF1214663F989008A +:10A4F000930DC4FF232E04FEDE8A6E84014682473C +:10A500004DBF93059002639CB60889072320FB008A +:10A5100063870B086379B4019D4763C6C700EE8566 +:10A520002285EFF01FEE63FA8904CE87110403271A +:10A53000C4FF910723AEE7FEE37A89FE910723AEBD +:10A5400007FEE37DF9FE8327090091E763173905CC +:10A5500085472320F9001545A1A00506850B635802 +:10A56000CC00E3FE89F8232E04FE054671141C403E +:10A570003D899207C98F1CC059B7E3060AFC9307AF +:10A580000002B38747417D5AB357FA0003AAC4FFBC +:10A59000337AFA0023AE44FF7DB771196DB71145C8 +:10A5A000B640264496440649F259625AD25A425B52 +:10A5B000B25B225C925C025DF24D61618280032598 +:10A5C000C50E82801305050F82809387C1829C434C +:10A5D000885309E51765FF1F1305C5A91305050F66 +:10A5E00082801971A6DAAE848395E500A2DC86DE4E +:10A5F000328463DC050083D7C40023A0060093F7F0 +:10A60000070885E7930700401DA0300836C6EF1005 +:10A61000C02EB246E34105FE7247BD67F98F7977D8 +:10A62000BA9793B717009CC2F1BF930700041CC0F0 +:10A63000F6506654D65401450961828083D7C5001F +:10A64000011122CC06CE26CA4AC8898B2E8489CF16 +:10A65000930774041CC01CC885475CC8F240624460 +:10A66000D24442490561828074003000AA84EFF030 +:10A670005FF7A2452A892685EF00103201ED831786 +:10A68000C40013F7072079FBF19B93E727002316FB +:10A69000F4007DBF97F7FFFF938707629CD4835731 +:10A6A000C40008C008C893E707082316F400A247AF +:10A6B0005CC8B24791CF8315E4002685EF100027D0 +:10A6C00001C98357C400F19B93E717002316F400D8 +:10A6D0008357C4003369F9002316240141B79387D7 +:10A6E000C182AA8588436F00302B85E141116C003F +:10A6F000014511CA795581CA834706009CC10345AB +:10A7000006003335A00041018280014519CA795500 +:10A7100089CA834706009CC1034506003335A00063 +:10A720008280828093F5F50F2A966314C500014557 +:10A73000828083470500E38DB7FE0505FDB75C51B8 +:10A74000411122C44AC006C626C22A842E8989EF36 +:10A750004145EFF0DFF848D023220500232405000F +:10A7600023200500232605004450DC449DC7585093 +:10A77000931729005847BA97884329E18544B39431 +:10A780002401138654000A0685452285EF00F01344 +:10A7900019CD2322250104C525A0130610029145D9 +:10A7A0002285EF0090125C50C8C4DC47E9F30145F4 +:10A7B000B24022449244024941018280184198C328 +:10A7C0002328050023260500E5B75C51011122CCA2 +:10A7D00006CE2A8499EF41452EC6EFF05FF0B245D0 +:10A7E00048D023220500232405002320050023262A +:10A7F000050091C95450DC4113972700DC46BA97F5 +:10A80000984398C18CC3F24062440561828079719B +:10A810004ECEAA89416522D426D22E84844906D6FA +:10A820004AD0D10501487D159C419105050833F7B3 +:10A83000A7003307C702C183B387C7023697935671 +:10A840000701698FB69793D60701C207BA9723AE5F +:10A85000F5FEE34B98FCA1C21C4463C7F4024C40D4 +:10A860004E8536C68505EFF09FED10489305C40070 +:10A870002A8909060A063105EFB0FFEAA2854E854E +:10A88000EFF0BFF4B2464A84938744008A07A29748 +:10A89000D4C3850404C82285B2502254925402596C +:10A8A000F2494561828079719387860052CC368A5D +:10A8B000A54622D426D24ECE2E84B3C7D70206D6C2 +:10A8C0004AD056CAAA89B2848546814563CCF6042B +:10A8D0004E853AC6EFF0BFE6324785471CC958C9D6 +:10A8E000A54763D49704930A9400568926940509D2 +:10A8F0008346F9FFAA852946938606FD4E85EFF02B +:10A900001FF1E31689FE138484FF56942689634160 +:10A910004903B250225492540259F249624AD24A2F +:10A92000456182808606850555B72904A544F9BF8F +:10A93000B3079940A29783C60700AA852946938644 +:10A9400006FD4E85EFF0BFEC0509D1B74177698F61 +:10A95000AA87014519E3C2074145370700FF7D8FEC +:10A9600019E32105A207370700F07D8F19E31105D0 +:10A970009207370700C07D8F19E309058A0763C96D +:10A98000070013971700050563440700130500022D +:10A9900082801C4113F777000DC393F6170001471F +:10A9A00099E613F7270011C785831CC105473A852F +:10A9B000828089831CC10947DDBF93960701C1824C +:10A9C000014799E2C183414793F6F70F99E22107C6 +:10A9D000A18393F6F70099E21107918393F637006C +:10A9E00099E20907898393F6170081E685830507B5 +:10A9F00099C31CC16DBF1307000255BF411122C48A +:10AA00002E84854506C6EFF09FD340C9B24022444C +:10AA1000054718C94101828098491C4A797126D29C +:10AA200006D622D44AD04ECEAE846354F700B28408 +:10AA30002E8683A90401032906019C44CC4033845B +:10AA4000290163D38700850532C6EFF05FCF324618 +:10AA500013084501131324004293C28763ED670274 +:10AA600093854401939829005106131E2900C1665D +:10AA7000AE98329EFD166364C60363568000711360 +:10AA800083270300F1CB00C9B250225492540259DB +:10AA9000F2494561828023A007009107C1B7832F47 +:10AAA0000600B3FFDF00638A0F04428FAE82814449 +:10AAB00003A7020083230F00110FB37ED700B38ECC +:10AAC000FE03B3F7D30093D303019102BE9E9357C5 +:10AAD0000701B387F703A69E13D70E01B3FEDE006E +:10AAE0009E97BA9793D40701C207B3E7D701232EE5 +:10AAF000FFFEE3EF12FB23209F0083522600638AB0 +:10AB0000020483270800C28E2E8F814F03270F0077 +:10AB100083D32E00F58F758F33075702910E110FD7 +:10AB20001E977E97931F0701B3E7FF0023AEFEFE3B +:10AB30008357EFFF83AF0E004183B3875702B3FF04 +:10AB4000DF00FE97BA9793DF0701E3611FFD23A0A3 +:10AB5000FE001106110805B77D1405B7011126CABC +:10AB60004AC84EC606CE22CC52C4937736002A89F4 +:10AB7000B284AE8989CFFD1717270000130707E1BC +:10AB80008A07BA9790438146EFF07FC8AA898984E3 +:10AB9000A5CC8327490291EF4145EFF05FB4232212 +:10ABA000A9022322050023240500232005002326D3 +:10ABB0000500032A490203248A0019E89305102797 +:10ABC0004A85EFF0BFE32324AA002A84232005004E +:10ABD00093F7140081CFCE8522864A85EFF0DFE31C +:10ABE0002A8ACE854A85EFF05FBED289858489CCDA +:10ABF000084009E92286A2854A85EFF0FFE108C0F6 +:10AC0000232005002A84E9B7F24062444E85D244ED +:10AC10004249B249224A05618280797126D2AE84C6 +:10AC20004ECE83A9040122D4CC41135456409C44F7 +:10AC3000A2994AD056CA06D652CCAA8A13891900BC +:10AC400063C42709568532C6EFF07FAF32469307BB +:10AC500045012A8ABE8601479106634A87066353E7 +:10AC60000400014494480A04338787008A069387C6 +:10AC700044017D8ABE9625C2130800023308C840ED +:10AC800081458843110791073315C500C98D232ECF +:10AC9000B7FE83A5C7FFB3D50501E3E4D7FE0CC318 +:10ACA00099C1138929007D1923282A015685A68573 +:10ACB000EFF0BFB1B2502254528592540259F2497A +:10ACC000624AD24A456182808505860795BF23AED8 +:10ACD00006FE050751B7910703A6C7FF1107232EEC +:10ACE000C7FEE3EAD7FEC1B71C499849998F8DE3A7 +:10ACF0000A075105D105B306E500BA95F116F1151D +:10AD0000904298416308E600FD576363E60085477B +:10AD10003E858280E364D5FEE5BF011126CAAE847C +:10AD20004EC6B285AA89268522CC06CE4AC8328470 +:10AD3000EFF09FFB05E181454E85EFF05FA0854771 +:10AD40001CC9232A0500F2406244D2444249B24958 +:10AD500005618280054963460500A2870149268472 +:10AD6000BE844C404E85EFF09F9D0323040183A8D1 +:10AD7000040113064401131E2300138844018A08AA +:10AD8000C16E23262501329EC29893064501014FCC +:10AD9000FD1E1842832F08009106B375D701B3F743 +:10ADA000DF01FA959D8D93DF0F0193570701B3875C +:10ADB000F74113D70541BA9713DF0741B3F5D50122 +:10ADC000C207CD8F110823AEF6FE1106E36318FD0E +:10ADD000C165FD156368C601F1169C4295C723281D +:10ADE000650095B71C429106110633F7B7007A97B4 +:10ADF00013580741C183C29713DF07416D8FC20704 +:10AE0000D98F23AEF6FEF9B77D13F9B7B707F07FF8 +:10AE1000FD8DB707C0FCBE956355B00081473E85E8 +:10AE20008280B305B04093D745414D476347F70053 +:10AE3000B7050800B3D5F540D5B71387C7FEF94667 +:10AE400081458547E3CDE6FCB7070080B3D7E7002F +:10AE5000F9B7797126D204494ECE930945018A0487 +:10AE6000CE9422D403A4C4FF4AD02EC6228506D68F +:10AE7000EFF0DFADB24593070002898F9CC1A9476F +:10AE80001389C4FF63CDA702AD47898F3707F03F11 +:10AE9000B356F400D98E014763F4290103A784FF58 +:10AEA00055053315A400B357F700C98FB25022548B +:10AEB00092540259F2493E85B685456182808147A8 +:10AEC00063F6290183A784FF138984FF551505C9FB +:10AED000130700023306A74033D7C7003314A4007A +:10AEE000598CB706F03FC18E014763F4290103274F +:10AEF000C9FFB397A7003357C700D98F45BFB7061F +:10AF0000F03FC18E65B7797122D42E84854526D253 +:10AF10004AD0B2844ECE52CC3A8906D6368AEFF069 +:10AF20001F82370710009307F7FFE58FD18093F456 +:10AF3000F47FAA89B5E03EC62DC4280022C4EFF0F4 +:10AF40005FA5A24621CD324793070002898FB31730 +:10AF5000F700D58F3357A70023AAF9003AC6324429 +:10AF600023AC890033348000050423A88900B9C4C8 +:10AF70009384D4BCAA949307500323209A0033856A +:10AF8000A7402320A900B25022544E859254025962 +:10AF9000F249624A45618280D98F71BF23AAD900E4 +:10AFA0007DBF6800EFF0FF9EB24713050502054420 +:10AFB00023AAF900854723A8F90055BF9317240059 +:10AFC0001305E5BCCE972320AA00884B1604EFF0AA +:10AFD000FF97098C232089007DB779714AD02E898B +:10AFE0002C0006D622D426D24ECE52CC2A8AEFF09E +:10AFF0005FE6AA89AE842E844A856C00EFF07FE577 +:10B000008327090103270A01A2461D8FB2471607AD +:10B010009D8EB307D7006355F002D2072E86338486 +:10B0200097003287A2852A86BA864E85EFA0CF94F4 +:10B03000B250225492540259F249624A45618280C8 +:10B040003707F0FFB387E7023386B700D9BF93878E +:10B05000F5FF184A958785078A07930646010A0770 +:10B06000AA97369763E5E600636AF5008280910649 +:10B0700003A6C6FF1105232EC5FEEDB71105232E2D +:10B0800005FEDDB7144993D755401307450163C743 +:10B09000F60263DFD700FD8981CD93962700BA962B +:10B0A00090420545B356B600B395B600631EB60090 +:10B0B0008A07BA976366F70001458280B687CDBFDD +:10B0C000F1179443E5DA054582803386C502011104 +:10B0D00022CC06CEB28532C6C1202A8409C53246AA +:10B0E0008145EF504FAA2285F2406244056182807B +:10B0F000DDC183A7C5FF411122C406C626C2138441 +:10B10000C5FF63D307003E94AA84EF0070089387BD +:10B1100001879C4381EF2322040023A881862244D7 +:10B12000B2402685924441016F00B006637EF40070 +:10B1300014403307D4006396E7009843DC43369706 +:10B1400018C05CC0D9BFBA87D84319C3E37DE4FEF9 +:10B1500094433386D700631F86001040B29694C391 +:10B160003386D700E31DC7FA10435843B29694C301 +:10B17000D8C375B76375C400B1479CC04DB71040C4 +:10B18000B306C4006316D70014435843B29614C0E4 +:10B1900058C0C0C369B78280011126CA93843500A4 +:10B1A000F19806CE22CC4AC84EC6A104B14763F33B +:10B1B000F404B14463E2B4042A89EF00607D93870C +:10B1C000018798433A8439E0938741879C4391E70C +:10B1D00081454A85CD2123AAA186A6854A85E129F4 +:10B1E000FD5963193507B1472320F9004A85EF005F +:10B1F000407A29A0E3D004FCB1471CC10145F240CC +:10B200006244D2444249B249056182801C40858F24 +:10B2100063CF0702AD4663F6F6001CC03E9404C03F +:10B2200031A05C406313870223A8F1864A85EF00B2 +:10B2300040761305B4009307440061993307F54045 +:10B240005DDF3A94898F1CC05DBF5CC3C5B72287A0 +:10B25000404095BF130435007198E30285FCB305A7 +:10B26000A4404A858929E31C35FBB5BF81E5B28539 +:10B270006FF09FF2011122CC06CE26CA4AC84EC6F4 +:10B28000328401EEEFF0DFE60149F24062444A8584 +:10B29000D2444249B24905618280AE84AA89DD2D3B +:10B2A0002689E37485FEA2854E85EFF0FFEE2A899C +:10B2B00069DDA6852286EFB00FC7A6854E85EFF023 +:10B2C0003FE3E1B701114AC803A9850022CC52C46B +:10B2D0005AC006CE26CA4EC656C22E84328B368A35 +:10B2E00063EE260983D7C50013F7074851C704400A +:10B2F0008C495848AA8AB389B4408D44B384E40287 +:10B300000947B3C4E402138716004E9763F3E400C1 +:10B31000BA8493F70740D9C3A6855685EFF0DFE7D7 +:10B320002A890DE5B14723A0FA008357C4007D5553 +:10B3300093E707042316F400F2406244D2444249E2 +:10B34000B249224A924A024B056182800C484E86DD +:10B35000EFB06FBD8357C40093F7F7B793E70708C3 +:10B360002316F4002328240144C84E99B3843441A1 +:10B370002320240104C4528963732A01528908409E +:10B380004A86DA85EFB08FC51C440145B387274153 +:10B390001CC41C403E992320240179BF2686568573 +:10B3A000EFF0DFEC2A895DFD0C485685EFF05FD4A5 +:10B3B00095BF83D7C500717126D34AD14ECF06D72A +:10B3C00022D552CD56CB5AC95EC762C566C393F724 +:10B3D0000708AA892E89B284B9C39C49A9E39305B9 +:10B3E000000436C6EFF05FDB2320A9002328A90064 +:10B3F000B24615E1B14723A0F9007D55BA502A5451 +:10B400009A540A59FA496A4ADA4A4A4BBA4B2A4CC0 +:10B410009A4C4D61828093070004232AF900930718 +:10B420000002A30CF1029307000302DA230DF102DC +:10B4300036CE930B5002971A0000938AAA29054C26 +:10B44000294B26848347040099C3639D7709B30C75 +:10B450009440638E0C00E6862686CA854E85EFF002 +:10B460007FE6FD576302F51AD256E69636DA834731 +:10B470000400638B0718FD579304140002D002D612 +:10B480003ED202D4A301010682DC83C50400154626 +:10B490005685EFF02FA913841400825731E513F776 +:10B4A000070109C713070002A301E10613F787008C +:10B4B00009C71307B002A301E10683C604001307FE +:10B4C000A002638BE602B2572684814625460347D5 +:10B4D000040093051400130707FD6374E6068DC688 +:10B4E0003ED61DA00504B9BF330555413315AC0048 +:10B4F000C98F3ED0A28451BF7247930647001843BC +:10B5000036CE634907023AD6034704009307E002A8 +:10B51000631FF704034714009307A002631BF7029D +:10B52000F2470904138747009C433ACE63C10702E0 +:10B530003ED235A83307E04093E727003AD63ED005 +:10B54000E1B7B387670385462E84BA9749B7FD579D +:10B55000C5B7050402D2814681472546034704004A +:10B5600093051400130707FD6378E606F1F283459F +:10B5700004000D461715000013054516EFF08F9ACD +:10B5800011CD97170000938767151D8D9307000451 +:10B59000B397A700025505045D8D2AD083450400AA +:10B5A0001946171500001305A51393041400230C66 +:10B5B000B102EFF02F9735C197B7FFFF9387276F41 +:10B5C00095E70257F2471377071009CF91073ECE50 +:10B5D000D257D2973EDAB5B5B387670385462E8436 +:10B5E000BA97ADBF9D07E19BA107D5B7780897062D +:10B5F0000000938666CD4A860C104E85EFB0EFEAC8 +:10B60000FD572A8AE316F5FC8357C9007D5593F749 +:10B610000704E39507DE5255D5B378089706000076 +:10B62000938686CA4A860C104E85EFB01FC5C9BFE7 +:10B63000011122CC06CE2A8409C91C4D99E732C6D5 +:10B640002EC4EFE04FEC3246A245971700009387D7 +:10B65000E71F6316F60250401C46FD171CC663D058 +:10B660000704184E63C7E70093F7F50F294763985F +:10B67000E70222856244F24005616FD0AFCE971792 +:10B6800000009387A71E6314F6001044F1B79717C4 +:10B6900000009387A719E311F6FC504475BF1C42C4 +:10B6A00013F5F50F1387170018C22380B700F24077 +:10B6B000624405618280411122C42A842E8597E765 +:10B6C000FF1F23A9075A06C6EF80FFFBFD5763192A +:10B6D000F50097E7FF1F9387E7599C4391C31CC070 +:10B6E000B240224441018280FD4763F6B700D9474A +:10B6F0001CC17D5582807C41011122CC06CE2E8654 +:10B700002A8491C713972500BA97984319EB22858D +:10B7100032C6A528AA85228562443246F2400561D8 +:10B720001DA8854601456308D700FD566319D7005B +:10B73000D9471CC00545F2406244056182802E85D0 +:10B7400023A0070002970145FDB79387C182AA8510 +:10B7500088436FF07FF9411122C42A842E85B28577 +:10B7600097E7FF1F23A8075006C6EF007007FD5795 +:10B770006319F50097E7FF1F9387C74F9C4391C359 +:10B780001CC0B2402244410182806F00700341110D +:10B7900022C42E848395E50006C63924634905003A +:10B7A0007C48AA977CC8B2402244410182808357DA +:10B7B000C4007D777D17F98F2316F400EDB783D78A +:10B7C000C500011122CC26CA4AC84EC606CE93F740 +:10B7D0000710AA842E843289B68991C78395E50023 +:10B7E00089460146A52A8357C4007D777D17F98FC6 +:10B7F0002316F4008315E4006244F240CE864A86A4 +:10B80000B24942492685D244056169A0411122C44A +:10B810002E848395E50006C69122FD570357C40088 +:10B82000631BF500FD77FD17F98F2316F400B24076 +:10B830002244410182808567D98F2316F40068C8AD +:10B84000FDB78395E50051A005C67D160147B307F6 +:10B85000E500B386E50083C7070083C6060063964C +:10B86000D7006304C7000507FDF33385D740828006 +:10B870000145828091CD9307F00F63F7C7009307CE +:10B88000A0081CC17D5582802380C50005458280AB +:10B8900001458280411122C42A842E85B2853686D4 +:10B8A00097E7FF1F23A8073C06C6EF80FFD9FD5787 +:10B8B0006319F50097E7FF1F9387C73B9C4391C32C +:10B8C0001CC0B240224441018280411122C42A841A +:10B8D0002E8597E7FF1F23AF073806C6D125FD57F2 +:10B8E0006319F50097E7FF1F9387C7389C4391C3FF +:10B8F0001CC0B240224441018280411122C42A84EA +:10B900002E85B28597E7FF1F23A6073606C64D256D +:10B91000FD576319F50097E7FF1F9387A7359C43F1 +:10B9200091C31CC0B240224441018280411122C413 +:10B930002A842E8597E7FF1F23AE073206C6492DBE +:10B94000FD576319F50097E7FF1F9387A7329C43C4 +:10B9500091C31CC0B240224441018280411122C4E3 +:10B960002A842E85B285368697E7FF1F23A40730E9 +:10B9700006C6BD2DFD576319F50097E7FF1F938796 +:10B98000672F9C4391C31CC0B24022444101828076 +:10B990008280828083A7C5FF1385C7FF63D5070018 +:10B9A000AA959C413E958280411122C42A842E850D +:10B9B000B285368697E7FF1F23AE072A06C689257C +:10B9C000FD576319F50097E7FF1F9387A72A9C434C +:10B9D00091C31CC0B24022444101828013D745016B +:10B9E000B7071000FD171347F7FF13D84601FD8D69 +:10B9F000F58F931657011378F87F99CA1307F07FD4 +:10BA000001456303E8008280D18F3335F0008280E6 +:10BA1000C98D0545E5D5828093D74501B70610004D +:10BA20001387F6FF93F7F77F1306E03F2A886D8FA1 +:10BA30000145FD816354F60099C18280828013061E +:10BA4000E0417D55E34BF6FE130530431D8D7D46E9 +:10BA5000558F634AA6009387D7BE3317F700335537 +:10BA6000A800598D828013053041B307F540335546 +:10BA7000F7008280935746011317C60093F7F77FAC +:10BA8000797131839386170022D426D206D64AD004 +:10BA90002EC83ACA02CE02CC93F6E67F2A8493548B +:10BAA000F601A1CE9166938606C0B69713D64500DF +:10BAB0009316C701C607D18E1395C5011183C5839F +:10BAC00001482316E1003247C607B7050180C58348 +:10BAD000FD15C2076D8FD98F86071396F4018583F4 +:10BAE000D18F48C02320040114C45CC42285B25005 +:10BAF000225492540259456182803365B700A5EB08 +:10BB000059CD5DC33A85EFA05FB2130715031378D3 +:10BB1000F7011587631E080A100893162700B3065D +:10BB2000D6408A8813182700CC46B3870601F11641 +:10BB3000CCC7E39BD8FE7D170A0732972320070066 +:10BB40009306C7FF6309E6003687232007009306A4 +:10BB5000C7FFE31BE6FE91679387C7C0898FC607BF +:10BB600042485245E2460357C101C58399BF15C1FA +:10BB7000A167135547009316C7013367F50013D625 +:10BB800045004207D18E1395C5014183FD17014839 +:10BB90000DBFA1678146FD17014701481DB78146CA +:10BBA00081470147014831BF2E852E89EFA0FFA7AD +:10BBB000130715051378F701130505021587E30D23 +:10BBC00008F489476306F70009471008B14835A80B +:10BBD000B306E0408A061008B106130E0002B296C2 +:10BBE00093182700330E0E4183A5C6FF9C42338372 +:10BBF0001601B3D5C501B3970701DD8D2320B3002E +:10BC0000F116E313D6FE42497D171C10BE98331976 +:10BC1000090123A828FF0DB793D645019397C500C6 +:10BC200093F6F67FB183138616008E071357D5015E +:10BC30001376E67FFD815D8F9318350035CE13882E +:10BC400006C89307E00F63DD07018147139597004E +:10BC50009306F00FDE062581FE05558D4D8D828001 +:10BC60006355000B931765000E07B337F000D98FAB +:10BC700093D8D801B3E7170113F7770063010710D2 +:10BC800013F7F70091466303D700910737070004C5 +:10BC90007D8F75C7130718001306F00F9376F70F03 +:10BCA000E305C7FA9A07A58313959700DE06258159 +:10BCB000FE05558D4D8D8280B367170199EE85CFB6 +:10BCC00095479A07A5831395970093F6F60FDE061E +:10BCD0002581FE05558D4D8D8280A5DBB70740007F +:10BCE000139597009306F00FDE0681452581FE052A +:10BCF000558D4D8D82808147139597008146DE06D4 +:10BD00002581FE05558D4D8D8280A5576348F80429 +:10BD1000F94737068000B38707417D45598E635147 +:10BD2000F504795733070741130500023357E6003E +:10BD30006388A700938626CAB316D600B3E8D80056 +:10BD4000B3371001D98F13F77700014815FB13970C +:10BD500057008546E34807F48146A5B781468DB76D +:10BD6000938626C83397D8003337E000B316D60041 +:10BD7000B3D8F800B367D700B3E7F800E9B7C286D5 +:10BD800089B70328C500184154410C452165930724 +:10BD9000F5FF13560801139E35007D8E9358D70189 +:10BDA00093D7D601131308018E064111B3E7C701DB +:10BDB000B3E6160113530301131E37009308160050 +:10BDC0007915F5810E033EC436C272C033F5A80062 +:10BDD0001358F801B3E5650005C9717713070740EB +:10BDE0003A961307E07F635DC7041306F07F0147AF +:10BDF00081473207520631837E08518F336707012E +:10BE00003E85BA8541018280D58FCD8FB3E7C701CA +:10BE100005E2F1CB8147954693D5360013979700FD +:10BE20009396D701B3E7B60031831376F67FD1B787 +:10BE3000CDDF01481306F07F37070800814755BF63 +:10BE40006346C00A9307C0FC634FF60E9307D00306 +:10BE50003386C7409357564037070800D98D13954E +:10BE600027000A8781462EC6B308A10011077D8AE4 +:10BE7000B3E6C60163091701032E07001107B3E6F5 +:10BE8000C601E31B17FF0D471D8F79CA93080101F7 +:10BE9000AA9883A808FF130E0002330ECE40B39871 +:10BEA000C801B3E6160175CB0A070A95B30EE10087 +:10BEB0008A880C41032345009108B3D5C50033138C +:10BEC000C301B3E5650023AEB8FE1105E3931EFF81 +:10BED0009145B387F540B24508082A97B3D5C50008 +:10BEE0002328B7FE61A80146014721B713974600F2 +:10BEF000139547003367C701F182F1839205333709 +:10BF0000E000C98ECD8FD98E13F7760011C713F7D5 +:10BF1000F6009145631CB702370780007D8FE30D63 +:10BF200007EE05061307F07FE301E6EC370780FF15 +:10BF30007D177D8F9317D7018D8226071376F67FA5 +:10BF4000D58F31837DB585468147014613B7C6FF3E +:10BF500013471700BA973707800091067D8FC1B746 +:10BF60008A85B388A50083A808009105050623AE3D +:10BF700015FFE358C7FE1147B307F7408A078A97B2 +:10BF8000180823A007009107E39DE7FE0247B33698 +:10BF9000D0009247D98E014685BF854701472DBF06 +:10BFA0009307800517E7FF1F2326F7CC7D55828076 +:10BFB0009307800517E7FF1F232EF7CA7D55828060 +:10BFC0009307800517E7FF1F2326F7CA7D55828058 +:10BFD0009307800517E7FF1F232EF7C801458280CE +:10BFE0009307800517E7FF1F2326F7C87D5582803A +:10BFF0009307800517E7FF1F232EF7C67D55828024 +:10C000009307800517E7FF1F2326F7C67D5582801B +:10C0100001A0000084C400008CC4000094C400008F +:10C0200078C4000070C400009CC40000A4C40000D8 +:10C0300020C20000ACC40000B4C40000BCC40000B6 +:10C04000C0C4000025732573000000005379737489 +:10C05000656D436C6B3A25640D0A0000322E342E58 +:10C060003500000057656C636F6D6520746F205458 +:10C07000656E63656E744F532074696E79282573FD +:10C08000290D0A007461736B310000007461736BD9 +:10C090003200000073686F756C64206E6F742072DC +:10C0A000756E2061742068657265210D00000000C6 +:10C0B0002323234920616D207461736B310D0000CF +:10C0C0007072696E740000006C65742061203D2000 +:10C0D000313B000061202A3D20323B207072696EA6 +:10C0E0007428277265733A272C2061293B000000D1 +:10C0F000440A0000620A0000D40A0000040B000099 +:10C100001E0B0000720D0000720D0000820B00007B +:10C11000720D0000720D0000CE0B0000720D0000C9 +:10C12000EA0B0000720D0000720D0000720D00009D +:10C130001E0C00003A0C0000560C0000D20C00004F +:10C14000EE0C0000220D0000720D0000560D0000E4 +:10C150007A120000061400004C1300003612000092 +:10C160004E120000901300005A120000C813000085 +:10C1700012140000F2130000DA200000E621000093 +:10C18000E6210000E62100009C2000008E20000037 +:10C19000E62100000222000082200000E6210000CB +:10C1A0001A200000CA1F0000F01F00002820000015 +:10C1B00036200000AA200000C2200000E621000076 +:10C1C0009A210000AC210000BE210000D021000017 +:10C1D0006621000080210000562000003C20000065 +:10C1E0006C200000241B0000301E0000461E0000D2 +:10C1F000561E0000801E0000D01A00003F3F0000C5 +:10C20000626164206C6873006261642063616C6CBD +:10C210000000000063616C6C696E67206E6F6E2DAC +:10C2200066756E6374696F6E0000000063616C6C0C +:10C23000206F6F6D000000006261642073747220D3 +:10C240006F70000074797065206D69736D6174633F +:10C2500068000000646976206279207A65726F0058 +:10C260006964656E74206578706563746564000048 +:10C270006C656E67746800006C6F6F6B7570206919 +:10C280006E206E6F6E2D6F626A000000756E6B6EB1 +:10C290006F776E206F7020256400000070617273EC +:10C2A00065206572726F720029206578706563740D +:10C2B000656400004320737461636B0062616420F5 +:10C2C000657870720000000027252E2A73272061F0 +:10C2D0006C7265616479206465636C617265640089 +:10C2E0004552524F523A200027252E2A7327206E9E +:10C2F0006F7420696D706C656D656E7465640000A7 +:10C300006E6F7420696E206C6F6F70006E6F74209A +:10C31000696E2066756E63003B2065787065637496 +:10C320006564000062616420737472206C697465D6 +:10C3300072616C0027252E2A7327206E6F74206689 +:10C340006F756E64000000006A732D3E62726B2090 +:10C350003C3D206A732D3E73697A65002E2E2F5462 +:10C36000656E63656E744F535F54696E792F746F99 +:10C37000735F6A732F746F735F6A732E63000000BC +:10C380006F6F6D00286A732D3E666C61677320269F +:10C3900020465F4E4F4558454329203D3D20300003 +:10C3A000627265616B000000636C61737300000072 +:10C3B00063617365000000006361746368000000DE +:10C3C000636F6E7374000000636F6E74696E7565E1 +:10C3D00000000000646F000064656661756C7400A5 +:10C3E000656C736500000000666F720066696E61BF +:10C3F0006C6C790066616C73650000006966000012 +:10C40000696E0000696E7374616E63656F6600002B +:10C410006C6574006E65770072657475726E0000ED +:10C420007377697463680000747279007468697363 +:10C43000000000007468726F770000007472756508 +:10C4400000000000747970656F660000766172000C +:10C45000766F6964000000007768696C6500000011 +:10C4600077697468000000007969656C64000000F9 +:10C470006E756C6C00000000756E646566696E65B3 +:10C48000640000006F626A656374000070726F7010 +:10C4900000000000737472696E6700006E756D6253 +:10C4A00065720000626F6F6C65616E00636F64653A +:10C4B000726566006366756E6300000065727200E7 +:10C4C0006E616E00252E3137670000002567000081 +:10C4D0007B0000002C0000003A0000007D000000FE +:10C4E0002200000022635F66756E635F3078256C02 +:10C4F0007822000050524F5040256C75000000001B +:10C50000565459504525640069646C65000000006C +:10C51000AA8EFFFF2E8DFFFF3E8EFFFF468EFFFF90 +:10C520003E8EFFFF5E8DFFFF3E8EFFFF468EFFFFBC +:10C530002E8DFFFF2E8DFFFF5E8DFFFF468EFFFFCE +:10C54000A08EFFFFA08EFFFFA08EFFFF5E8DFFFF7E +:10C55000BA95FFFFAC94FFFFAC94FFFFAA94FFFFD6 +:10C56000B294FFFFB294FFFF7894FFFFAA94FFFFFD +:10C57000B294FFFF7894FFFFB294FFFFAA94FFFFED +:10C58000A695FFFFA695FFFFA695FFFF7894FFFFF6 +:10C59000000102020303030304040404040404046A +:10C5A000050505050505050505050505050505053B +:10C5B000060606060606060606060606060606061B +:10C5C000060606060606060606060606060606060B +:10C5D00007070707070707070707070707070707EB +:10C5E00007070707070707070707070707070707DB +:10C5F00007070707070707070707070707070707CB +:10C6000007070707070707070707070707070707BA +:10C61000080808080808080808080808080808089A +:10C62000080808080808080808080808080808088A +:10C63000080808080808080808080808080808087A +:10C64000080808080808080808080808080808086A +:10C65000080808080808080808080808080808085A +:10C66000080808080808080808080808080808084A +:10C67000080808080808080808080808080808083A +:10C68000080808080808080808080808080808082A +:10C690002C2066756E6374696F6E3A20000000008E +:10C6A000617373657274696F6E2022257322206630 +:10C6B00061696C65643A2066696C65202225732285 +:10C6C0002C206C696E65202564257325730A000093 +:10C6D000232D302B20000000686C4C0065666745F8 +:10C6E0004647000000000000FFFFFFFFFFFFEF7F55 +:10C6F000494E4600696E66004E414E003000000013 +:10C700003031323334353637383941424344454687 +:10C710000000000030313233343536373839616249 +:10C72000636465660000000065256C64000000001D +:10C730000000C07F16B7FFFF02B7FFFF34B7FFFF4F +:10C740003AB7FFFF16B7FFFF000000000000E03F10 +:10C75000000000000000F03F00000000000000406A +:10C760000000C0FFFFFFDF419535A094FFFFDF3FD2 +:10C7700035E5AF350000E03F9535A094FFFFCF3F92 +:10C780006E660000696E697479000000616E0000D9 +:10C7900035000000CEFBFFFFCB03000001000000CE +:10C7A0000000000034000000CEFBFFFFCB030000C0 +:10C7B0000100000000000000BC89D897B2D29C3C68 +:10C7C00033A7A8D523F649393DA7F444FD0FA53278 +:10C7D0009D978CCF08BA5B25436FAC64280668111F +:10C7E000000000000000F83F61436F63A787D23F5D +:10C7F000B3C8608B288AC63FFB799F501344D33F50 +:10C8000000000000000024400000000000001C4068 +:10C810000000000000001440496E66696E6974797A +:10C82000000000004E614E0000000000000000000B +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C88000000000000000000043000000504F53492A +:10C89000580000002E0000000080E03779C34143BB +:10C8A000176E05B5B5B89346F5F93FE9034F384D16 +:10C8B000321D30F94877825A3CBF737FDD4F1575C2 +:10C8C000000000000000F03F0000000000002440D5 +:10C8D00000000000000059400000000000408F40B0 +:10C8E000000000000088C34000000000006AF8401B +:10C8F0000000000080842E4100000000D01263413F +:10C900000000000084D797410000000065CDCD41B4 +:10C91000000000205FA00242000000E87648374295 +:10C92000000000A2941A6D42000040E59C30A24233 +:10C930000000901EC4BCD64200003426F56B0C43A8 +:10C940000080E03779C3414300A0D885573476434F +:10C9500000C84E676DC1AB43003D9160E458E143B0 +:10C96000408CB5781DAF154450EFE2D6E41A4B4425 +:10C9700092D54D06CFF08044F64AE1C7022DB5446A +:10C98000B49DD9794378EA440500000019000000FD +:10C990007D000000002020202020202020202828AA +:10C9A000282828202020202020202020202020206F +:10C9B00020202020208810101010101010101010AF +:10C9C00010101010100404040404040404040410DF +:10C9D000101010101010414141414141010101016D +:10C9E0000101010101010101010101010101010137 +:10C9F0001010101010104242424242420202020243 +:10CA00000202020202020202020202020202020206 +:10CA100010101010200000000000000000000000B6 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:08CA900000000000000000009E +:10CA9800000000000102030401020304060708095C +:10CAA8000000000048C8000068C8000028C800004E +:10CAB800000000000000000000000000000000006E +:10CAC800000000000000000000000000000000005E +:10CAD800000000000000000000000000000000004E +:10CAE800000000000000000000000000000000003E +:10CAF800000000000000000000000000000000002E +:10CB080043000000000000000000000000000000DA +:10CB1800000000000000000000000000000000000D +:10CB280043000000000000000000000000000000BA +:10CB380000000000000000000000000000000000ED +:10CB4800430000000000000000000000000000009A +:10CB580000000000000000000000000000000000CD +:10CB6800430000000000000000000000000000007A +:10CB780000000000000000000000000000000000AD +:10CB8800430000000000000000000000000000005A +:10CB9800000000000000000000000000000000008D +:10CBA800430000000000000000000000000000003A +:10CBB800000000000000000000000000000000006D +:10CBC800430000000000000000000000000000001A +:10CBD800000000000000000000000000000000004D +:10CBE80074B80000EAA600000000000094C9000024 +:10CBF80094C80000ACC00000ACC00000ACC000008D +:10CC0800ACC00000ACC00000ACC00000ACC000006C +:10CC1800ACC00000ACC00000FFFFFFFFFFFFFFFF3C +:10CC2800FFFFFFFFFFFF0000010041534349490098 +:10CC380000000000000000000000000000000000EC +:10CC48000000000000000000000041534349490073 +:10CC580000000000000000000000000000000000CC +:10CC680000000000000000000000000000000000BC +:10CC780000A24A0400000000E803000000000000D1 +:10CC8800F0010020F0010020F8010020F801002048 +:10CC9800709C002002040608749C002010000020EC +:10CCA8006C6F61646F6666006D6B73636F706500AF +:10CCB800705B00200002000010000020000000004F +:00000001FF diff --git a/obj/JSInterpreter-TencentOS.lst b/obj/JSInterpreter-TencentOS.lst new file mode 100644 index 0000000..25bff51 --- /dev/null +++ b/obj/JSInterpreter-TencentOS.lst @@ -0,0 +1,19457 @@ + +JSInterpreter-TencentOS.elf: file format elf32-littleriscv +JSInterpreter-TencentOS.elf +architecture: riscv:rv32, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x00000000 + +Program Header: + LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 + filesz 0x0000ca98 memsz 0x0000ca98 flags r-x + LOAD off 0x0000e000 vaddr 0x20000000 paddr 0x0000ca98 align 2**12 + filesz 0x00000230 memsz 0x00009c74 flags rw- + LOAD off 0x0000f000 vaddr 0x2000b000 paddr 0x2000b000 align 2**12 + filesz 0x00000000 memsz 0x00005000 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .init 00000038 00000000 00000000 00001000 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .vector 000001c8 00000038 00000038 00001038 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 0000c898 00000200 00000200 00001200 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .fini 00000000 0000ca98 0000ca98 0000e230 2**0 + CONTENTS, ALLOC, LOAD, CODE + 4 .dalign 00000000 20000000 20000000 0000e230 2**0 + CONTENTS + 5 .dlalign 00000000 0000ca98 0000ca98 0000e230 2**0 + CONTENTS + 6 .data 00000230 20000000 0000ca98 0000e000 2**3 + CONTENTS, ALLOC, LOAD, DATA + 7 .bss 00009a44 20000230 0000ccc8 0000e230 2**3 + ALLOC + 8 .stack 00005000 2000b000 2000b000 0000f000 2**0 + ALLOC + 9 .debug_info 0001ea36 00000000 00000000 0000e230 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 000040de 00000000 00000000 0002cc66 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_aranges 00000b18 00000000 00000000 00030d48 2**3 + CONTENTS, READONLY, DEBUGGING + 12 .debug_ranges 00001e80 00000000 00000000 00031860 2**3 + CONTENTS, READONLY, DEBUGGING + 13 .debug_line 00013f4f 00000000 00000000 000336e0 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_str 000043d9 00000000 00000000 0004762f 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .comment 00000033 00000000 00000000 0004ba08 2**0 + CONTENTS, READONLY + 16 .debug_frame 00003b98 00000000 00000000 0004ba3c 2**2 + CONTENTS, READONLY, DEBUGGING + 17 .debug_loc 00009093 00000000 00000000 0004f5d4 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .stab 000000b4 00000000 00000000 00058668 2**2 + CONTENTS, READONLY, DEBUGGING + 19 .stabstr 00000183 00000000 00000000 0005871c 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +00000000 l d .init 00000000 .init +00000038 l d .vector 00000000 .vector +00000200 l d .text 00000000 .text +0000ca98 l d .fini 00000000 .fini +20000000 l d .dalign 00000000 .dalign +0000ca98 l d .dlalign 00000000 .dlalign +20000000 l d .data 00000000 .data +20000230 l d .bss 00000000 .bss +2000b000 l d .stack 00000000 .stack +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .comment 00000000 .comment +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .stab 00000000 .stab +00000000 l d .stabstr 00000000 .stabstr +00000000 l df *ABS* 00000000 ./Startup/startup_ch32v30x.o +00000038 l .vector 00000000 _vector_base +00000000 l df *ABS* 00000000 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o +0000020c l F .text 00000000 restore_context +00000000 l df *ABS* 00000000 ch32v30x_it.c +00000000 l df *ABS* 00000000 main.c +00000000 l df *ABS* 00000000 system_ch32v30x.c +00000000 l df *ABS* 00000000 tos_js.c +000006b4 l F .text 00000016 vtype +000006ca l F .text 0000000e is_err +000006d8 l F .text 00000030 setlwm +00000708 l F .text 00000038 cpy +00000740 l F .text 00000098 skiptonext +000007d8 l F .text 0000001a streq +000007f2 l F .text 0000003c unhex +0000082e l F .text 00000028 esize +00000856 l F .text 0000001a is_err2.isra.2 +00000870 l F .text 0000003e loadoff +000008ae l F .text 0000001c vstr +000008ca l F .text 00000016 delscope +000008e0 l F .text 00000054 js_truthy +00000934 l F .text 0000004a lkp +0000097e l F .text 00000036 resolveprop +000009b4 l F .text 000003c2 parseident +00000d76 l F .text 000003e4 next.part.9 +0000115a l F .text 00000016 next +00001170 l F .text 00000094 js_unmark_entity +00001204 l F .text 00000218 tostr +00001480 l F .text 00000078 mkentity +000014f8 l F .text 0000004c setprop +00001544 l F .text 00000042 mkscope +00001586 l F .text 00000036 expect +00001624 l F .text 00000148 js_str_literal +000025d4 l F .text 00000448 js_stmt +00001a52 l F .text 00000806 do_op +00002442 l F .text 00000074 js_assignment +000033b6 l F .text 00000076 do_assign_op +00002258 l F .text 000000c8 js_logical_and +0000334e l F .text 00000068 js_bitwise_xor +00002320 l F .text 00000070 js_logical_or +00002390 l F .text 000000b2 js_ternary +000024b6 l F .text 0000011e js_let +00002ab0 l F .text 0000003a js_block_or_stmt +00002a1c l F .text 00000094 js_block +00002aea l F .text 0000032e js_group +00002e18 l F .text 0000025a js_unary +00003072 l F .text 00000078 js_mul_div_rem +000030ea l F .text 00000070 js_plus_minus +0000315a l F .text 00000084 js_shifts +000031de l F .text 00000092 js_comparison +00003270 l F .text 00000076 js_equality +000032e6 l F .text 00000068 js_bitwise_and +20000210 l O .data 00000008 __func__.3873 +20000218 l O .data 00000008 __func__.4194 +00000000 l df *ABS* 00000000 tos_mmheap.c +0000342c l F .text 0000000a blk_next +00003436 l F .text 00000010 blk_link_next +00003446 l F .text 00000058 mmheap_ctl_init +0000349e l F .text 0000003c generic_fls.part.0 +000034da l F .text 0000003c mapping_insert +00003516 l F .text 00000062 blk_insert +00000000 l df *ABS* 00000000 tos_mutex.c +00003622 l F .text 00000046 mutex_old_owner_release +00000000 l df *ABS* 00000000 tos_pend.c +0000367e l F .text 00000040 pend_list_add +00000000 l df *ABS* 00000000 tos_sched.c +00003766 l F .text 00000030 readyqueue_prio_mark +00000000 l df *ABS* 00000000 tos_sys.c +000038f2 l F .text 00000002 knl_idle_entry +00000000 l df *ABS* 00000000 tos_task.c +00003c2e l F .text 0000000e task_exit +00000000 l df *ABS* 00000000 tos_tick.c +00000000 l df *ABS* 00000000 port_c.c +00000000 l df *ABS* 00000000 tos_cpu.c +00000000 l df *ABS* 00000000 ch32v30x_gpio.c +00000000 l df *ABS* 00000000 ch32v30x_rcc.c +20000000 l O .data 00000010 APBAHBPrescTable +20000204 l O .data 00000004 ADCPrescTable +00000000 l df *ABS* 00000000 ch32v30x_usart.c +00000000 l df *ABS* 00000000 debug.c +20000208 l O .data 00000004 curbrk.5216 +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 adddf3.c +00000000 l df *ABS* 00000000 divdf3.c +00000000 l df *ABS* 00000000 eqdf2.c +00000000 l df *ABS* 00000000 gedf2.c +00000000 l df *ABS* 00000000 ledf2.c +00000000 l df *ABS* 00000000 muldf3.c +00000000 l df *ABS* 00000000 subdf3.c +00000000 l df *ABS* 00000000 fixdfsi.c +00000000 l df *ABS* 00000000 floatsidf.c +00000000 l df *ABS* 00000000 floatunsidf.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 assert.c +00000000 l df *ABS* 00000000 fprintf.c +00000000 l df *ABS* 00000000 memcmp.c +00000000 l df *ABS* 00000000 memcpy.c +00000000 l df *ABS* 00000000 memmove.c +00000000 l df *ABS* 00000000 nano-vfprintf.c +00006826 l F .text 0000002a __sfputc_r +00000000 l df *ABS* 00000000 nano-vfprintf_float.c +00000000 l df *ABS* 00000000 nano-vfprintf_i.c +00000000 l df *ABS* 00000000 nano-vfscanf_float.c +00000000 l df *ABS* 00000000 printf.c +00000000 l df *ABS* 00000000 putchar.c +00000000 l df *ABS* 00000000 puts.c +00000000 l df *ABS* 00000000 s_modf.c +00000000 l df *ABS* 00000000 sf_nan.c +00000000 l df *ABS* 00000000 snprintf.c +00000000 l df *ABS* 00000000 sprintf.c +00000000 l df *ABS* 00000000 strlen.c +00000000 l df *ABS* 00000000 strncpy.c +00000000 l df *ABS* 00000000 strtod.c +00007c9a l F .text 0000004e sulp +0000c790 l O .text 00000014 fpi.3395 +0000c7a4 l O .text 00000014 fpinan.3431 +0000c7b8 l O .text 00000028 tinytens +00000000 l df *ABS* 00000000 strtol.c +00008998 l F .text 00000144 _strtol_l.isra.0 +00000000 l df *ABS* 00000000 vsnprintf.c +00000000 l df *ABS* 00000000 wbuf.c +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 abort.c +00000000 l df *ABS* 00000000 dtoa.c +00008d4c l F .text 0000013a quorem +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 findfp.c +00009c4a l F .text 0000006a std +00000000 l df *ABS* 00000000 fwalk.c +00000000 l df *ABS* 00000000 gdtoa-gethex.c +00009e7e l F .text 00000076 rshift +00000000 l df *ABS* 00000000 gdtoa-hexnan.c +0000a402 l F .text 0000002c L_shift +00000000 l df *ABS* 00000000 locale.c +00000000 l df *ABS* 00000000 localeconv.c +00000000 l df *ABS* 00000000 makebuf.c +00000000 l df *ABS* 00000000 malloc.c +00000000 l df *ABS* 00000000 mbtowc_r.c +00000000 l df *ABS* 00000000 memchr.c +00000000 l df *ABS* 00000000 mprec.c +0000c988 l O .text 0000000c p05.3319 +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 nano-vfprintf.c +00000000 l df *ABS* 00000000 putc.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 signal.c +00000000 l df *ABS* 00000000 signalr.c +00000000 l df *ABS* 00000000 stdio.c +00000000 l df *ABS* 00000000 strncmp.c +00000000 l df *ABS* 00000000 wctomb_r.c +00000000 l df *ABS* 00000000 writer.c +00000000 l df *ABS* 00000000 closer.c +00000000 l df *ABS* 00000000 fstatr.c +00000000 l df *ABS* 00000000 isattyr.c +00000000 l df *ABS* 00000000 lseekr.c +00000000 l df *ABS* 00000000 mlock.c +00000000 l df *ABS* 00000000 nano-mallocr.c +00000000 l df *ABS* 00000000 readr.c +00000000 l df *ABS* 00000000 unorddf2.c +00000000 l df *ABS* 00000000 fixunsdfsi.c +00000000 l df *ABS* 00000000 extenddftf2.c +00000000 l df *ABS* 00000000 truncdfsf2.c +00000000 l df *ABS* 00000000 trunctfdf2.c +00000000 l df *ABS* 00000000 close.c +00000000 l df *ABS* 00000000 fstat.c +00000000 l df *ABS* 00000000 getpid.c +00000000 l df *ABS* 00000000 isatty.c +00000000 l df *ABS* 00000000 kill.c +00000000 l df *ABS* 00000000 lseek.c +00000000 l df *ABS* 00000000 read.c +00000000 l df *ABS* 00000000 _exit.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 ctype_.c +00000000 l df *ABS* 00000000 impure.c +20000010 l O .data 00000060 impure_data +00000000 l df *ABS* 00000000 tos_global.c +00000000 l df *ABS* 00000000 reent.c +0000b994 g F .text 00000014 _malloc_usable_size_r +00003ece g F .text 000000a2 tick_update +00006b30 g F .text 000000ee __cvt +000041f8 w .text 00000000 EXTI2_IRQHandler +000079de g F .text 0000002c putchar +00004242 w .text 00000000 TIM8_TRG_COM_IRQHandler +00004244 w .text 00000000 TIM8_CC_IRQHandler +0000b084 g F .text 00000046 __any_on +0000b92c g F .text 00000030 _isatty_r +0000bfc0 g F .text 00000010 _getpid +00007a0a g F .text 000000e4 _puts_r +0000b95c g F .text 00000034 _lseek_r +0000427a w .text 00000000 UART8_IRQHandler +2000023c g O .bss 00000004 k_knl_state +0000572c g F .text 0000006a .hidden __eqdf2 +000040d0 g F .text 0000000c cpu_context_switch +20000258 g O .bss 00002800 task1_stk +0000b756 g F .text 00000034 _kill_r +0000799c g F .text 00000042 printf +200009e0 g .data 00000000 __global_pointer$ +0000032e g F .text 00000028 .hidden __riscv_save_8 +0000421e w .text 00000000 TIM1_CC_IRQHandler +0000b80c g F .text 00000036 __sseek +00009d06 g F .text 0000006c __sinit +00008b64 g F .text 000000c6 __swbuf_r +00000432 g F .text 00000002 HardFault_Handler +20005b18 g O .bss 00000058 k_rdyq +00009cbe g F .text 00000048 __sfmoreglue +0000b992 g F .text 00000002 __malloc_unlock +0000037a g F .text 0000000c .hidden __riscv_restore_3 +00004254 w .text 00000000 TIM6_IRQHandler +00008966 g F .text 00000016 _strtod_r +0000199a g F .text 0000003e js_set +20000234 g O .bss 00000004 k_curr_task +0000400c g F .text 000000ac SysTick_Handler +00009ef4 g F .text 00000040 __hexdig_fun +000040b8 g F .text 0000000c tos_cpu_cpsr_save +000041ea w .text 00000000 PVD_IRQHandler +0000424a w .text 00000000 SDIO_IRQHandler +00003a62 g F .text 000000ee tos_task_create +000067dc g F .text 0000004a memmove +0000427c w .text 00000000 TIM9_BRK_IRQHandler +20000230 g O .bss 00000004 k_cpu_cycle_per_tick +000040f0 g F .text 00000018 cpu_systick_init +00000366 g F .text 00000020 .hidden __riscv_restore_10 +00007bae g F .text 00000070 snprintf +00004290 w .text 00000000 DMA2_Channel8_IRQHandler +0000042e g F .text 00000004 NMI_Handler +0000a73e g F .text 0000008c _Balloc +00003fe6 g F .text 0000000e port_systick_priority_set +00004108 g F .text 00000038 cpu_init +0000426a w .text 00000000 CAN2_RX1_IRQHandler +000041fa w .text 00000000 EXTI3_IRQHandler +0000032e g F .text 00000028 .hidden __riscv_save_11 +00005796 g F .text 000000ae .hidden __gtdf2 +0000a5c4 g F .text 00000006 __localeconv_l +00004272 w .text 00000000 USBHS_IRQHandler +0000025c g .text 00000000 SW_handler +00003a0e g F .text 00000030 knl_idle_init +000045e4 g F .text 0000000a USART_GetFlagStatus +00004292 w .text 00000000 DMA2_Channel9_IRQHandler +0000b8fa g F .text 00000032 _fstat_r +0000428a w .text 00000000 TIM10_CC_IRQHandler +20009c70 g O .bss 00000004 errno +20000230 g .bss 00000000 _sbss +00005000 g *ABS* 00000000 __stack_size +000045ee g F .text 0000005a USART_Printf_Init +000015bc g F .text 00000018 js_mkstr +0000037a g F .text 0000000c .hidden __riscv_restore_2 +00006726 g F .text 000000b6 memcpy +0000a45e g F .text 00000160 __hexnan +00009cb4 g F .text 0000000a _cleanup_r +0000b3b2 g F .text 0000027e _svfprintf_r +00006554 g F .text 00000070 .hidden __floatsidf +000040c4 g F .text 0000000c tos_cpu_cpsr_restore +00005844 g F .text 000000b6 .hidden __ltdf2 +000041f4 w .text 00000000 EXTI0_IRQHandler +0000422a w .text 00000000 I2C2_EV_IRQHandler +00004288 w .text 00000000 TIM10_TRG_COM_IRQHandler +00007aee g F .text 0000000c puts +200001e0 g O .data 00000004 SystemCoreClock +0000afda g F .text 00000074 __ratio +200001e8 g O .data 00000008 k_cpu_tick_per_second +00000200 g F .text 00000000 port_sched_start +0000a6de g F .text 0000000c malloc +0000b6e8 g F .text 00000062 _raise_r +0000bfb0 g F .text 00000010 _fstat +000066a0 g F .text 0000003a __assert_func +0000c8c0 g O .text 000000c8 __mprec_tens +00000038 g .init 00000000 _einit +00000450 g F .text 00000056 js_print +00008b52 g F .text 00000012 vsnprintf +000044ec g F .text 0000001e RCC_APB2PeriphClockCmd +0000ba18 g F .text 0000005c .hidden __fixunsdfsi +00000326 g F .text 00000030 .hidden __riscv_save_12 +0000426c w .text 00000000 CAN2_SCE_IRQHandler +0000420c w .text 00000000 ADC1_2_IRQHandler +0000b78a g F .text 00000004 _getpid_r +00004326 g F .text 000000c0 GPIO_Init +20000224 g O .data 00000004 k_idle_task_stk_size +000041e2 w .text 00000000 Break_Point_Handler +00001992 g F .text 00000008 js_glob +00003736 g F .text 00000030 pend_wakeup_all +0000a5ca g F .text 00000018 _localeconv_r +0000198c g F .text 00000006 js_mkfun +0000a9fc g F .text 0000001c __i2b +00000366 g F .text 00000020 .hidden __riscv_restore_11 +0000422e w .text 00000000 SPI1_IRQHandler +000045c6 g F .text 00000016 USART_Cmd +0000b6b6 g F .text 00000032 _sbrk_r +000041ec w .text 00000000 TAMPER_IRQHandler +00000356 g F .text 0000000c .hidden __riscv_save_1 +000040e8 g F .text 00000008 cpu_sched_start +0000037a g F .text 0000000c .hidden __riscv_restore_0 +0000b9a8 g F .text 00000034 _read_r +20005b70 g O .bss 00000200 k_idle_task_stk +0000033c g F .text 0000001a .hidden __riscv_save_7 +00004268 w .text 00000000 CAN2_RX0_IRQHandler +00003ff4 g F .text 00000018 port_cpu_init +20000200 g O .data 00000004 k_irq_stk_top +20000244 g O .bss 00000001 k_sched_lock_nest_cnt +00004240 w .text 00000000 TIM8_UP_IRQHandler +00004a48 g F .text 00000730 .hidden __adddf3 +000041de w .text 00000000 Ecall_M_Mode_Handler +2000b000 g .stack 00000000 _heap_end +0000ae52 g F .text 000000b4 __b2d +0000bfd0 g F .text 00000010 _isatty +20000228 g O .data 00000004 _global_impure_ptr +00000370 g F .text 00000016 .hidden __riscv_restore_5 +0000b26c g F .text 00000058 _realloc_r +0000425a w .text 00000000 DMA2_Channel2_IRQHandler +000046b0 g F .text 00000398 .hidden __udivdi3 +00004204 w .text 00000000 DMA1_Channel4_IRQHandler +0000c898 g O .text 00000028 __mprec_bigtens +0000a8a6 g F .text 000000a6 __s2b +00008d3c g F .text 00000010 abort +000065c4 g F .text 00000066 .hidden __floatunsidf +00004686 g F .text 0000002a _sbrk +0000ace8 g F .text 00000032 __mcmp +00003c66 g F .text 000000c0 tos_task_prio_change +0000427e w .text 00000000 TIM9_UP_IRQHandler +00000370 g F .text 00000016 .hidden __riscv_restore_6 +00004236 w .text 00000000 USART3_IRQHandler +20005d70 g O .bss 00000c84 k_mmheap_ctl +000041ee w .text 00000000 RTC_IRQHandler +00007ce8 g F .text 00000c7e _strtod_l +0000a42e g F .text 00000030 __match +0000141c g F .text 00000064 js_mkerr +20009c74 g .bss 00000000 _ebss +0000420a w .text 00000000 DMA1_Channel7_IRQHandler +00008b52 g F .text 00000012 vsniprintf +0000a94c g F .text 00000046 __hi0bits +00004212 w .text 00000000 CAN1_RX1_IRQHandler +000064ec g F .text 00000068 .hidden __fixdfsi +00004274 w .text 00000000 DVP_IRQHandler +00004252 w .text 00000000 UART5_IRQHandler +00003876 g F .text 0000007c readyqueue_remove +0000897c g F .text 0000001c strtod +0000b630 g F .text 00000086 _putc_r +00003854 g F .text 00000022 readyqueue_add +00003b50 g F .text 000000de tos_task_destroy +000066da g F .text 00000026 fprintf +00004224 w .text 00000000 TIM4_IRQHandler +00005844 g F .text 000000b6 .hidden __ledf2 +0000032e g F .text 00000028 .hidden __riscv_save_9 +0000176c g F .text 000001ca js_gc +00004258 w .text 00000000 DMA2_Channel1_IRQHandler +0000ab5c g F .text 000000be __pow5mult +0000c828 g O .text 00000020 __sf_fake_stderr +00007bae g F .text 00000070 sniprintf +0000033c g F .text 0000001a .hidden __riscv_save_4 +00004226 w .text 00000000 I2C1_EV_IRQHandler +00007afa g F .text 000000a8 modf +20000220 g O .data 00000004 k_idle_task_stk_addr +0000b2c4 g F .text 000000ee __ssputs_r +0000419a g F .text 00000040 tos_cpu_clz +000043e6 g F .text 00000106 RCC_GetClocksFreq +000039e6 g F .text 0000000a knl_is_inirq +00004208 w .text 00000000 DMA1_Channel6_IRQHandler +0000662a g F .text 00000076 .hidden __clzsi2 +00006850 g F .text 00000044 __sfputs_r +00004250 w .text 00000000 UART4_IRQHandler +0000425e w .text 00000000 DMA2_Channel4_IRQHandler +0000a724 g F .text 0000001a memchr +00003d82 g F .text 000000ca tick_list_add +00006caa w F .text 000004c4 _printf_float +20002a58 g O .bss 00000078 task1 +0000450a g F .text 000000bc USART_Init +0000b0f0 g F .text 000000a8 _free_r +00004222 w .text 00000000 TIM3_IRQHandler +000041f2 w .text 00000000 RCC_IRQHandler +00000356 g F .text 0000000c .hidden __riscv_save_3 +0000421c w .text 00000000 TIM1_TRG_COM_IRQHandler +200001f8 g O .data 00000008 k_tick_list +000041fe w .text 00000000 DMA1_Channel1_IRQHandler +200069f8 g O .bss 00000078 k_idle_task +00000000 g .init 00000000 _start +000040dc g F .text 0000000c cpu_irq_context_switch +000036d6 g F .text 00000018 pend_list_remove +20002ad0 g O .bss 00000078 task2 +0000428e w .text 00000000 DMA2_Channel7_IRQHandler +20006a70 g O .bss 00003000 k_mmheap_default_pool +000036be g F .text 00000018 pend_highest_pending_prio_get +0000bff0 g F .text 00000010 _lseek +0000ac1a g F .text 000000ce __lshift +00003912 g F .text 00000050 tos_knl_irq_leave +00003fc2 g F .text 00000024 port_systick_config +00004238 w .text 00000000 EXTI15_10_IRQHandler +00003796 g F .text 00000018 readyqueue_highest_ready_task_get +0000b848 g F .text 0000002c strncmp +0000aa18 g F .text 00000144 __multiply +00003814 g F .text 00000040 readyqueue_add_tail +00007c76 g F .text 00000024 strncpy +0000af06 g F .text 000000d4 __d2b +00004256 w .text 00000000 TIM7_IRQHandler +0000ba74 g F .text 000001a4 .hidden __extenddftf2 +0000b8ca g F .text 00000030 _close_r +00004266 w .text 00000000 CAN2_TX_IRQHandler +20000000 g .dalign 00000000 _data_vma +0000424c w .text 00000000 TIM5_IRQHandler +00006700 g F .text 00000026 memcmp +00008c2a g F .text 00000112 __swsetup_r +00004216 w .text 00000000 EXTI9_5_IRQHandler +00005178 g F .text 000005b4 .hidden __divdf3 +00003f98 g F .text 0000000e sw_clearpend +00009d72 g F .text 000000a0 __sfp +0000b04e g F .text 00000036 __copybits +00008af2 g F .text 00000060 _vsnprintf_r +000058fa g F .text 000004b8 .hidden __muldf3 +0000032e g F .text 00000028 .hidden __riscv_save_10 +0000b78e g F .text 00000030 __sread +000036ee g F .text 00000016 pend_list_adjust +00004264 w .text 00000000 ETH_WKUP_IRQHandler +000037ae g F .text 00000026 readyqueue_init +00003606 g F .text 0000001c mmheap_init_with_pool +0000b990 g F .text 00000002 __malloc_lock +00000370 g F .text 00000016 .hidden __riscv_restore_4 +00000366 g F .text 00000020 .hidden __riscv_restore_8 +00009be4 g F .text 00000066 _fflush_r +00001936 g F .text 0000004e js_create +0000033c g F .text 0000001a .hidden __riscv_save_6 +0000b0ca g F .text 00000026 _calloc_r +00003704 g F .text 00000032 pend_task_wakeup +00004230 w .text 00000000 SPI2_IRQHandler +0000c848 g O .text 00000020 __sf_fake_stdin +00003a00 g F .text 0000000e knl_is_self +00000386 g F .text 000000a8 memset +00000366 g F .text 00000020 .hidden __riscv_restore_9 +00000370 g F .text 00000016 .hidden __riscv_restore_7 +0000050e g F .text 000000ac main +000039dc g F .text 0000000a knl_is_sched_locked +00004284 w .text 00000000 TIM10_BRK_IRQHandler +00004282 w .text 00000000 TIM9_CC_IRQHandler +0000b842 g F .text 00000006 __sclose +00004260 w .text 00000000 DMA2_Channel5_IRQHandler +20002b48 g O .bss 00002800 task2_stk +20005348 g O .bss 000007d0 js_mem +00008adc g F .text 00000016 _strtol_r +0000bc18 g F .text 0000016a .hidden __truncdfsf2 +00008e86 g F .text 00000c20 _dtoa_r +0000b198 g F .text 000000d4 _malloc_r +20009a70 g O .bss 00000200 k_irq_stk +0000b874 g F .text 00000020 __ascii_wctomb +00003f86 g F .text 0000000c port_cpsr_save +00004206 w .text 00000000 DMA1_Channel5_IRQHandler +000041fc w .text 00000000 EXTI4_IRQHandler +00004210 w .text 00000000 USB_LP_CAN1_RX0_IRQHandler +000005ba g F .text 000000fa SystemInit +00004246 w .text 00000000 RNG_IRQHandler +0000572c g F .text 0000006a .hidden __nedf2 +0000799c g F .text 00000042 iprintf +0000420e w .text 00000000 USB_HP_CAN1_TX_IRQHandler +00007c1e g F .text 00000046 sprintf +0000c590 g O .text 00000100 .hidden __clz_tab +00006c1e g F .text 0000008c __exponent +00003e4c g F .text 00000082 tick_list_remove +00000000 g .init 00000000 _sinit +00000434 g F .text 0000001c task1_entry +0000b894 g F .text 00000036 _write_r +20000240 g O .bss 00000004 k_next_task +200001f0 g O .data 00000008 k_stat_list +00004202 w .text 00000000 DMA1_Channel3_IRQHandler +000037d4 g F .text 00000040 readyqueue_add_head +00001984 g F .text 00000008 js_mkundef +00004248 w .text 00000000 FSMC_IRQHandler +00004262 w .text 00000000 ETH_IRQHandler +00007ba2 g F .text 0000000c nanf +0000716e g F .text 0000010c _printf_common +2000020c g O .data 00000004 _impure_ptr +0000421a w .text 00000000 TIM1_UP_IRQHandler +20000238 g O .bss 00000001 k_irq_nest_cnt +00009aa6 g F .text 0000013e __sflush_r +00003f92 g F .text 00000006 port_cpsr_restore +00003578 g F .text 0000008e tos_mmheap_pool_add +0000b3b2 g F .text 0000027e _svfiprintf_r +000041e8 w .text 00000000 WWDG_IRQHandler +00004270 w .text 00000000 USBHSWakeup_IRQHandler +00004296 w .text 00000000 DMA2_Channel11_IRQHandler +0000a6ea g F .text 0000003a __ascii_mbtowc +000041e0 w .text 00000000 Ecall_U_Mode_Handler +0000ae0c g F .text 00000046 __ulp +00004140 g F .text 0000005a cpu_task_stk_init +0000428c w .text 00000000 DMA2_Channel6_IRQHandler +00004220 w .text 00000000 TIM2_IRQHandler +20010000 g .stack 00000000 _eusrstack +00003d26 g F .text 0000005c tos_task_delay +00000356 g F .text 0000000c .hidden __riscv_save_2 +00008af2 g F .text 00000060 _vsniprintf_r +20000248 g O .bss 00000008 k_tick_count +000038f4 g F .text 0000001e tos_knl_irq_enter +00004218 w .text 00000000 TIM1_BRK_IRQHandler +0000a5e2 g F .text 0000005a __swhatbuf_r +000045dc g F .text 00000008 USART_SendData +00004294 w .text 00000000 DMA2_Channel10_IRQHandler +000041f6 w .text 00000000 EXTI1_IRQHandler +0000033c g F .text 0000001a .hidden __riscv_save_5 +000019d8 g F .text 0000006e js_eval +0000398e g F .text 0000000c tos_knl_is_running +00004648 g F .text 0000003e _write +20000230 g .data 00000000 _edata +20009c74 g .bss 00000000 _end +0000423a w .text 00000000 RTCAlarm_IRQHandler +0000ca98 g .dlalign 00000000 _data_lma +00004286 w .text 00000000 TIM10_UP_IRQHandler +00004280 w .text 00000000 TIM9_TRG_COM_IRQHandler +00004278 w .text 00000000 UART7_IRQHandler +00004234 w .text 00000000 USART2_IRQHandler +00004276 w .text 00000000 UART6_IRQHandler +0000b7be g F .text 0000004e __swrite +000066da g F .text 00000026 fiprintf +00006894 g F .text 0000029c _vfiprintf_r +00009e12 g F .text 0000006c _fwalk_reent +0000ad1a g F .text 000000f2 __mdiff +00003fa6 g F .text 00000010 port_context_switch +0000bfe0 g F .text 00000010 _kill +0000422c w .text 00000000 I2C2_ER_IRQHandler +00004200 w .text 00000000 DMA1_Channel2_IRQHandler +00003c3c g F .text 0000002a tos_task_yield +0000c868 g O .text 00000020 __sf_fake_stdout +00007c1e g F .text 00000046 siprintf +00000362 g F .text 00000024 .hidden __riscv_restore_12 +0000423e w .text 00000000 TIM8_BRK_IRQHandler +00003962 g F .text 0000002c tos_knl_start +0000c994 g O .text 00000101 _ctype_ +0000c000 g F .text 00000010 _read +0000b9dc g F .text 0000003c .hidden __unorddf2 +00004298 w .text 00000000 handle_reset +00004214 w .text 00000000 CAN1_SCE_IRQHandler +000041f0 w .text 00000000 FLASH_IRQHandler +00000356 g F .text 0000000c .hidden __riscv_save_0 +0000c010 g F .text 00000002 _exit +00004232 w .text 00000000 USART1_IRQHandler +0000a63c g F .text 000000a2 __smakebuf_r +00007c64 g F .text 00000012 strlen +0000426e w .text 00000000 OTG_FS_IRQHandler +0000727a g F .text 000002ac _printf_i +0000424e w .text 00000000 SPI3_IRQHandler +0000a5be g F .text 00000006 __locale_ctype_ptr_l +00005796 g F .text 000000ae .hidden __gedf2 +00009f34 g F .text 000004ce __gethex +00001a46 g F .text 0000000c js_run +20000254 g O .bss 00000004 __malloc_sbrk_start +00003a3e g F .text 00000024 tos_knl_init +00004228 w .text 00000000 I2C1_ER_IRQHandler +000015d4 g F .text 00000050 js_str +00003fb6 g F .text 0000000c port_irq_context_switch +0000399a g F .text 00000042 knl_sched +20000250 g O .bss 00000004 __malloc_free_list +0000037a g F .text 0000000c .hidden __riscv_restore_1 +00003f70 g F .text 00000016 tos_tick_handler +000004a6 g F .text 00000068 task2_entry +00003668 g F .text 00000016 mutex_release +00005db2 g F .text 0000073a .hidden __subdf3 +00006894 g F .text 0000029c _vfprintf_r +0000a992 g F .text 0000006a __lo0bits +000039f0 g F .text 00000010 knl_is_idle +20000070 g O .data 0000016c __global_locale +0000423c w .text 00000000 USBWakeUp_IRQHandler +0000bd82 g F .text 0000021e .hidden __trunctfdf2 +0000bfa0 g F .text 00000010 _close +0000b74a g F .text 0000000c raise +00007526 w F .text 00000476 _scanf_float +0000425c w .text 00000000 DMA2_Channel3_IRQHandler +0000a80e g F .text 00000098 __multadd +0000a7ca g F .text 00000044 _Bfree + + + +Disassembly of section .init: + +00000000 <_sinit>: + 0: 2980406f j 4298 + 4: 00000013 nop + 8: 00000013 nop + c: 00000013 nop + 10: 00000013 nop + 14: 00000013 nop + 18: 00000013 nop + 1c: 00000013 nop + 20: 00000013 nop + 24: 00000013 nop + 28: 00000013 nop + 2c: 00000013 nop + 30: 00000013 nop + 34: 00100073 ebreak + +Disassembly of section .vector: + +00000038 <_vector_base>: + ... + 40: 042e slli s0,s0,0xb + 42: 0000 unimp + 44: 0432 slli s0,s0,0xc + 46: 0000 unimp + 48: 0000 unimp + 4a: 0000 unimp + 4c: 41de lw gp,212(sp) + ... + 56: 0000 unimp + 58: 41e0 lw s0,68(a1) + 5a: 0000 unimp + 5c: 41e2 lw gp,24(sp) + ... + 66: 0000 unimp + 68: 400c lw a1,0(s0) + 6a: 0000 unimp + 6c: 0000 unimp + 6e: 0000 unimp + 70: 025c addi a5,sp,260 + 72: 0000 unimp + 74: 0000 unimp + 76: 0000 unimp + 78: 41e8 lw a0,68(a1) + 7a: 0000 unimp + 7c: 41ea lw gp,152(sp) + 7e: 0000 unimp + 80: 41ec lw a1,68(a1) + 82: 0000 unimp + 84: 41ee lw gp,216(sp) + 86: 0000 unimp + 88: 41f0 lw a2,68(a1) + 8a: 0000 unimp + 8c: 41f2 lw gp,28(sp) + 8e: 0000 unimp + 90: 41f4 lw a3,68(a1) + 92: 0000 unimp + 94: 41f6 lw gp,92(sp) + 96: 0000 unimp + 98: 41f8 lw a4,68(a1) + 9a: 0000 unimp + 9c: 41fa lw gp,156(sp) + 9e: 0000 unimp + a0: 41fc lw a5,68(a1) + a2: 0000 unimp + a4: 41fe lw gp,220(sp) + a6: 0000 unimp + a8: 4200 lw s0,0(a2) + aa: 0000 unimp + ac: 4202 lw tp,0(sp) + ae: 0000 unimp + b0: 4204 lw s1,0(a2) + b2: 0000 unimp + b4: 4206 lw tp,64(sp) + b6: 0000 unimp + b8: 4208 lw a0,0(a2) + ba: 0000 unimp + bc: 420a lw tp,128(sp) + be: 0000 unimp + c0: 420c lw a1,0(a2) + c2: 0000 unimp + c4: 420e lw tp,192(sp) + c6: 0000 unimp + c8: 4210 lw a2,0(a2) + ca: 0000 unimp + cc: 4212 lw tp,4(sp) + ce: 0000 unimp + d0: 4214 lw a3,0(a2) + d2: 0000 unimp + d4: 4216 lw tp,68(sp) + d6: 0000 unimp + d8: 4218 lw a4,0(a2) + da: 0000 unimp + dc: 421a lw tp,132(sp) + de: 0000 unimp + e0: 421c lw a5,0(a2) + e2: 0000 unimp + e4: 421e lw tp,196(sp) + e6: 0000 unimp + e8: 4220 lw s0,64(a2) + ea: 0000 unimp + ec: 4222 lw tp,8(sp) + ee: 0000 unimp + f0: 4224 lw s1,64(a2) + f2: 0000 unimp + f4: 4226 lw tp,72(sp) + f6: 0000 unimp + f8: 4228 lw a0,64(a2) + fa: 0000 unimp + fc: 422a lw tp,136(sp) + fe: 0000 unimp + 100: 422c lw a1,64(a2) + 102: 0000 unimp + 104: 422e lw tp,200(sp) + 106: 0000 unimp + 108: 4230 lw a2,64(a2) + 10a: 0000 unimp + 10c: 4232 lw tp,12(sp) + 10e: 0000 unimp + 110: 4234 lw a3,64(a2) + 112: 0000 unimp + 114: 4236 lw tp,76(sp) + 116: 0000 unimp + 118: 4238 lw a4,64(a2) + 11a: 0000 unimp + 11c: 423a lw tp,140(sp) + 11e: 0000 unimp + 120: 423c lw a5,64(a2) + 122: 0000 unimp + 124: 423e lw tp,204(sp) + 126: 0000 unimp + 128: 4240 lw s0,4(a2) + 12a: 0000 unimp + 12c: 4242 lw tp,16(sp) + 12e: 0000 unimp + 130: 4244 lw s1,4(a2) + 132: 0000 unimp + 134: 4246 lw tp,80(sp) + 136: 0000 unimp + 138: 4248 lw a0,4(a2) + 13a: 0000 unimp + 13c: 424a lw tp,144(sp) + 13e: 0000 unimp + 140: 424c lw a1,4(a2) + 142: 0000 unimp + 144: 424e lw tp,208(sp) + 146: 0000 unimp + 148: 4250 lw a2,4(a2) + 14a: 0000 unimp + 14c: 4252 lw tp,20(sp) + 14e: 0000 unimp + 150: 4254 lw a3,4(a2) + 152: 0000 unimp + 154: 4256 lw tp,84(sp) + 156: 0000 unimp + 158: 4258 lw a4,4(a2) + 15a: 0000 unimp + 15c: 425a lw tp,148(sp) + 15e: 0000 unimp + 160: 425c lw a5,4(a2) + 162: 0000 unimp + 164: 425e lw tp,212(sp) + 166: 0000 unimp + 168: 4260 lw s0,68(a2) + 16a: 0000 unimp + 16c: 4262 lw tp,24(sp) + 16e: 0000 unimp + 170: 4264 lw s1,68(a2) + 172: 0000 unimp + 174: 4266 lw tp,88(sp) + 176: 0000 unimp + 178: 4268 lw a0,68(a2) + 17a: 0000 unimp + 17c: 426a lw tp,152(sp) + 17e: 0000 unimp + 180: 426c lw a1,68(a2) + 182: 0000 unimp + 184: 426e lw tp,216(sp) + 186: 0000 unimp + 188: 4270 lw a2,68(a2) + 18a: 0000 unimp + 18c: 4272 lw tp,28(sp) + 18e: 0000 unimp + 190: 4274 lw a3,68(a2) + 192: 0000 unimp + 194: 4276 lw tp,92(sp) + 196: 0000 unimp + 198: 4278 lw a4,68(a2) + 19a: 0000 unimp + 19c: 427a lw tp,156(sp) + 19e: 0000 unimp + 1a0: 427c lw a5,68(a2) + 1a2: 0000 unimp + 1a4: 427e lw tp,220(sp) + 1a6: 0000 unimp + 1a8: 4280 lw s0,0(a3) + 1aa: 0000 unimp + 1ac: 4282 lw t0,0(sp) + 1ae: 0000 unimp + 1b0: 4284 lw s1,0(a3) + 1b2: 0000 unimp + 1b4: 4286 lw t0,64(sp) + 1b6: 0000 unimp + 1b8: 4288 lw a0,0(a3) + 1ba: 0000 unimp + 1bc: 428a lw t0,128(sp) + 1be: 0000 unimp + 1c0: 428c lw a1,0(a3) + 1c2: 0000 unimp + 1c4: 428e lw t0,192(sp) + 1c6: 0000 unimp + 1c8: 4290 lw a2,0(a3) + 1ca: 0000 unimp + 1cc: 4292 lw t0,4(sp) + 1ce: 0000 unimp + 1d0: 4294 lw a3,0(a3) + 1d2: 0000 unimp + 1d4: 4296 lw t0,68(sp) + ... + +Disassembly of section .text: + +00000200 : + 200: 8541a283 lw t0,-1964(gp) # 20000234 + 204: 0002a103 lw sp,0(t0) + 208: a011 j 20c + 20a: 0001 nop + +0000020c : + 20c: 4282 lw t0,0(sp) + 20e: 34129073 csrw mepc,t0 + 212: 4292 lw t0,4(sp) + 214: 30029073 csrw mstatus,t0 + 218: 40a2 lw ra,8(sp) + 21a: 41b2 lw gp,12(sp) + 21c: 4242 lw tp,16(sp) + 21e: 42d2 lw t0,20(sp) + 220: 4362 lw t1,24(sp) + 222: 43f2 lw t2,28(sp) + 224: 5402 lw s0,32(sp) + 226: 5492 lw s1,36(sp) + 228: 5522 lw a0,40(sp) + 22a: 55b2 lw a1,44(sp) + 22c: 5642 lw a2,48(sp) + 22e: 56d2 lw a3,52(sp) + 230: 5762 lw a4,56(sp) + 232: 57f2 lw a5,60(sp) + 234: 4806 lw a6,64(sp) + 236: 4896 lw a7,68(sp) + 238: 4926 lw s2,72(sp) + 23a: 49b6 lw s3,76(sp) + 23c: 4a46 lw s4,80(sp) + 23e: 4ad6 lw s5,84(sp) + 240: 4b66 lw s6,88(sp) + 242: 4bf6 lw s7,92(sp) + 244: 5c06 lw s8,96(sp) + 246: 5c96 lw s9,100(sp) + 248: 5d26 lw s10,104(sp) + 24a: 5db6 lw s11,108(sp) + 24c: 5e46 lw t3,112(sp) + 24e: 5ed6 lw t4,116(sp) + 250: 5f66 lw t5,120(sp) + 252: 5ff6 lw t6,124(sp) + 254: 6109 addi sp,sp,128 + 256: 30200073 mret + 25a: 0001 nop + +0000025c : + 25c: 7119 addi sp,sp,-128 + 25e: ca16 sw t0,20(sp) + 260: 02000293 li t0,32 + 264: 8042a073 csrs 0x804,t0 + 268: 300022f3 csrr t0,mstatus + 26c: c216 sw t0,4(sp) + 26e: 341022f3 csrr t0,mepc + 272: c016 sw t0,0(sp) + 274: c406 sw ra,8(sp) + 276: c60e sw gp,12(sp) + 278: c812 sw tp,16(sp) + 27a: cc1a sw t1,24(sp) + 27c: ce1e sw t2,28(sp) + 27e: d022 sw s0,32(sp) + 280: d226 sw s1,36(sp) + 282: d42a sw a0,40(sp) + 284: d62e sw a1,44(sp) + 286: d832 sw a2,48(sp) + 288: da36 sw a3,52(sp) + 28a: dc3a sw a4,56(sp) + 28c: de3e sw a5,60(sp) + 28e: c0c2 sw a6,64(sp) + 290: c2c6 sw a7,68(sp) + 292: c4ca sw s2,72(sp) + 294: c6ce sw s3,76(sp) + 296: c8d2 sw s4,80(sp) + 298: cad6 sw s5,84(sp) + 29a: ccda sw s6,88(sp) + 29c: cede sw s7,92(sp) + 29e: d0e2 sw s8,96(sp) + 2a0: d2e6 sw s9,100(sp) + 2a2: d4ea sw s10,104(sp) + 2a4: d6ee sw s11,108(sp) + 2a6: d8f2 sw t3,112(sp) + 2a8: daf6 sw t4,116(sp) + 2aa: dcfa sw t5,120(sp) + 2ac: defe sw t6,124(sp) + 2ae: 828a mv t0,sp + 2b0: 8201a103 lw sp,-2016(gp) # 20000200 + 2b4: c016 sw t0,0(sp) + 2b6: 4e3030ef jal ra,3f98 + 2ba: 4102 lw sp,0(sp) + 2bc: 85418293 addi t0,gp,-1964 # 20000234 + 2c0: 86018313 addi t1,gp,-1952 # 20000240 + 2c4: 0002a383 lw t2,0(t0) + 2c8: 0023a023 sw sp,0(t2) + 2cc: 00032303 lw t1,0(t1) + 2d0: 0062a023 sw t1,0(t0) + 2d4: 00032103 lw sp,0(t1) + 2d8: 4292 lw t0,4(sp) + 2da: 30029073 csrw mstatus,t0 + 2de: 4282 lw t0,0(sp) + 2e0: 34129073 csrw mepc,t0 + 2e4: 40a2 lw ra,8(sp) + 2e6: 41b2 lw gp,12(sp) + 2e8: 4242 lw tp,16(sp) + 2ea: 42d2 lw t0,20(sp) + 2ec: 4362 lw t1,24(sp) + 2ee: 43f2 lw t2,28(sp) + 2f0: 5402 lw s0,32(sp) + 2f2: 5492 lw s1,36(sp) + 2f4: 5522 lw a0,40(sp) + 2f6: 55b2 lw a1,44(sp) + 2f8: 5642 lw a2,48(sp) + 2fa: 56d2 lw a3,52(sp) + 2fc: 5762 lw a4,56(sp) + 2fe: 57f2 lw a5,60(sp) + 300: 4806 lw a6,64(sp) + 302: 4896 lw a7,68(sp) + 304: 4926 lw s2,72(sp) + 306: 49b6 lw s3,76(sp) + 308: 4a46 lw s4,80(sp) + 30a: 4ad6 lw s5,84(sp) + 30c: 4b66 lw s6,88(sp) + 30e: 4bf6 lw s7,92(sp) + 310: 5c06 lw s8,96(sp) + 312: 5c96 lw s9,100(sp) + 314: 5d26 lw s10,104(sp) + 316: 5db6 lw s11,108(sp) + 318: 5e46 lw t3,112(sp) + 31a: 5ed6 lw t4,116(sp) + 31c: 5f66 lw t5,120(sp) + 31e: 5ff6 lw t6,124(sp) + 320: 6109 addi sp,sp,128 + 322: 30200073 mret + +00000326 <__riscv_save_12>: + 326: 7139 addi sp,sp,-64 + 328: 4301 li t1,0 + 32a: c66e sw s11,12(sp) + 32c: a019 j 332 <__riscv_save_10+0x4> + +0000032e <__riscv_save_10>: + 32e: 7139 addi sp,sp,-64 + 330: 5341 li t1,-16 + 332: c86a sw s10,16(sp) + 334: ca66 sw s9,20(sp) + 336: cc62 sw s8,24(sp) + 338: ce5e sw s7,28(sp) + 33a: a019 j 340 <__riscv_save_4+0x4> + +0000033c <__riscv_save_4>: + 33c: 7139 addi sp,sp,-64 + 33e: 5301 li t1,-32 + 340: d05a sw s6,32(sp) + 342: d256 sw s5,36(sp) + 344: d452 sw s4,40(sp) + 346: d64e sw s3,44(sp) + 348: d84a sw s2,48(sp) + 34a: da26 sw s1,52(sp) + 34c: dc22 sw s0,56(sp) + 34e: de06 sw ra,60(sp) + 350: 40610133 sub sp,sp,t1 + 354: 8282 jr t0 + +00000356 <__riscv_save_0>: + 356: 1141 addi sp,sp,-16 + 358: c04a sw s2,0(sp) + 35a: c226 sw s1,4(sp) + 35c: c422 sw s0,8(sp) + 35e: c606 sw ra,12(sp) + 360: 8282 jr t0 + +00000362 <__riscv_restore_12>: + 362: 4db2 lw s11,12(sp) + 364: 0141 addi sp,sp,16 + +00000366 <__riscv_restore_10>: + 366: 4d02 lw s10,0(sp) + 368: 4c92 lw s9,4(sp) + 36a: 4c22 lw s8,8(sp) + 36c: 4bb2 lw s7,12(sp) + 36e: 0141 addi sp,sp,16 + +00000370 <__riscv_restore_4>: + 370: 4b02 lw s6,0(sp) + 372: 4a92 lw s5,4(sp) + 374: 4a22 lw s4,8(sp) + 376: 49b2 lw s3,12(sp) + 378: 0141 addi sp,sp,16 + +0000037a <__riscv_restore_0>: + 37a: 4902 lw s2,0(sp) + 37c: 4492 lw s1,4(sp) + 37e: 4422 lw s0,8(sp) + 380: 40b2 lw ra,12(sp) + 382: 0141 addi sp,sp,16 + 384: 8082 ret + +00000386 : + 386: 433d li t1,15 + 388: 872a mv a4,a0 + 38a: 02c37363 bgeu t1,a2,3b0 + 38e: 00f77793 andi a5,a4,15 + 392: efbd bnez a5,410 + 394: e5ad bnez a1,3fe + 396: ff067693 andi a3,a2,-16 + 39a: 8a3d andi a2,a2,15 + 39c: 96ba add a3,a3,a4 + 39e: c30c sw a1,0(a4) + 3a0: c34c sw a1,4(a4) + 3a2: c70c sw a1,8(a4) + 3a4: c74c sw a1,12(a4) + 3a6: 0741 addi a4,a4,16 + 3a8: fed76be3 bltu a4,a3,39e + 3ac: e211 bnez a2,3b0 + 3ae: 8082 ret + 3b0: 40c306b3 sub a3,t1,a2 + 3b4: 068a slli a3,a3,0x2 + 3b6: 00000297 auipc t0,0x0 + 3ba: 9696 add a3,a3,t0 + 3bc: 00a68067 jr 10(a3) + 3c0: 00b70723 sb a1,14(a4) + 3c4: 00b706a3 sb a1,13(a4) + 3c8: 00b70623 sb a1,12(a4) + 3cc: 00b705a3 sb a1,11(a4) + 3d0: 00b70523 sb a1,10(a4) + 3d4: 00b704a3 sb a1,9(a4) + 3d8: 00b70423 sb a1,8(a4) + 3dc: 00b703a3 sb a1,7(a4) + 3e0: 00b70323 sb a1,6(a4) + 3e4: 00b702a3 sb a1,5(a4) + 3e8: 00b70223 sb a1,4(a4) + 3ec: 00b701a3 sb a1,3(a4) + 3f0: 00b70123 sb a1,2(a4) + 3f4: 00b700a3 sb a1,1(a4) + 3f8: 00b70023 sb a1,0(a4) + 3fc: 8082 ret + 3fe: 0ff5f593 andi a1,a1,255 + 402: 00859693 slli a3,a1,0x8 + 406: 8dd5 or a1,a1,a3 + 408: 01059693 slli a3,a1,0x10 + 40c: 8dd5 or a1,a1,a3 + 40e: b761 j 396 + 410: 00279693 slli a3,a5,0x2 + 414: 00000297 auipc t0,0x0 + 418: 9696 add a3,a3,t0 + 41a: 8286 mv t0,ra + 41c: fa8680e7 jalr -88(a3) + 420: 8096 mv ra,t0 + 422: 17c1 addi a5,a5,-16 + 424: 8f1d sub a4,a4,a5 + 426: 963e add a2,a2,a5 + 428: f8c374e3 bgeu t1,a2,3b0 + 42c: b7a5 j 394 + +0000042e : + 42e: 30200073 mret + +00000432 : + 432: a001 j 432 + +00000434 : + 434: f23ff2ef jal t0,356 <__riscv_save_0> + 438: 0000c437 lui s0,0xc + 43c: 0b040513 addi a0,s0,176 # c0b0 <_exit+0xa0> + 440: 6ae070ef jal ra,7aee + 444: 4581 li a1,0 + 446: 7d000513 li a0,2000 + 44a: 0dd030ef jal ra,3d26 + 44e: b7fd j 43c + +00000450 : + 450: edfff2ef jal t0,32e <__riscv_save_10> + 454: 0000c4b7 lui s1,0xc + 458: 0000c937 lui s2,0xc + 45c: 8aaa mv s5,a0 + 45e: 8b2e mv s6,a1 + 460: 8a32 mv s4,a2 + 462: 4401 li s0,0 + 464: 0ac48493 addi s1,s1,172 # c0ac <_exit+0x9c> + 468: 6d490913 addi s2,s2,1748 # c6d4 <__clz_tab+0x144> + 46c: 0000cbb7 lui s7,0xc + 470: 01444863 blt s0,s4,480 + 474: 4529 li a0,10 + 476: 568070ef jal ra,79de + 47a: 50a010ef jal ra,1984 + 47e: b5e5 j 366 <__riscv_restore_10> + 480: 89a6 mv s3,s1 + 482: c011 beqz s0,486 + 484: 89ca mv s3,s2 + 486: 00341793 slli a5,s0,0x3 + 48a: 97da add a5,a5,s6 + 48c: 438c lw a1,0(a5) + 48e: 43d0 lw a2,4(a5) + 490: 8556 mv a0,s5 + 492: 0405 addi s0,s0,1 + 494: 140010ef jal ra,15d4 + 498: 862a mv a2,a0 + 49a: 85ce mv a1,s3 + 49c: 044b8513 addi a0,s7,68 # c044 <_exit+0x34> + 4a0: 4fc070ef jal ra,799c + 4a4: b7f1 j 470 + +000004a6 : + 4a6: e97ff2ef jal t0,33c <__riscv_save_4> + 4aa: 20005537 lui a0,0x20005 + 4ae: 7d000593 li a1,2000 + 4b2: 34850513 addi a0,a0,840 # 20005348 + 4b6: 480010ef jal ra,1936 + 4ba: 842a mv s0,a0 + 4bc: 4d6010ef jal ra,1992 + 4c0: 892a mv s2,a0 + 4c2: 00000537 lui a0,0x0 + 4c6: 45050513 addi a0,a0,1104 # 450 + 4ca: 89ae mv s3,a1 + 4cc: 4c0010ef jal ra,198c + 4d0: 0000c6b7 lui a3,0xc + 4d4: 872a mv a4,a0 + 4d6: 87ae mv a5,a1 + 4d8: 0c068693 addi a3,a3,192 # c0c0 <_exit+0xb0> + 4dc: 85ca mv a1,s2 + 4de: 864e mv a2,s3 + 4e0: 8522 mv a0,s0 + 4e2: 4b8010ef jal ra,199a + 4e6: 0000c5b7 lui a1,0xc + 4ea: 0c858593 addi a1,a1,200 # c0c8 <_exit+0xb8> + 4ee: 8522 mv a0,s0 + 4f0: 556010ef jal ra,1a46 + 4f4: 0000c4b7 lui s1,0xc + 4f8: 0d448593 addi a1,s1,212 # c0d4 <_exit+0xc4> + 4fc: 8522 mv a0,s0 + 4fe: 548010ef jal ra,1a46 + 502: 4581 li a1,0 + 504: 3e800513 li a0,1000 + 508: 01f030ef jal ra,3d26 + 50c: b7f5 j 4f8 + +0000050e
: + 50e: e49ff2ef jal t0,356 <__riscv_save_0> + 512: 6571 lui a0,0x1c + 514: 20050513 addi a0,a0,512 # 1c200 <_data_lma+0xf768> + 518: 0d6040ef jal ra,45ee + 51c: 200007b7 lui a5,0x20000 + 520: 1e07a583 lw a1,480(a5) # 200001e0 + 524: 0000c537 lui a0,0xc + 528: 04c50513 addi a0,a0,76 # c04c <_exit+0x3c> + 52c: 470070ef jal ra,799c + 530: 0000c5b7 lui a1,0xc + 534: 0000c537 lui a0,0xc + 538: 05c58593 addi a1,a1,92 # c05c <_exit+0x4c> + 53c: 06450513 addi a0,a0,100 # c064 <_exit+0x54> + 540: 45c070ef jal ra,799c + 544: 4fa030ef jal ra,3a3e + 548: 640d lui s0,0x3 + 54a: 200007b7 lui a5,0x20000 + 54e: 00000637 lui a2,0x0 + 552: 0000c5b7 lui a1,0xc + 556: 20003537 lui a0,0x20003 + 55a: 4881 li a7,0 + 55c: 80040813 addi a6,s0,-2048 # 2800 + 560: 25878793 addi a5,a5,600 # 20000258 + 564: 470d li a4,3 + 566: 4681 li a3,0 + 568: 43460613 addi a2,a2,1076 # 434 + 56c: 08458593 addi a1,a1,132 # c084 <_exit+0x74> + 570: a5850513 addi a0,a0,-1448 # 20002a58 + 574: 4ee030ef jal ra,3a62 + 578: 200037b7 lui a5,0x20003 + 57c: 00000637 lui a2,0x0 + 580: 0000c5b7 lui a1,0xc + 584: 20003537 lui a0,0x20003 + 588: 4881 li a7,0 + 58a: 80040813 addi a6,s0,-2048 + 58e: b4878793 addi a5,a5,-1208 # 20002b48 + 592: 4711 li a4,4 + 594: 4681 li a3,0 + 596: 4a660613 addi a2,a2,1190 # 4a6 + 59a: 08c58593 addi a1,a1,140 # c08c <_exit+0x7c> + 59e: ad050513 addi a0,a0,-1328 # 20002ad0 + 5a2: 4c0030ef jal ra,3a62 + 5a6: 3bc030ef jal ra,3962 + 5aa: 0000c537 lui a0,0xc + 5ae: 09450513 addi a0,a0,148 # c094 <_exit+0x84> + 5b2: 53c070ef jal ra,7aee + 5b6: 0001 nop + 5b8: bffd j 5b6 + +000005ba : + 5ba: 400217b7 lui a5,0x40021 + 5be: 4398 lw a4,0(a5) + 5c0: f8ff06b7 lui a3,0xf8ff0 + 5c4: 1141 addi sp,sp,-16 + 5c6: 00176713 ori a4,a4,1 + 5ca: c398 sw a4,0(a5) + 5cc: 43d8 lw a4,4(a5) + 5ce: 00020637 lui a2,0x20 + 5d2: 8f75 and a4,a4,a3 + 5d4: c3d8 sw a4,4(a5) + 5d6: 4398 lw a4,0(a5) + 5d8: fef706b7 lui a3,0xfef70 + 5dc: 16fd addi a3,a3,-1 + 5de: 8f75 and a4,a4,a3 + 5e0: c398 sw a4,0(a5) + 5e2: 4398 lw a4,0(a5) + 5e4: fffc06b7 lui a3,0xfffc0 + 5e8: 16fd addi a3,a3,-1 + 5ea: 8f75 and a4,a4,a3 + 5ec: c398 sw a4,0(a5) + 5ee: 43d8 lw a4,4(a5) + 5f0: ff8106b7 lui a3,0xff810 + 5f4: 16fd addi a3,a3,-1 + 5f6: 8f75 and a4,a4,a3 + 5f8: c3d8 sw a4,4(a5) + 5fa: 4398 lw a4,0(a5) + 5fc: ec0006b7 lui a3,0xec000 + 600: 16fd addi a3,a3,-1 + 602: 8f75 and a4,a4,a3 + 604: c398 sw a4,0(a5) + 606: 00ff0737 lui a4,0xff0 + 60a: c798 sw a4,8(a5) + 60c: 0207a623 sw zero,44(a5) # 4002102c <_eusrstack+0x2001102c> + 610: c402 sw zero,8(sp) + 612: c602 sw zero,12(sp) + 614: 4398 lw a4,0(a5) + 616: 66c1 lui a3,0x10 + 618: 8f55 or a4,a4,a3 + 61a: c398 sw a4,0(a5) + 61c: 400216b7 lui a3,0x40021 + 620: 6705 lui a4,0x1 + 622: 429c lw a5,0(a3) + 624: 8ff1 and a5,a5,a2 + 626: c63e sw a5,12(sp) + 628: 47a2 lw a5,8(sp) + 62a: 0785 addi a5,a5,1 + 62c: c43e sw a5,8(sp) + 62e: 47b2 lw a5,12(sp) + 630: e781 bnez a5,638 + 632: 47a2 lw a5,8(sp) + 634: fee797e3 bne a5,a4,622 + 638: 400217b7 lui a5,0x40021 + 63c: 439c lw a5,0(a5) + 63e: 00e79713 slli a4,a5,0xe + 642: 06075763 bgez a4,6b0 + 646: 4785 li a5,1 + 648: c63e sw a5,12(sp) + 64a: 4732 lw a4,12(sp) + 64c: 4785 li a5,1 + 64e: 04f71f63 bne a4,a5,6ac + 652: 400217b7 lui a5,0x40021 + 656: 43d8 lw a4,4(a5) + 658: ffc106b7 lui a3,0xffc10 + 65c: 16fd addi a3,a3,-1 + 65e: c3d8 sw a4,4(a5) + 660: 43d8 lw a4,4(a5) + 662: c3d8 sw a4,4(a5) + 664: 43d8 lw a4,4(a5) + 666: 40076713 ori a4,a4,1024 + 66a: c3d8 sw a4,4(a5) + 66c: 43d8 lw a4,4(a5) + 66e: 8f75 and a4,a4,a3 + 670: c3d8 sw a4,4(a5) + 672: 43d8 lw a4,4(a5) + 674: 001d06b7 lui a3,0x1d0 + 678: 8f55 or a4,a4,a3 + 67a: c3d8 sw a4,4(a5) + 67c: 4398 lw a4,0(a5) + 67e: 010006b7 lui a3,0x1000 + 682: 8f55 or a4,a4,a3 + 684: c398 sw a4,0(a5) + 686: 4398 lw a4,0(a5) + 688: 00671693 slli a3,a4,0x6 + 68c: fe06dde3 bgez a3,686 + 690: 43d8 lw a4,4(a5) + 692: 400216b7 lui a3,0x40021 + 696: 9b71 andi a4,a4,-4 + 698: c3d8 sw a4,4(a5) + 69a: 43d8 lw a4,4(a5) + 69c: 00276713 ori a4,a4,2 + 6a0: c3d8 sw a4,4(a5) + 6a2: 4721 li a4,8 + 6a4: 42dc lw a5,4(a3) + 6a6: 8bb1 andi a5,a5,12 + 6a8: fee79ee3 bne a5,a4,6a4 + 6ac: 0141 addi sp,sp,16 + 6ae: 8082 ret + 6b0: c602 sw zero,12(sp) + 6b2: bf61 j 64a + +000006b4 : + 6b4: 0145d713 srli a4,a1,0x14 + 6b8: 7ff00793 li a5,2047 + 6bc: 4515 li a0,5 + 6be: 00f71563 bne a4,a5,6c8 + 6c2: 81c1 srli a1,a1,0x10 + 6c4: 00f5f513 andi a0,a1,15 + 6c8: 8082 ret + +000006ca : + 6ca: c8dff2ef jal t0,356 <__riscv_save_0> + 6ce: 37dd jal 6b4 + 6d0: 1559 addi a0,a0,-10 + 6d2: 00153513 seqz a0,a0 + 6d6: b155 j 37a <__riscv_restore_0> + +000006d8 : + 6d8: 5138 lw a4,96(a0) + 6da: 4d7c lw a5,92(a0) + 6dc: 1141 addi sp,sp,-16 + 6de: c602 sw zero,12(sp) + 6e0: 00f77463 bgeu a4,a5,6e8 + 6e4: 8f99 sub a5,a5,a4 + 6e6: c63e sw a5,12(sp) + 6e8: 47b2 lw a5,12(sp) + 6ea: 4158 lw a4,4(a0) + 6ec: 00e7f363 bgeu a5,a4,6f2 + 6f0: c15c sw a5,4(a0) + 6f2: 557c lw a5,108(a0) + 6f4: 0078 addi a4,sp,12 + 6f6: 00f77763 bgeu a4,a5,704 + 6fa: 8f99 sub a5,a5,a4 + 6fc: 4118 lw a4,0(a0) + 6fe: 00f77363 bgeu a4,a5,704 + 702: c11c sw a5,0(a0) + 704: 0141 addi sp,sp,16 + 706: 8082 ret + +00000708 : + 708: 87aa mv a5,a0 + 70a: 4501 li a0,0 + 70c: 02b50863 beq a0,a1,73c + 710: 00d50763 beq a0,a3,71e + 714: 00a60733 add a4,a2,a0 + 718: 00070703 lb a4,0(a4) # 1000 + 71c: e701 bnez a4,724 + 71e: c185 beqz a1,73e + 720: 85aa mv a1,a0 + 722: a801 j 732 + 724: 00a78833 add a6,a5,a0 + 728: 00e80023 sb a4,0(a6) + 72c: 0505 addi a0,a0,1 + 72e: bff9 j 70c + 730: 157d addi a0,a0,-1 + 732: 953e add a0,a0,a5 + 734: 00050023 sb zero,0(a0) + 738: 852e mv a0,a1 + 73a: 8082 ret + 73c: f975 bnez a0,730 + 73e: 8082 ret + +00000740 : + 740: 02000e13 li t3,32 + 744: 4e91 li t4,4 + 746: 02f00693 li a3,47 + 74a: 02a00313 li t1,42 + 74e: 4f29 li t5,10 + 750: 00b66463 bltu a2,a1,758 + 754: 8532 mv a0,a2 + 756: 8082 ret + 758: 00c50733 add a4,a0,a2 + 75c: 00070803 lb a6,0(a4) + 760: 00160793 addi a5,a2,1 # 20001 <_data_lma+0x13569> + 764: 03c80c63 beq a6,t3,79c + 768: ff780893 addi a7,a6,-9 + 76c: 0ff8f893 andi a7,a7,255 + 770: 031ef663 bgeu t4,a7,79c + 774: 02b7f863 bgeu a5,a1,7a4 + 778: 02d81663 bne a6,a3,7a4 + 77c: 00f508b3 add a7,a0,a5 + 780: 00088883 lb a7,0(a7) + 784: 02d89063 bne a7,a3,7a4 + 788: 00260793 addi a5,a2,2 + 78c: 00b78863 beq a5,a1,79c + 790: 00f50733 add a4,a0,a5 + 794: 00070703 lb a4,0(a4) + 798: 01e71463 bne a4,t5,7a0 + 79c: 863e mv a2,a5 + 79e: bf4d j 750 + 7a0: 0785 addi a5,a5,1 + 7a2: b7ed j 78c + 7a4: 00360893 addi a7,a2,3 + 7a8: fab8f6e3 bgeu a7,a1,754 + 7ac: fad814e3 bne a6,a3,754 + 7b0: 97aa add a5,a5,a0 + 7b2: 00078783 lb a5,0(a5) # 40021000 <_eusrstack+0x20011000> + 7b6: f8679fe3 bne a5,t1,754 + 7ba: 00460793 addi a5,a2,4 + 7be: fcb78fe3 beq a5,a1,79c + 7c2: 00270603 lb a2,2(a4) + 7c6: 00661663 bne a2,t1,7d2 + 7ca: 00370603 lb a2,3(a4) + 7ce: fcd607e3 beq a2,a3,79c + 7d2: 0785 addi a5,a5,1 + 7d4: 0705 addi a4,a4,1 + 7d6: b7e5 j 7be + +000007d8 : + 7d8: 00b69b63 bne a3,a1,7ee + 7dc: b7bff2ef jal t0,356 <__riscv_save_0> + 7e0: 85b2 mv a1,a2 + 7e2: 8636 mv a2,a3 + 7e4: 71d050ef jal ra,6700 + 7e8: 00153513 seqz a0,a0 + 7ec: b679 j 37a <__riscv_restore_0> + 7ee: 4501 li a0,0 + 7f0: 8082 ret + +000007f2 : + 7f2: 87aa mv a5,a0 + 7f4: fd050513 addi a0,a0,-48 + 7f8: 0ff57513 andi a0,a0,255 + 7fc: 4725 li a4,9 + 7fe: 00a77d63 bgeu a4,a0,818 + 802: f9f78713 addi a4,a5,-97 + 806: 0ff77713 andi a4,a4,255 + 80a: 4695 li a3,5 + 80c: 00e6e763 bltu a3,a4,81a + 810: fa978793 addi a5,a5,-87 + 814: 0ff7f513 andi a0,a5,255 + 818: 8082 ret + 81a: fbf78713 addi a4,a5,-65 + 81e: 0ff77713 andi a4,a4,255 + 822: 4501 li a0,0 + 824: fee6eae3 bltu a3,a4,818 + 828: fc978793 addi a5,a5,-55 + 82c: b7e5 j 814 + +0000082e : + 82e: 00357713 andi a4,a0,3 + 832: 4685 li a3,1 + 834: 87aa mv a5,a0 + 836: 00d70e63 beq a4,a3,852 + 83a: 4521 li a0,8 + 83c: cf01 beqz a4,854 + 83e: 4689 li a3,2 + 840: 557d li a0,-1 + 842: 00d71963 bne a4,a3,854 + 846: 0027d513 srli a0,a5,0x2 + 84a: 050d addi a0,a0,3 + 84c: 9971 andi a0,a0,-4 + 84e: 0511 addi a0,a0,4 + 850: 8082 ret + 852: 4541 li a0,16 + 854: 8082 ret + +00000856 : + 856: b01ff2ef jal t0,356 <__riscv_save_0> + 85a: 1141 addi sp,sp,-16 + 85c: 842a mv s0,a0 + 85e: 84ae mv s1,a1 + 860: c632 sw a2,12(sp) + 862: 35a5 jal 6ca + 864: c501 beqz a0,86c + 866: 4632 lw a2,12(sp) + 868: c200 sw s0,0(a2) + 86a: c244 sw s1,4(a2) + 86c: 0141 addi sp,sp,16 + 86e: b631 j 37a <__riscv_restore_0> + +00000870 : + 870: ae7ff2ef jal t0,356 <__riscv_save_0> + 874: 5138 lw a4,96(a0) + 876: 4d7c lw a5,92(a0) + 878: 1141 addi sp,sp,-16 + 87a: c602 sw zero,12(sp) + 87c: 02e7f063 bgeu a5,a4,89c + 880: 0000c6b7 lui a3,0xc + 884: 0000c537 lui a0,0xc + 888: 34868693 addi a3,a3,840 # c348 <_exit+0x338> + 88c: 83018613 addi a2,gp,-2000 # 20000210 <__func__.3873> + 890: 09e00593 li a1,158 + 894: 35c50513 addi a0,a0,860 # c35c <_exit+0x34c> + 898: 609050ef jal ra,66a0 <__assert_func> + 89c: 4d3c lw a5,88(a0) + 89e: 4611 li a2,4 + 8a0: 0068 addi a0,sp,12 + 8a2: 95be add a1,a1,a5 + 8a4: 683050ef jal ra,6726 + 8a8: 4532 lw a0,12(sp) + 8aa: 0141 addi sp,sp,16 + 8ac: b4f9 j 37a <__riscv_restore_0> + +000008ae : + 8ae: aa9ff2ef jal t0,356 <__riscv_save_0> + 8b2: 1141 addi sp,sp,-16 + 8b4: 842e mv s0,a1 + 8b6: c636 sw a3,12(sp) + 8b8: 3f65 jal 870 + 8ba: 46b2 lw a3,12(sp) + 8bc: 8109 srli a0,a0,0x2 + 8be: 157d addi a0,a0,-1 + 8c0: c288 sw a0,0(a3) + 8c2: 00440513 addi a0,s0,4 + 8c6: 0141 addi sp,sp,16 + 8c8: bc4d j 37a <__riscv_restore_0> + +000008ca : + 8ca: a8dff2ef jal t0,356 <__riscv_save_0> + 8ce: 492c lw a1,80(a0) + 8d0: 842a mv s0,a0 + 8d2: 0591 addi a1,a1,4 + 8d4: 3f71 jal 870 + 8d6: 7ff007b7 lui a5,0x7ff00 + 8da: c828 sw a0,80(s0) + 8dc: c87c sw a5,84(s0) + 8de: bc71 j 37a <__riscv_restore_0> + +000008e0 : + 8e0: a77ff2ef jal t0,356 <__riscv_save_0> + 8e4: 892a mv s2,a0 + 8e6: 842e mv s0,a1 + 8e8: 852e mv a0,a1 + 8ea: 85b2 mv a1,a2 + 8ec: 84b2 mv s1,a2 + 8ee: 33d9 jal 6b4 + 8f0: 4719 li a4,6 + 8f2: 00e51563 bne a0,a4,8fc + 8f6: 00803533 snez a0,s0 + 8fa: b441 j 37a <__riscv_restore_0> + 8fc: 4715 li a4,5 + 8fe: 87aa mv a5,a0 + 900: 00e51b63 bne a0,a4,916 + 904: 4601 li a2,0 + 906: 4681 li a3,0 + 908: 8522 mv a0,s0 + 90a: 85a6 mv a1,s1 + 90c: 621040ef jal ra,572c <__eqdf2> + 910: 00a03533 snez a0,a0 + 914: b7dd j 8fa + 916: 4505 li a0,1 + 918: d3ed beqz a5,8fa + 91a: 471d li a4,7 + 91c: fce78fe3 beq a5,a4,8fa + 920: 4709 li a4,2 + 922: 4501 li a0,0 + 924: fce79be3 bne a5,a4,8fa + 928: 85a2 mv a1,s0 + 92a: 854a mv a0,s2 + 92c: 3791 jal 870 + 92e: 8109 srli a0,a0,0x2 + 930: 157d addi a0,a0,-1 + 932: bff9 j 910 + +00000934 : + 934: a09ff2ef jal t0,33c <__riscv_save_4> + 938: 84aa mv s1,a0 + 93a: 89b6 mv s3,a3 + 93c: 8a3a mv s4,a4 + 93e: 3f0d jal 870 + 940: 50bc lw a5,96(s1) + 942: ffc57413 andi s0,a0,-4 + 946: 02f47a63 bgeu s0,a5,97a + 94a: e019 bnez s0,950 + 94c: 8522 mv a0,s0 + 94e: b40d j 370 <__riscv_restore_4> + 950: 00440593 addi a1,s0,4 + 954: 8526 mv a0,s1 + 956: 3f29 jal 870 + 958: 85aa mv a1,a0 + 95a: 892a mv s2,a0 + 95c: 8526 mv a0,s1 + 95e: 3f09 jal 870 + 960: 4cb0 lw a2,88(s1) + 962: 00255693 srli a3,a0,0x2 + 966: 0911 addi s2,s2,4 + 968: 16fd addi a3,a3,-1 + 96a: 964a add a2,a2,s2 + 96c: 85d2 mv a1,s4 + 96e: 854e mv a0,s3 + 970: 35a5 jal 7d8 + 972: fd69 bnez a0,94c + 974: 85a2 mv a1,s0 + 976: 8526 mv a0,s1 + 978: b7d9 j 93e + 97a: 4401 li s0,0 + 97c: bfc1 j 94c + +0000097e : + 97e: 9bfff2ef jal t0,33c <__riscv_save_4> + 982: 1141 addi sp,sp,-16 + 984: 892a mv s2,a0 + 986: 842e mv s0,a1 + 988: 84b2 mv s1,a2 + 98a: 4985 li s3,1 + 98c: 8522 mv a0,s0 + 98e: 85a6 mv a1,s1 + 990: 3315 jal 6b4 + 992: 01351d63 bne a0,s3,9ac + 996: 05892583 lw a1,88(s2) + 99a: 0421 addi s0,s0,8 + 99c: 4621 li a2,8 + 99e: 95a2 add a1,a1,s0 + 9a0: 0028 addi a0,sp,8 + 9a2: 585050ef jal ra,6726 + 9a6: 4422 lw s0,8(sp) + 9a8: 44b2 lw s1,12(sp) + 9aa: b7cd j 98c + 9ac: 8522 mv a0,s0 + 9ae: 85a6 mv a1,s1 + 9b0: 0141 addi sp,sp,16 + 9b2: ba7d j 370 <__riscv_restore_4> + +000009b4 : + 9b4: 00050783 lb a5,0(a0) + 9b8: 05f00713 li a4,95 + 9bc: 06e78b63 beq a5,a4,a32 + 9c0: 02400713 li a4,36 + 9c4: 06e78763 beq a5,a4,a32 + 9c8: fdf7f793 andi a5,a5,-33 + 9cc: fbf78793 addi a5,a5,-65 # 7fefffbf <_eusrstack+0x5feeffbf> + 9d0: 0ff7f793 andi a5,a5,255 + 9d4: 4765 li a4,25 + 9d6: 04f77e63 bgeu a4,a5,a32 + 9da: 4781 li a5,0 + 9dc: 853e mv a0,a5 + 9de: 8082 ret + 9e0: 0485 addi s1,s1,1 + 9e2: c204 sw s1,0(a2) + 9e4: 4204 lw s1,0(a2) + 9e6: 02b4f663 bgeu s1,a1,a12 + 9ea: 009507b3 add a5,a0,s1 + 9ee: 00078783 lb a5,0(a5) + 9f2: ff0787e3 beq a5,a6,9e0 + 9f6: ff1785e3 beq a5,a7,9e0 + 9fa: fdf7f713 andi a4,a5,-33 + 9fe: fbf70713 addi a4,a4,-65 + a02: 0ff77713 andi a4,a4,255 + a06: fce37de3 bgeu t1,a4,9e0 + a0a: fd078793 addi a5,a5,-48 + a0e: fcf6f9e3 bgeu a3,a5,9e0 + a12: 211c lbu a5,0(a0) + a14: 475d li a4,23 + a16: f9e78793 addi a5,a5,-98 + a1a: 0ff7f793 andi a5,a5,255 + a1e: 34f76a63 bltu a4,a5,d72 + a22: 6731 lui a4,0xc + a24: 078a slli a5,a5,0x2 + a26: 0f070713 addi a4,a4,240 # c0f0 <_exit+0xe0> + a2a: 97ba add a5,a5,a4 + a2c: 439c lw a5,0(a5) + a2e: 842a mv s0,a0 + a30: 8782 jr a5 + a32: 925ff2ef jal t0,356 <__riscv_save_0> + a36: 05f00813 li a6,95 + a3a: 02400893 li a7,36 + a3e: 4365 li t1,25 + a40: 46a5 li a3,9 + a42: b74d j 9e4 + a44: 862a mv a2,a0 + a46: 0000c537 lui a0,0xc + a4a: 86a6 mv a3,s1 + a4c: 4595 li a1,5 + a4e: 3a050513 addi a0,a0,928 # c3a0 <_exit+0x390> + a52: 3359 jal 7d8 + a54: 4789 li a5,2 + a56: c119 beqz a0,a5c + a58: 03200793 li a5,50 + a5c: 853e mv a0,a5 + a5e: 91dff06f j 37a <__riscv_restore_0> + a62: 862a mv a2,a0 + a64: 0000c537 lui a0,0xc + a68: 86a6 mv a3,s1 + a6a: 4595 li a1,5 + a6c: 3a850513 addi a0,a0,936 # c3a8 <_exit+0x398> + a70: 33a5 jal 7d8 + a72: 03500793 li a5,53 + a76: f17d bnez a0,a5c + a78: 0000c537 lui a0,0xc + a7c: 86a6 mv a3,s1 + a7e: 8622 mv a2,s0 + a80: 4591 li a1,4 + a82: 3b050513 addi a0,a0,944 # c3b0 <_exit+0x3a0> + a86: 3b89 jal 7d8 + a88: 03300793 li a5,51 + a8c: f961 bnez a0,a5c + a8e: 0000c537 lui a0,0xc + a92: 86a6 mv a3,s1 + a94: 8622 mv a2,s0 + a96: 4595 li a1,5 + a98: 3b850513 addi a0,a0,952 # c3b8 <_exit+0x3a8> + a9c: 3b35 jal 7d8 + a9e: 03400793 li a5,52 + aa2: fd4d bnez a0,a5c + aa4: 0000c537 lui a0,0xc + aa8: 86a6 mv a3,s1 + aaa: 8622 mv a2,s0 + aac: 4595 li a1,5 + aae: 3c050513 addi a0,a0,960 # c3c0 <_exit+0x3b0> + ab2: 331d jal 7d8 + ab4: 03600793 li a5,54 + ab8: f155 bnez a0,a5c + aba: 0000c537 lui a0,0xc + abe: 86a6 mv a3,s1 + ac0: 8622 mv a2,s0 + ac2: 45a1 li a1,8 + ac4: 3c850513 addi a0,a0,968 # c3c8 <_exit+0x3b8> + ac8: 3b01 jal 7d8 + aca: 4789 li a5,2 + acc: d941 beqz a0,a5c + ace: 03700793 li a5,55 + ad2: b769 j a5c + ad4: 862a mv a2,a0 + ad6: 0000c537 lui a0,0xc + ada: 86a6 mv a3,s1 + adc: 4589 li a1,2 + ade: 3d450513 addi a0,a0,980 # c3d4 <_exit+0x3c4> + ae2: 39dd jal 7d8 + ae4: 03a00793 li a5,58 + ae8: f935 bnez a0,a5c + aea: 0000c537 lui a0,0xc + aee: 86a6 mv a3,s1 + af0: 8622 mv a2,s0 + af2: 459d li a1,7 + af4: 3d850513 addi a0,a0,984 # c3d8 <_exit+0x3c8> + af8: 31c5 jal 7d8 + afa: 4789 li a5,2 + afc: d125 beqz a0,a5c + afe: 03800793 li a5,56 + b02: bfa9 j a5c + b04: 862a mv a2,a0 + b06: 0000c537 lui a0,0xc + b0a: 86a6 mv a3,s1 + b0c: 4591 li a1,4 + b0e: 3e050513 addi a0,a0,992 # c3e0 <_exit+0x3d0> + b12: 31d9 jal 7d8 + b14: 4789 li a5,2 + b16: d139 beqz a0,a5c + b18: 03b00793 li a5,59 + b1c: b781 j a5c + b1e: 862a mv a2,a0 + b20: 0000c537 lui a0,0xc + b24: 86a6 mv a3,s1 + b26: 458d li a1,3 + b28: 3e850513 addi a0,a0,1000 # c3e8 <_exit+0x3d8> + b2c: 3175 jal 7d8 + b2e: 03d00793 li a5,61 + b32: f20515e3 bnez a0,a5c + b36: 0000c537 lui a0,0xc + b3a: 86a6 mv a3,s1 + b3c: 8622 mv a2,s0 + b3e: 45a1 li a1,8 + b40: 22050513 addi a0,a0,544 # c220 <_exit+0x210> + b44: 3951 jal 7d8 + b46: 03e00793 li a5,62 + b4a: f00519e3 bnez a0,a5c + b4e: 0000c537 lui a0,0xc + b52: 86a6 mv a3,s1 + b54: 8622 mv a2,s0 + b56: 459d li a1,7 + b58: 3ec50513 addi a0,a0,1004 # c3ec <_exit+0x3dc> + b5c: 39b5 jal 7d8 + b5e: 03c00793 li a5,60 + b62: ee051de3 bnez a0,a5c + b66: 0000c537 lui a0,0xc + b6a: 86a6 mv a3,s1 + b6c: 8622 mv a2,s0 + b6e: 4595 li a1,5 + b70: 3f450513 addi a0,a0,1012 # c3f4 <_exit+0x3e4> + b74: 3195 jal 7d8 + b76: 4789 li a5,2 + b78: ee0502e3 beqz a0,a5c + b7c: 05100793 li a5,81 + b80: bdf1 j a5c + b82: 862a mv a2,a0 + b84: 0000c537 lui a0,0xc + b88: 86a6 mv a3,s1 + b8a: 4589 li a1,2 + b8c: 3fc50513 addi a0,a0,1020 # c3fc <_exit+0x3ec> + b90: 31a1 jal 7d8 + b92: 03f00793 li a5,63 + b96: ec0513e3 bnez a0,a5c + b9a: 0000c537 lui a0,0xc + b9e: 86a6 mv a3,s1 + ba0: 8622 mv a2,s0 + ba2: 4589 li a1,2 + ba4: 40050513 addi a0,a0,1024 # c400 <_exit+0x3f0> + ba8: 3905 jal 7d8 + baa: 04000793 li a5,64 + bae: ea0517e3 bnez a0,a5c + bb2: 0000c537 lui a0,0xc + bb6: 86a6 mv a3,s1 + bb8: 8622 mv a2,s0 + bba: 45a9 li a1,10 + bbc: 40450513 addi a0,a0,1028 # c404 <_exit+0x3f4> + bc0: 3921 jal 7d8 + bc2: 4789 li a5,2 + bc4: e8050ce3 beqz a0,a5c + bc8: 04100793 li a5,65 + bcc: bd41 j a5c + bce: 862a mv a2,a0 + bd0: 0000c537 lui a0,0xc + bd4: 86a6 mv a3,s1 + bd6: 458d li a1,3 + bd8: 41050513 addi a0,a0,1040 # c410 <_exit+0x400> + bdc: 3ef5 jal 7d8 + bde: 4789 li a5,2 + be0: e6050ee3 beqz a0,a5c + be4: 04200793 li a5,66 + be8: bd95 j a5c + bea: 862a mv a2,a0 + bec: 0000c537 lui a0,0xc + bf0: 86a6 mv a3,s1 + bf2: 458d li a1,3 + bf4: 41450513 addi a0,a0,1044 # c414 <_exit+0x404> + bf8: 36c5 jal 7d8 + bfa: 04300793 li a5,67 + bfe: e4051fe3 bnez a0,a5c + c02: 0000c537 lui a0,0xc + c06: 86a6 mv a3,s1 + c08: 8622 mv a2,s0 + c0a: 4591 li a1,4 + c0c: 47050513 addi a0,a0,1136 # c470 <_exit+0x460> + c10: 36e1 jal 7d8 + c12: 4789 li a5,2 + c14: e40504e3 beqz a0,a5c + c18: 04f00793 li a5,79 + c1c: b581 j a5c + c1e: 862a mv a2,a0 + c20: 0000c537 lui a0,0xc + c24: 86a6 mv a3,s1 + c26: 4599 li a1,6 + c28: 41850513 addi a0,a0,1048 # c418 <_exit+0x408> + c2c: 3675 jal 7d8 + c2e: 4789 li a5,2 + c30: e20506e3 beqz a0,a5c + c34: 04400793 li a5,68 + c38: b515 j a5c + c3a: 862a mv a2,a0 + c3c: 0000c537 lui a0,0xc + c40: 86a6 mv a3,s1 + c42: 4599 li a1,6 + c44: 42050513 addi a0,a0,1056 # c420 <_exit+0x410> + c48: 3e41 jal 7d8 + c4a: 4789 li a5,2 + c4c: e00508e3 beqz a0,a5c + c50: 04500793 li a5,69 + c54: b521 j a5c + c56: 862a mv a2,a0 + c58: 0000c537 lui a0,0xc + c5c: 86a6 mv a3,s1 + c5e: 458d li a1,3 + c60: 42850513 addi a0,a0,1064 # c428 <_exit+0x418> + c64: 3e95 jal 7d8 + c66: 04800793 li a5,72 + c6a: de0519e3 bnez a0,a5c + c6e: 0000c537 lui a0,0xc + c72: 86a6 mv a3,s1 + c74: 8622 mv a2,s0 + c76: 4591 li a1,4 + c78: 42c50513 addi a0,a0,1068 # c42c <_exit+0x41c> + c7c: 3eb1 jal 7d8 + c7e: 04600793 li a5,70 + c82: dc051de3 bnez a0,a5c + c86: 0000c537 lui a0,0xc + c8a: 86a6 mv a3,s1 + c8c: 8622 mv a2,s0 + c8e: 4595 li a1,5 + c90: 43450513 addi a0,a0,1076 # c434 <_exit+0x424> + c94: 3691 jal 7d8 + c96: 04700793 li a5,71 + c9a: dc0511e3 bnez a0,a5c + c9e: 0000c537 lui a0,0xc + ca2: 86a6 mv a3,s1 + ca4: 8622 mv a2,s0 + ca6: 4591 li a1,4 + ca8: 43c50513 addi a0,a0,1084 # c43c <_exit+0x42c> + cac: 3635 jal 7d8 + cae: 05000793 li a5,80 + cb2: da0515e3 bnez a0,a5c + cb6: 0000c537 lui a0,0xc + cba: 86a6 mv a3,s1 + cbc: 8622 mv a2,s0 + cbe: 4599 li a1,6 + cc0: 44450513 addi a0,a0,1092 # c444 <_exit+0x434> + cc4: 3e11 jal 7d8 + cc6: 4789 li a5,2 + cc8: d8050ae3 beqz a0,a5c + ccc: 06a00793 li a5,106 + cd0: b371 j a5c + cd2: 862a mv a2,a0 + cd4: 0000c537 lui a0,0xc + cd8: 86a6 mv a3,s1 + cda: 45a5 li a1,9 + cdc: 47850513 addi a0,a0,1144 # c478 <_exit+0x468> + ce0: 3ce5 jal 7d8 + ce2: 4789 li a5,2 + ce4: d6050ce3 beqz a0,a5c + ce8: 04e00793 li a5,78 + cec: bb85 j a5c + cee: 862a mv a2,a0 + cf0: 0000c537 lui a0,0xc + cf4: 86a6 mv a3,s1 + cf6: 458d li a1,3 + cf8: 44c50513 addi a0,a0,1100 # c44c <_exit+0x43c> + cfc: 3cf1 jal 7d8 + cfe: 04900793 li a5,73 + d02: d4051de3 bnez a0,a5c + d06: 0000c537 lui a0,0xc + d0a: 86a6 mv a3,s1 + d0c: 8622 mv a2,s0 + d0e: 4591 li a1,4 + d10: 45050513 addi a0,a0,1104 # c450 <_exit+0x440> + d14: 34d1 jal 7d8 + d16: 4789 li a5,2 + d18: d40502e3 beqz a0,a5c + d1c: 04a00793 li a5,74 + d20: bb35 j a5c + d22: 862a mv a2,a0 + d24: 0000c537 lui a0,0xc + d28: 86a6 mv a3,s1 + d2a: 4595 li a1,5 + d2c: 45850513 addi a0,a0,1112 # c458 <_exit+0x448> + d30: 3465 jal 7d8 + d32: 04b00793 li a5,75 + d36: d20513e3 bnez a0,a5c + d3a: 0000c537 lui a0,0xc + d3e: 86a6 mv a3,s1 + d40: 8622 mv a2,s0 + d42: 4591 li a1,4 + d44: 46050513 addi a0,a0,1120 # c460 <_exit+0x450> + d48: 3c41 jal 7d8 + d4a: 4789 li a5,2 + d4c: d00508e3 beqz a0,a5c + d50: 04c00793 li a5,76 + d54: b321 j a5c + d56: 862a mv a2,a0 + d58: 0000c537 lui a0,0xc + d5c: 86a6 mv a3,s1 + d5e: 4595 li a1,5 + d60: 46850513 addi a0,a0,1128 # c468 <_exit+0x458> + d64: 3c95 jal 7d8 + d66: 4789 li a5,2 + d68: ce050ae3 beqz a0,a5c + d6c: 04d00793 li a5,77 + d70: b1f5 j a5c + d72: 4789 li a5,2 + d74: b1e5 j a5c + +00000d76 : + d76: de0ff2ef jal t0,356 <__riscv_save_0> + d7a: 03052903 lw s2,48(a0) + d7e: 4504 lw s1,8(a0) + d80: 5950 lw a2,52(a0) + d82: 842a mv s0,a0 + d84: 02050723 sb zero,46(a0) + d88: 020506a3 sb zero,45(a0) + d8c: 1141 addi sp,sp,-16 + d8e: 85ca mv a1,s2 + d90: 8526 mv a0,s1 + d92: 9afff0ef jal ra,740 + d96: d848 sw a0,52(s0) + d98: dc08 sw a0,56(s0) + d9a: 02042e23 sw zero,60(s0) + d9e: 01256963 bltu a0,s2,db0 + da2: 4785 li a5,1 + da4: 02f406a3 sb a5,45(s0) + da8: 4505 li a0,1 + daa: 0141 addi sp,sp,16 + dac: dceff06f j 37a <__riscv_restore_0> + db0: 94aa add s1,s1,a0 + db2: 00048783 lb a5,0(s1) + db6: 02f00713 li a4,47 + dba: 20e78463 beq a5,a4,fc2 + dbe: 08f74963 blt a4,a5,e50 + dc2: 02800713 li a4,40 + dc6: 14e78263 beq a5,a4,f0a + dca: 04f74063 blt a4,a5,e0a + dce: 02500713 li a4,37 + dd2: 20e78763 beq a5,a4,fe0 + dd6: 02f74363 blt a4,a5,dfc + dda: 02100713 li a4,33 + dde: 14e78363 beq a5,a4,f24 + de2: 02200713 li a4,34 + de6: 2ee78e63 beq a5,a4,10e2 + dea: 40a905b3 sub a1,s2,a0 + dee: 03c40613 addi a2,s0,60 + df2: 8526 mv a0,s1 + df4: 36c1 jal 9b4 + df6: 02a406a3 sb a0,45(s0) + dfa: a8f5 j ef6 + dfc: 02600713 li a4,38 + e00: 1ee78f63 beq a5,a4,ffe + e04: 02700713 li a4,39 + e08: bff9 j de6 + e0a: 02b00713 li a4,43 + e0e: 16e78c63 beq a5,a4,f86 + e12: 02f74663 blt a4,a5,e3e + e16: 02900713 li a4,41 + e1a: 0ee78a63 beq a5,a4,f0e + e1e: 02a00713 li a4,42 + e22: fce794e3 bne a5,a4,dea + e26: 0505 addi a0,a0,1 + e28: 19257a63 bgeu a0,s2,fbc + e2c: 00148783 lb a5,1(s1) + e30: 02a00713 li a4,42 + e34: 16e79d63 bne a5,a4,fae + e38: 06d00793 li a5,109 + e3c: a23d j f6a + e3e: 02d00713 li a4,45 + e42: 10e78b63 beq a5,a4,f58 + e46: 0cf75c63 bge a4,a5,f1e + e4a: 06400793 li a5,100 + e4e: a045 j eee + e50: 03e00713 li a4,62 + e54: 24e78363 beq a5,a4,109a + e58: 04f74263 blt a4,a5,e9c + e5c: 03a00713 li a4,58 + e60: 0ae78263 beq a5,a4,f04 + e64: 2ce7cd63 blt a5,a4,113e + e68: 03c00713 li a4,60 + e6c: 1ee78663 beq a5,a4,1058 + e70: 0af75563 bge a4,a5,f1a + e74: 00150793 addi a5,a0,1 + e78: 1d27fd63 bgeu a5,s2,1052 + e7c: 00148783 lb a5,1(s1) + e80: 03d00713 li a4,61 + e84: 1ce79763 bne a5,a4,1052 + e88: 0509 addi a0,a0,2 + e8a: 1d257463 bgeu a0,s2,1052 + e8e: 00248703 lb a4,2(s1) + e92: 1cf71063 bne a4,a5,1052 + e96: 07a00793 li a5,122 + e9a: a845 j f4a + e9c: 07b00713 li a4,123 + ea0: 06e78963 beq a5,a4,f12 + ea4: 02f74663 blt a4,a5,ed0 + ea8: 03f00713 li a4,63 + eac: 02e78f63 beq a5,a4,eea + eb0: 05e00713 li a4,94 + eb4: f2e79be3 bne a5,a4,dea + eb8: 0505 addi a0,a0,1 + eba: 23257163 bgeu a0,s2,10dc + ebe: 00148703 lb a4,1(s1) + ec2: 03d00793 li a5,61 + ec6: 20f71b63 bne a4,a5,10dc + eca: f8d00793 li a5,-115 + ece: a871 j f6a + ed0: 07d00713 li a4,125 + ed4: 04e78163 beq a5,a4,f16 + ed8: 14e7c763 blt a5,a4,1026 + edc: 07e00713 li a4,126 + ee0: f0e795e3 bne a5,a4,dea + ee4: 06900793 li a5,105 + ee8: a019 j eee + eea: f8200793 li a5,-126 + eee: 02f406a3 sb a5,45(s0) + ef2: 4785 li a5,1 + ef4: dc5c sw a5,60(s0) + ef6: 5c1c lw a5,56(s0) + ef8: 5c58 lw a4,60(s0) + efa: 02d44503 lbu a0,45(s0) + efe: 97ba add a5,a5,a4 + f00: d85c sw a5,52(s0) + f02: b565 j daa + f04: f8100793 li a5,-127 + f08: b7dd j eee + f0a: 4799 li a5,6 + f0c: b7cd j eee + f0e: 479d li a5,7 + f10: bff9 j eee + f12: 47a1 li a5,8 + f14: bfe9 j eee + f16: 47a5 li a5,9 + f18: bfd9 j eee + f1a: 4795 li a5,5 + f1c: bfc9 j eee + f1e: f8f00793 li a5,-113 + f22: b7f1 j eee + f24: 00150793 addi a5,a0,1 + f28: 0327f563 bgeu a5,s2,f52 + f2c: 00148703 lb a4,1(s1) + f30: 03d00793 li a5,61 + f34: 00f71f63 bne a4,a5,f52 + f38: 0509 addi a0,a0,2 + f3a: 01257c63 bgeu a0,s2,f52 + f3e: 00248703 lb a4,2(s1) + f42: 00f71863 bne a4,a5,f52 + f46: 07b00793 li a5,123 + f4a: 02f406a3 sb a5,45(s0) + f4e: 478d li a5,3 + f50: b755 j ef4 + f52: 06800793 li a5,104 + f56: bf61 j eee + f58: 0505 addi a0,a0,1 + f5a: 03257363 bgeu a0,s2,f80 + f5e: 00148703 lb a4,1(s1) + f62: 00f71863 bne a4,a5,f72 + f66: 06700793 li a5,103 + f6a: 02f406a3 sb a5,45(s0) + f6e: 4789 li a5,2 + f70: b751 j ef4 + f72: 03d00793 li a5,61 + f76: 00f71563 bne a4,a5,f80 + f7a: f8500793 li a5,-123 + f7e: b7f5 j f6a + f80: 07200793 li a5,114 + f84: b7ad j eee + f86: 0505 addi a0,a0,1 + f88: 03257063 bgeu a0,s2,fa8 + f8c: 00148703 lb a4,1(s1) + f90: 00f71563 bne a4,a5,f9a + f94: 06600793 li a5,102 + f98: bfc9 j f6a + f9a: 03d00793 li a5,61 + f9e: 00f71563 bne a4,a5,fa8 + fa2: f8400793 li a5,-124 + fa6: b7d1 j f6a + fa8: 07100793 li a5,113 + fac: b789 j eee + fae: 03d00713 li a4,61 + fb2: 00e79563 bne a5,a4,fbc + fb6: f8600793 li a5,-122 + fba: bf45 j f6a + fbc: 06e00793 li a5,110 + fc0: b73d j eee + fc2: 0505 addi a0,a0,1 + fc4: 01257b63 bgeu a0,s2,fda + fc8: 00148703 lb a4,1(s1) + fcc: 03d00793 li a5,61 + fd0: 00f71563 bne a4,a5,fda + fd4: f8700793 li a5,-121 + fd8: bf49 j f6a + fda: 06f00793 li a5,111 + fde: bf01 j eee + fe0: 0505 addi a0,a0,1 + fe2: 01257b63 bgeu a0,s2,ff8 + fe6: 00148703 lb a4,1(s1) + fea: 03d00793 li a5,61 + fee: 00f71563 bne a4,a5,ff8 + ff2: f8800793 li a5,-120 + ff6: bf95 j f6a + ff8: 07000793 li a5,112 + ffc: bdcd j eee + ffe: 0505 addi a0,a0,1 + 1000: 03257063 bgeu a0,s2,1020 + 1004: 00148703 lb a4,1(s1) + 1008: 00f71563 bne a4,a5,1012 + 100c: 07f00793 li a5,127 + 1010: bfa9 j f6a + 1012: 03d00793 li a5,61 + 1016: 00f71563 bne a4,a5,1020 + 101a: f8c00793 li a5,-116 + 101e: b7b1 j f6a + 1020: 07c00793 li a5,124 + 1024: b5e9 j eee + 1026: 0505 addi a0,a0,1 + 1028: 03257263 bgeu a0,s2,104c + 102c: 00148783 lb a5,1(s1) + 1030: 07c00713 li a4,124 + 1034: 00e79563 bne a5,a4,103e + 1038: f8000793 li a5,-128 + 103c: b73d j f6a + 103e: 03d00713 li a4,61 + 1042: 00e79563 bne a5,a4,104c + 1046: f8e00793 li a5,-114 + 104a: b705 j f6a + 104c: 07e00793 li a5,126 + 1050: bd79 j eee + 1052: f8300793 li a5,-125 + 1056: bd61 j eee + 1058: 00150713 addi a4,a0,1 + 105c: 03277c63 bgeu a4,s2,1094 + 1060: 00148703 lb a4,1(s1) + 1064: 02f71163 bne a4,a5,1086 + 1068: 0509 addi a0,a0,2 + 106a: 01257b63 bgeu a0,s2,1080 + 106e: 00248703 lb a4,2(s1) + 1072: 03d00793 li a5,61 + 1076: 00f71563 bne a4,a5,1080 + 107a: f8900793 li a5,-119 + 107e: b5f1 j f4a + 1080: 07300793 li a5,115 + 1084: b5dd j f6a + 1086: 03d00793 li a5,61 + 108a: 00f71563 bne a4,a5,1094 + 108e: 07700793 li a5,119 + 1092: bde1 j f6a + 1094: 07600793 li a5,118 + 1098: bd99 j eee + 109a: 00150713 addi a4,a0,1 + 109e: 03277c63 bgeu a4,s2,10d6 + 10a2: 00148703 lb a4,1(s1) + 10a6: 02f71163 bne a4,a5,10c8 + 10aa: 0509 addi a0,a0,2 + 10ac: 01257b63 bgeu a0,s2,10c2 + 10b0: 00248703 lb a4,2(s1) + 10b4: 03d00793 li a5,61 + 10b8: 00f71563 bne a4,a5,10c2 + 10bc: f8a00793 li a5,-118 + 10c0: b569 j f4a + 10c2: 07400793 li a5,116 + 10c6: b555 j f6a + 10c8: 03d00793 li a5,61 + 10cc: 00f71563 bne a4,a5,10d6 + 10d0: 07900793 li a5,121 + 10d4: bd59 j f6a + 10d6: 07800793 li a5,120 + 10da: bd11 j eee + 10dc: 07d00793 li a5,125 + 10e0: b539 j eee + 10e2: 4785 li a5,1 + 10e4: dc5c sw a5,60(s0) + 10e6: 05c00893 li a7,92 + 10ea: 07800313 li t1,120 + 10ee: 5c5c lw a5,60(s0) + 10f0: 00048583 lb a1,0(s1) + 10f4: 00f48833 add a6,s1,a5 + 10f8: 00f50733 add a4,a0,a5 + 10fc: 00080603 lb a2,0(a6) + 1100: 03277c63 bgeu a4,s2,1138 + 1104: 00c59763 bne a1,a2,1112 + 1108: 4711 li a4,4 + 110a: 02e406a3 sb a4,45(s0) + 110e: 0785 addi a5,a5,1 + 1110: b3d5 j ef4 + 1112: 4685 li a3,1 + 1114: 01161f63 bne a2,a7,1132 + 1118: 00270693 addi a3,a4,2 + 111c: 00d96e63 bltu s2,a3,1138 + 1120: 00180803 lb a6,1(a6) + 1124: 4689 li a3,2 + 1126: 00681663 bne a6,t1,1132 + 112a: 0711 addi a4,a4,4 + 112c: 00e96663 bltu s2,a4,1138 + 1130: 4691 li a3,4 + 1132: 97b6 add a5,a5,a3 + 1134: dc5c sw a5,60(s0) + 1136: bf65 j 10ee + 1138: dab61fe3 bne a2,a1,ef6 + 113c: b7f1 j 1108 + 113e: 8526 mv a0,s1 + 1140: 006c addi a1,sp,12 + 1142: 03b070ef jal ra,897c + 1146: 478d li a5,3 + 1148: 02f406a3 sb a5,45(s0) + 114c: 47b2 lw a5,12(sp) + 114e: c428 sw a0,72(s0) + 1150: c46c sw a1,76(s0) + 1152: 409784b3 sub s1,a5,s1 + 1156: dc44 sw s1,60(s0) + 1158: bb79 j ef6 + +0000115a : + 115a: 02e54703 lbu a4,46(a0) + 115e: e701 bnez a4,1166 + 1160: 02d54503 lbu a0,45(a0) + 1164: 8082 ret + 1166: 9f0ff2ef jal t0,356 <__riscv_save_0> + 116a: 3131 jal d76 + 116c: a0eff06f j 37a <__riscv_restore_0> + +00001170 : + 1170: 9ccff2ef jal t0,33c <__riscv_save_4> + 1174: 1141 addi sp,sp,-16 + 1176: 842a mv s0,a0 + 1178: 89ae mv s3,a1 + 117a: ef6ff0ef jal ra,870 + 117e: 892a mv s2,a0 + 1180: 02055863 bgez a0,11b0 + 1184: 4c28 lw a0,88(s0) + 1186: 800004b7 lui s1,0x80000 + 118a: fff4c793 not a5,s1 + 118e: 00f977b3 and a5,s2,a5 + 1192: 002c addi a1,sp,8 + 1194: 4611 li a2,4 + 1196: 954e add a0,a0,s3 + 1198: c43e sw a5,8(sp) + 119a: 58c050ef jal ra,6726 + 119e: ffc4c593 xori a1,s1,-4 + 11a2: 00397793 andi a5,s2,3 + 11a6: 00b975b3 and a1,s2,a1 + 11aa: ef81 bnez a5,11c2 + 11ac: 8522 mv a0,s0 + 11ae: 37c9 jal 1170 + 11b0: 80000537 lui a0,0x80000 + 11b4: ffc54513 xori a0,a0,-4 + 11b8: 00a97533 and a0,s2,a0 + 11bc: 0141 addi sp,sp,16 + 11be: 9b2ff06f j 370 <__riscv_restore_4> + 11c2: 4705 li a4,1 + 11c4: fee796e3 bne a5,a4,11b0 + 11c8: 8522 mv a0,s0 + 11ca: 375d jal 1170 + 11cc: 00498593 addi a1,s3,4 + 11d0: 8522 mv a0,s0 + 11d2: e9eff0ef jal ra,870 + 11d6: 85aa mv a1,a0 + 11d8: 8522 mv a0,s0 + 11da: 3f59 jal 1170 + 11dc: 4c2c lw a1,88(s0) + 11de: 09a1 addi s3,s3,8 + 11e0: 4621 li a2,8 + 11e2: 95ce add a1,a1,s3 + 11e4: 0028 addi a0,sp,8 + 11e6: 540050ef jal ra,6726 + 11ea: 44a2 lw s1,8(sp) + 11ec: 45b2 lw a1,12(sp) + 11ee: 8526 mv a0,s1 + 11f0: cc4ff0ef jal ra,6b4 + 11f4: 4789 li a5,2 + 11f6: 00a7f563 bgeu a5,a0,1200 + 11fa: 479d li a5,7 + 11fc: faf51ae3 bne a0,a5,11b0 + 1200: 85a6 mv a1,s1 + 1202: b76d j 11ac + +00001204 : + 1204: 922ff2ef jal t0,326 <__riscv_save_12> + 1208: 1101 addi sp,sp,-32 + 120a: 89aa mv s3,a0 + 120c: 8a2e mv s4,a1 + 120e: 852e mv a0,a1 + 1210: 85b2 mv a1,a2 + 1212: 84b6 mv s1,a3 + 1214: 893a mv s2,a4 + 1216: c632 sw a2,12(sp) + 1218: c9cff0ef jal ra,6b4 + 121c: 47a5 li a5,9 + 121e: 86aa mv a3,a0 + 1220: 1ea7e963 bltu a5,a0,1412 + 1224: 6731 lui a4,0xc + 1226: 00251793 slli a5,a0,0x2 + 122a: 15070713 addi a4,a4,336 # c150 <_exit+0x140> + 122e: 97ba add a5,a5,a4 + 1230: 439c lw a5,0(a5) + 1232: 4632 lw a2,12(sp) + 1234: 8782 jr a5 + 1236: 0000c637 lui a2,0xc + 123a: 46a5 li a3,9 + 123c: 47860613 addi a2,a2,1144 # c478 <_exit+0x468> + 1240: 85ca mv a1,s2 + 1242: 8526 mv a0,s1 + 1244: cc4ff0ef jal ra,708 + 1248: 6105 addi sp,sp,32 + 124a: 918ff06f j 362 <__riscv_restore_12> + 124e: 0000c637 lui a2,0xc + 1252: 4691 li a3,4 + 1254: 47060613 addi a2,a2,1136 # c470 <_exit+0x460> + 1258: b7e5 j 1240 + 125a: 001a7a13 andi s4,s4,1 + 125e: 000a1863 bnez s4,126e + 1262: 0000c637 lui a2,0xc + 1266: 3f460613 addi a2,a2,1012 # c3f4 <_exit+0x3e4> + 126a: 4695 li a3,5 + 126c: bfd1 j 1240 + 126e: 0000c637 lui a2,0xc + 1272: 43c60613 addi a2,a2,1084 # c43c <_exit+0x42c> + 1276: 4691 li a3,4 + 1278: b7e1 j 1240 + 127a: 0000c637 lui a2,0xc + 127e: 4685 li a3,1 + 1280: 4d060613 addi a2,a2,1232 # c4d0 <_exit+0x4c0> + 1284: 85ca mv a1,s2 + 1286: 8526 mv a0,s1 + 1288: c80ff0ef jal ra,708 + 128c: 842a mv s0,a0 + 128e: 85d2 mv a1,s4 + 1290: 854e mv a0,s3 + 1292: ddeff0ef jal ra,870 + 1296: ffc57b13 andi s6,a0,-4 + 129a: 0000cbb7 lui s7,0xc + 129e: 0000cc37 lui s8,0xc + 12a2: 0609a783 lw a5,96(s3) + 12a6: 00848cb3 add s9,s1,s0 + 12aa: 40890d33 sub s10,s2,s0 + 12ae: 00fb7463 bgeu s6,a5,12b6 + 12b2: 000b1d63 bnez s6,12cc + 12b6: 0000c637 lui a2,0xc + 12ba: 4685 li a3,1 + 12bc: 4dc60613 addi a2,a2,1244 # c4dc <_exit+0x4cc> + 12c0: 85ea mv a1,s10 + 12c2: 8566 mv a0,s9 + 12c4: c44ff0ef jal ra,708 + 12c8: 9522 add a0,a0,s0 + 12ca: bfbd j 1248 + 12cc: 004b0593 addi a1,s6,4 + 12d0: 854e mv a0,s3 + 12d2: d9eff0ef jal ra,870 + 12d6: 0589a583 lw a1,88(s3) + 12da: 008b0793 addi a5,s6,8 + 12de: 8daa mv s11,a0 + 12e0: 95be add a1,a1,a5 + 12e2: 4621 li a2,8 + 12e4: 0828 addi a0,sp,24 + 12e6: 440050ef jal ra,6726 + 12ea: fff40693 addi a3,s0,-1 + 12ee: 00d036b3 snez a3,a3 + 12f2: 4d4b8613 addi a2,s7,1236 # c4d4 <_exit+0x4c4> + 12f6: 85ea mv a1,s10 + 12f8: 8566 mv a0,s9 + 12fa: 4a62 lw s4,24(sp) + 12fc: 4af2 lw s5,28(sp) + 12fe: c0aff0ef jal ra,708 + 1302: 942a add s0,s0,a0 + 1304: 40890733 sub a4,s2,s0 + 1308: 008486b3 add a3,s1,s0 + 130c: 85ee mv a1,s11 + 130e: 7ff20637 lui a2,0x7ff20 + 1312: 854e mv a0,s3 + 1314: 3dc5 jal 1204 + 1316: 942a add s0,s0,a0 + 1318: 408905b3 sub a1,s2,s0 + 131c: 4685 li a3,1 + 131e: 4d8c0613 addi a2,s8,1240 # c4d8 <_exit+0x4c8> + 1322: 00848533 add a0,s1,s0 + 1326: be2ff0ef jal ra,708 + 132a: 942a add s0,s0,a0 + 132c: 40890733 sub a4,s2,s0 + 1330: 008486b3 add a3,s1,s0 + 1334: 85d2 mv a1,s4 + 1336: 8656 mv a2,s5 + 1338: 854e mv a0,s3 + 133a: 35e9 jal 1204 + 133c: 85da mv a1,s6 + 133e: 942a add s0,s0,a0 + 1340: 854e mv a0,s3 + 1342: d2eff0ef jal ra,870 + 1346: ffc57b13 andi s6,a0,-4 + 134a: bfa1 j 12a2 + 134c: 85d2 mv a1,s4 + 134e: 0834 addi a3,sp,24 + 1350: 854e mv a0,s3 + 1352: d5cff0ef jal ra,8ae + 1356: 0000ca37 lui s4,0xc + 135a: 8aaa mv s5,a0 + 135c: 4685 li a3,1 + 135e: 4e0a0613 addi a2,s4,1248 # c4e0 <_exit+0x4d0> + 1362: 85ca mv a1,s2 + 1364: 8526 mv a0,s1 + 1366: ba2ff0ef jal ra,708 + 136a: 0589a603 lw a2,88(s3) + 136e: 46e2 lw a3,24(sp) + 1370: 842a mv s0,a0 + 1372: 9656 add a2,a2,s5 + 1374: 40a905b3 sub a1,s2,a0 + 1378: 9526 add a0,a0,s1 + 137a: b8eff0ef jal ra,708 + 137e: 942a add s0,s0,a0 + 1380: 4685 li a3,1 + 1382: 4e0a0613 addi a2,s4,1248 + 1386: 408905b3 sub a1,s2,s0 + 138a: 00848533 add a0,s1,s0 + 138e: bf1d j 12c4 + 1390: 87b2 mv a5,a2 + 1392: 89b2 mv s3,a2 + 1394: 8552 mv a0,s4 + 1396: 0830 addi a2,sp,24 + 1398: 85be mv a1,a5 + 139a: 760060ef jal ra,7afa + 139e: 4601 li a2,0 + 13a0: 4681 li a3,0 + 13a2: 8952 mv s2,s4 + 13a4: 388040ef jal ra,572c <__eqdf2> + 13a8: c919 beqz a0,13be + 13aa: 0000c5b7 lui a1,0xc + 13ae: 4cc58593 addi a1,a1,1228 # c4cc <_exit+0x4bc> + 13b2: 864a mv a2,s2 + 13b4: 86ce mv a3,s3 + 13b6: 8526 mv a0,s1 + 13b8: 067060ef jal ra,7c1e + 13bc: b571 j 1248 + 13be: 0000c5b7 lui a1,0xc + 13c2: 4c458593 addi a1,a1,1220 # c4c4 <_exit+0x4b4> + 13c6: b7f5 j 13b2 + 13c8: 85d2 mv a1,s4 + 13ca: 0834 addi a3,sp,24 + 13cc: 854e mv a0,s3 + 13ce: ce0ff0ef jal ra,8ae + 13d2: 0000c637 lui a2,0xc + 13d6: 8a2a mv s4,a0 + 13d8: 46a1 li a3,8 + 13da: 22060613 addi a2,a2,544 # c220 <_exit+0x210> + 13de: 85ca mv a1,s2 + 13e0: 8526 mv a0,s1 + 13e2: b26ff0ef jal ra,708 + 13e6: 0589a603 lw a2,88(s3) + 13ea: 842a mv s0,a0 + 13ec: 46e2 lw a3,24(sp) + 13ee: 9652 add a2,a2,s4 + 13f0: bf59 j 1386 + 13f2: 0000c637 lui a2,0xc + 13f6: 86d2 mv a3,s4 + 13f8: 4e460613 addi a2,a2,1252 # c4e4 <_exit+0x4d4> + 13fc: 85ca mv a1,s2 + 13fe: 8526 mv a0,s1 + 1400: 7ae060ef jal ra,7bae + 1404: b591 j 1248 + 1406: 0000c637 lui a2,0xc + 140a: 86d2 mv a3,s4 + 140c: 4f460613 addi a2,a2,1268 # c4f4 <_exit+0x4e4> + 1410: b7f5 j 13fc + 1412: 0000c637 lui a2,0xc + 1416: 50060613 addi a2,a2,1280 # c500 <_exit+0x4f0> + 141a: b7cd j 13fc + +0000141c : + 141c: 7139 addi sp,sp,-64 + 141e: ca26 sw s1,20(sp) + 1420: d432 sw a2,40(sp) + 1422: 00c50493 addi s1,a0,12 # 8000000c <_eusrstack+0x5fff000c> + 1426: 0000c637 lui a2,0xc + 142a: cc22 sw s0,24(sp) + 142c: c84a sw s2,16(sp) + 142e: 842a mv s0,a0 + 1430: 892e mv s2,a1 + 1432: d636 sw a3,44(sp) + 1434: 2e060613 addi a2,a2,736 # c2e0 <_exit+0x2d0> + 1438: 469d li a3,7 + 143a: 02100593 li a1,33 + 143e: 8526 mv a0,s1 + 1440: ce06 sw ra,28(sp) + 1442: da3e sw a5,52(sp) + 1444: d83a sw a4,48(sp) + 1446: dc42 sw a6,56(sp) + 1448: de46 sw a7,60(sp) + 144a: abeff0ef jal ra,708 + 144e: 02100593 li a1,33 + 1452: 1034 addi a3,sp,40 + 1454: 8d89 sub a1,a1,a0 + 1456: 864a mv a2,s2 + 1458: 9526 add a0,a0,s1 + 145a: c636 sw a3,12(sp) + 145c: 6f6070ef jal ra,8b52 + 1460: 581c lw a5,48(s0) + 1462: 02040723 sb zero,46(s0) + 1466: 40f2 lw ra,28(sp) + 1468: d85c sw a5,52(s0) + 146a: 10000793 li a5,256 + 146e: b45e sh a5,44(s0) + 1470: 4462 lw s0,24(sp) + 1472: 44d2 lw s1,20(sp) + 1474: 4942 lw s2,16(sp) + 1476: 4501 li a0,0 + 1478: 7ffa05b7 lui a1,0x7ffa0 + 147c: 6121 addi sp,sp,64 + 147e: 8082 ret + +00001480 : + 1480: ebdfe2ef jal t0,33c <__riscv_save_4> + 1484: 5120 lw s0,96(a0) + 1486: 00768793 addi a5,a3,7 + 148a: 4d78 lw a4,92(a0) + 148c: 1141 addi sp,sp,-16 + 148e: 9bf1 andi a5,a5,-4 + 1490: c62e sw a1,12(sp) + 1492: 97a2 add a5,a5,s0 + 1494: 84aa mv s1,a0 + 1496: 00f77b63 bgeu a4,a5,14ac + 149a: 0000c5b7 lui a1,0xc + 149e: 38058593 addi a1,a1,896 # c380 <_exit+0x370> + 14a2: 8526 mv a0,s1 + 14a4: 3fa5 jal 141c + 14a6: 0141 addi sp,sp,16 + 14a8: ec9fe06f j 370 <__riscv_restore_4> + 14ac: d13c sw a5,96(a0) + 14ae: 57fd li a5,-1 + 14b0: fef405e3 beq s0,a5,149a + 14b4: 4d28 lw a0,88(a0) + 14b6: 89b2 mv s3,a2 + 14b8: 006c addi a1,sp,12 + 14ba: 4611 li a2,4 + 14bc: 9522 add a0,a0,s0 + 14be: 8936 mv s2,a3 + 14c0: 266050ef jal ra,6726 + 14c4: 00098a63 beqz s3,14d8 + 14c8: 4cbc lw a5,88(s1) + 14ca: 00440513 addi a0,s0,4 + 14ce: 864a mv a2,s2 + 14d0: 85ce mv a1,s3 + 14d2: 953e add a0,a0,a5 + 14d4: 308050ef jal ra,67dc + 14d8: 45b2 lw a1,12(sp) + 14da: 4789 li a5,2 + 14dc: 898d andi a1,a1,3 + 14de: 00f59763 bne a1,a5,14ec + 14e2: 4cbc lw a5,88(s1) + 14e4: 97a2 add a5,a5,s0 + 14e6: 97ca add a5,a5,s2 + 14e8: 000781a3 sb zero,3(a5) + 14ec: 05c2 slli a1,a1,0x10 + 14ee: 7ff007b7 lui a5,0x7ff00 + 14f2: 8522 mv a0,s0 + 14f4: 8ddd or a1,a1,a5 + 14f6: bf45 j 14a6 + +000014f8 : + 14f8: e5ffe2ef jal t0,356 <__riscv_save_0> + 14fc: 4d20 lw s0,88(a0) + 14fe: 7179 addi sp,sp,-48 + 1500: 84aa mv s1,a0 + 1502: 942e add s0,s0,a1 + 1504: 85a2 mv a1,s0 + 1506: 4611 li a2,4 + 1508: 0868 addi a0,sp,28 + 150a: c642 sw a6,12(sp) + 150c: c236 sw a3,4(sp) + 150e: c43e sw a5,8(sp) + 1510: 216050ef jal ra,6726 + 1514: 47a2 lw a5,8(sp) + 1516: 4692 lw a3,4(sp) + 1518: 100c addi a1,sp,32 + 151a: d43e sw a5,40(sp) + 151c: 47b2 lw a5,12(sp) + 151e: 4611 li a2,4 + 1520: 8522 mv a0,s0 + 1522: d63e sw a5,44(sp) + 1524: 50bc lw a5,96(s1) + 1526: d236 sw a3,36(sp) + 1528: d03e sw a5,32(sp) + 152a: 1fc050ef jal ra,6726 + 152e: 45f2 lw a1,28(sp) + 1530: 1050 addi a2,sp,36 + 1532: 46b1 li a3,12 + 1534: 99f1 andi a1,a1,-4 + 1536: 8526 mv a0,s1 + 1538: 0015e593 ori a1,a1,1 + 153c: 3791 jal 1480 + 153e: 6145 addi sp,sp,48 + 1540: e3bfe06f j 37a <__riscv_restore_0> + +00001544 : + 1544: e13fe2ef jal t0,356 <__riscv_save_0> + 1548: 02f54783 lbu a5,47(a0) + 154c: 1141 addi sp,sp,-16 + 154e: 8b85 andi a5,a5,1 + 1550: cf99 beqz a5,156e + 1552: 0000c6b7 lui a3,0xc + 1556: 0000c537 lui a0,0xc + 155a: 38468693 addi a3,a3,900 # c384 <_exit+0x374> + 155e: 83818613 addi a2,gp,-1992 # 20000218 <__func__.4194> + 1562: 22d00593 li a1,557 + 1566: 35c50513 addi a0,a0,860 # c35c <_exit+0x34c> + 156a: 136050ef jal ra,66a0 <__assert_func> + 156e: 493c lw a5,80(a0) + 1570: 0070 addi a2,sp,12 + 1572: 4691 li a3,4 + 1574: 4581 li a1,0 + 1576: 842a mv s0,a0 + 1578: c63e sw a5,12(sp) + 157a: 3719 jal 1480 + 157c: c828 sw a0,80(s0) + 157e: c86c sw a1,84(s0) + 1580: 0141 addi sp,sp,16 + 1582: df9fe06f j 37a <__riscv_restore_0> + +00001586 : + 1586: dd1fe2ef jal t0,356 <__riscv_save_0> + 158a: 1141 addi sp,sp,-16 + 158c: c62e sw a1,12(sp) + 158e: 842a mv s0,a0 + 1590: 84b2 mv s1,a2 + 1592: 36e1 jal 115a + 1594: 45b2 lw a1,12(sp) + 1596: 00b50e63 beq a0,a1,15b2 + 159a: 0000c5b7 lui a1,0xc + 159e: 29c58593 addi a1,a1,668 # c29c <_exit+0x28c> + 15a2: 8522 mv a0,s0 + 15a4: 3da5 jal 141c + 15a6: c088 sw a0,0(s1) + 15a8: c0cc sw a1,4(s1) + 15aa: 4501 li a0,0 + 15ac: 0141 addi sp,sp,16 + 15ae: dcdfe06f j 37a <__riscv_restore_0> + 15b2: 4785 li a5,1 + 15b4: 02f40723 sb a5,46(s0) + 15b8: 4505 li a0,1 + 15ba: bfcd j 15ac + +000015bc : + 15bc: d9bfe2ef jal t0,356 <__riscv_save_0> + 15c0: 00160693 addi a3,a2,1 + 15c4: 00269793 slli a5,a3,0x2 + 15c8: 862e mv a2,a1 + 15ca: 0027e593 ori a1,a5,2 + 15ce: 3d4d jal 1480 + 15d0: dabfe06f j 37a <__riscv_restore_0> + +000015d4 : + 15d4: d69fe2ef jal t0,33c <__riscv_save_4> + 15d8: 84aa mv s1,a0 + 15da: 892e mv s2,a1 + 15dc: 852e mv a0,a1 + 15de: 85b2 mv a1,a2 + 15e0: 89b2 mv s3,a2 + 15e2: 8e8ff0ef jal ra,6ca + 15e6: 00c48413 addi s0,s1,12 # 8000000c <_eusrstack+0x5fff000c> + 15ea: e50d bnez a0,1614 + 15ec: 50b8 lw a4,96(s1) + 15ee: 4cfc lw a5,92(s1) + 15f0: 00470693 addi a3,a4,4 + 15f4: 02f6f363 bgeu a3,a5,161a + 15f8: 4ca0 lw s0,88(s1) + 15fa: 17f1 addi a5,a5,-4 + 15fc: 85ca mv a1,s2 + 15fe: 9436 add s0,s0,a3 + 1600: 864e mv a2,s3 + 1602: 40e78733 sub a4,a5,a4 + 1606: 86a2 mv a3,s0 + 1608: 8526 mv a0,s1 + 160a: 3eed jal 1204 + 160c: 862a mv a2,a0 + 160e: 4581 li a1,0 + 1610: 8526 mv a0,s1 + 1612: 376d jal 15bc + 1614: 8522 mv a0,s0 + 1616: d5bfe06f j 370 <__riscv_restore_4> + 161a: 0000c437 lui s0,0xc + 161e: 0ac40413 addi s0,s0,172 # c0ac <_exit+0x9c> + 1622: bfcd j 1614 + +00001624 : + 1624: d03fe2ef jal t0,326 <__riscv_save_12> + 1628: 5d1c lw a5,56(a0) + 162a: 00852983 lw s3,8(a0) + 162e: 4d24 lw s1,88(a0) + 1630: 1101 addi sp,sp,-32 + 1632: 99be add s3,s3,a5 + 1634: 513c lw a5,96(a0) + 1636: 00478713 addi a4,a5,4 # 7ff00004 <_eusrstack+0x5fef0004> + 163a: 94ba add s1,s1,a4 + 163c: 5d58 lw a4,60(a0) + 163e: 97ba add a5,a5,a4 + 1640: 4d78 lw a4,92(a0) + 1642: 0791 addi a5,a5,4 + 1644: 10f77163 bgeu a4,a5,1746 + 1648: 0000c5b7 lui a1,0xc + 164c: 38058593 addi a1,a1,896 # c380 <_exit+0x370> + 1650: 33f1 jal 141c + 1652: 6105 addi sp,sp,32 + 1654: d0ffe06f j 362 <__riscv_restore_12> + 1658: 01298533 add a0,s3,s2 + 165c: 2108 lbu a0,0(a0) + 165e: 0d751b63 bne a0,s7,1734 + 1662: 974e add a4,a4,s3 + 1664: 2318 lbu a4,0(a4) + 1666: 0009c503 lbu a0,0(s3) + 166a: 02a71363 bne a4,a0,1690 + 166e: 00c487b3 add a5,s1,a2 + 1672: a398 sb a4,0(a5) + 1674: 0905 addi s2,s2,1 + 1676: 0605 addi a2,a2,1 + 1678: 87ca mv a5,s2 + 167a: 5c48 lw a0,60(s0) + 167c: 00278713 addi a4,a5,2 + 1680: 00178913 addi s2,a5,1 + 1684: fca76ae3 bltu a4,a0,1658 + 1688: 8522 mv a0,s0 + 168a: 4581 li a1,0 + 168c: 3f05 jal 15bc + 168e: b7d1 j 1652 + 1690: 01871763 bne a4,s8,169e + 1694: 00c487b3 add a5,s1,a2 + 1698: 01078023 sb a6,0(a5) + 169c: bfe1 j 1674 + 169e: 01971663 bne a4,s9,16aa + 16a2: 00c487b3 add a5,s1,a2 + 16a6: a38c sb a1,0(a5) + 16a8: b7f1 j 1674 + 16aa: 01a71663 bne a4,s10,16b6 + 16ae: 00c487b3 add a5,s1,a2 + 16b2: a394 sb a3,0(a5) + 16b4: b7c1 j 1674 + 16b6: 07b71963 bne a4,s11,1728 + 16ba: 00378913 addi s2,a5,3 + 16be: 01298733 add a4,s3,s2 + 16c2: 2308 lbu a0,0(a4) + 16c4: fd050713 addi a4,a0,-48 + 16c8: 00eafa63 bgeu s5,a4,16dc + 16cc: fdf57713 andi a4,a0,-33 + 16d0: fbf70713 addi a4,a4,-65 + 16d4: 0ff77713 andi a4,a4,255 + 16d8: 04eb6863 bltu s6,a4,1728 + 16dc: 97ce add a5,a5,s3 + 16de: 23d8 lbu a4,4(a5) + 16e0: fd070793 addi a5,a4,-48 + 16e4: 00fafa63 bgeu s5,a5,16f8 + 16e8: fdf77793 andi a5,a4,-33 + 16ec: fbf78793 addi a5,a5,-65 + 16f0: 0ff7f793 andi a5,a5,255 + 16f4: 02fb6a63 bltu s6,a5,1728 + 16f8: ce42 sw a6,28(sp) + 16fa: cc2e sw a1,24(sp) + 16fc: ca36 sw a3,20(sp) + 16fe: c832 sw a2,16(sp) + 1700: c63a sw a4,12(sp) + 1702: 8f0ff0ef jal ra,7f2 + 1706: 4732 lw a4,12(sp) + 1708: 8a2a mv s4,a0 + 170a: 0a12 slli s4,s4,0x4 + 170c: 853a mv a0,a4 + 170e: 8e4ff0ef jal ra,7f2 + 1712: 4642 lw a2,16(sp) + 1714: 00aa6a33 or s4,s4,a0 + 1718: 46d2 lw a3,20(sp) + 171a: 00c487b3 add a5,s1,a2 + 171e: 01478023 sb s4,0(a5) + 1722: 45e2 lw a1,24(sp) + 1724: 4872 lw a6,28(sp) + 1726: b7b9 j 1674 + 1728: 0000c5b7 lui a1,0xc + 172c: 32458593 addi a1,a1,804 # c324 <_exit+0x314> + 1730: 8522 mv a0,s0 + 1732: bf39 j 1650 + 1734: 441c lw a5,8(s0) + 1736: 5c18 lw a4,56(s0) + 1738: 97ca add a5,a5,s2 + 173a: 97ba add a5,a5,a4 + 173c: 2398 lbu a4,0(a5) + 173e: 00c487b3 add a5,s1,a2 + 1742: a398 sb a4,0(a5) + 1744: bf0d j 1676 + 1746: 842a mv s0,a0 + 1748: 4601 li a2,0 + 174a: 4781 li a5,0 + 174c: 05c00b93 li s7,92 + 1750: 06e00c13 li s8,110 + 1754: 07400c93 li s9,116 + 1758: 07200d13 li s10,114 + 175c: 07800d93 li s11,120 + 1760: 4aa5 li s5,9 + 1762: 4b15 li s6,5 + 1764: 46b5 li a3,13 + 1766: 45a5 li a1,9 + 1768: 4829 li a6,10 + 176a: bf01 j 167a + +0000176c : + 176c: bbbfe2ef jal t0,326 <__riscv_save_12> + 1770: 1141 addi sp,sp,-16 + 1772: 842a mv s0,a0 + 1774: f65fe0ef jal ra,6d8 + 1778: 4038 lw a4,64(s0) + 177a: 57fd li a5,-1 + 177c: 14f70763 beq a4,a5,18ca + 1780: 4481 li s1,0 + 1782: 800009b7 lui s3,0x80000 + 1786: 503c lw a5,96(s0) + 1788: 02f4eb63 bltu s1,a5,17be + 178c: 4824 lw s1,80(s0) + 178e: 85a6 mv a1,s1 + 1790: 8522 mv a0,s0 + 1792: 9dfff0ef jal ra,1170 + 1796: 00448593 addi a1,s1,4 + 179a: 8522 mv a0,s0 + 179c: 8d4ff0ef jal ra,870 + 17a0: 84aa mv s1,a0 + 17a2: f575 bnez a0,178e + 17a4: 402c lw a1,64(s0) + 17a6: c581 beqz a1,17ae + 17a8: 8522 mv a0,s0 + 17aa: 9c7ff0ef jal ra,1170 + 17ae: 80000ab7 lui s5,0x80000 + 17b2: 4481 li s1,0 + 17b4: fffaca93 not s5,s5 + 17b8: 4b05 li s6,1 + 17ba: 4b89 li s7,2 + 17bc: a221 j 18c4 + 17be: 85a6 mv a1,s1 + 17c0: 8522 mv a0,s0 + 17c2: 8aeff0ef jal ra,870 + 17c6: 892a mv s2,a0 + 17c8: 4c28 lw a0,88(s0) + 17ca: 013967b3 or a5,s2,s3 + 17ce: 4611 li a2,4 + 17d0: 002c addi a1,sp,8 + 17d2: 9526 add a0,a0,s1 + 17d4: c43e sw a5,8(sp) + 17d6: 751040ef jal ra,6726 + 17da: 854a mv a0,s2 + 17dc: 852ff0ef jal ra,82e + 17e0: 94aa add s1,s1,a0 + 17e2: b755 j 1786 + 17e4: 85a6 mv a1,s1 + 17e6: 8522 mv a0,s0 + 17e8: 888ff0ef jal ra,870 + 17ec: 89aa mv s3,a0 + 17ee: 01557533 and a0,a0,s5 + 17f2: 83cff0ef jal ra,82e + 17f6: 892a mv s2,a0 + 17f8: 0c09d563 bgez s3,18c2 + 17fc: 4a01 li s4,0 + 17fe: 7ff00c37 lui s8,0x7ff00 + 1802: 4c9d li s9,7 + 1804: a095 j 1868 + 1806: 85d2 mv a1,s4 + 1808: 8522 mv a0,s0 + 180a: 866ff0ef jal ra,870 + 180e: 89aa mv s3,a0 + 1810: 01557533 and a0,a0,s5 + 1814: 81aff0ef jal ra,82e + 1818: 8d2a mv s10,a0 + 181a: 0409c663 bltz s3,1866 + 181e: 0029f793 andi a5,s3,2 + 1822: e3b1 bnez a5,1866 + 1824: 0134fb63 bgeu s1,s3,183a + 1828: 4c28 lw a0,88(s0) + 182a: 412987b3 sub a5,s3,s2 + 182e: 4611 li a2,4 + 1830: 002c addi a1,sp,8 + 1832: 9552 add a0,a0,s4 + 1834: c43e sw a5,8(sp) + 1836: 6f1040ef jal ra,6726 + 183a: 0039f993 andi s3,s3,3 + 183e: 08099963 bnez s3,18d0 + 1842: 004a0993 addi s3,s4,4 + 1846: 85ce mv a1,s3 + 1848: 8522 mv a0,s0 + 184a: 826ff0ef jal ra,870 + 184e: 00a4fc63 bgeu s1,a0,1866 + 1852: 4c3c lw a5,88(s0) + 1854: 41250533 sub a0,a0,s2 + 1858: c42a sw a0,8(sp) + 185a: 4611 li a2,4 + 185c: 002c addi a1,sp,8 + 185e: 01378533 add a0,a5,s3 + 1862: 6c5040ef jal ra,6726 + 1866: 9a6a add s4,s4,s10 + 1868: 5030 lw a2,96(s0) + 186a: f8ca6ee3 bltu s4,a2,1806 + 186e: 483c lw a5,80(s0) + 1870: 00f4f863 bgeu s1,a5,1880 + 1874: 412787b3 sub a5,a5,s2 + 1878: c83c sw a5,80(s0) + 187a: 7ff007b7 lui a5,0x7ff00 + 187e: c87c sw a5,84(s0) + 1880: 403c lw a5,64(s0) + 1882: 0097e563 bltu a5,s1,188c + 1886: 412787b3 sub a5,a5,s2 + 188a: c03c sw a5,64(s0) + 188c: 441c lw a5,8(s0) + 188e: 4c28 lw a0,88(s0) + 1890: 00f57c63 bgeu a0,a5,18a8 + 1894: 4c74 lw a3,92(s0) + 1896: 40a78733 sub a4,a5,a0 + 189a: 00d77763 bgeu a4,a3,18a8 + 189e: 00e4f563 bgeu s1,a4,18a8 + 18a2: 412787b3 sub a5,a5,s2 + 18a6: c41c sw a5,8(s0) + 18a8: 012485b3 add a1,s1,s2 + 18ac: 8e0d sub a2,a2,a1 + 18ae: 95aa add a1,a1,a0 + 18b0: 9526 add a0,a0,s1 + 18b2: 72b040ef jal ra,67dc + 18b6: 503c lw a5,96(s0) + 18b8: 41278933 sub s2,a5,s2 + 18bc: 07242023 sw s2,96(s0) + 18c0: 4901 li s2,0 + 18c2: 94ca add s1,s1,s2 + 18c4: 503c lw a5,96(s0) + 18c6: f0f4efe3 bltu s1,a5,17e4 + 18ca: 0141 addi sp,sp,16 + 18cc: a97fe06f j 362 <__riscv_restore_12> + 18d0: f9699be3 bne s3,s6,1866 + 18d4: 004a0993 addi s3,s4,4 + 18d8: 85ce mv a1,s3 + 18da: 8522 mv a0,s0 + 18dc: f95fe0ef jal ra,870 + 18e0: 00a4fc63 bgeu s1,a0,18f8 + 18e4: 4c3c lw a5,88(s0) + 18e6: 41250533 sub a0,a0,s2 + 18ea: c42a sw a0,8(sp) + 18ec: 4611 li a2,4 + 18ee: 002c addi a1,sp,8 + 18f0: 01378533 add a0,a5,s3 + 18f4: 633040ef jal ra,6726 + 18f8: 4c3c lw a5,88(s0) + 18fa: 008a0d93 addi s11,s4,8 + 18fe: 4621 li a2,8 + 1900: 9dbe add s11,s11,a5 + 1902: 85ee mv a1,s11 + 1904: 0028 addi a0,sp,8 + 1906: 621040ef jal ra,6726 + 190a: 49a2 lw s3,8(sp) + 190c: 45b2 lw a1,12(sp) + 190e: 854e mv a0,s3 + 1910: da5fe0ef jal ra,6b4 + 1914: 00abf463 bgeu s7,a0,191c + 1918: f59517e3 bne a0,s9,1866 + 191c: f534f5e3 bgeu s1,s3,1866 + 1920: 0542 slli a0,a0,0x10 + 1922: 00ac6533 or a0,s8,a0 + 1926: 412989b3 sub s3,s3,s2 + 192a: c62a sw a0,12(sp) + 192c: c44e sw s3,8(sp) + 192e: 4621 li a2,8 + 1930: 002c addi a1,sp,8 + 1932: 856e mv a0,s11 + 1934: b73d j 1862 + +00001936 : + 1936: a21fe2ef jal t0,356 <__riscv_save_0> + 193a: 07700793 li a5,119 + 193e: 1141 addi sp,sp,-16 + 1940: 4401 li s0,0 + 1942: 02b7fd63 bgeu a5,a1,197c + 1946: 862e mv a2,a1 + 1948: 84ae mv s1,a1 + 194a: 4581 li a1,0 + 194c: 842a mv s0,a0 + 194e: a39fe0ef jal ra,386 + 1952: 07040793 addi a5,s0,112 + 1956: f9048493 addi s1,s1,-112 + 195a: cc3c sw a5,88(s0) + 195c: cc64 sw s1,92(s0) + 195e: 4691 li a3,4 + 1960: 0070 addi a2,sp,12 + 1962: 4581 li a1,0 + 1964: 8522 mv a0,s0 + 1966: c602 sw zero,12(sp) + 1968: b19ff0ef jal ra,1480 + 196c: 4c7c lw a5,92(s0) + 196e: c828 sw a0,80(s0) + 1970: c86c sw a1,84(s0) + 1972: 9be1 andi a5,a5,-8 + 1974: cc7c sw a5,92(s0) + 1976: c05c sw a5,4(s0) + 1978: 8385 srli a5,a5,0x1 + 197a: d07c sw a5,100(s0) + 197c: 8522 mv a0,s0 + 197e: 0141 addi sp,sp,16 + 1980: 9fbfe06f j 37a <__riscv_restore_0> + +00001984 : + 1984: 4501 li a0,0 + 1986: 7ff305b7 lui a1,0x7ff30 + 198a: 8082 ret + +0000198c : + 198c: 7ff905b7 lui a1,0x7ff90 + 1990: 8082 ret + +00001992 : + 1992: 4501 li a0,0 + 1994: 7ff005b7 lui a1,0x7ff00 + 1998: 8082 ret + +0000199a : + 199a: 9a3fe2ef jal t0,33c <__riscv_save_4> + 199e: 842a mv s0,a0 + 19a0: 892e mv s2,a1 + 19a2: 852e mv a0,a1 + 19a4: 85b2 mv a1,a2 + 19a6: 89b2 mv s3,a2 + 19a8: 84b6 mv s1,a3 + 19aa: 8a3a mv s4,a4 + 19ac: 8abe mv s5,a5 + 19ae: d07fe0ef jal ra,6b4 + 19b2: e10d bnez a0,19d4 + 19b4: 8526 mv a0,s1 + 19b6: 2ae060ef jal ra,7c64 + 19ba: 862a mv a2,a0 + 19bc: 85a6 mv a1,s1 + 19be: 8522 mv a0,s0 + 19c0: 3ef5 jal 15bc + 19c2: 86aa mv a3,a0 + 19c4: 872e mv a4,a1 + 19c6: 87d2 mv a5,s4 + 19c8: 8856 mv a6,s5 + 19ca: 85ca mv a1,s2 + 19cc: 864e mv a2,s3 + 19ce: 8522 mv a0,s0 + 19d0: b29ff0ef jal ra,14f8 + 19d4: 99dfe06f j 370 <__riscv_restore_4> + +000019d8 : + 19d8: 965fe2ef jal t0,33c <__riscv_save_4> + 19dc: 1101 addi sp,sp,-32 + 19de: 4701 li a4,0 + 19e0: 7ff307b7 lui a5,0x7ff30 + 19e4: cc3a sw a4,24(sp) + 19e6: ce3e sw a5,28(sp) + 19e8: fff60713 addi a4,a2,-1 + 19ec: 57f5 li a5,-3 + 19ee: 842a mv s0,a0 + 19f0: 00e7f863 bgeu a5,a4,1a00 + 19f4: 852e mv a0,a1 + 19f6: c62e sw a1,12(sp) + 19f8: 26c060ef jal ra,7c64 + 19fc: 45b2 lw a1,12(sp) + 19fe: 862a mv a2,a0 + 1a00: 4785 li a5,1 + 1a02: 02f40723 sb a5,46(s0) + 1a06: 083c addi a5,sp,24 + 1a08: 020406a3 sb zero,45(s0) + 1a0c: c40c sw a1,8(s0) + 1a0e: d810 sw a2,48(s0) + 1a10: 02042a23 sw zero,52(s0) + 1a14: d47c sw a5,108(s0) + 1a16: 4485 li s1,1 + 1a18: 8522 mv a0,s0 + 1a1a: f40ff0ef jal ra,115a + 1a1e: 4962 lw s2,24(sp) + 1a20: 49f2 lw s3,28(sp) + 1a22: 00950763 beq a0,s1,1a30 + 1a26: 854a mv a0,s2 + 1a28: 85ce mv a1,s3 + 1a2a: ca1fe0ef jal ra,6ca + 1a2e: c511 beqz a0,1a3a + 1a30: 854a mv a0,s2 + 1a32: 85ce mv a1,s3 + 1a34: 6105 addi sp,sp,32 + 1a36: 93bfe06f j 370 <__riscv_restore_4> + 1a3a: 8522 mv a0,s0 + 1a3c: 399000ef jal ra,25d4 + 1a40: cc2a sw a0,24(sp) + 1a42: ce2e sw a1,28(sp) + 1a44: bfd1 j 1a18 + +00001a46 : + 1a46: 911fe2ef jal t0,356 <__riscv_save_0> + 1a4a: 567d li a2,-1 + 1a4c: 3771 jal 19d8 + 1a4e: 92dfe06f j 37a <__riscv_restore_0> + +00001a52 : + 1a52: 8d5fe2ef jal t0,326 <__riscv_save_12> + 1a56: 8cbe mv s9,a5 + 1a58: 02f54783 lbu a5,47(a0) + 1a5c: 711d addi sp,sp,-96 + 1a5e: 8b85 andi a5,a5,1 + 1a60: 78079d63 bnez a5,21fa + 1a64: 8ab2 mv s5,a2 + 1a66: 89ae mv s3,a1 + 1a68: 85b2 mv a1,a2 + 1a6a: 8636 mv a2,a3 + 1a6c: 8c3a mv s8,a4 + 1a6e: 8d2a mv s10,a0 + 1a70: 8b36 mv s6,a3 + 1a72: f0dfe0ef jal ra,97e + 1a76: 842a mv s0,a0 + 1a78: 84ae mv s1,a1 + 1a7a: 8666 mv a2,s9 + 1a7c: 85e2 mv a1,s8 + 1a7e: 856a mv a0,s10 + 1a80: efffe0ef jal ra,97e + 1a84: 892a mv s2,a0 + 1a86: 856a mv a0,s10 + 1a88: 8a2e mv s4,a1 + 1a8a: c4ffe0ef jal ra,6d8 + 1a8e: 8522 mv a0,s0 + 1a90: 85a6 mv a1,s1 + 1a92: c39fe0ef jal ra,6ca + 1a96: ed2d bnez a0,1b10 + 1a98: 854a mv a0,s2 + 1a9a: 85d2 mv a1,s4 + 1a9c: c2ffe0ef jal ra,6ca + 1aa0: 76051163 bnez a0,2202 + 1aa4: 07d98793 addi a5,s3,125 # 8000007d <_eusrstack+0x5fff007d> + 1aa8: 0ff7f793 andi a5,a5,255 + 1aac: 472d li a4,11 + 1aae: 76f76363 bltu a4,a5,2214 + 1ab2: 8556 mv a0,s5 + 1ab4: 85da mv a1,s6 + 1ab6: bfffe0ef jal ra,6b4 + 1aba: 4785 li a5,1 + 1abc: 76f50a63 beq a0,a5,2230 + 1ac0: 0000c5b7 lui a1,0xc + 1ac4: 20058593 addi a1,a1,512 # c200 <_exit+0x1f0> + 1ac8: 856a mv a0,s10 + 1aca: 953ff0ef jal ra,141c + 1ace: a83d j 1b0c + 1ad0: 85d2 mv a1,s4 + 1ad2: 854a mv a0,s2 + 1ad4: be1fe0ef jal ra,6b4 + 1ad8: 65b1 lui a1,0xc + 1ada: 842a mv s0,a0 + 1adc: 03000613 li a2,48 + 1ae0: 01458593 addi a1,a1,20 # c014 <_exit+0x4> + 1ae4: 1808 addi a0,sp,48 + 1ae6: 441040ef jal ra,6726 + 1aea: 47ad li a5,11 + 1aec: 0287e763 bltu a5,s0,1b1a + 1af0: 040a slli s0,s0,0x2 + 1af2: 109c addi a5,sp,96 + 1af4: 943e add s0,s0,a5 + 1af6: fd042583 lw a1,-48(s0) + 1afa: 852e mv a0,a1 + 1afc: c02e sw a1,0(sp) + 1afe: 166060ef jal ra,7c64 + 1b02: 4582 lw a1,0(sp) + 1b04: 862a mv a2,a0 + 1b06: 856a mv a0,s10 + 1b08: ab5ff0ef jal ra,15bc + 1b0c: 842a mv s0,a0 + 1b0e: 84ae mv s1,a1 + 1b10: 8522 mv a0,s0 + 1b12: 85a6 mv a1,s1 + 1b14: 6125 addi sp,sp,96 + 1b16: 84dfe06f j 362 <__riscv_restore_12> + 1b1a: 0000c5b7 lui a1,0xc + 1b1e: 1fc58593 addi a1,a1,508 # c1fc <_exit+0x1ec> + 1b22: bfe1 j 1afa + 1b24: 854a mv a0,s2 + 1b26: 85d2 mv a1,s4 + 1b28: b8dfe0ef jal ra,6b4 + 1b2c: 47a1 li a5,8 + 1b2e: 00f50763 beq a0,a5,1b3c + 1b32: 0000c5b7 lui a1,0xc + 1b36: 20858593 addi a1,a1,520 # c208 <_exit+0x1f8> + 1b3a: b779 j 1ac8 + 1b3c: 8522 mv a0,s0 + 1b3e: 85a6 mv a1,s1 + 1b40: b75fe0ef jal ra,6b4 + 1b44: ff950793 addi a5,a0,-7 + 1b48: 0fd7f793 andi a5,a5,253 + 1b4c: 8aaa mv s5,a0 + 1b4e: c791 beqz a5,1b5a + 1b50: 0000c5b7 lui a1,0xc + 1b54: 21458593 addi a1,a1,532 # c214 <_exit+0x204> + 1b58: bf85 j 1ac8 + 1b5a: 010005b7 lui a1,0x1000 + 1b5e: 008d2983 lw s3,8(s10) + 1b62: 15fd addi a1,a1,-1 + 1b64: 00b97533 and a0,s2,a1 + 1b68: 0a22 slli s4,s4,0x8 + 1b6a: 01895913 srli s2,s2,0x18 + 1b6e: 034d2783 lw a5,52(s10) + 1b72: 012a6933 or s2,s4,s2 + 1b76: 00b975b3 and a1,s2,a1 + 1b7a: 954e add a0,a0,s3 + 1b7c: 030d2b83 lw s7,48(s10) + 1b80: 00ad2423 sw a0,8(s10) + 1b84: 02bd2823 sw a1,48(s10) + 1b88: 4601 li a2,0 + 1b8a: c03e sw a5,0(sp) + 1b8c: bb5fe0ef jal ra,740 + 1b90: 02dd4783 lbu a5,45(s10) + 1b94: 02ad2a23 sw a0,52(s10) + 1b98: 4901 li s2,0 + 1b9a: c23e sw a5,4(sp) + 1b9c: 02fd4783 lbu a5,47(s10) + 1ba0: c43e sw a5,8(sp) + 1ba2: 040d2783 lw a5,64(s10) + 1ba6: c63e sw a5,12(sp) + 1ba8: 479d li a5,7 + 1baa: 04fa8b63 beq s5,a5,1c00 + 1bae: 449d li s1,7 + 1bb0: 08f00a13 li s4,143 + 1bb4: 4a85 li s5,1 + 1bb6: 034d2703 lw a4,52(s10) + 1bba: 030d2783 lw a5,48(s10) + 1bbe: 1ef76863 bltu a4,a5,1dae + 1bc2: 058d2583 lw a1,88(s10) + 1bc6: 05cd2783 lw a5,92(s10) + 1bca: 40195613 srai a2,s2,0x1 + 1bce: 00391a13 slli s4,s2,0x3 + 1bd2: 95be add a1,a1,a5 + 1bd4: 060e slli a2,a2,0x3 + 1bd6: 86ae mv a3,a1 + 1bd8: 01458533 add a0,a1,s4 + 1bdc: 962e add a2,a2,a1 + 1bde: 1561 addi a0,a0,-8 + 1be0: 22d61a63 bne a2,a3,1e14 + 1be4: 864a mv a2,s2 + 1be6: 856a mv a0,s10 + 1be8: 9402 jalr s0 + 1bea: 842a mv s0,a0 + 1bec: 856a mv a0,s10 + 1bee: 84ae mv s1,a1 + 1bf0: ae9fe0ef jal ra,6d8 + 1bf4: 05cd2783 lw a5,92(s10) + 1bf8: 97d2 add a5,a5,s4 + 1bfa: 04fd2e23 sw a5,92(s10) + 1bfe: aaa5 j 1d76 + 1c00: 85a2 mv a1,s0 + 1c02: 8626 mv a2,s1 + 1c04: 1074 addi a3,sp,44 + 1c06: 856a mv a0,s10 + 1c08: ca7fe0ef jal ra,8ae + 1c0c: 058d2483 lw s1,88(s10) + 1c10: ffc50793 addi a5,a0,-4 + 1c14: 04fd2023 sw a5,64(s10) + 1c18: 94aa add s1,s1,a0 + 1c1a: 856a mv a0,s10 + 1c1c: 5432 lw s0,44(sp) + 1c1e: 4b05 li s6,1 + 1c20: 925ff0ef jal ra,1544 + 1c24: 02900a13 li s4,41 + 1c28: 4c09 li s8,2 + 1c2a: 4c85 li s9,1 + 1c2c: 7ff30db7 lui s11,0x7ff30 + 1c30: 02c00a93 li s5,44 + 1c34: 0e8b7863 bgeu s6,s0,1d24 + 1c38: 865a mv a2,s6 + 1c3a: 85a2 mv a1,s0 + 1c3c: 8526 mv a0,s1 + 1c3e: b03fe0ef jal ra,740 + 1c42: 8b2a mv s6,a0 + 1c44: 00a48933 add s2,s1,a0 + 1c48: 00857663 bgeu a0,s0,1c54 + 1c4c: 00090783 lb a5,0(s2) + 1c50: 15478763 beq a5,s4,1d9e + 1c54: 1810 addi a2,sp,48 + 1c56: 416405b3 sub a1,s0,s6 + 1c5a: 854a mv a0,s2 + 1c5c: d802 sw zero,48(sp) + 1c5e: d57fe0ef jal ra,9b4 + 1c62: 0b851f63 bne a0,s8,1d20 + 1c66: 008d2783 lw a5,8(s10) + 1c6a: 034d2603 lw a2,52(s10) + 1c6e: 030d2583 lw a1,48(s10) + 1c72: 853e mv a0,a5 + 1c74: c83e sw a5,16(sp) + 1c76: acbfe0ef jal ra,740 + 1c7a: 47c2 lw a5,16(sp) + 1c7c: 02ad2a23 sw a0,52(s10) + 1c80: 039d0723 sb s9,46(s10) + 1c84: 97aa add a5,a5,a0 + 1c86: 00078703 lb a4,0(a5) # 7ff30000 <_eusrstack+0x5ff20000> + 1c8a: 886e mv a6,s11 + 1c8c: 4781 li a5,0 + 1c8e: 01470763 beq a4,s4,1c9c + 1c92: 856a mv a0,s10 + 1c94: 7ae000ef jal ra,2442 + 1c98: 87aa mv a5,a0 + 1c9a: 882e mv a6,a1 + 1c9c: 050d2303 lw t1,80(s10) + 1ca0: 054d2383 lw t2,84(s10) + 1ca4: 5642 lw a2,48(sp) + 1ca6: 85ca mv a1,s2 + 1ca8: 856a mv a0,s10 + 1caa: ce42 sw a6,28(sp) + 1cac: cc3e sw a5,24(sp) + 1cae: c81a sw t1,16(sp) + 1cb0: ca1e sw t2,20(sp) + 1cb2: 90bff0ef jal ra,15bc + 1cb6: 4342 lw t1,16(sp) + 1cb8: 43d2 lw t2,20(sp) + 1cba: 47e2 lw a5,24(sp) + 1cbc: 4872 lw a6,28(sp) + 1cbe: 86aa mv a3,a0 + 1cc0: 872e mv a4,a1 + 1cc2: 861e mv a2,t2 + 1cc4: 859a mv a1,t1 + 1cc6: 856a mv a0,s10 + 1cc8: 831ff0ef jal ra,14f8 + 1ccc: 030d2783 lw a5,48(s10) + 1cd0: 008d2903 lw s2,8(s10) + 1cd4: 034d2603 lw a2,52(s10) + 1cd8: 85be mv a1,a5 + 1cda: 854a mv a0,s2 + 1cdc: c83e sw a5,16(sp) + 1cde: a63fe0ef jal ra,740 + 1ce2: 47c2 lw a5,16(sp) + 1ce4: 02ad2a23 sw a0,52(s10) + 1ce8: 00f57a63 bgeu a0,a5,1cfc + 1cec: 992a add s2,s2,a0 + 1cee: 00090783 lb a5,0(s2) + 1cf2: 01579563 bne a5,s5,1cfc + 1cf6: 0505 addi a0,a0,1 + 1cf8: 02ad2a23 sw a0,52(s10) + 1cfc: 5642 lw a2,48(sp) + 1cfe: 85a2 mv a1,s0 + 1d00: 8526 mv a0,s1 + 1d02: 965a add a2,a2,s6 + 1d04: a3dfe0ef jal ra,740 + 1d08: 8b2a mv s6,a0 + 1d0a: f28575e3 bgeu a0,s0,1c34 + 1d0e: 00a487b3 add a5,s1,a0 + 1d12: 00078783 lb a5,0(a5) + 1d16: f1579fe3 bne a5,s5,1c34 + 1d1a: 00150b13 addi s6,a0,1 + 1d1e: bf19 j 1c34 + 1d20: 068b6f63 bltu s6,s0,1d9e + 1d24: 865a mv a2,s6 + 1d26: 85a2 mv a1,s0 + 1d28: 8526 mv a0,s1 + 1d2a: a17fe0ef jal ra,740 + 1d2e: 00857b63 bgeu a0,s0,1d44 + 1d32: 00a487b3 add a5,s1,a0 + 1d36: 00078703 lb a4,0(a5) + 1d3a: 07b00793 li a5,123 + 1d3e: 00f71363 bne a4,a5,1d44 + 1d42: 0505 addi a0,a0,1 + 1d44: 4791 li a5,4 + 1d46: fff40613 addi a2,s0,-1 + 1d4a: 00a485b3 add a1,s1,a0 + 1d4e: 8e09 sub a2,a2,a0 + 1d50: 02fd07a3 sb a5,47(s10) + 1d54: 856a mv a0,s10 + 1d56: 3149 jal 19d8 + 1d58: 842a mv s0,a0 + 1d5a: 84ae mv s1,a1 + 1d5c: 96ffe0ef jal ra,6ca + 1d60: e901 bnez a0,1d70 + 1d62: 02fd4783 lbu a5,47(s10) + 1d66: 8bc1 andi a5,a5,16 + 1d68: e781 bnez a5,1d70 + 1d6a: 4401 li s0,0 + 1d6c: 7ff304b7 lui s1,0x7ff30 + 1d70: 856a mv a0,s10 + 1d72: b59fe0ef jal ra,8ca + 1d76: 4782 lw a5,0(sp) + 1d78: 013d2423 sw s3,8(s10) + 1d7c: 037d2823 sw s7,48(s10) + 1d80: 02fd2a23 sw a5,52(s10) + 1d84: 47a2 lw a5,8(sp) + 1d86: 02fd07a3 sb a5,47(s10) + 1d8a: 4792 lw a5,4(sp) + 1d8c: 02fd06a3 sb a5,45(s10) + 1d90: 47b2 lw a5,12(sp) + 1d92: 04fd2023 sw a5,64(s10) + 1d96: 4785 li a5,1 + 1d98: 02fd0723 sb a5,46(s10) + 1d9c: bb95 j 1b10 + 1d9e: 00090703 lb a4,0(s2) + 1da2: 02900793 li a5,41 + 1da6: f6f71fe3 bne a4,a5,1d24 + 1daa: 0b05 addi s6,s6,1 + 1dac: bfa5 j 1d24 + 1dae: 856a mv a0,s10 + 1db0: baaff0ef jal ra,115a + 1db4: e09507e3 beq a0,s1,1bc2 + 1db8: 856a mv a0,s10 + 1dba: 688000ef jal ra,2442 + 1dbe: 862e mv a2,a1 + 1dc0: 85aa mv a1,a0 + 1dc2: 856a mv a0,s10 + 1dc4: bbbfe0ef jal ra,97e + 1dc8: 060d2703 lw a4,96(s10) + 1dcc: 05cd2783 lw a5,92(s10) + 1dd0: d82a sw a0,48(sp) + 1dd2: da2e sw a1,52(sp) + 1dd4: 0721 addi a4,a4,8 + 1dd6: 00e7fc63 bgeu a5,a4,1dee + 1dda: 0000c5b7 lui a1,0xc + 1dde: 22c58593 addi a1,a1,556 # c22c <_exit+0x21c> + 1de2: 856a mv a0,s10 + 1de4: e38ff0ef jal ra,141c + 1de8: 842a mv s0,a0 + 1dea: 84ae mv s1,a1 + 1dec: b769 j 1d76 + 1dee: 058d2503 lw a0,88(s10) + 1df2: 17e1 addi a5,a5,-8 + 1df4: 04fd2e23 sw a5,92(s10) + 1df8: 4621 li a2,8 + 1dfa: 180c addi a1,sp,48 + 1dfc: 953e add a0,a0,a5 + 1dfe: 129040ef jal ra,6726 + 1e02: 856a mv a0,s10 + 1e04: 0905 addi s2,s2,1 + 1e06: b54ff0ef jal ra,115a + 1e0a: db4516e3 bne a0,s4,1bb6 + 1e0e: 035d0723 sb s5,46(s10) + 1e12: b355 j 1bb6 + 1e14: 4118 lw a4,0(a0) + 1e16: 415c lw a5,4(a0) + 1e18: 0006a303 lw t1,0(a3) + 1e1c: 0046a383 lw t2,4(a3) + 1e20: c298 sw a4,0(a3) + 1e22: c2dc sw a5,4(a3) + 1e24: 00652023 sw t1,0(a0) + 1e28: 00752223 sw t2,4(a0) + 1e2c: 06a1 addi a3,a3,8 + 1e2e: bb45 j 1bde + 1e30: 4701 li a4,0 + 1e32: 3ff007b7 lui a5,0x3ff00 + 1e36: 8656 mv a2,s5 + 1e38: 86da mv a3,s6 + 1e3a: 08400593 li a1,132 + 1e3e: 856a mv a0,s10 + 1e40: 576010ef jal ra,33b6 + 1e44: b1f1 j 1b10 + 1e46: 4701 li a4,0 + 1e48: 3ff007b7 lui a5,0x3ff00 + 1e4c: 8656 mv a2,s5 + 1e4e: 86da mv a3,s6 + 1e50: 08500593 li a1,133 + 1e54: b7ed j 1e3e + 1e56: 854a mv a0,s2 + 1e58: 85d2 mv a1,s4 + 1e5a: 85bfe0ef jal ra,6b4 + 1e5e: 4799 li a5,6 + 1e60: 02f51063 bne a0,a5,1e80 + 1e64: 00193413 seqz s0,s2 + 1e68: 7ff604b7 lui s1,0x7ff60 + 1e6c: b155 j 1b10 + 1e6e: 874a mv a4,s2 + 1e70: 87d2 mv a5,s4 + 1e72: 8656 mv a2,s5 + 1e74: 86da mv a3,s6 + 1e76: 85ce mv a1,s3 + 1e78: 856a mv a0,s10 + 1e7a: 53c010ef jal ra,33b6 + 1e7e: b179 j 1b0c + 1e80: 8522 mv a0,s0 + 1e82: 85a6 mv a1,s1 + 1e84: 831fe0ef jal ra,6b4 + 1e88: 4789 li a5,2 + 1e8a: 8aaa mv s5,a0 + 1e8c: 0cf51f63 bne a0,a5,1f6a + 1e90: 854a mv a0,s2 + 1e92: 85d2 mv a1,s4 + 1e94: 821fe0ef jal ra,6b4 + 1e98: 8b2a mv s6,a0 + 1e9a: 0d551863 bne a0,s5,1f6a + 1e9e: 1034 addi a3,sp,40 + 1ea0: 85a2 mv a1,s0 + 1ea2: 8626 mv a2,s1 + 1ea4: 856a mv a0,s10 + 1ea6: a09fe0ef jal ra,8ae + 1eaa: 8652 mv a2,s4 + 1eac: 8aaa mv s5,a0 + 1eae: 1074 addi a3,sp,44 + 1eb0: 85ca mv a1,s2 + 1eb2: 856a mv a0,s10 + 1eb4: 9fbfe0ef jal ra,8ae + 1eb8: 07100793 li a5,113 + 1ebc: 8a2a mv s4,a0 + 1ebe: 04f99963 bne s3,a5,1f10 + 1ec2: 5622 lw a2,40(sp) + 1ec4: 57b2 lw a5,44(sp) + 1ec6: 4581 li a1,0 + 1ec8: 856a mv a0,s10 + 1eca: 963e add a2,a2,a5 + 1ecc: ef0ff0ef jal ra,15bc + 1ed0: 842a mv s0,a0 + 1ed2: 84ae mv s1,a1 + 1ed4: fe0fe0ef jal ra,6b4 + 1ed8: c3651ce3 bne a0,s6,1b10 + 1edc: 1814 addi a3,sp,48 + 1ede: 85a2 mv a1,s0 + 1ee0: 8626 mv a2,s1 + 1ee2: 856a mv a0,s10 + 1ee4: 9cbfe0ef jal ra,8ae + 1ee8: 892a mv s2,a0 + 1eea: 058d2503 lw a0,88(s10) + 1eee: 5622 lw a2,40(sp) + 1ef0: 015505b3 add a1,a0,s5 + 1ef4: 954a add a0,a0,s2 + 1ef6: 0e7040ef jal ra,67dc + 1efa: 57a2 lw a5,40(sp) + 1efc: 058d2503 lw a0,88(s10) + 1f00: 5632 lw a2,44(sp) + 1f02: 993e add s2,s2,a5 + 1f04: 014505b3 add a1,a0,s4 + 1f08: 954a add a0,a0,s2 + 1f0a: 0d3040ef jal ra,67dc + 1f0e: b109 j 1b10 + 1f10: 07a00793 li a5,122 + 1f14: 02f99163 bne s3,a5,1f36 + 1f18: 5622 lw a2,40(sp) + 1f1a: 57b2 lw a5,44(sp) + 1f1c: 4401 li s0,0 + 1f1e: f4f615e3 bne a2,a5,1e68 + 1f22: 058d2503 lw a0,88(s10) + 1f26: 014505b3 add a1,a0,s4 + 1f2a: 9556 add a0,a0,s5 + 1f2c: 7d4040ef jal ra,6700 + 1f30: 00153413 seqz s0,a0 + 1f34: bf15 j 1e68 + 1f36: 07b00793 li a5,123 + 1f3a: 02f99363 bne s3,a5,1f60 + 1f3e: 5622 lw a2,40(sp) + 1f40: 57b2 lw a5,44(sp) + 1f42: 4501 li a0,0 + 1f44: 00f61b63 bne a2,a5,1f5a + 1f48: 058d2503 lw a0,88(s10) + 1f4c: 014505b3 add a1,a0,s4 + 1f50: 9556 add a0,a0,s5 + 1f52: 7ae040ef jal ra,6700 + 1f56: 00153513 seqz a0,a0 + 1f5a: 00154413 xori s0,a0,1 + 1f5e: b729 j 1e68 + 1f60: 0000c5b7 lui a1,0xc + 1f64: 23858593 addi a1,a1,568 # c238 <_exit+0x228> + 1f68: b685 j 1ac8 + 1f6a: f9a98793 addi a5,s3,-102 + 1f6e: 0ff7f793 andi a5,a5,255 + 1f72: 4719 li a4,6 + 1f74: 00f76e63 bltu a4,a5,1f90 + 1f78: 854a mv a0,s2 + 1f7a: 85d2 mv a1,s4 + 1f7c: f38fe0ef jal ra,6b4 + 1f80: 4795 li a5,5 + 1f82: 02f50463 beq a0,a5,1faa + 1f86: 0000c5b7 lui a1,0xc + 1f8a: 24458593 addi a1,a1,580 # c244 <_exit+0x234> + 1f8e: be2d j 1ac8 + 1f90: 06400793 li a5,100 + 1f94: 00f98b63 beq s3,a5,1faa + 1f98: 4795 li a5,5 + 1f9a: fefa96e3 bne s5,a5,1f86 + 1f9e: 854a mv a0,s2 + 1fa0: 85d2 mv a1,s4 + 1fa2: f12fe0ef jal ra,6b4 + 1fa6: ff5510e3 bne a0,s5,1f86 + 1faa: f9c98793 addi a5,s3,-100 + 1fae: 0ff7f793 andi a5,a5,255 + 1fb2: 4769 li a4,26 + 1fb4: 8b22 mv s6,s0 + 1fb6: 8ba6 mv s7,s1 + 1fb8: 22f76763 bltu a4,a5,21e6 + 1fbc: 6731 lui a4,0xc + 1fbe: 078a slli a5,a5,0x2 + 1fc0: 17870713 addi a4,a4,376 # c178 <_exit+0x168> + 1fc4: 97ba add a5,a5,a4 + 1fc6: 439c lw a5,0(a5) + 1fc8: 8782 jr a5 + 1fca: 4601 li a2,0 + 1fcc: 4681 li a3,0 + 1fce: 854a mv a0,s2 + 1fd0: 85d2 mv a1,s4 + 1fd2: 75a030ef jal ra,572c <__eqdf2> + 1fd6: e511 bnez a0,1fe2 + 1fd8: 0000c5b7 lui a1,0xc + 1fdc: 25458593 addi a1,a1,596 # c254 <_exit+0x244> + 1fe0: b4e5 j 1ac8 + 1fe2: 864a mv a2,s2 + 1fe4: 86d2 mv a3,s4 + 1fe6: 8522 mv a0,s0 + 1fe8: 85a6 mv a1,s1 + 1fea: 18e030ef jal ra,5178 <__divdf3> + 1fee: be39 j 1b0c + 1ff0: 864a mv a2,s2 + 1ff2: 86d2 mv a3,s4 + 1ff4: 855a mv a0,s6 + 1ff6: 85de mv a1,s7 + 1ff8: 180030ef jal ra,5178 <__divdf3> + 1ffc: 4f0040ef jal ra,64ec <__fixdfsi> + 2000: 554040ef jal ra,6554 <__floatsidf> + 2004: 864a mv a2,s2 + 2006: 86d2 mv a3,s4 + 2008: 0f3030ef jal ra,58fa <__muldf3> + 200c: 862a mv a2,a0 + 200e: 86ae mv a3,a1 + 2010: 855a mv a0,s6 + 2012: 85de mv a1,s7 + 2014: 59f030ef jal ra,5db2 <__subdf3> + 2018: bcd5 j 1b0c + 201a: 864a mv a2,s2 + 201c: 86d2 mv a3,s4 + 201e: 8522 mv a0,s0 + 2020: 85a6 mv a1,s1 + 2022: 0d9030ef jal ra,58fa <__muldf3> + 2026: b4dd j 1b0c + 2028: 864a mv a2,s2 + 202a: 86d2 mv a3,s4 + 202c: 8522 mv a0,s0 + 202e: 85a6 mv a1,s1 + 2030: 219020ef jal ra,4a48 <__adddf3> + 2034: bce1 j 1b0c + 2036: 864a mv a2,s2 + 2038: 86d2 mv a3,s4 + 203a: bfd9 j 2010 + 203c: 8522 mv a0,s0 + 203e: 85a6 mv a1,s1 + 2040: 4ac040ef jal ra,64ec <__fixdfsi> + 2044: 842a mv s0,a0 + 2046: 85d2 mv a1,s4 + 2048: 854a mv a0,s2 + 204a: 4a2040ef jal ra,64ec <__fixdfsi> + 204e: 8d21 xor a0,a0,s0 + 2050: 504040ef jal ra,6554 <__floatsidf> + 2054: bc65 j 1b0c + 2056: 8522 mv a0,s0 + 2058: 85a6 mv a1,s1 + 205a: 492040ef jal ra,64ec <__fixdfsi> + 205e: 842a mv s0,a0 + 2060: 85d2 mv a1,s4 + 2062: 854a mv a0,s2 + 2064: 488040ef jal ra,64ec <__fixdfsi> + 2068: 8d61 and a0,a0,s0 + 206a: b7dd j 2050 + 206c: 8522 mv a0,s0 + 206e: 85a6 mv a1,s1 + 2070: 47c040ef jal ra,64ec <__fixdfsi> + 2074: 842a mv s0,a0 + 2076: 85d2 mv a1,s4 + 2078: 854a mv a0,s2 + 207a: 472040ef jal ra,64ec <__fixdfsi> + 207e: 8d41 or a0,a0,s0 + 2080: bfc1 j 2050 + 2082: 800005b7 lui a1,0x80000 + 2086: 844a mv s0,s2 + 2088: 0145c4b3 xor s1,a1,s4 + 208c: b451 j 1b10 + 208e: 854a mv a0,s2 + 2090: 85d2 mv a1,s4 + 2092: 45a040ef jal ra,64ec <__fixdfsi> + 2096: fff54513 not a0,a0 + 209a: bf5d j 2050 + 209c: 4601 li a2,0 + 209e: 4681 li a3,0 + 20a0: 854a mv a0,s2 + 20a2: 85d2 mv a1,s4 + 20a4: 688030ef jal ra,572c <__eqdf2> + 20a8: b561 j 1f30 + 20aa: 8522 mv a0,s0 + 20ac: 85a6 mv a1,s1 + 20ae: 43e040ef jal ra,64ec <__fixdfsi> + 20b2: 842a mv s0,a0 + 20b4: 85d2 mv a1,s4 + 20b6: 854a mv a0,s2 + 20b8: 434040ef jal ra,64ec <__fixdfsi> + 20bc: 00a41533 sll a0,s0,a0 + 20c0: bf41 j 2050 + 20c2: 8522 mv a0,s0 + 20c4: 85a6 mv a1,s1 + 20c6: 426040ef jal ra,64ec <__fixdfsi> + 20ca: 842a mv s0,a0 + 20cc: 85d2 mv a1,s4 + 20ce: 854a mv a0,s2 + 20d0: 41c040ef jal ra,64ec <__fixdfsi> + 20d4: 40a45533 sra a0,s0,a0 + 20d8: bfa5 j 2050 + 20da: 854a mv a0,s2 + 20dc: 85d2 mv a1,s4 + 20de: dd6fe0ef jal ra,6b4 + 20e2: 47a1 li a5,8 + 20e4: 00f50763 beq a0,a5,20f2 + 20e8: 0000c5b7 lui a1,0xc + 20ec: 26058593 addi a1,a1,608 # c260 <_exit+0x250> + 20f0: bae1 j 1ac8 + 20f2: 010007b7 lui a5,0x1000 + 20f6: 008d2503 lw a0,8(s10) + 20fa: 17fd addi a5,a5,-1 + 20fc: 00f97733 and a4,s2,a5 + 2100: 953a add a0,a0,a4 + 2102: 4709 li a4,2 + 2104: 02ea9963 bne s5,a4,2136 + 2108: 0a22 slli s4,s4,0x8 + 210a: 01895593 srli a1,s2,0x18 + 210e: 00ba65b3 or a1,s4,a1 + 2112: 0000c637 lui a2,0xc + 2116: 4699 li a3,6 + 2118: 27060613 addi a2,a2,624 # c270 <_exit+0x260> + 211c: 8dfd and a1,a1,a5 + 211e: ebafe0ef jal ra,7d8 + 2122: cd01 beqz a0,213a + 2124: 85a2 mv a1,s0 + 2126: 856a mv a0,s10 + 2128: f48fe0ef jal ra,870 + 212c: 8109 srli a0,a0,0x2 + 212e: 157d addi a0,a0,-1 + 2130: 494040ef jal ra,65c4 <__floatunsidf> + 2134: bae1 j 1b0c + 2136: 000a8763 beqz s5,2144 + 213a: 0000c5b7 lui a1,0xc + 213e: 27858593 addi a1,a1,632 # c278 <_exit+0x268> + 2142: b259 j 1ac8 + 2144: 0a22 slli s4,s4,0x8 + 2146: 01895713 srli a4,s2,0x18 + 214a: 00ea6733 or a4,s4,a4 + 214e: 86aa mv a3,a0 + 2150: 8f7d and a4,a4,a5 + 2152: 85a2 mv a1,s0 + 2154: 8626 mv a2,s1 + 2156: 856a mv a0,s10 + 2158: fdcfe0ef jal ra,934 + 215c: c55d beqz a0,220a + 215e: 842a mv s0,a0 + 2160: 7ff104b7 lui s1,0x7ff10 + 2164: b275 j 1b10 + 2166: 8522 mv a0,s0 + 2168: 85a6 mv a1,s1 + 216a: 382040ef jal ra,64ec <__fixdfsi> + 216e: 842a mv s0,a0 + 2170: 85d2 mv a1,s4 + 2172: 854a mv a0,s2 + 2174: 378040ef jal ra,64ec <__fixdfsi> + 2178: 8c09 sub s0,s0,a0 + 217a: 00143413 seqz s0,s0 + 217e: b1ed j 1e68 + 2180: 8522 mv a0,s0 + 2182: 85a6 mv a1,s1 + 2184: 368040ef jal ra,64ec <__fixdfsi> + 2188: 842a mv s0,a0 + 218a: 85d2 mv a1,s4 + 218c: 854a mv a0,s2 + 218e: 35e040ef jal ra,64ec <__fixdfsi> + 2192: 8c09 sub s0,s0,a0 + 2194: 00803433 snez s0,s0 + 2198: b9c1 j 1e68 + 219a: 8522 mv a0,s0 + 219c: 864a mv a2,s2 + 219e: 86d2 mv a3,s4 + 21a0: 85a6 mv a1,s1 + 21a2: 6a2030ef jal ra,5844 <__ledf2> + 21a6: 00052413 slti s0,a0,0 + 21aa: b97d j 1e68 + 21ac: 8522 mv a0,s0 + 21ae: 864a mv a2,s2 + 21b0: 86d2 mv a3,s4 + 21b2: 85a6 mv a1,s1 + 21b4: 690030ef jal ra,5844 <__ledf2> + 21b8: 00152413 slti s0,a0,1 + 21bc: b175 j 1e68 + 21be: 8522 mv a0,s0 + 21c0: 864a mv a2,s2 + 21c2: 86d2 mv a3,s4 + 21c4: 85a6 mv a1,s1 + 21c6: 5d0030ef jal ra,5796 <__gedf2> + 21ca: 00a02433 sgtz s0,a0 + 21ce: b969 j 1e68 + 21d0: 8522 mv a0,s0 + 21d2: 864a mv a2,s2 + 21d4: 86d2 mv a3,s4 + 21d6: 85a6 mv a1,s1 + 21d8: 5be030ef jal ra,5796 <__gedf2> + 21dc: fff54513 not a0,a0 + 21e0: 01f55413 srli s0,a0,0x1f + 21e4: b151 j 1e68 + 21e6: 0000c5b7 lui a1,0xc + 21ea: 864e mv a2,s3 + 21ec: 856a mv a0,s10 + 21ee: 28c58593 addi a1,a1,652 # c28c <_exit+0x27c> + 21f2: a2aff0ef jal ra,141c + 21f6: 917ff06f j 1b0c + 21fa: 4401 li s0,0 + 21fc: 4481 li s1,0 + 21fe: 913ff06f j 1b10 + 2202: 844a mv s0,s2 + 2204: 84d2 mv s1,s4 + 2206: 90bff06f j 1b10 + 220a: 4401 li s0,0 + 220c: 7ff304b7 lui s1,0x7ff30 + 2210: 901ff06f j 1b10 + 2214: f9b98793 addi a5,s3,-101 + 2218: 0ff7f793 andi a5,a5,255 + 221c: 4715 li a4,5 + 221e: c6f761e3 bltu a4,a5,1e80 + 2222: 6731 lui a4,0xc + 2224: 078a slli a5,a5,0x2 + 2226: 1e470713 addi a4,a4,484 # c1e4 <_exit+0x1d4> + 222a: 97ba add a5,a5,a4 + 222c: 439c lw a5,0(a5) + 222e: 8782 jr a5 + 2230: 08300793 li a5,131 + 2234: c2f99de3 bne s3,a5,1e6e + 2238: 058d2503 lw a0,88(s10) + 223c: ffcaf793 andi a5,s5,-4 + 2240: 07a1 addi a5,a5,8 + 2242: 4621 li a2,8 + 2244: 180c addi a1,sp,48 + 2246: 953e add a0,a0,a5 + 2248: d84a sw s2,48(sp) + 224a: da52 sw s4,52(sp) + 224c: 8456 mv s0,s5 + 224e: 4d8040ef jal ra,6726 + 2252: 84da mv s1,s6 + 2254: 8bdff06f j 1b10 + +00002258 : + 2258: 8e4fe2ef jal t0,33c <__riscv_save_4> + 225c: 1141 addi sp,sp,-16 + 225e: 842a mv s0,a0 + 2260: 0ee010ef jal ra,334e + 2264: 892a mv s2,a0 + 2266: 84ae mv s1,a1 + 2268: 07e00993 li s3,126 + 226c: 4a05 li s4,1 + 226e: 854a mv a0,s2 + 2270: 85a6 mv a1,s1 + 2272: c58fe0ef jal ra,6ca + 2276: e511 bnez a0,2282 + 2278: 8522 mv a0,s0 + 227a: ee1fe0ef jal ra,115a + 227e: 03350863 beq a0,s3,22ae + 2282: 854a mv a0,s2 + 2284: 85a6 mv a1,s1 + 2286: c44fe0ef jal ra,6ca + 228a: ed09 bnez a0,22a4 + 228c: 02f44983 lbu s3,47(s0) + 2290: 07f00a13 li s4,127 + 2294: 4a85 li s5,1 + 2296: 8522 mv a0,s0 + 2298: ec3fe0ef jal ra,115a + 229c: 05450363 beq a0,s4,22e2 + 22a0: 033407a3 sb s3,47(s0) + 22a4: 854a mv a0,s2 + 22a6: 85a6 mv a1,s1 + 22a8: 0141 addi sp,sp,16 + 22aa: 8c6fe06f j 370 <__riscv_restore_4> + 22ae: 03440723 sb s4,46(s0) + 22b2: 8522 mv a0,s0 + 22b4: 02d44a83 lbu s5,45(s0) + 22b8: 096010ef jal ra,334e + 22bc: c62a sw a0,12(sp) + 22be: c42e sw a1,8(sp) + 22c0: c0afe0ef jal ra,6ca + 22c4: 47a2 lw a5,8(sp) + 22c6: 4732 lw a4,12(sp) + 22c8: e911 bnez a0,22dc + 22ca: 864a mv a2,s2 + 22cc: 86a6 mv a3,s1 + 22ce: 85d6 mv a1,s5 + 22d0: 8522 mv a0,s0 + 22d2: f80ff0ef jal ra,1a52 + 22d6: 892a mv s2,a0 + 22d8: 84ae mv s1,a1 + 22da: bf51 j 226e + 22dc: 893a mv s2,a4 + 22de: 84be mv s1,a5 + 22e0: b74d j 2282 + 22e2: 8626 mv a2,s1 + 22e4: 85ca mv a1,s2 + 22e6: 03540723 sb s5,46(s0) + 22ea: 8522 mv a0,s0 + 22ec: e92fe0ef jal ra,97e + 22f0: 84ae mv s1,a1 + 22f2: 892a mv s2,a0 + 22f4: 85aa mv a1,a0 + 22f6: 8626 mv a2,s1 + 22f8: 8522 mv a0,s0 + 22fa: de6fe0ef jal ra,8e0 + 22fe: 02f44783 lbu a5,47(s0) + 2302: e901 bnez a0,2312 + 2304: 0017e793 ori a5,a5,1 + 2308: 02f407a3 sb a5,47(s0) + 230c: 8522 mv a0,s0 + 230e: 37a9 jal 2258 + 2310: b759 j 2296 + 2312: 8b85 andi a5,a5,1 + 2314: ffe5 bnez a5,230c + 2316: 8522 mv a0,s0 + 2318: 3781 jal 2258 + 231a: 892a mv s2,a0 + 231c: 84ae mv s1,a1 + 231e: bfa5 j 2296 + +00002320 : + 2320: 81cfe2ef jal t0,33c <__riscv_save_4> + 2324: 842a mv s0,a0 + 2326: 3f0d jal 2258 + 2328: 892a mv s2,a0 + 232a: 89ae mv s3,a1 + 232c: b9efe0ef jal ra,6ca + 2330: ed09 bnez a0,234a + 2332: 02f44483 lbu s1,47(s0) + 2336: 08000a13 li s4,128 + 233a: 4a85 li s5,1 + 233c: 8522 mv a0,s0 + 233e: e1dfe0ef jal ra,115a + 2342: 01450863 beq a0,s4,2352 + 2346: 029407a3 sb s1,47(s0) + 234a: 854a mv a0,s2 + 234c: 85ce mv a1,s3 + 234e: 822fe06f j 370 <__riscv_restore_4> + 2352: 864e mv a2,s3 + 2354: 85ca mv a1,s2 + 2356: 03540723 sb s5,46(s0) + 235a: 8522 mv a0,s0 + 235c: e22fe0ef jal ra,97e + 2360: 89ae mv s3,a1 + 2362: 892a mv s2,a0 + 2364: 85aa mv a1,a0 + 2366: 864e mv a2,s3 + 2368: 8522 mv a0,s0 + 236a: d76fe0ef jal ra,8e0 + 236e: 02f44783 lbu a5,47(s0) + 2372: c901 beqz a0,2382 + 2374: 0017e793 ori a5,a5,1 + 2378: 02f407a3 sb a5,47(s0) + 237c: 8522 mv a0,s0 + 237e: 374d jal 2320 + 2380: bf75 j 233c + 2382: 8b85 andi a5,a5,1 + 2384: ffe5 bnez a5,237c + 2386: 8522 mv a0,s0 + 2388: 3f61 jal 2320 + 238a: 892a mv s2,a0 + 238c: 89ae mv s3,a1 + 238e: b77d j 233c + +00002390 : + 2390: fadfd2ef jal t0,33c <__riscv_save_4> + 2394: 842a mv s0,a0 + 2396: 08200a93 li s5,130 + 239a: 4a05 li s4,1 + 239c: 08100b13 li s6,129 + 23a0: 8522 mv a0,s0 + 23a2: 3fbd jal 2320 + 23a4: 892a mv s2,a0 + 23a6: 8522 mv a0,s0 + 23a8: 89ae mv s3,a1 + 23aa: db1fe0ef jal ra,115a + 23ae: 07551463 bne a0,s5,2416 + 23b2: 864e mv a2,s3 + 23b4: 03440723 sb s4,46(s0) + 23b8: 85ca mv a1,s2 + 23ba: 8522 mv a0,s0 + 23bc: 02f44483 lbu s1,47(s0) + 23c0: dbefe0ef jal ra,97e + 23c4: 862e mv a2,a1 + 23c6: 85aa mv a1,a0 + 23c8: 8522 mv a0,s0 + 23ca: d16fe0ef jal ra,8e0 + 23ce: c921 beqz a0,241e + 23d0: 8522 mv a0,s0 + 23d2: 3f7d jal 2390 + 23d4: 02f44783 lbu a5,47(s0) + 23d8: 892a mv s2,a0 + 23da: 8522 mv a0,s0 + 23dc: 0017e793 ori a5,a5,1 + 23e0: 02f407a3 sb a5,47(s0) + 23e4: 89ae mv s3,a1 + 23e6: d75fe0ef jal ra,115a + 23ea: 08100793 li a5,129 + 23ee: 00f50e63 beq a0,a5,240a + 23f2: 0000c5b7 lui a1,0xc + 23f6: 029407a3 sb s1,47(s0) + 23fa: 29c58593 addi a1,a1,668 # c29c <_exit+0x28c> + 23fe: 8522 mv a0,s0 + 2400: 81cff0ef jal ra,141c + 2404: 892a mv s2,a0 + 2406: 89ae mv s3,a1 + 2408: a039 j 2416 + 240a: 03440723 sb s4,46(s0) + 240e: 8522 mv a0,s0 + 2410: 3741 jal 2390 + 2412: 029407a3 sb s1,47(s0) + 2416: 854a mv a0,s2 + 2418: 85ce mv a1,s3 + 241a: f57fd06f j 370 <__riscv_restore_4> + 241e: 02f44783 lbu a5,47(s0) + 2422: 8522 mv a0,s0 + 2424: 0017e793 ori a5,a5,1 + 2428: 02f407a3 sb a5,47(s0) + 242c: 3795 jal 2390 + 242e: 8522 mv a0,s0 + 2430: d2bfe0ef jal ra,115a + 2434: fb651fe3 bne a0,s6,23f2 + 2438: 03440723 sb s4,46(s0) + 243c: 029407a3 sb s1,47(s0) + 2440: b785 j 23a0 + +00002442 : + 2442: efbfd2ef jal t0,33c <__riscv_save_4> + 2446: 1141 addi sp,sp,-16 + 2448: 842a mv s0,a0 + 244a: 3799 jal 2390 + 244c: 892a mv s2,a0 + 244e: 84ae mv s1,a1 + 2450: 08300993 li s3,131 + 2454: 4a29 li s4,10 + 2456: 4a85 li s5,1 + 2458: 854a mv a0,s2 + 245a: 85a6 mv a1,s1 + 245c: a6efe0ef jal ra,6ca + 2460: e531 bnez a0,24ac + 2462: 8522 mv a0,s0 + 2464: cf7fe0ef jal ra,115a + 2468: 01350a63 beq a0,s3,247c + 246c: 02d44783 lbu a5,45(s0) + 2470: 07c78793 addi a5,a5,124 # 100007c <_data_lma+0xff35e4> + 2474: 0ff7f793 andi a5,a5,255 + 2478: 02fa6a63 bltu s4,a5,24ac + 247c: 03540723 sb s5,46(s0) + 2480: 8522 mv a0,s0 + 2482: 02d44b03 lbu s6,45(s0) + 2486: 3f75 jal 2442 + 2488: c62a sw a0,12(sp) + 248a: c42e sw a1,8(sp) + 248c: a3efe0ef jal ra,6ca + 2490: 47a2 lw a5,8(sp) + 2492: 4732 lw a4,12(sp) + 2494: e911 bnez a0,24a8 + 2496: 864a mv a2,s2 + 2498: 86a6 mv a3,s1 + 249a: 85da mv a1,s6 + 249c: 8522 mv a0,s0 + 249e: db4ff0ef jal ra,1a52 + 24a2: 892a mv s2,a0 + 24a4: 84ae mv s1,a1 + 24a6: bf4d j 2458 + 24a8: 893a mv s2,a4 + 24aa: 84be mv s1,a5 + 24ac: 854a mv a0,s2 + 24ae: 85a6 mv a1,s1 + 24b0: 0141 addi sp,sp,16 + 24b2: ebffd06f j 370 <__riscv_restore_4> + +000024b6 : + 24b6: e71fd2ef jal t0,326 <__riscv_save_12> + 24ba: 02f54483 lbu s1,47(a0) + 24be: 4785 li a5,1 + 24c0: 1141 addi sp,sp,-16 + 24c2: 8baa mv s7,a0 + 24c4: 8885 andi s1,s1,1 + 24c6: 02f50723 sb a5,46(a0) + 24ca: 4a05 li s4,1 + 24cc: 4c81 li s9,0 + 24ce: 7ff30d37 lui s10,0x7ff30 + 24d2: 4985 li s3,1 + 24d4: 08f00c13 li s8,143 + 24d8: 855e mv a0,s7 + 24da: c81fe0ef jal ra,115a + 24de: 4789 li a5,2 + 24e0: 00f50a63 beq a0,a5,24f4 + 24e4: 0000c5b7 lui a1,0xc + 24e8: 855e mv a0,s7 + 24ea: 29c58593 addi a1,a1,668 # c29c <_exit+0x28c> + 24ee: f2ffe0ef jal ra,141c + 24f2: a895 j 2566 + 24f4: 034b8723 sb s4,46(s7) + 24f8: 855e mv a0,s7 + 24fa: 038bad83 lw s11,56(s7) + 24fe: 03cba903 lw s2,60(s7) + 2502: 008ba403 lw s0,8(s7) + 2506: 871fe0ef jal ra,d76 + 250a: 08300793 li a5,131 + 250e: 8b66 mv s6,s9 + 2510: 8aea mv s5,s10 + 2512: 00f51b63 bne a0,a5,2528 + 2516: 034b8723 sb s4,46(s7) + 251a: 855e mv a0,s7 + 251c: 371d jal 2442 + 251e: 8b2a mv s6,a0 + 2520: 8aae mv s5,a1 + 2522: 9a8fe0ef jal ra,6ca + 2526: e131 bnez a0,256a + 2528: c899 beqz s1,253e + 252a: 855e mv a0,s7 + 252c: c2ffe0ef jal ra,115a + 2530: 4795 li a5,5 + 2532: 08f51463 bne a0,a5,25ba + 2536: 4b01 li s6,0 + 2538: 7ff30ab7 lui s5,0x7ff30 + 253c: a03d j 256a + 253e: 050ba583 lw a1,80(s7) + 2542: 054ba603 lw a2,84(s7) + 2546: 946e add s0,s0,s11 + 2548: 874a mv a4,s2 + 254a: 86a2 mv a3,s0 + 254c: 855e mv a0,s7 + 254e: be6fe0ef jal ra,934 + 2552: c10d beqz a0,2574 + 2554: 0000c5b7 lui a1,0xc + 2558: 86a2 mv a3,s0 + 255a: 864a mv a2,s2 + 255c: 2c858593 addi a1,a1,712 # c2c8 <_exit+0x2b8> + 2560: 855e mv a0,s7 + 2562: ebbfe0ef jal ra,141c + 2566: 8b2a mv s6,a0 + 2568: 8aae mv s5,a1 + 256a: 855a mv a0,s6 + 256c: 85d6 mv a1,s5 + 256e: 0141 addi sp,sp,16 + 2570: df3fd06f j 362 <__riscv_restore_12> + 2574: 050ba303 lw t1,80(s7) + 2578: 054ba383 lw t2,84(s7) + 257c: 864a mv a2,s2 + 257e: 85a2 mv a1,s0 + 2580: 855e mv a0,s7 + 2582: c41a sw t1,8(sp) + 2584: c61e sw t2,12(sp) + 2586: 836ff0ef jal ra,15bc + 258a: 8656 mv a2,s5 + 258c: c02a sw a0,0(sp) + 258e: c22e sw a1,4(sp) + 2590: 855e mv a0,s7 + 2592: 85da mv a1,s6 + 2594: beafe0ef jal ra,97e + 2598: 4322 lw t1,8(sp) + 259a: 43b2 lw t2,12(sp) + 259c: 4682 lw a3,0(sp) + 259e: 4712 lw a4,4(sp) + 25a0: 87aa mv a5,a0 + 25a2: 882e mv a6,a1 + 25a4: 861e mv a2,t2 + 25a6: 859a mv a1,t1 + 25a8: 855e mv a0,s7 + 25aa: f4ffe0ef jal ra,14f8 + 25ae: 8b2a mv s6,a0 + 25b0: 8aae mv s5,a1 + 25b2: 918fe0ef jal ra,6ca + 25b6: d935 beqz a0,252a + 25b8: bf4d j 256a + 25ba: 855e mv a0,s7 + 25bc: b9ffe0ef jal ra,115a + 25c0: f7350be3 beq a0,s3,2536 + 25c4: 855e mv a0,s7 + 25c6: b95fe0ef jal ra,115a + 25ca: f1851de3 bne a0,s8,24e4 + 25ce: 033b8723 sb s3,46(s7) + 25d2: b719 j 24d8 + +000025d4 : + 25d4: d53fd2ef jal t0,326 <__riscv_save_12> + 25d8: 5138 lw a4,96(a0) + 25da: 517c lw a5,100(a0) + 25dc: 1141 addi sp,sp,-16 + 25de: 842a mv s0,a0 + 25e0: 00e7f463 bgeu a5,a4,25e8 + 25e4: 988ff0ef jal ra,176c + 25e8: 8522 mv a0,s0 + 25ea: b71fe0ef jal ra,115a + 25ee: 03d00793 li a5,61 + 25f2: 20f50863 beq a0,a5,2802 + 25f6: 06a7e063 bltu a5,a0,2656 + 25fa: 03600793 li a5,54 + 25fe: 02a7e163 bltu a5,a0,2620 + 2602: 03300793 li a5,51 + 2606: 02f57563 bgeu a0,a5,2630 + 260a: 47a1 li a5,8 + 260c: 1ef50363 beq a0,a5,27f2 + 2610: 03200793 li a5,50 + 2614: 08f50b63 beq a0,a5,26aa + 2618: 8522 mv a0,s0 + 261a: e29ff0ef jal ra,2442 + 261e: a6ed j 2a08 + 2620: 03a00793 li a5,58 + 2624: 02a7e463 bltu a5,a0,264c + 2628: 03800793 li a5,56 + 262c: 04f56d63 bltu a0,a5,2686 + 2630: 4414 lw a3,8(s0) + 2632: 5c1c lw a5,56(s0) + 2634: 5c50 lw a2,60(s0) + 2636: 0000c5b7 lui a1,0xc + 263a: 96be add a3,a3,a5 + 263c: 2e858593 addi a1,a1,744 # c2e8 <_exit+0x2d8> + 2640: 8522 mv a0,s0 + 2642: ddbfe0ef jal ra,141c + 2646: 892a mv s2,a0 + 2648: 84ae mv s1,a1 + 264a: a051 j 26ce + 264c: 03c00793 li a5,60 + 2650: fef500e3 beq a0,a5,2630 + 2654: b7d1 j 2618 + 2656: 04200793 li a5,66 + 265a: 0af50a63 beq a0,a5,270e + 265e: 00a7e963 bltu a5,a0,2670 + 2662: 03f00793 li a5,63 + 2666: 0af50863 beq a0,a5,2716 + 266a: fcf573e3 bgeu a0,a5,2630 + 266e: b76d j 2618 + 2670: 04400793 li a5,68 + 2674: 34f50063 beq a0,a5,29b4 + 2678: faf56ce3 bltu a0,a5,2630 + 267c: 04d00793 li a5,77 + 2680: f8a7ece3 bltu a5,a0,2618 + 2684: b775 j 2630 + 2686: 02f44783 lbu a5,47(s0) + 268a: 0017f713 andi a4,a5,1 + 268e: eb15 bnez a4,26c2 + 2690: 0027f713 andi a4,a5,2 + 2694: 0017e793 ori a5,a5,1 + 2698: e31d bnez a4,26be + 269a: 0000c5b7 lui a1,0xc + 269e: 30058593 addi a1,a1,768 # c300 <_exit+0x2f0> + 26a2: 8522 mv a0,s0 + 26a4: d79fe0ef jal ra,141c + 26a8: bf79 j 2646 + 26aa: 02f44783 lbu a5,47(s0) + 26ae: 0017f713 andi a4,a5,1 + 26b2: eb01 bnez a4,26c2 + 26b4: 0027f713 andi a4,a5,2 + 26b8: 0097e793 ori a5,a5,9 + 26bc: df79 beqz a4,269a + 26be: 02f407a3 sb a5,47(s0) + 26c2: 4785 li a5,1 + 26c4: 02f40723 sb a5,46(s0) + 26c8: 4901 li s2,0 + 26ca: 7ff304b7 lui s1,0x7ff30 + 26ce: 8522 mv a0,s0 + 26d0: a8bfe0ef jal ra,115a + 26d4: 4795 li a5,5 + 26d6: 32f50f63 beq a0,a5,2a14 + 26da: 8522 mv a0,s0 + 26dc: a7ffe0ef jal ra,115a + 26e0: 4785 li a5,1 + 26e2: 32f50963 beq a0,a5,2a14 + 26e6: 8522 mv a0,s0 + 26e8: a73fe0ef jal ra,115a + 26ec: 47a5 li a5,9 + 26ee: 32f50363 beq a0,a5,2a14 + 26f2: 0000c5b7 lui a1,0xc + 26f6: 31858593 addi a1,a1,792 # c318 <_exit+0x308> + 26fa: 8522 mv a0,s0 + 26fc: d21fe0ef jal ra,141c + 2700: 892a mv s2,a0 + 2702: 84ae mv s1,a1 + 2704: 854a mv a0,s2 + 2706: 85a6 mv a1,s1 + 2708: 0141 addi sp,sp,16 + 270a: c59fd06f j 362 <__riscv_restore_12> + 270e: 8522 mv a0,s0 + 2710: da7ff0ef jal ra,24b6 + 2714: bf0d j 2646 + 2716: 4485 li s1,1 + 2718: 02940723 sb s1,46(s0) + 271c: 8522 mv a0,s0 + 271e: e58fe0ef jal ra,d76 + 2722: 4799 li a5,6 + 2724: 00f50763 beq a0,a5,2732 + 2728: 0000c5b7 lui a1,0xc + 272c: 29c58593 addi a1,a1,668 # c29c <_exit+0x28c> + 2730: bf8d j 26a2 + 2732: 02940723 sb s1,46(s0) + 2736: 8522 mv a0,s0 + 2738: d0bff0ef jal ra,2442 + 273c: 862e mv a2,a1 + 273e: 85aa mv a1,a0 + 2740: 8522 mv a0,s0 + 2742: a3cfe0ef jal ra,97e + 2746: 892a mv s2,a0 + 2748: 8522 mv a0,s0 + 274a: 89ae mv s3,a1 + 274c: a0ffe0ef jal ra,115a + 2750: 479d li a5,7 + 2752: fcf51be3 bne a0,a5,2728 + 2756: 864e mv a2,s3 + 2758: 02940723 sb s1,46(s0) + 275c: 85ca mv a1,s2 + 275e: 8522 mv a0,s0 + 2760: 980fe0ef jal ra,8e0 + 2764: 02f44783 lbu a5,47(s0) + 2768: 89aa mv s3,a0 + 276a: 0017fa93 andi s5,a5,1 + 276e: e509 bnez a0,2778 + 2770: 0017e793 ori a5,a5,1 + 2774: 02f407a3 sb a5,47(s0) + 2778: 8522 mv a0,s0 + 277a: 2e1d jal 2ab0 + 277c: 892a mv s2,a0 + 277e: 84ae mv s1,a1 + 2780: 00099c63 bnez s3,2798 + 2784: 000a9763 bnez s5,2792 + 2788: 02f44783 lbu a5,47(s0) + 278c: 9bf9 andi a5,a5,-2 + 278e: 02f407a3 sb a5,47(s0) + 2792: 4901 li s2,0 + 2794: 7ff304b7 lui s1,0x7ff30 + 2798: 02d44b03 lbu s6,45(s0) + 279c: 03442b83 lw s7,52(s0) + 27a0: 4a05 li s4,1 + 27a2: 03440723 sb s4,46(s0) + 27a6: 8522 mv a0,s0 + 27a8: dcefe0ef jal ra,d76 + 27ac: 03b00793 li a5,59 + 27b0: 03742a23 sw s7,52(s0) + 27b4: 036406a3 sb s6,45(s0) + 27b8: f0f51be3 bne a0,a5,26ce + 27bc: 03440723 sb s4,46(s0) + 27c0: 8522 mv a0,s0 + 27c2: 999fe0ef jal ra,115a + 27c6: 03440723 sb s4,46(s0) + 27ca: 00098863 beqz s3,27da + 27ce: 02f44783 lbu a5,47(s0) + 27d2: 0017e793 ori a5,a5,1 + 27d6: 02f407a3 sb a5,47(s0) + 27da: 8522 mv a0,s0 + 27dc: 2cd1 jal 2ab0 + 27de: e60984e3 beqz s3,2646 + 27e2: ee0a96e3 bnez s5,26ce + 27e6: 02f44783 lbu a5,47(s0) + 27ea: 9bf9 andi a5,a5,-2 + 27ec: 02f407a3 sb a5,47(s0) + 27f0: bdf9 j 26ce + 27f2: 02f44583 lbu a1,47(s0) + 27f6: 8522 mv a0,s0 + 27f8: fff5c593 not a1,a1 + 27fc: 8985 andi a1,a1,1 + 27fe: 2c39 jal 2a1c + 2800: b599 j 2646 + 2802: 02f44483 lbu s1,47(s0) + 2806: 4701 li a4,0 + 2808: 7ff307b7 lui a5,0x7ff30 + 280c: 0014f913 andi s2,s1,1 + 2810: c43a sw a4,8(sp) + 2812: c63e sw a5,12(sp) + 2814: 00091563 bnez s2,281e + 2818: 8522 mv a0,s0 + 281a: d2bfe0ef jal ra,1544 + 281e: 0030 addi a2,sp,8 + 2820: 03d00593 li a1,61 + 2824: 8522 mv a0,s0 + 2826: d61fe0ef jal ra,1586 + 282a: 0e050963 beqz a0,291c + 282e: 0030 addi a2,sp,8 + 2830: 4599 li a1,6 + 2832: 8522 mv a0,s0 + 2834: d53fe0ef jal ra,1586 + 2838: 0e050263 beqz a0,291c + 283c: 8522 mv a0,s0 + 283e: 91dfe0ef jal ra,115a + 2842: 4795 li a5,5 + 2844: 0af51d63 bne a0,a5,28fe + 2848: 0030 addi a2,sp,8 + 284a: 4595 li a1,5 + 284c: 8522 mv a0,s0 + 284e: d39fe0ef jal ra,1586 + 2852: 0c050563 beqz a0,291c + 2856: 02f44783 lbu a5,47(s0) + 285a: 8522 mv a0,s0 + 285c: 03442a03 lw s4,52(s0) + 2860: 0017e793 ori a5,a5,1 + 2864: 02f407a3 sb a5,47(s0) + 2868: 8f3fe0ef jal ra,115a + 286c: 4795 li a5,5 + 286e: 0af51e63 bne a0,a5,292a + 2872: 0030 addi a2,sp,8 + 2874: 4595 li a1,5 + 2876: 8522 mv a0,s0 + 2878: d0ffe0ef jal ra,1586 + 287c: c145 beqz a0,291c + 287e: 8522 mv a0,s0 + 2880: 03442a83 lw s5,52(s0) + 2884: 8d7fe0ef jal ra,115a + 2888: 479d li a5,7 + 288a: 0af51963 bne a0,a5,293c + 288e: 0030 addi a2,sp,8 + 2890: 459d li a1,7 + 2892: 8522 mv a0,s0 + 2894: cf3fe0ef jal ra,1586 + 2898: c151 beqz a0,291c + 289a: 8522 mv a0,s0 + 289c: 03442b03 lw s6,52(s0) + 28a0: 2c01 jal 2ab0 + 28a2: 0030 addi a2,sp,8 + 28a4: fb3fd0ef jal ra,856 + 28a8: e935 bnez a0,291c + 28aa: 03442b83 lw s7,52(s0) + 28ae: 4985 li s3,1 + 28b0: 4c15 li s8,5 + 28b2: 4c9d li s9,7 + 28b4: 0c091063 bnez s2,2974 + 28b8: 029407a3 sb s1,47(s0) + 28bc: 03442a23 sw s4,52(s0) + 28c0: 03340723 sb s3,46(s0) + 28c4: 8522 mv a0,s0 + 28c6: cb0fe0ef jal ra,d76 + 28ca: 09851163 bne a0,s8,294c + 28ce: 02f44783 lbu a5,47(s0) + 28d2: 03642a23 sw s6,52(s0) + 28d6: 03340723 sb s3,46(s0) + 28da: 0027e793 ori a5,a5,2 + 28de: 02f407a3 sb a5,47(s0) + 28e2: 8522 mv a0,s0 + 28e4: 22f1 jal 2ab0 + 28e6: 0030 addi a2,sp,8 + 28e8: f6ffd0ef jal ra,856 + 28ec: cd41 beqz a0,2984 + 28ee: 8522 mv a0,s0 + 28f0: fdbfd0ef jal ra,8ca + 28f4: 029407a3 sb s1,47(s0) + 28f8: 4922 lw s2,8(sp) + 28fa: 44b2 lw s1,12(sp) + 28fc: bbc9 j 26ce + 28fe: 8522 mv a0,s0 + 2900: 85bfe0ef jal ra,115a + 2904: 04200793 li a5,66 + 2908: 00f51d63 bne a0,a5,2922 + 290c: 8522 mv a0,s0 + 290e: ba9ff0ef jal ra,24b6 + 2912: 0030 addi a2,sp,8 + 2914: f43fd0ef jal ra,856 + 2918: f20508e3 beqz a0,2848 + 291c: fc091ce3 bnez s2,28f4 + 2920: b7f9 j 28ee + 2922: 8522 mv a0,s0 + 2924: b1fff0ef jal ra,2442 + 2928: b7ed j 2912 + 292a: 8522 mv a0,s0 + 292c: b17ff0ef jal ra,2442 + 2930: 0030 addi a2,sp,8 + 2932: f25fd0ef jal ra,856 + 2936: f2050ee3 beqz a0,2872 + 293a: b7cd j 291c + 293c: 8522 mv a0,s0 + 293e: b05ff0ef jal ra,2442 + 2942: 0030 addi a2,sp,8 + 2944: f13fd0ef jal ra,856 + 2948: d139 beqz a0,288e + 294a: bfc9 j 291c + 294c: 8522 mv a0,s0 + 294e: af5ff0ef jal ra,2442 + 2952: 862e mv a2,a1 + 2954: 85aa mv a1,a0 + 2956: 8522 mv a0,s0 + 2958: 826fe0ef jal ra,97e + 295c: 0030 addi a2,sp,8 + 295e: 8d2a mv s10,a0 + 2960: 8dae mv s11,a1 + 2962: ef5fd0ef jal ra,856 + 2966: f541 bnez a0,28ee + 2968: 85ea mv a1,s10 + 296a: 866e mv a2,s11 + 296c: 8522 mv a0,s0 + 296e: f73fd0ef jal ra,8e0 + 2972: fd31 bnez a0,28ce + 2974: 4795 li a5,5 + 2976: 03742a23 sw s7,52(s0) + 297a: 02f406a3 sb a5,45(s0) + 297e: 02040723 sb zero,46(s0) + 2982: bf69 j 291c + 2984: 02f44783 lbu a5,47(s0) + 2988: 8ba1 andi a5,a5,8 + 298a: f7ed bnez a5,2974 + 298c: 029407a3 sb s1,47(s0) + 2990: 03542a23 sw s5,52(s0) + 2994: 03340723 sb s3,46(s0) + 2998: 8522 mv a0,s0 + 299a: bdcfe0ef jal ra,d76 + 299e: f1950de3 beq a0,s9,28b8 + 29a2: 8522 mv a0,s0 + 29a4: a9fff0ef jal ra,2442 + 29a8: 0030 addi a2,sp,8 + 29aa: eadfd0ef jal ra,856 + 29ae: f00505e3 beqz a0,28b8 + 29b2: bf35 j 28ee + 29b4: 02f44983 lbu s3,47(s0) + 29b8: 4785 li a5,1 + 29ba: 02f40723 sb a5,46(s0) + 29be: 0059f793 andi a5,s3,5 + 29c2: e791 bnez a5,29ce + 29c4: 0000c5b7 lui a1,0xc + 29c8: 30c58593 addi a1,a1,780 # c30c <_exit+0x2fc> + 29cc: b9d9 j 26a2 + 29ce: 8522 mv a0,s0 + 29d0: f8afe0ef jal ra,115a + 29d4: 4795 li a5,5 + 29d6: 4901 li s2,0 + 29d8: 7ff304b7 lui s1,0x7ff30 + 29dc: cef509e3 beq a0,a5,26ce + 29e0: 8522 mv a0,s0 + 29e2: a61ff0ef jal ra,2442 + 29e6: 862e mv a2,a1 + 29e8: 0019f993 andi s3,s3,1 + 29ec: 85aa mv a1,a0 + 29ee: 8522 mv a0,s0 + 29f0: f8ffd0ef jal ra,97e + 29f4: 00099a63 bnez s3,2a08 + 29f8: 581c lw a5,48(s0) + 29fa: d85c sw a5,52(s0) + 29fc: 02f44783 lbu a5,47(s0) + 2a00: 0107e793 ori a5,a5,16 + 2a04: 02f407a3 sb a5,47(s0) + 2a08: 862e mv a2,a1 + 2a0a: 85aa mv a1,a0 + 2a0c: 8522 mv a0,s0 + 2a0e: f71fd0ef jal ra,97e + 2a12: b915 j 2646 + 2a14: 4785 li a5,1 + 2a16: 02f40723 sb a5,46(s0) + 2a1a: b1ed j 2704 + +00002a1c : + 2a1c: 913fd2ef jal t0,32e <__riscv_save_10> + 2a20: 842a mv s0,a0 + 2a22: 8a2e mv s4,a1 + 2a24: c199 beqz a1,2a2a + 2a26: b1ffe0ef jal ra,1544 + 2a2a: 4785 li a5,1 + 2a2c: 02f40723 sb a5,46(s0) + 2a30: 4901 li s2,0 + 2a32: 7ff309b7 lui s3,0x7ff30 + 2a36: 4a85 li s5,1 + 2a38: 4b25 li s6,9 + 2a3a: 4ba1 li s7,8 + 2a3c: 03f00c13 li s8,63 + 2a40: 04b00c93 li s9,75 + 2a44: 4d15 li s10,5 + 2a46: 8522 mv a0,s0 + 2a48: f12fe0ef jal ra,115a + 2a4c: 05550963 beq a0,s5,2a9e + 2a50: 8522 mv a0,s0 + 2a52: f08fe0ef jal ra,115a + 2a56: 05650463 beq a0,s6,2a9e + 2a5a: 854a mv a0,s2 + 2a5c: 85ce mv a1,s3 + 2a5e: c6dfd0ef jal ra,6ca + 2a62: ed15 bnez a0,2a9e + 2a64: 8522 mv a0,s0 + 2a66: 02d44483 lbu s1,45(s0) + 2a6a: b6bff0ef jal ra,25d4 + 2a6e: 892a mv s2,a0 + 2a70: 89ae mv s3,a1 + 2a72: c59fd0ef jal ra,6ca + 2a76: f961 bnez a0,2a46 + 2a78: fd7487e3 beq s1,s7,2a46 + 2a7c: fd8485e3 beq s1,s8,2a46 + 2a80: fd9483e3 beq s1,s9,2a46 + 2a84: 02d44783 lbu a5,45(s0) + 2a88: fba78fe3 beq a5,s10,2a46 + 2a8c: 0000c5b7 lui a1,0xc + 2a90: 31858593 addi a1,a1,792 # c318 <_exit+0x308> + 2a94: 8522 mv a0,s0 + 2a96: 987fe0ef jal ra,141c + 2a9a: 892a mv s2,a0 + 2a9c: 89ae mv s3,a1 + 2a9e: 000a0563 beqz s4,2aa8 + 2aa2: 8522 mv a0,s0 + 2aa4: e27fd0ef jal ra,8ca + 2aa8: 854a mv a0,s2 + 2aaa: 85ce mv a1,s3 + 2aac: 8bbfd06f j 366 <__riscv_restore_10> + +00002ab0 : + 2ab0: 8a7fd2ef jal t0,356 <__riscv_save_0> + 2ab4: 842a mv s0,a0 + 2ab6: ea4fe0ef jal ra,115a + 2aba: 47a1 li a5,8 + 2abc: 00f51c63 bne a0,a5,2ad4 + 2ac0: 02f44583 lbu a1,47(s0) + 2ac4: 8522 mv a0,s0 + 2ac6: fff5c593 not a1,a1 + 2aca: 8985 andi a1,a1,1 + 2acc: f51ff0ef jal ra,2a1c + 2ad0: 8abfd06f j 37a <__riscv_restore_0> + 2ad4: 8522 mv a0,s0 + 2ad6: affff0ef jal ra,25d4 + 2ada: 862e mv a2,a1 + 2adc: 85aa mv a1,a0 + 2ade: 8522 mv a0,s0 + 2ae0: e9ffd0ef jal ra,97e + 2ae4: 02040723 sb zero,46(s0) + 2ae8: b7e5 j 2ad0 + +00002aea : + 2aea: 83dfd2ef jal t0,326 <__riscv_save_12> + 2aee: 1101 addi sp,sp,-32 + 2af0: 8c2a mv s8,a0 + 2af2: e68fe0ef jal ra,115a + 2af6: 4799 li a5,6 + 2af8: 04f51463 bne a0,a5,2b40 + 2afc: 4905 li s2,1 + 2afe: 032c0723 sb s2,46(s8) # 7ff0002e <_eusrstack+0x5fef002e> + 2b02: 8562 mv a0,s8 + 2b04: 93fff0ef jal ra,2442 + 2b08: 842a mv s0,a0 + 2b0a: 84ae mv s1,a1 + 2b0c: bbffd0ef jal ra,6ca + 2b10: e11d bnez a0,2b36 + 2b12: 8562 mv a0,s8 + 2b14: e46fe0ef jal ra,115a + 2b18: 479d li a5,7 + 2b1a: 00f50c63 beq a0,a5,2b32 + 2b1e: 0000c5b7 lui a1,0xc + 2b22: 2a858593 addi a1,a1,680 # c2a8 <_exit+0x298> + 2b26: 8562 mv a0,s8 + 2b28: 8f5fe0ef jal ra,141c + 2b2c: 842a mv s0,a0 + 2b2e: 84ae mv s1,a1 + 2b30: a019 j 2b36 + 2b32: 032c0723 sb s2,46(s8) + 2b36: 8522 mv a0,s0 + 2b38: 85a6 mv a1,s1 + 2b3a: 6105 addi sp,sp,32 + 2b3c: 827fd06f j 362 <__riscv_restore_12> + 2b40: 8562 mv a0,s8 + 2b42: e18fe0ef jal ra,115a + 2b46: 8562 mv a0,s8 + 2b48: b91fd0ef jal ra,6d8 + 2b4c: 068c2783 lw a5,104(s8) + 2b50: cb91 beqz a5,2b64 + 2b52: 000c2703 lw a4,0(s8) + 2b56: 00e7f763 bgeu a5,a4,2b64 + 2b5a: 0000c5b7 lui a1,0xc + 2b5e: 2b458593 addi a1,a1,692 # c2b4 <_exit+0x2a4> + 2b62: b7d1 j 2b26 + 2b64: 02dc4783 lbu a5,45(s8) + 2b68: 4405 li s0,1 + 2b6a: 028c0723 sb s0,46(s8) + 2b6e: 4721 li a4,8 + 2b70: 06e78c63 beq a5,a4,2be8 + 2b74: 02f76763 bltu a4,a5,2ba2 + 2b78: 4709 li a4,2 + 2b7a: 26e78563 beq a5,a4,2de4 + 2b7e: 00f76863 bltu a4,a5,2b8e + 2b82: c3f5 beqz a5,2c66 + 2b84: 0000c5b7 lui a1,0xc + 2b88: 2bc58593 addi a1,a1,700 # c2bc <_exit+0x2ac> + 2b8c: bf69 j 2b26 + 2b8e: 470d li a4,3 + 2b90: 04e78763 beq a5,a4,2bde + 2b94: 4711 li a4,4 + 2b96: fee797e3 bne a5,a4,2b84 + 2b9a: 8562 mv a0,s8 + 2b9c: a89fe0ef jal ra,1624 + 2ba0: b771 j 2b2c + 2ba2: 04f00713 li a4,79 + 2ba6: 26e78063 beq a5,a4,2e06 + 2baa: 00f76e63 bltu a4,a5,2bc6 + 2bae: 03e00713 li a4,62 + 2bb2: 14e78d63 beq a5,a4,2d0c + 2bb6: 04e00713 li a4,78 + 2bba: fce795e3 bne a5,a4,2b84 + 2bbe: 4401 li s0,0 + 2bc0: 7ff304b7 lui s1,0x7ff30 + 2bc4: bf8d j 2b36 + 2bc6: 05000713 li a4,80 + 2bca: 24e78263 beq a5,a4,2e0e + 2bce: 05100713 li a4,81 + 2bd2: 4401 li s0,0 + 2bd4: fae798e3 bne a5,a4,2b84 + 2bd8: 7ff604b7 lui s1,0x7ff60 + 2bdc: bfa9 j 2b36 + 2bde: 048c2403 lw s0,72(s8) + 2be2: 04cc2483 lw s1,76(s8) + 2be6: bf81 j 2b36 + 2be8: 02fc4a03 lbu s4,47(s8) + 2bec: 001a7a13 andi s4,s4,1 + 2bf0: 080a1063 bnez s4,2c70 + 2bf4: 4691 li a3,4 + 2bf6: 0870 addi a2,sp,28 + 2bf8: 4581 li a1,0 + 2bfa: 8562 mv a0,s8 + 2bfc: ce02 sw zero,28(sp) + 2bfe: 883fe0ef jal ra,1480 + 2c02: 842a mv s0,a0 + 2c04: 84ae mv s1,a1 + 2c06: 8522 mv a0,s0 + 2c08: 85a6 mv a1,s1 + 2c0a: ac1fd0ef jal ra,6ca + 2c0e: f505 bnez a0,2b36 + 2c10: 4785 li a5,1 + 2c12: 02fc0723 sb a5,46(s8) + 2c16: 4ba5 li s7,9 + 2c18: 4c91 li s9,4 + 2c1a: 4a85 li s5,1 + 2c1c: 08100d13 li s10,129 + 2c20: 08f00d93 li s11,143 + 2c24: 8562 mv a0,s8 + 2c26: d34fe0ef jal ra,115a + 2c2a: 07750e63 beq a0,s7,2ca6 + 2c2e: 02dc4783 lbu a5,45(s8) + 2c32: 4709 li a4,2 + 2c34: 04e79263 bne a5,a4,2c78 + 2c38: 4981 li s3,0 + 2c3a: 4901 li s2,0 + 2c3c: 000a1e63 bnez s4,2c58 + 2c40: 008c2583 lw a1,8(s8) + 2c44: 038c2783 lw a5,56(s8) + 2c48: 03cc2603 lw a2,60(s8) + 2c4c: 8562 mv a0,s8 + 2c4e: 95be add a1,a1,a5 + 2c50: 96dfe0ef jal ra,15bc + 2c54: 89aa mv s3,a0 + 2c56: 892e mv s2,a1 + 2c58: 035c0723 sb s5,46(s8) + 2c5c: 8562 mv a0,s8 + 2c5e: 918fe0ef jal ra,d76 + 2c62: 03a50563 beq a0,s10,2c8c + 2c66: 0000c5b7 lui a1,0xc + 2c6a: 29c58593 addi a1,a1,668 # c29c <_exit+0x28c> + 2c6e: bd65 j 2b26 + 2c70: 4401 li s0,0 + 2c72: 7ff304b7 lui s1,0x7ff30 + 2c76: bf41 j 2c06 + 2c78: ff9797e3 bne a5,s9,2c66 + 2c7c: 4981 li s3,0 + 2c7e: 4901 li s2,0 + 2c80: fc0a1ce3 bnez s4,2c58 + 2c84: 8562 mv a0,s8 + 2c86: 99ffe0ef jal ra,1624 + 2c8a: b7e9 j 2c54 + 2c8c: 035c0723 sb s5,46(s8) + 2c90: 8562 mv a0,s8 + 2c92: fb0ff0ef jal ra,2442 + 2c96: 8b2a mv s6,a0 + 2c98: 020a0163 beqz s4,2cba + 2c9c: 8562 mv a0,s8 + 2c9e: cbcfe0ef jal ra,115a + 2ca2: 05751d63 bne a0,s7,2cfc + 2ca6: 8562 mv a0,s8 + 2ca8: cb2fe0ef jal ra,115a + 2cac: 47a5 li a5,9 + 2cae: faf51ce3 bne a0,a5,2c66 + 2cb2: 4785 li a5,1 + 2cb4: 02fc0723 sb a5,46(s8) + 2cb8: bdbd j 2b36 + 2cba: c62e sw a1,12(sp) + 2cbc: a0ffd0ef jal ra,6ca + 2cc0: 4632 lw a2,12(sp) + 2cc2: 14051863 bnez a0,2e12 + 2cc6: 854e mv a0,s3 + 2cc8: 85ca mv a1,s2 + 2cca: a01fd0ef jal ra,6ca + 2cce: e505 bnez a0,2cf6 + 2cd0: 4632 lw a2,12(sp) + 2cd2: 85da mv a1,s6 + 2cd4: 8562 mv a0,s8 + 2cd6: ca9fd0ef jal ra,97e + 2cda: 87aa mv a5,a0 + 2cdc: 882e mv a6,a1 + 2cde: 86ce mv a3,s3 + 2ce0: 874a mv a4,s2 + 2ce2: 85a2 mv a1,s0 + 2ce4: 8626 mv a2,s1 + 2ce6: 8562 mv a0,s8 + 2ce8: 811fe0ef jal ra,14f8 + 2cec: 89aa mv s3,a0 + 2cee: 892e mv s2,a1 + 2cf0: 9dbfd0ef jal ra,6ca + 2cf4: d545 beqz a0,2c9c + 2cf6: 844e mv s0,s3 + 2cf8: 84ca mv s1,s2 + 2cfa: bd35 j 2b36 + 2cfc: 8562 mv a0,s8 + 2cfe: c5cfe0ef jal ra,115a + 2d02: f7b512e3 bne a0,s11,2c66 + 2d06: 035c0723 sb s5,46(s8) + 2d0a: bf29 j 2c24 + 2d0c: 8562 mv a0,s8 + 2d0e: 02fc4903 lbu s2,47(s8) + 2d12: 864fe0ef jal ra,d76 + 2d16: 4799 li a5,6 + 2d18: 00f50563 beq a0,a5,2d22 + 2d1c: 032c07a3 sb s2,47(s8) + 2d20: b799 j 2c66 + 2d22: 034c2983 lw s3,52(s8) + 2d26: 028c0723 sb s0,46(s8) + 2d2a: 4a85 li s5,1 + 2d2c: 4401 li s0,0 + 2d2e: 449d li s1,7 + 2d30: 4b09 li s6,2 + 2d32: 4a05 li s4,1 + 2d34: 08f00b93 li s7,143 + 2d38: 8562 mv a0,s8 + 2d3a: c20fe0ef jal ra,115a + 2d3e: 03550d63 beq a0,s5,2d78 + 2d42: c415 beqz s0,2d6e + 2d44: 8562 mv a0,s8 + 2d46: c14fe0ef jal ra,115a + 2d4a: fd6519e3 bne a0,s6,2d1c + 2d4e: 034c0723 sb s4,46(s8) + 2d52: 8562 mv a0,s8 + 2d54: 822fe0ef jal ra,d76 + 2d58: 02950063 beq a0,s1,2d78 + 2d5c: 8562 mv a0,s8 + 2d5e: bfcfe0ef jal ra,115a + 2d62: fb751de3 bne a0,s7,2d1c + 2d66: 034c0723 sb s4,46(s8) + 2d6a: 4405 li s0,1 + 2d6c: b7f1 j 2d38 + 2d6e: 8562 mv a0,s8 + 2d70: beafe0ef jal ra,115a + 2d74: fc9518e3 bne a0,s1,2d44 + 2d78: 8562 mv a0,s8 + 2d7a: be0fe0ef jal ra,115a + 2d7e: 479d li a5,7 + 2d80: f8f51ee3 bne a0,a5,2d1c + 2d84: 4a05 li s4,1 + 2d86: 034c0723 sb s4,46(s8) + 2d8a: 8562 mv a0,s8 + 2d8c: febfd0ef jal ra,d76 + 2d90: 47a1 li a5,8 + 2d92: f8f515e3 bne a0,a5,2d1c + 2d96: 02fc4783 lbu a5,47(s8) + 2d9a: 020c0723 sb zero,46(s8) + 2d9e: 4581 li a1,0 + 2da0: 0017e793 ori a5,a5,1 + 2da4: 02fc07a3 sb a5,47(s8) + 2da8: 8562 mv a0,s8 + 2daa: c73ff0ef jal ra,2a1c + 2dae: 842a mv s0,a0 + 2db0: 84ae mv s1,a1 + 2db2: 919fd0ef jal ra,6ca + 2db6: c501 beqz a0,2dbe + 2db8: 032c07a3 sb s2,47(s8) + 2dbc: bbad j 2b36 + 2dbe: 034c2603 lw a2,52(s8) + 2dc2: 008c2583 lw a1,8(s8) + 2dc6: 19fd addi s3,s3,-1 + 2dc8: 032c07a3 sb s2,47(s8) + 2dcc: 41360633 sub a2,a2,s3 + 2dd0: 95ce add a1,a1,s3 + 2dd2: 8562 mv a0,s8 + 2dd4: fe8fe0ef jal ra,15bc + 2dd8: 842a mv s0,a0 + 2dda: 034c0723 sb s4,46(s8) + 2dde: 7ff704b7 lui s1,0x7ff70 + 2de2: bb91 j 2b36 + 2de4: 03cc2403 lw s0,60(s8) + 2de8: 038c2783 lw a5,56(s8) + 2dec: 00845493 srli s1,s0,0x8 + 2df0: 01049713 slli a4,s1,0x10 + 2df4: 07a2 slli a5,a5,0x8 + 2df6: 0462 slli s0,s0,0x18 + 2df8: 8341 srli a4,a4,0x10 + 2dfa: 83a1 srli a5,a5,0x8 + 2dfc: 7ff804b7 lui s1,0x7ff80 + 2e00: 8c5d or s0,s0,a5 + 2e02: 8cd9 or s1,s1,a4 + 2e04: bb0d j 2b36 + 2e06: 4401 li s0,0 + 2e08: 7ff404b7 lui s1,0x7ff40 + 2e0c: b32d j 2b36 + 2e0e: 4405 li s0,1 + 2e10: b3e1 j 2bd8 + 2e12: 845a mv s0,s6 + 2e14: 84b2 mv s1,a2 + 2e16: b305 j 2b36 + +00002e18 : + 2e18: d0efd2ef jal t0,326 <__riscv_save_12> + 2e1c: 1141 addi sp,sp,-16 + 2e1e: 8c2a mv s8,a0 + 2e20: b3afe0ef jal ra,115a + 2e24: 06800793 li a5,104 + 2e28: 04f50963 beq a0,a5,2e7a + 2e2c: 02dc4783 lbu a5,45(s8) + 2e30: f9778793 addi a5,a5,-105 # 7ff2ff97 <_eusrstack+0x5ff1ff97> + 2e34: 0f67f793 andi a5,a5,246 + 2e38: c3a9 beqz a5,2e7a + 2e3a: 8562 mv a0,s8 + 2e3c: cafff0ef jal ra,2aea + 2e40: 892a mv s2,a0 + 2e42: 89ae mv s3,a1 + 2e44: 887fd0ef jal ra,6ca + 2e48: cd2d beqz a0,2ec2 + 2e4a: 854a mv a0,s2 + 2e4c: 85ce mv a1,s3 + 2e4e: 87dfd0ef jal ra,6ca + 2e52: e125 bnez a0,2eb2 + 2e54: 8562 mv a0,s8 + 2e56: b04fe0ef jal ra,115a + 2e5a: 02dc4583 lbu a1,45(s8) + 2e5e: 4705 li a4,1 + 2e60: f9a58793 addi a5,a1,-102 + 2e64: 0ff7f793 andi a5,a5,255 + 2e68: 04f76563 bltu a4,a5,2eb2 + 2e6c: 02ec0723 sb a4,46(s8) + 2e70: 4781 li a5,0 + 2e72: 4701 li a4,0 + 2e74: 864a mv a2,s2 + 2e76: 86ce mv a3,s3 + 2e78: a805 j 2ea8 + 2e7a: 02dc4403 lbu s0,45(s8) + 2e7e: 07200793 li a5,114 + 2e82: 02f40d63 beq s0,a5,2ebc + 2e86: 07100793 li a5,113 + 2e8a: 00f41463 bne s0,a5,2e92 + 2e8e: 06b00413 li s0,107 + 2e92: 4785 li a5,1 + 2e94: 02fc0723 sb a5,46(s8) + 2e98: 8562 mv a0,s8 + 2e9a: 3fbd jal 2e18 + 2e9c: 87ae mv a5,a1 + 2e9e: 872a mv a4,a0 + 2ea0: 4601 li a2,0 + 2ea2: 7ff306b7 lui a3,0x7ff30 + 2ea6: 85a2 mv a1,s0 + 2ea8: 8562 mv a0,s8 + 2eaa: ba9fe0ef jal ra,1a52 + 2eae: 892a mv s2,a0 + 2eb0: 89ae mv s3,a1 + 2eb2: 854a mv a0,s2 + 2eb4: 85ce mv a1,s3 + 2eb6: 0141 addi sp,sp,16 + 2eb8: caafd06f j 362 <__riscv_restore_12> + 2ebc: 06c00413 li s0,108 + 2ec0: bfc9 j 2e92 + 2ec2: 854a mv a0,s2 + 2ec4: 85ce mv a1,s3 + 2ec6: feefd0ef jal ra,6b4 + 2eca: 47a1 li a5,8 + 2ecc: 04f51363 bne a0,a5,2f12 + 2ed0: 02fc4783 lbu a5,47(s8) + 2ed4: 8b85 andi a5,a5,1 + 2ed6: efd9 bnez a5,2f74 + 2ed8: 01000437 lui s0,0x1000 + 2edc: 147d addi s0,s0,-1 + 2ede: 008977b3 and a5,s2,s0 + 2ee2: 09a2 slli s3,s3,0x8 + 2ee4: 008c2483 lw s1,8(s8) + 2ee8: 01895913 srli s2,s2,0x18 + 2eec: 0129e933 or s2,s3,s2 + 2ef0: 054c2603 lw a2,84(s8) + 2ef4: 050c2983 lw s3,80(s8) + 2ef8: 94be add s1,s1,a5 + 2efa: 00897433 and s0,s2,s0 + 2efe: 8722 mv a4,s0 + 2f00: 86a6 mv a3,s1 + 2f02: 85ce mv a1,s3 + 2f04: 8562 mv a0,s8 + 2f06: a2ffd0ef jal ra,934 + 2f0a: cd15 beqz a0,2f46 + 2f0c: 892a mv s2,a0 + 2f0e: 7ff109b7 lui s3,0x7ff10 + 2f12: 6ac1 lui s5,0x10 + 2f14: 01000b37 lui s6,0x1000 + 2f18: 84ca mv s1,s2 + 2f1a: 844e mv s0,s3 + 2f1c: 4a1d li s4,7 + 2f1e: 1afd addi s5,s5,-1 + 2f20: 1b7d addi s6,s6,-1 + 2f22: 0000cbb7 lui s7,0xc + 2f26: 8562 mv a0,s8 + 2f28: a32fe0ef jal ra,115a + 2f2c: 4799 li a5,6 + 2f2e: 04f50663 beq a0,a5,2f7a + 2f32: 8562 mv a0,s8 + 2f34: a26fe0ef jal ra,115a + 2f38: 06400793 li a5,100 + 2f3c: 02f50f63 beq a0,a5,2f7a + 2f40: 8926 mv s2,s1 + 2f42: 89a2 mv s3,s0 + 2f44: b719 j 2e4a + 2f46: 00098b63 beqz s3,2f5c + 2f4a: 00498593 addi a1,s3,4 # 7ff10004 <_eusrstack+0x5ff00004> + 2f4e: 8562 mv a0,s8 + 2f50: 921fd0ef jal ra,870 + 2f54: 89aa mv s3,a0 + 2f56: 7ff00637 lui a2,0x7ff00 + 2f5a: b755 j 2efe + 2f5c: 0000c5b7 lui a1,0xc + 2f60: 86a6 mv a3,s1 + 2f62: 8622 mv a2,s0 + 2f64: 33458593 addi a1,a1,820 # c334 <_exit+0x324> + 2f68: 8562 mv a0,s8 + 2f6a: cb2fe0ef jal ra,141c + 2f6e: 892a mv s2,a0 + 2f70: 89ae mv s3,a1 + 2f72: b745 j 2f12 + 2f74: 4901 li s2,0 + 2f76: 4981 li s3,0 + 2f78: bf69 j 2f12 + 2f7a: 02dc4703 lbu a4,45(s8) + 2f7e: 06400793 li a5,100 + 2f82: 02f71463 bne a4,a5,2faa + 2f86: 4785 li a5,1 + 2f88: 02fc0723 sb a5,46(s8) + 2f8c: 8562 mv a0,s8 + 2f8e: b5dff0ef jal ra,2aea + 2f92: 87ae mv a5,a1 + 2f94: 872a mv a4,a0 + 2f96: 8626 mv a2,s1 + 2f98: 86a2 mv a3,s0 + 2f9a: 06400593 li a1,100 + 2f9e: 8562 mv a0,s8 + 2fa0: ab3fe0ef jal ra,1a52 + 2fa4: 84aa mv s1,a0 + 2fa6: 842e mv s0,a1 + 2fa8: bfbd j 2f26 + 2faa: 02fc4983 lbu s3,47(s8) + 2fae: 034c2903 lw s2,52(s8) + 2fb2: 4c85 li s9,1 + 2fb4: 0019e793 ori a5,s3,1 + 2fb8: 02fc07a3 sb a5,47(s8) + 2fbc: 4785 li a5,1 + 2fbe: 02fc0723 sb a5,46(s8) + 2fc2: 08f00d13 li s10,143 + 2fc6: 4781 li a5,0 + 2fc8: 4d85 li s11,1 + 2fca: 8562 mv a0,s8 + 2fcc: c63e sw a5,12(sp) + 2fce: 98cfe0ef jal ra,115a + 2fd2: 47b2 lw a5,12(sp) + 2fd4: 01950b63 beq a0,s9,2fea + 2fd8: c7a1 beqz a5,3020 + 2fda: 8562 mv a0,s8 + 2fdc: c66ff0ef jal ra,2442 + 2fe0: 8562 mv a0,s8 + 2fe2: 978fe0ef jal ra,115a + 2fe6: 05451363 bne a0,s4,302c + 2fea: 8562 mv a0,s8 + 2fec: 96efe0ef jal ra,115a + 2ff0: 05450763 beq a0,s4,303e + 2ff4: 033c07a3 sb s3,47(s8) + 2ff8: 29cb8593 addi a1,s7,668 # c29c <_exit+0x28c> + 2ffc: 8562 mv a0,s8 + 2ffe: c1efe0ef jal ra,141c + 3002: 892a mv s2,a0 + 3004: 89ae mv s3,a1 + 3006: 854a mv a0,s2 + 3008: 85ce mv a1,s3 + 300a: ec0fd0ef jal ra,6ca + 300e: e2051ee3 bnez a0,2e4a + 3012: 874a mv a4,s2 + 3014: 87ce mv a5,s3 + 3016: 8626 mv a2,s1 + 3018: 86a2 mv a3,s0 + 301a: 06500593 li a1,101 + 301e: b741 j 2f9e + 3020: 8562 mv a0,s8 + 3022: 938fe0ef jal ra,115a + 3026: fb451ae3 bne a0,s4,2fda + 302a: b7c1 j 2fea + 302c: 8562 mv a0,s8 + 302e: 92cfe0ef jal ra,115a + 3032: fda511e3 bne a0,s10,2ff4 + 3036: 03bc0723 sb s11,46(s8) + 303a: 4785 li a5,1 + 303c: b779 j 2fca + 303e: 03cc2603 lw a2,60(s8) + 3042: 4785 li a5,1 + 3044: 033c07a3 sb s3,47(s8) + 3048: 00c90533 add a0,s2,a2 + 304c: 034c2603 lw a2,52(s8) + 3050: 01697933 and s2,s2,s6 + 3054: 7ff809b7 lui s3,0x7ff80 + 3058: 8e09 sub a2,a2,a0 + 305a: 00865693 srli a3,a2,0x8 + 305e: 0156f6b3 and a3,a3,s5 + 3062: 0662 slli a2,a2,0x18 + 3064: 02fc0723 sb a5,46(s8) + 3068: 01266933 or s2,a2,s2 + 306c: 00d9e9b3 or s3,s3,a3 + 3070: bf59 j 3006 + +00003072 : + 3072: acafd2ef jal t0,33c <__riscv_save_4> + 3076: 1141 addi sp,sp,-16 + 3078: 842a mv s0,a0 + 307a: d9fff0ef jal ra,2e18 + 307e: 892a mv s2,a0 + 3080: 84ae mv s1,a1 + 3082: 06e00993 li s3,110 + 3086: 4a05 li s4,1 + 3088: 4a85 li s5,1 + 308a: 854a mv a0,s2 + 308c: 85a6 mv a1,s1 + 308e: e3cfd0ef jal ra,6ca + 3092: e539 bnez a0,30e0 + 3094: 8522 mv a0,s0 + 3096: 8c4fe0ef jal ra,115a + 309a: 01350a63 beq a0,s3,30ae + 309e: 02d44783 lbu a5,45(s0) # 100002d <_data_lma+0xff3595> + 30a2: f9178793 addi a5,a5,-111 + 30a6: 0ff7f793 andi a5,a5,255 + 30aa: 02fa6b63 bltu s4,a5,30e0 + 30ae: 03540723 sb s5,46(s0) + 30b2: 8522 mv a0,s0 + 30b4: 02d44b03 lbu s6,45(s0) + 30b8: d61ff0ef jal ra,2e18 + 30bc: c62a sw a0,12(sp) + 30be: c42e sw a1,8(sp) + 30c0: e0afd0ef jal ra,6ca + 30c4: 47a2 lw a5,8(sp) + 30c6: 4732 lw a4,12(sp) + 30c8: e911 bnez a0,30dc + 30ca: 864a mv a2,s2 + 30cc: 86a6 mv a3,s1 + 30ce: 85da mv a1,s6 + 30d0: 8522 mv a0,s0 + 30d2: 981fe0ef jal ra,1a52 + 30d6: 892a mv s2,a0 + 30d8: 84ae mv s1,a1 + 30da: bf45 j 308a + 30dc: 893a mv s2,a4 + 30de: 84be mv s1,a5 + 30e0: 854a mv a0,s2 + 30e2: 85a6 mv a1,s1 + 30e4: 0141 addi sp,sp,16 + 30e6: a8afd06f j 370 <__riscv_restore_4> + +000030ea : + 30ea: a52fd2ef jal t0,33c <__riscv_save_4> + 30ee: 1141 addi sp,sp,-16 + 30f0: 892a mv s2,a0 + 30f2: f81ff0ef jal ra,3072 + 30f6: 84aa mv s1,a0 + 30f8: 842e mv s0,a1 + 30fa: 07100a93 li s5,113 + 30fe: 07200a13 li s4,114 + 3102: 4b05 li s6,1 + 3104: 8526 mv a0,s1 + 3106: 85a2 mv a1,s0 + 3108: dc2fd0ef jal ra,6ca + 310c: e911 bnez a0,3120 + 310e: 854a mv a0,s2 + 3110: 84afe0ef jal ra,115a + 3114: 02d94983 lbu s3,45(s2) + 3118: 01550963 beq a0,s5,312a + 311c: 01498763 beq s3,s4,312a + 3120: 8526 mv a0,s1 + 3122: 85a2 mv a1,s0 + 3124: 0141 addi sp,sp,16 + 3126: a4afd06f j 370 <__riscv_restore_4> + 312a: 03690723 sb s6,46(s2) + 312e: 854a mv a0,s2 + 3130: f43ff0ef jal ra,3072 + 3134: c62a sw a0,12(sp) + 3136: c42e sw a1,8(sp) + 3138: d92fd0ef jal ra,6ca + 313c: 47a2 lw a5,8(sp) + 313e: 4732 lw a4,12(sp) + 3140: e911 bnez a0,3154 + 3142: 8626 mv a2,s1 + 3144: 86a2 mv a3,s0 + 3146: 85ce mv a1,s3 + 3148: 854a mv a0,s2 + 314a: 909fe0ef jal ra,1a52 + 314e: 84aa mv s1,a0 + 3150: 842e mv s0,a1 + 3152: bf4d j 3104 + 3154: 84ba mv s1,a4 + 3156: 843e mv s0,a5 + 3158: b7e1 j 3120 + +0000315a : + 315a: 9d4fd2ef jal t0,32e <__riscv_save_10> + 315e: 1141 addi sp,sp,-16 + 3160: 842a mv s0,a0 + 3162: f89ff0ef jal ra,30ea + 3166: 892a mv s2,a0 + 3168: 84ae mv s1,a1 + 316a: 07400a13 li s4,116 + 316e: 07300a93 li s5,115 + 3172: 07500993 li s3,117 + 3176: 4b05 li s6,1 + 3178: 854a mv a0,s2 + 317a: 85a6 mv a1,s1 + 317c: d4efd0ef jal ra,6ca + 3180: e105 bnez a0,31a0 + 3182: 8522 mv a0,s0 + 3184: fd7fd0ef jal ra,115a + 3188: 03450163 beq a0,s4,31aa + 318c: 8522 mv a0,s0 + 318e: fcdfd0ef jal ra,115a + 3192: 01550c63 beq a0,s5,31aa + 3196: 8522 mv a0,s0 + 3198: fc3fd0ef jal ra,115a + 319c: 01350763 beq a0,s3,31aa + 31a0: 854a mv a0,s2 + 31a2: 85a6 mv a1,s1 + 31a4: 0141 addi sp,sp,16 + 31a6: 9c0fd06f j 366 <__riscv_restore_10> + 31aa: 03640723 sb s6,46(s0) + 31ae: 8522 mv a0,s0 + 31b0: 02d44b83 lbu s7,45(s0) + 31b4: f37ff0ef jal ra,30ea + 31b8: c62a sw a0,12(sp) + 31ba: c42e sw a1,8(sp) + 31bc: d0efd0ef jal ra,6ca + 31c0: 47a2 lw a5,8(sp) + 31c2: 4732 lw a4,12(sp) + 31c4: e911 bnez a0,31d8 + 31c6: 864a mv a2,s2 + 31c8: 86a6 mv a3,s1 + 31ca: 85de mv a1,s7 + 31cc: 8522 mv a0,s0 + 31ce: 885fe0ef jal ra,1a52 + 31d2: 892a mv s2,a0 + 31d4: 84ae mv s1,a1 + 31d6: b74d j 3178 + 31d8: 893a mv s2,a4 + 31da: 84be mv s1,a5 + 31dc: b7d1 j 31a0 + +000031de : + 31de: 950fd2ef jal t0,32e <__riscv_save_10> + 31e2: 1141 addi sp,sp,-16 + 31e4: 842a mv s0,a0 + 31e6: f75ff0ef jal ra,315a + 31ea: 892a mv s2,a0 + 31ec: 84ae mv s1,a1 + 31ee: 07600a13 li s4,118 + 31f2: 07700a93 li s5,119 + 31f6: 07800b13 li s6,120 + 31fa: 07900993 li s3,121 + 31fe: 4b85 li s7,1 + 3200: 854a mv a0,s2 + 3202: 85a6 mv a1,s1 + 3204: cc6fd0ef jal ra,6ca + 3208: e50d bnez a0,3232 + 320a: 8522 mv a0,s0 + 320c: f4ffd0ef jal ra,115a + 3210: 03450663 beq a0,s4,323c + 3214: 8522 mv a0,s0 + 3216: f45fd0ef jal ra,115a + 321a: 03550163 beq a0,s5,323c + 321e: 8522 mv a0,s0 + 3220: f3bfd0ef jal ra,115a + 3224: 01650c63 beq a0,s6,323c + 3228: 8522 mv a0,s0 + 322a: f31fd0ef jal ra,115a + 322e: 01350763 beq a0,s3,323c + 3232: 854a mv a0,s2 + 3234: 85a6 mv a1,s1 + 3236: 0141 addi sp,sp,16 + 3238: 92efd06f j 366 <__riscv_restore_10> + 323c: 03740723 sb s7,46(s0) + 3240: 8522 mv a0,s0 + 3242: 02d44c03 lbu s8,45(s0) + 3246: f15ff0ef jal ra,315a + 324a: c62a sw a0,12(sp) + 324c: c42e sw a1,8(sp) + 324e: c7cfd0ef jal ra,6ca + 3252: 47a2 lw a5,8(sp) + 3254: 4732 lw a4,12(sp) + 3256: e911 bnez a0,326a + 3258: 864a mv a2,s2 + 325a: 86a6 mv a3,s1 + 325c: 85e2 mv a1,s8 + 325e: 8522 mv a0,s0 + 3260: ff2fe0ef jal ra,1a52 + 3264: 892a mv s2,a0 + 3266: 84ae mv s1,a1 + 3268: bf61 j 3200 + 326a: 893a mv s2,a4 + 326c: 84be mv s1,a5 + 326e: b7d1 j 3232 + +00003270 : + 3270: 8ccfd2ef jal t0,33c <__riscv_save_4> + 3274: 1141 addi sp,sp,-16 + 3276: 842a mv s0,a0 + 3278: f67ff0ef jal ra,31de + 327c: 892a mv s2,a0 + 327e: 84ae mv s1,a1 + 3280: 07a00a13 li s4,122 + 3284: 07b00993 li s3,123 + 3288: 4a85 li s5,1 + 328a: 854a mv a0,s2 + 328c: 85a6 mv a1,s1 + 328e: c3cfd0ef jal ra,6ca + 3292: e919 bnez a0,32a8 + 3294: 8522 mv a0,s0 + 3296: ec5fd0ef jal ra,115a + 329a: 01450c63 beq a0,s4,32b2 + 329e: 8522 mv a0,s0 + 32a0: ebbfd0ef jal ra,115a + 32a4: 01350763 beq a0,s3,32b2 + 32a8: 854a mv a0,s2 + 32aa: 85a6 mv a1,s1 + 32ac: 0141 addi sp,sp,16 + 32ae: 8c2fd06f j 370 <__riscv_restore_4> + 32b2: 03540723 sb s5,46(s0) + 32b6: 8522 mv a0,s0 + 32b8: 02d44b03 lbu s6,45(s0) + 32bc: f23ff0ef jal ra,31de + 32c0: c62a sw a0,12(sp) + 32c2: c42e sw a1,8(sp) + 32c4: c06fd0ef jal ra,6ca + 32c8: 47a2 lw a5,8(sp) + 32ca: 4732 lw a4,12(sp) + 32cc: e911 bnez a0,32e0 + 32ce: 864a mv a2,s2 + 32d0: 86a6 mv a3,s1 + 32d2: 85da mv a1,s6 + 32d4: 8522 mv a0,s0 + 32d6: f7cfe0ef jal ra,1a52 + 32da: 892a mv s2,a0 + 32dc: 84ae mv s1,a1 + 32de: b775 j 328a + 32e0: 893a mv s2,a4 + 32e2: 84be mv s1,a5 + 32e4: b7d1 j 32a8 + +000032e6 : + 32e6: 856fd2ef jal t0,33c <__riscv_save_4> + 32ea: 1141 addi sp,sp,-16 + 32ec: 892a mv s2,a0 + 32ee: f83ff0ef jal ra,3270 + 32f2: 84aa mv s1,a0 + 32f4: 842e mv s0,a1 + 32f6: 07c00993 li s3,124 + 32fa: 4a05 li s4,1 + 32fc: 8526 mv a0,s1 + 32fe: 85a2 mv a1,s0 + 3300: bcafd0ef jal ra,6ca + 3304: e511 bnez a0,3310 + 3306: 854a mv a0,s2 + 3308: e53fd0ef jal ra,115a + 330c: 01350763 beq a0,s3,331a + 3310: 8526 mv a0,s1 + 3312: 85a2 mv a1,s0 + 3314: 0141 addi sp,sp,16 + 3316: 85afd06f j 370 <__riscv_restore_4> + 331a: 03490723 sb s4,46(s2) + 331e: 854a mv a0,s2 + 3320: 02d94a83 lbu s5,45(s2) + 3324: f4dff0ef jal ra,3270 + 3328: c62a sw a0,12(sp) + 332a: c42e sw a1,8(sp) + 332c: b9efd0ef jal ra,6ca + 3330: 47a2 lw a5,8(sp) + 3332: 4732 lw a4,12(sp) + 3334: e911 bnez a0,3348 + 3336: 8626 mv a2,s1 + 3338: 86a2 mv a3,s0 + 333a: 85d6 mv a1,s5 + 333c: 854a mv a0,s2 + 333e: f14fe0ef jal ra,1a52 + 3342: 84aa mv s1,a0 + 3344: 842e mv s0,a1 + 3346: bf5d j 32fc + 3348: 84ba mv s1,a4 + 334a: 843e mv s0,a5 + 334c: b7d1 j 3310 + +0000334e : + 334e: feffc2ef jal t0,33c <__riscv_save_4> + 3352: 1141 addi sp,sp,-16 + 3354: 892a mv s2,a0 + 3356: f91ff0ef jal ra,32e6 + 335a: 84aa mv s1,a0 + 335c: 842e mv s0,a1 + 335e: 07d00993 li s3,125 + 3362: 4a05 li s4,1 + 3364: 8526 mv a0,s1 + 3366: 85a2 mv a1,s0 + 3368: b62fd0ef jal ra,6ca + 336c: e511 bnez a0,3378 + 336e: 854a mv a0,s2 + 3370: debfd0ef jal ra,115a + 3374: 01350763 beq a0,s3,3382 + 3378: 8526 mv a0,s1 + 337a: 85a2 mv a1,s0 + 337c: 0141 addi sp,sp,16 + 337e: ff3fc06f j 370 <__riscv_restore_4> + 3382: 03490723 sb s4,46(s2) + 3386: 854a mv a0,s2 + 3388: 02d94a83 lbu s5,45(s2) + 338c: f5bff0ef jal ra,32e6 + 3390: c62a sw a0,12(sp) + 3392: c42e sw a1,8(sp) + 3394: b36fd0ef jal ra,6ca + 3398: 47a2 lw a5,8(sp) + 339a: 4732 lw a4,12(sp) + 339c: e911 bnez a0,33b0 + 339e: 8626 mv a2,s1 + 33a0: 86a2 mv a3,s0 + 33a2: 85d6 mv a1,s5 + 33a4: 854a mv a0,s2 + 33a6: eacfe0ef jal ra,1a52 + 33aa: 84aa mv s1,a0 + 33ac: 842e mv s0,a1 + 33ae: bf5d j 3364 + 33b0: 84ba mv s1,a4 + 33b2: 843e mv s0,a5 + 33b4: b7d1 j 3378 + +000033b6 : + 33b6: f87fc2ef jal t0,33c <__riscv_save_4> + 33ba: 89be mv s3,a5 + 33bc: 6f6e77b7 lui a5,0x6f6e7 + 33c0: 1101 addi sp,sp,-32 + 33c2: 27178793 addi a5,a5,625 # 6f6e7271 <_eusrstack+0x4f6d7271> + 33c6: ca3e sw a5,20(sp) + 33c8: 757477b7 lui a5,0x75747 + 33cc: 37078793 addi a5,a5,880 # 75747370 <_eusrstack+0x55737370> + 33d0: cc3e sw a5,24(sp) + 33d2: 77e1 lui a5,0xffff8 + 33d4: d7c7c793 xori a5,a5,-644 + 33d8: 86fc sh a5,28(sp) + 33da: 07e00793 li a5,126 + 33de: 00f10f23 sb a5,30(sp) + 33e2: 101c addi a5,sp,32 + 33e4: 95be add a1,a1,a5 + 33e6: f705ca83 lbu s5,-144(a1) + 33ea: 8432 mv s0,a2 + 33ec: 85b2 mv a1,a2 + 33ee: 8636 mv a2,a3 + 33f0: 8a2a mv s4,a0 + 33f2: 84b6 mv s1,a3 + 33f4: 893a mv s2,a4 + 33f6: d88fd0ef jal ra,97e + 33fa: 86ae mv a3,a1 + 33fc: 874a mv a4,s2 + 33fe: 87ce mv a5,s3 + 3400: 862a mv a2,a0 + 3402: 85d6 mv a1,s5 + 3404: 8552 mv a0,s4 + 3406: e4cfe0ef jal ra,1a52 + 340a: 058a2783 lw a5,88(s4) + 340e: c42a sw a0,8(sp) + 3410: ffc47513 andi a0,s0,-4 + 3414: 0521 addi a0,a0,8 + 3416: c62e sw a1,12(sp) + 3418: 4621 li a2,8 + 341a: 002c addi a1,sp,8 + 341c: 953e add a0,a0,a5 + 341e: 308030ef jal ra,6726 + 3422: 8522 mv a0,s0 + 3424: 85a6 mv a1,s1 + 3426: 6105 addi sp,sp,32 + 3428: f49fc06f j 370 <__riscv_restore_4> + +0000342c : + 342c: 415c lw a5,4(a0) + 342e: 0511 addi a0,a0,4 + 3430: 9bf1 andi a5,a5,-4 + 3432: 953e add a0,a0,a5 + 3434: 8082 ret + +00003436 : + 3436: f21fc2ef jal t0,356 <__riscv_save_0> + 343a: 842a mv s0,a0 + 343c: ff1ff0ef jal ra,342c + 3440: c100 sw s0,0(a0) + 3442: f39fc06f j 37a <__riscv_restore_0> + +00003446 : + 3446: 200067b7 lui a5,0x20006 + 344a: 200066b7 lui a3,0x20006 + 344e: d7078713 addi a4,a5,-656 # 20005d70 + 3452: d8068613 addi a2,a3,-640 # 20005d80 + 3456: d607a823 sw zero,-656(a5) + 345a: 00072223 sw zero,4(a4) + 345e: 00072423 sw zero,8(a4) + 3462: 00072623 sw zero,12(a4) + 3466: cf10 sw a2,24(a4) + 3468: cf50 sw a2,28(a4) + 346a: 02072023 sw zero,32(a4) + 346e: 06070513 addi a0,a4,96 + 3472: d7078793 addi a5,a5,-656 + 3476: d8068693 addi a3,a3,-640 + 347a: 02000813 li a6,32 + 347e: 02072223 sw zero,36(a4) + 3482: 85be mv a1,a5 + 3484: 4601 li a2,0 + 3486: 08d5a223 sw a3,132(a1) + 348a: 0605 addi a2,a2,1 + 348c: 0591 addi a1,a1,4 + 348e: ff061ce3 bne a2,a6,3486 + 3492: 0711 addi a4,a4,4 + 3494: 08078793 addi a5,a5,128 + 3498: fea713e3 bne a4,a0,347e + 349c: 8082 ret + +0000349e : + 349e: 7741 lui a4,0xffff0 + 34a0: 8f69 and a4,a4,a0 + 34a2: 87aa mv a5,a0 + 34a4: 02000513 li a0,32 + 34a8: e319 bnez a4,34ae + 34aa: 07c2 slli a5,a5,0x10 + 34ac: 4541 li a0,16 + 34ae: ff000737 lui a4,0xff000 + 34b2: 8f7d and a4,a4,a5 + 34b4: e319 bnez a4,34ba + 34b6: 07a2 slli a5,a5,0x8 + 34b8: 1561 addi a0,a0,-8 + 34ba: f0000737 lui a4,0xf0000 + 34be: 8f7d and a4,a4,a5 + 34c0: e319 bnez a4,34c6 + 34c2: 0792 slli a5,a5,0x4 + 34c4: 1571 addi a0,a0,-4 + 34c6: c0000737 lui a4,0xc0000 + 34ca: 8f7d and a4,a4,a5 + 34cc: e319 bnez a4,34d2 + 34ce: 078a slli a5,a5,0x2 + 34d0: 1579 addi a0,a0,-2 + 34d2: 0007c363 bltz a5,34d8 + 34d6: 157d addi a0,a0,-1 + 34d8: 8082 ret + +000034da : + 34da: e7dfc2ef jal t0,356 <__riscv_save_0> + 34de: 07f00793 li a5,127 + 34e2: 1141 addi sp,sp,-16 + 34e4: 842a mv s0,a0 + 34e6: 00a7ea63 bltu a5,a0,34fa + 34ea: 40255413 srai s0,a0,0x2 + 34ee: 4501 li a0,0 + 34f0: c188 sw a0,0(a1) + 34f2: c200 sw s0,0(a2) + 34f4: 0141 addi sp,sp,16 + 34f6: e85fc06f j 37a <__riscv_restore_0> + 34fa: c632 sw a2,12(sp) + 34fc: c42e sw a1,8(sp) + 34fe: fa1ff0ef jal ra,349e + 3502: ffa50793 addi a5,a0,-6 + 3506: 40f45433 sra s0,s0,a5 + 350a: 02044413 xori s0,s0,32 + 350e: 1565 addi a0,a0,-7 + 3510: 4632 lw a2,12(sp) + 3512: 45a2 lw a1,8(sp) + 3514: bff1 j 34f0 + +00003516 : + 3516: e41fc2ef jal t0,356 <__riscv_save_0> + 351a: 842a mv s0,a0 + 351c: 4148 lw a0,4(a0) + 351e: 1141 addi sp,sp,-16 + 3520: 0070 addi a2,sp,12 + 3522: 002c addi a1,sp,8 + 3524: 9971 andi a0,a0,-4 + 3526: fb5ff0ef jal ra,34da + 352a: 46a2 lw a3,8(sp) + 352c: 45b2 lw a1,12(sp) + 352e: 20006737 lui a4,0x20006 + 3532: 00569793 slli a5,a3,0x5 + 3536: 97ae add a5,a5,a1 + 3538: 02078793 addi a5,a5,32 + 353c: d7070713 addi a4,a4,-656 # 20005d70 + 3540: 078a slli a5,a5,0x2 + 3542: 97ba add a5,a5,a4 + 3544: 43c8 lw a0,4(a5) + 3546: 20006637 lui a2,0x20006 + 354a: d8060613 addi a2,a2,-640 # 20005d80 + 354e: c408 sw a0,8(s0) + 3550: c450 sw a2,12(s0) + 3552: c540 sw s0,12(a0) + 3554: 5310 lw a2,32(a4) + 3556: c3c0 sw s0,4(a5) + 3558: 4785 li a5,1 + 355a: 00d79533 sll a0,a5,a3 + 355e: 06a1 addi a3,a3,8 + 3560: 8e49 or a2,a2,a0 + 3562: 068a slli a3,a3,0x2 + 3564: d310 sw a2,32(a4) + 3566: 9736 add a4,a4,a3 + 3568: 4354 lw a3,4(a4) + 356a: 00b797b3 sll a5,a5,a1 + 356e: 8fd5 or a5,a5,a3 + 3570: c35c sw a5,4(a4) + 3572: 0141 addi sp,sp,16 + 3574: e07fc06f j 37a <__riscv_restore_0> + +00003578 : + 3578: dc5fc2ef jal t0,33c <__riscv_save_4> + 357c: 20006437 lui s0,0x20006 + 3580: d7042683 lw a3,-656(s0) # 20005d70 + 3584: 478d li a5,3 + 3586: 06f68a63 beq a3,a5,35fa + 358a: d7040713 addi a4,s0,-656 + 358e: 4781 li a5,0 + 3590: d7040913 addi s2,s0,-656 + 3594: 04d7cd63 blt a5,a3,35ee + 3598: 15e1 addi a1,a1,-8 + 359a: 00357713 andi a4,a0,3 + 359e: 99f1 andi a1,a1,-4 + 35a0: 32000793 li a5,800 + 35a4: e331 bnez a4,35e8 + 35a6: 40000737 lui a4,0x40000 + 35aa: ff458693 addi a3,a1,-12 + 35ae: 1751 addi a4,a4,-12 + 35b0: 32100793 li a5,801 + 35b4: 02d76a63 bltu a4,a3,35e8 + 35b8: 0015e593 ori a1,a1,1 + 35bc: ffc50993 addi s3,a0,-4 + 35c0: c10c sw a1,0(a0) + 35c2: 84aa mv s1,a0 + 35c4: 854e mv a0,s3 + 35c6: f51ff0ef jal ra,3516 + 35ca: 854e mv a0,s3 + 35cc: e6bff0ef jal ra,3436 + 35d0: 4789 li a5,2 + 35d2: c15c sw a5,4(a0) + 35d4: d7042783 lw a5,-656(s0) + 35d8: 00178713 addi a4,a5,1 + 35dc: 078a slli a5,a5,0x2 + 35de: 97ca add a5,a5,s2 + 35e0: c3c4 sw s1,4(a5) + 35e2: d6e42823 sw a4,-656(s0) + 35e6: 4781 li a5,0 + 35e8: 853e mv a0,a5 + 35ea: d87fc06f j 370 <__riscv_restore_4> + 35ee: 0711 addi a4,a4,4 + 35f0: 4310 lw a2,0(a4) + 35f2: 00c50763 beq a0,a2,3600 + 35f6: 0785 addi a5,a5,1 + 35f8: bf71 j 3594 + 35fa: 32200793 li a5,802 + 35fe: b7ed j 35e8 + 3600: 32300793 li a5,803 + 3604: b7d5 j 35e8 + +00003606 : + 3606: d51fc2ef jal t0,356 <__riscv_save_0> + 360a: 1141 addi sp,sp,-16 + 360c: c62a sw a0,12(sp) + 360e: c42e sw a1,8(sp) + 3610: e37ff0ef jal ra,3446 + 3614: 45a2 lw a1,8(sp) + 3616: 4532 lw a0,12(sp) + 3618: f61ff0ef jal ra,3578 + 361c: 0141 addi sp,sp,16 + 361e: d5dfc06f j 37a <__riscv_restore_0> + +00003622 : + 3622: d1bfc2ef jal t0,33c <__riscv_save_4> + 3626: 4d5c lw a5,28(a0) + 3628: 4d18 lw a4,24(a0) + 362a: 4904 lw s1,16(a0) + 362c: 49a9 li s3,10 + 362e: c35c sw a5,4(a4) + 3630: c398 sw a4,0(a5) + 3632: 00052823 sw zero,16(a0) + 3636: 00050623 sb zero,12(a0) + 363a: 0584c903 lbu s2,88(s1) # 7ff40058 <_eusrstack+0x5ff30058> + 363e: 01390a63 beq s2,s3,3652 + 3642: 85ca mv a1,s2 + 3644: 8526 mv a0,s1 + 3646: 620000ef jal ra,3c66 + 364a: 05348c23 sb s3,88(s1) + 364e: d23fc06f j 370 <__riscv_restore_4> + 3652: 294c lbu a1,20(a0) + 3654: 0214c783 lbu a5,33(s1) + 3658: 842a mv s0,a0 + 365a: feb78ae3 beq a5,a1,364e + 365e: 8526 mv a0,s1 + 3660: 2519 jal 3c66 + 3662: 01240a23 sb s2,20(s0) + 3666: b7e5 j 364e + +00003668 : + 3668: ceffc2ef jal t0,356 <__riscv_save_0> + 366c: 842a mv s0,a0 + 366e: fb5ff0ef jal ra,3622 + 3672: 4591 li a1,4 + 3674: 00440513 addi a0,s0,4 + 3678: 287d jal 3736 + 367a: d01fc06f j 37a <__riscv_restore_0> + +0000367e : + 367e: 419c lw a5,0(a1) + 3680: fb878793 addi a5,a5,-72 + 3684: 04878713 addi a4,a5,72 + 3688: 00b71463 bne a4,a1,3690 + 368c: 872e mv a4,a1 + 368e: a039 j 369c + 3690: 02154603 lbu a2,33(a0) + 3694: 0217c683 lbu a3,33(a5) + 3698: 02d67163 bgeu a2,a3,36ba + 369c: 47f4 lw a3,76(a5) + 369e: 04850613 addi a2,a0,72 + 36a2: c7f0 sw a2,76(a5) + 36a4: c538 sw a4,72(a0) + 36a6: c574 sw a3,76(a0) + 36a8: c290 sw a2,0(a3) + 36aa: 02054783 lbu a5,32(a0) + 36ae: cd6c sw a1,92(a0) + 36b0: 0027e793 ori a5,a5,2 + 36b4: 02f50023 sb a5,32(a0) + 36b8: 8082 ret + 36ba: 47bc lw a5,72(a5) + 36bc: b7d1 j 3680 + +000036be : + 36be: 411c lw a5,0(a0) + 36c0: 00f50963 beq a0,a5,36d2 + 36c4: fb878713 addi a4,a5,-72 + 36c8: 4529 li a0,10 + 36ca: c709 beqz a4,36d4 + 36cc: fd97c503 lbu a0,-39(a5) + 36d0: 8082 ret + 36d2: 4529 li a0,10 + 36d4: 8082 ret + +000036d6 : + 36d6: 457c lw a5,76(a0) + 36d8: 4538 lw a4,72(a0) + 36da: c35c sw a5,4(a4) + 36dc: c398 sw a4,0(a5) + 36de: 02054783 lbu a5,32(a0) + 36e2: 04052e23 sw zero,92(a0) + 36e6: 9bf5 andi a5,a5,-3 + 36e8: 02f50023 sb a5,32(a0) + 36ec: 8082 ret + +000036ee : + 36ee: c69fc2ef jal t0,356 <__riscv_save_0> + 36f2: 4578 lw a4,76(a0) + 36f4: 4534 lw a3,72(a0) + 36f6: 4d6c lw a1,92(a0) + 36f8: c2d8 sw a4,4(a3) + 36fa: c314 sw a3,0(a4) + 36fc: f83ff0ef jal ra,367e + 3700: c7bfc06f j 37a <__riscv_restore_0> + +00003704 : + 3704: c53fc2ef jal t0,356 <__riscv_save_0> + 3708: 02054783 lbu a5,32(a0) + 370c: 842a mv s0,a0 + 370e: 8b89 andi a5,a5,2 + 3710: c781 beqz a5,3718 + 3712: d12c sw a1,96(a0) + 3714: fc3ff0ef jal ra,36d6 + 3718: 02044783 lbu a5,32(s0) + 371c: 8b85 andi a5,a5,1 + 371e: c781 beqz a5,3726 + 3720: 8522 mv a0,s0 + 3722: 72a000ef jal ra,3e4c + 3726: 02044783 lbu a5,32(s0) + 372a: 8b91 andi a5,a5,4 + 372c: e399 bnez a5,3732 + 372e: 8522 mv a0,s0 + 3730: 2215 jal 3854 + 3732: c49fc06f j 37a <__riscv_restore_0> + +00003736 : + 3736: c21fc2ef jal t0,356 <__riscv_save_0> + 373a: 411c lw a5,0(a0) + 373c: 84aa mv s1,a0 + 373e: 892e mv s2,a1 + 3740: 4380 lw s0,0(a5) + 3742: fb878513 addi a0,a5,-72 + 3746: fb840413 addi s0,s0,-72 + 374a: 04850793 addi a5,a0,72 + 374e: 00f49463 bne s1,a5,3756 + 3752: c29fc06f j 37a <__riscv_restore_0> + 3756: 85ca mv a1,s2 + 3758: fadff0ef jal ra,3704 + 375c: 443c lw a5,72(s0) + 375e: 8522 mv a0,s0 + 3760: fb878413 addi s0,a5,-72 + 3764: b7dd j 374a + +00003766 : + 3766: 00555793 srli a5,a0,0x5 + 376a: 07d1 addi a5,a5,20 + 376c: 20006737 lui a4,0x20006 + 3770: b1870713 addi a4,a4,-1256 # 20005b18 + 3774: 078a slli a5,a5,0x2 + 3776: 97ba add a5,a5,a4 + 3778: fff54613 not a2,a0 + 377c: 4685 li a3,1 + 377e: 00c696b3 sll a3,a3,a2 + 3782: 4390 lw a2,0(a5) + 3784: 8ed1 or a3,a3,a2 + 3786: c394 sw a3,0(a5) + 3788: 05474783 lbu a5,84(a4) + 378c: 00f57463 bgeu a0,a5,3794 + 3790: 04a70a23 sb a0,84(a4) + 3794: 8082 ret + +00003796 : + 3796: 200067b7 lui a5,0x20006 + 379a: b1878713 addi a4,a5,-1256 # 20005b18 + 379e: 05474783 lbu a5,84(a4) + 37a2: 078e slli a5,a5,0x3 + 37a4: 97ba add a5,a5,a4 + 37a6: 4388 lw a0,0(a5) + 37a8: fb850513 addi a0,a0,-72 + 37ac: 8082 ret + +000037ae : + 37ae: 20006737 lui a4,0x20006 + 37b2: b1870793 addi a5,a4,-1256 # 20005b18 + 37b6: 46a9 li a3,10 + 37b8: 04d78a23 sb a3,84(a5) + 37bc: b1870713 addi a4,a4,-1256 + 37c0: 05078693 addi a3,a5,80 + 37c4: c39c sw a5,0(a5) + 37c6: c3dc sw a5,4(a5) + 37c8: 07a1 addi a5,a5,8 + 37ca: fef69de3 bne a3,a5,37c4 + 37ce: 04072823 sw zero,80(a4) + 37d2: 8082 ret + +000037d4 : + 37d4: b69fc2ef jal t0,33c <__riscv_save_4> + 37d8: 892a mv s2,a0 + 37da: 02154503 lbu a0,33(a0) + 37de: 200067b7 lui a5,0x20006 + 37e2: b1878493 addi s1,a5,-1256 # 20005b18 + 37e6: 00351993 slli s3,a0,0x3 + 37ea: 94ce add s1,s1,s3 + 37ec: 4098 lw a4,0(s1) + 37ee: b1878413 addi s0,a5,-1256 + 37f2: 00e49463 bne s1,a4,37fa + 37f6: f71ff0ef jal ra,3766 + 37fa: 013407b3 add a5,s0,s3 + 37fe: 4394 lw a3,0(a5) + 3800: 04890713 addi a4,s2,72 + 3804: c2d8 sw a4,4(a3) + 3806: 04d92423 sw a3,72(s2) + 380a: 04992623 sw s1,76(s2) + 380e: c398 sw a4,0(a5) + 3810: b61fc06f j 370 <__riscv_restore_4> + +00003814 : + 3814: b29fc2ef jal t0,33c <__riscv_save_4> + 3818: 892a mv s2,a0 + 381a: 02154503 lbu a0,33(a0) + 381e: 200067b7 lui a5,0x20006 + 3822: b1878493 addi s1,a5,-1256 # 20005b18 + 3826: 00351993 slli s3,a0,0x3 + 382a: 94ce add s1,s1,s3 + 382c: 4098 lw a4,0(s1) + 382e: b1878413 addi s0,a5,-1256 + 3832: 00e49463 bne s1,a4,383a + 3836: f31ff0ef jal ra,3766 + 383a: 013407b3 add a5,s0,s3 + 383e: 43d8 lw a4,4(a5) + 3840: 04890693 addi a3,s2,72 + 3844: c3d4 sw a3,4(a5) + 3846: 04992423 sw s1,72(s2) + 384a: 04e92623 sw a4,76(s2) + 384e: c314 sw a3,0(a4) + 3850: b21fc06f j 370 <__riscv_restore_4> + +00003854 : + 3854: b03fc2ef jal t0,356 <__riscv_save_0> + 3858: 8541a783 lw a5,-1964(gp) # 20000234 + 385c: 02154703 lbu a4,33(a0) + 3860: 0217c783 lbu a5,33(a5) + 3864: 00f71663 bne a4,a5,3870 + 3868: fadff0ef jal ra,3814 + 386c: b0ffc06f j 37a <__riscv_restore_0> + 3870: f65ff0ef jal ra,37d4 + 3874: bfe5 j 386c + +00003876 : + 3876: ae1fc2ef jal t0,356 <__riscv_save_0> + 387a: 842a mv s0,a0 + 387c: 2a95 jal 39f0 + 387e: e925 bnez a0,38ee + 3880: 447c lw a5,76(s0) + 3882: 4438 lw a4,72(s0) + 3884: 02144603 lbu a2,33(s0) + 3888: 200064b7 lui s1,0x20006 + 388c: c35c sw a5,4(a4) + 388e: c398 sw a4,0(a5) + 3890: b1848713 addi a4,s1,-1256 # 20005b18 + 3894: 00361793 slli a5,a2,0x3 + 3898: 97ba add a5,a5,a4 + 389a: 4398 lw a4,0(a5) + 389c: b1848493 addi s1,s1,-1256 + 38a0: 02f71163 bne a4,a5,38c2 + 38a4: 00565793 srli a5,a2,0x5 + 38a8: 07d1 addi a5,a5,20 + 38aa: 078a slli a5,a5,0x2 + 38ac: 97a6 add a5,a5,s1 + 38ae: 4685 li a3,1 + 38b0: fff64713 not a4,a2 + 38b4: 00e69733 sll a4,a3,a4 + 38b8: 4394 lw a3,0(a5) + 38ba: fff74713 not a4,a4 + 38be: 8f75 and a4,a4,a3 + 38c0: c398 sw a4,0(a5) + 38c2: 0544c783 lbu a5,84(s1) + 38c6: 02c79463 bne a5,a2,38ee + 38ca: 200067b7 lui a5,0x20006 + 38ce: 4401 li s0,0 + 38d0: b6878793 addi a5,a5,-1176 # 20005b68 + 38d4: a031 j 38e0 + 38d6: 02040413 addi s0,s0,32 + 38da: 0ff47413 andi s0,s0,255 + 38de: 0791 addi a5,a5,4 + 38e0: 4388 lw a0,0(a5) + 38e2: d975 beqz a0,38d6 + 38e4: 0b7000ef jal ra,419a + 38e8: 9522 add a0,a0,s0 + 38ea: 04a48a23 sb a0,84(s1) + 38ee: a8dfc06f j 37a <__riscv_restore_0> + +000038f2 : + 38f2: a001 j 38f2 + +000038f4 : + 38f4: 85c1a703 lw a4,-1956(gp) # 2000023c + 38f8: 4785 li a5,1 + 38fa: 00f71b63 bne a4,a5,3910 + 38fe: 8581c783 lbu a5,-1960(gp) # 20000238 + 3902: 0f900693 li a3,249 + 3906: 00f6e563 bltu a3,a5,3910 + 390a: 0785 addi a5,a5,1 + 390c: 84f18c23 sb a5,-1960(gp) # 20000238 + 3910: 8082 ret + +00003912 : + 3912: 85c1a703 lw a4,-1956(gp) # 2000023c + 3916: 4785 li a5,1 + 3918: 04f71463 bne a4,a5,3960 + 391c: a3bfc2ef jal t0,356 <__riscv_save_0> + 3920: 798000ef jal ra,40b8 + 3924: 8581c783 lbu a5,-1960(gp) # 20000238 + 3928: 842a mv s0,a0 + 392a: e789 bnez a5,3934 + 392c: 798000ef jal ra,40c4 + 3930: a4bfc06f j 37a <__riscv_restore_0> + 3934: 17fd addi a5,a5,-1 + 3936: 0ff7f793 andi a5,a5,255 + 393a: 84f18c23 sb a5,-1960(gp) # 20000238 + 393e: f7fd bnez a5,392c + 3940: 8641c783 lbu a5,-1948(gp) # 20000244 + 3944: f7e5 bnez a5,392c + 3946: e51ff0ef jal ra,3796 + 394a: 86a1a023 sw a0,-1952(gp) # 20000240 + 394e: 8541a783 lw a5,-1964(gp) # 20000234 + 3952: 00f51463 bne a0,a5,395a + 3956: 8522 mv a0,s0 + 3958: bfd1 j 392c + 395a: 782000ef jal ra,40dc + 395e: bfe5 j 3956 + 3960: 8082 ret + +00003962 : + 3962: 9f5fc2ef jal t0,356 <__riscv_save_0> + 3966: 85c1a783 lw a5,-1956(gp) # 2000023c + 396a: 4485 li s1,1 + 396c: 1f500513 li a0,501 + 3970: 00978d63 beq a5,s1,398a + 3974: e23ff0ef jal ra,3796 + 3978: 86a1a023 sw a0,-1952(gp) # 20000240 + 397c: 84a1aa23 sw a0,-1964(gp) # 20000234 + 3980: 8491ae23 sw s1,-1956(gp) # 2000023c + 3984: 764000ef jal ra,40e8 + 3988: 4501 li a0,0 + 398a: 9f1fc06f j 37a <__riscv_restore_0> + +0000398e : + 398e: 85c1a503 lw a0,-1956(gp) # 2000023c + 3992: 157d addi a0,a0,-1 + 3994: 00153513 seqz a0,a0 + 3998: 8082 ret + +0000399a : + 399a: 85c1a703 lw a4,-1956(gp) # 2000023c + 399e: 4785 li a5,1 + 39a0: 02f71d63 bne a4,a5,39da + 39a4: 8581c783 lbu a5,-1960(gp) # 20000238 + 39a8: 8641c703 lbu a4,-1948(gp) # 20000244 + 39ac: 8fd9 or a5,a5,a4 + 39ae: e795 bnez a5,39da + 39b0: 9a7fc2ef jal t0,356 <__riscv_save_0> + 39b4: 704000ef jal ra,40b8 + 39b8: 842a mv s0,a0 + 39ba: dddff0ef jal ra,3796 + 39be: 86a1a023 sw a0,-1952(gp) # 20000240 + 39c2: 8541a783 lw a5,-1964(gp) # 20000234 + 39c6: 00f51763 bne a0,a5,39d4 + 39ca: 8522 mv a0,s0 + 39cc: 6f8000ef jal ra,40c4 + 39d0: 9abfc06f j 37a <__riscv_restore_0> + 39d4: 6fc000ef jal ra,40d0 + 39d8: bfcd j 39ca + 39da: 8082 ret + +000039dc : + 39dc: 8641c503 lbu a0,-1948(gp) # 20000244 + 39e0: 00a03533 snez a0,a0 + 39e4: 8082 ret + +000039e6 : + 39e6: 8581c503 lbu a0,-1960(gp) # 20000238 + 39ea: 00a03533 snez a0,a0 + 39ee: 8082 ret + +000039f0 : + 39f0: 200077b7 lui a5,0x20007 + 39f4: 9f878793 addi a5,a5,-1544 # 200069f8 + 39f8: 8d1d sub a0,a0,a5 + 39fa: 00153513 seqz a0,a0 + 39fe: 8082 ret + +00003a00 : + 3a00: 8541a783 lw a5,-1964(gp) # 20000234 + 3a04: 40a78533 sub a0,a5,a0 + 3a08: 00153513 seqz a0,a0 + 3a0c: 8082 ret + +00003a0e : + 3a0e: 949fc2ef jal t0,356 <__riscv_save_0> + 3a12: 8441a803 lw a6,-1980(gp) # 20000224 + 3a16: 8401a783 lw a5,-1984(gp) # 20000220 + 3a1a: 00004637 lui a2,0x4 + 3a1e: 0000c5b7 lui a1,0xc + 3a22: 20007537 lui a0,0x20007 + 3a26: 4881 li a7,0 + 3a28: 4725 li a4,9 + 3a2a: 4681 li a3,0 + 3a2c: 8f260613 addi a2,a2,-1806 # 38f2 + 3a30: 50858593 addi a1,a1,1288 # c508 <_exit+0x4f8> + 3a34: 9f850513 addi a0,a0,-1544 # 200069f8 + 3a38: 202d jal 3a62 + 3a3a: 941fc06f j 37a <__riscv_restore_0> + +00003a3e : + 3a3e: 919fc2ef jal t0,356 <__riscv_save_0> + 3a42: 6c6000ef jal ra,4108 + 3a46: d69ff0ef jal ra,37ae + 3a4a: 20007537 lui a0,0x20007 + 3a4e: 658d lui a1,0x3 + 3a50: a7050513 addi a0,a0,-1424 # 20006a70 + 3a54: bb3ff0ef jal ra,3606 + 3a58: e119 bnez a0,3a5e + 3a5a: fb5ff0ef jal ra,3a0e + 3a5e: 91dfc06f j 37a <__riscv_restore_0> + +00003a62 : + 3a62: 8dbfc2ef jal t0,33c <__riscv_save_4> + 3a66: 842a mv s0,a0 + 3a68: 8b2e mv s6,a1 + 3a6a: 8932 mv s2,a2 + 3a6c: 8ab6 mv s5,a3 + 3a6e: 84ba mv s1,a4 + 3a70: 89be mv s3,a5 + 3a72: 8a42 mv s4,a6 + 3a74: f73ff0ef jal ra,39e6 + 3a78: e969 bnez a0,3b4a + 3a7a: 44c00513 li a0,1100 + 3a7e: c85d beqz s0,3b34 + 3a80: 0a090a63 beqz s2,3b34 + 3a84: 0a098863 beqz s3,3b34 + 3a88: 07f00793 li a5,127 + 3a8c: 77400513 li a0,1908 + 3a90: 0b47f263 bgeu a5,s4,3b34 + 3a94: 47a5 li a5,9 + 3a96: 0af49163 bne s1,a5,3b38 + 3a9a: 8522 mv a0,s0 + 3a9c: f55ff0ef jal ra,39f0 + 3aa0: cd51 beqz a0,3b3c + 3aa2: 04040793 addi a5,s0,64 + 3aa6: c03c sw a5,64(s0) + 3aa8: c07c sw a5,68(s0) + 3aaa: 04840793 addi a5,s0,72 + 3aae: c43c sw a5,72(s0) + 3ab0: c47c sw a5,76(s0) + 3ab2: 05040793 addi a5,s0,80 + 3ab6: c83c sw a5,80(s0) + 3ab8: c87c sw a5,84(s0) + 3aba: 47a9 li a5,10 + 3abc: 04f40c23 sb a5,88(s0) + 3ac0: 8101a683 lw a3,-2032(gp) # 200001f0 + 3ac4: 02c40713 addi a4,s0,44 + 3ac8: 06042023 sw zero,96(s0) + 3acc: 04042e23 sw zero,92(s0) + 3ad0: 06042223 sw zero,100(s0) + 3ad4: 06042423 sw zero,104(s0) + 3ad8: c2d8 sw a4,4(a3) + 3ada: d454 sw a3,44(s0) + 3adc: 00004637 lui a2,0x4 + 3ae0: 81018693 addi a3,gp,-2032 # 200001f0 + 3ae4: 80e1a823 sw a4,-2032(gp) # 200001f0 + 3ae8: d814 sw a3,48(s0) + 3aea: 8752 mv a4,s4 + 3aec: 86ce mv a3,s3 + 3aee: c2e60613 addi a2,a2,-978 # 3c2e + 3af2: 85d6 mv a1,s5 + 3af4: 854a mv a0,s2 + 3af6: 64a000ef jal ra,4140 + 3afa: 463d li a2,15 + 3afc: 85da mv a1,s6 + 3afe: c008 sw a0,0(s0) + 3b00: 029400a3 sb s1,33(s0) + 3b04: 01242c23 sw s2,24(s0) + 3b08: 01542e23 sw s5,28(s0) + 3b0c: 03342223 sw s3,36(s0) + 3b10: 03442423 sw s4,40(s0) + 3b14: 00840513 addi a0,s0,8 + 3b18: 15e040ef jal ra,7c76 + 3b1c: 2b71 jal 40b8 + 3b1e: 84aa mv s1,a0 + 3b20: 02040023 sb zero,32(s0) + 3b24: 8522 mv a0,s0 + 3b26: cefff0ef jal ra,3814 + 3b2a: 8526 mv a0,s1 + 3b2c: 2b61 jal 40c4 + 3b2e: e61ff0ef jal ra,398e + 3b32: e901 bnez a0,3b42 + 3b34: 83dfc06f j 370 <__riscv_restore_4> + 3b38: f697f5e3 bgeu a5,s1,3aa2 + 3b3c: 76f00513 li a0,1903 + 3b40: bfd5 j 3b34 + 3b42: e59ff0ef jal ra,399a + 3b46: 4501 li a0,0 + 3b48: b7f5 j 3b34 + 3b4a: 19000513 li a0,400 + 3b4e: b7dd j 3b34 + +00003b50 : + 3b50: fecfc2ef jal t0,33c <__riscv_save_4> + 3b54: 842a mv s0,a0 + 3b56: e91ff0ef jal ra,39e6 + 3b5a: 19000793 li a5,400 + 3b5e: ed11 bnez a0,3b7a + 3b60: e019 bnez s0,3b66 + 3b62: 8541a403 lw s0,-1964(gp) # 20000234 + 3b66: 8522 mv a0,s0 + 3b68: e99ff0ef jal ra,3a00 + 3b6c: e911 bnez a0,3b80 + 3b6e: 8522 mv a0,s0 + 3b70: e81ff0ef jal ra,39f0 + 3b74: 76d00793 li a5,1901 + 3b78: c911 beqz a0,3b8c + 3b7a: 853e mv a0,a5 + 3b7c: ff4fc06f j 370 <__riscv_restore_4> + 3b80: e5dff0ef jal ra,39dc + 3b84: 6a400793 li a5,1700 + 3b88: d17d beqz a0,3b6e + 3b8a: bfc5 j 3b7a + 3b8c: 2335 jal 40b8 + 3b8e: 483c lw a5,80(s0) + 3b90: 05040913 addi s2,s0,80 + 3b94: 89aa mv s3,a0 + 3b96: 06f91d63 bne s2,a5,3c10 + 3b9a: 02044783 lbu a5,32(s0) + 3b9e: e781 bnez a5,3ba6 + 3ba0: 8522 mv a0,s0 + 3ba2: cd5ff0ef jal ra,3876 + 3ba6: 02044783 lbu a5,32(s0) + 3baa: 8b85 andi a5,a5,1 + 3bac: c399 beqz a5,3bb2 + 3bae: 8522 mv a0,s0 + 3bb0: 2c71 jal 3e4c + 3bb2: 02044783 lbu a5,32(s0) + 3bb6: 8b89 andi a5,a5,2 + 3bb8: c781 beqz a5,3bc0 + 3bba: 8522 mv a0,s0 + 3bbc: b1bff0ef jal ra,36d6 + 3bc0: 581c lw a5,48(s0) + 3bc2: 5458 lw a4,44(s0) + 3bc4: 854e mv a0,s3 + 3bc6: c35c sw a5,4(a4) + 3bc8: c398 sw a4,0(a5) + 3bca: 02c40793 addi a5,s0,44 + 3bce: d45c sw a5,44(s0) + 3bd0: d81c sw a5,48(s0) + 3bd2: 04040793 addi a5,s0,64 + 3bd6: c03c sw a5,64(s0) + 3bd8: c07c sw a5,68(s0) + 3bda: 04840793 addi a5,s0,72 + 3bde: c43c sw a5,72(s0) + 3be0: c47c sw a5,76(s0) + 3be2: 47a9 li a5,10 + 3be4: 04f40c23 sb a5,88(s0) + 3be8: 47a1 li a5,8 + 3bea: 02f40023 sb a5,32(s0) + 3bee: 05242823 sw s2,80(s0) + 3bf2: 05242a23 sw s2,84(s0) + 3bf6: 06042023 sw zero,96(s0) + 3bfa: 04042e23 sw zero,92(s0) + 3bfe: 06042223 sw zero,100(s0) + 3c02: 06042423 sw zero,104(s0) + 3c06: 297d jal 40c4 + 3c08: d93ff0ef jal ra,399a + 3c0c: 4781 li a5,0 + 3c0e: b7b5 j 3b7a + 3c10: 4384 lw s1,0(a5) + 3c12: fe878513 addi a0,a5,-24 + 3c16: 14a1 addi s1,s1,-24 + 3c18: 01850793 addi a5,a0,24 + 3c1c: f6f90fe3 beq s2,a5,3b9a + 3c20: a49ff0ef jal ra,3668 + 3c24: 4c9c lw a5,24(s1) + 3c26: 8526 mv a0,s1 + 3c28: fe878493 addi s1,a5,-24 + 3c2c: b7f5 j 3c18 + +00003c2e : + 3c2e: f28fc2ef jal t0,356 <__riscv_save_0> + 3c32: 4501 li a0,0 + 3c34: f1dff0ef jal ra,3b50 + 3c38: f42fc06f j 37a <__riscv_restore_0> + +00003c3c : + 3c3c: f1afc2ef jal t0,356 <__riscv_save_0> + 3c40: da7ff0ef jal ra,39e6 + 3c44: ed19 bnez a0,3c62 + 3c46: 298d jal 40b8 + 3c48: 84aa mv s1,a0 + 3c4a: 8541a503 lw a0,-1964(gp) # 20000234 + 3c4e: c29ff0ef jal ra,3876 + 3c52: 8541a503 lw a0,-1964(gp) # 20000234 + 3c56: bbfff0ef jal ra,3814 + 3c5a: 8526 mv a0,s1 + 3c5c: 21a5 jal 40c4 + 3c5e: d3dff0ef jal ra,399a + 3c62: f18fc06f j 37a <__riscv_restore_0> + +00003c66 : + 3c66: ed6fc2ef jal t0,33c <__riscv_save_4> + 3c6a: 842a mv s0,a0 + 3c6c: 89ae mv s3,a1 + 3c6e: d79ff0ef jal ra,39e6 + 3c72: e55d bnez a0,3d20 + 3c74: 44c00513 li a0,1100 + 3c78: c005 beqz s0,3c98 + 3c7a: 47a1 li a5,8 + 3c7c: 76f00513 li a0,1903 + 3c80: 0137ec63 bltu a5,s3,3c98 + 3c84: 2915 jal 40b8 + 3c86: 02144783 lbu a5,33(s0) + 3c8a: 8aaa mv s5,a0 + 3c8c: 01379863 bne a5,s3,3c9c + 3c90: 2915 jal 40c4 + 3c92: d09ff0ef jal ra,399a + 3c96: 4501 li a0,0 + 3c98: ed8fc06f j 370 <__riscv_restore_4> + 3c9c: 4824 lw s1,80(s0) + 3c9e: 05040a13 addi s4,s0,80 + 3ca2: 009a1f63 bne s4,s1,3cc0 + 3ca6: 894e mv s2,s3 + 3ca8: 02044783 lbu a5,32(s0) + 3cac: 0027f713 andi a4,a5,2 + 3cb0: c321 beqz a4,3cf0 + 3cb2: 032400a3 sb s2,33(s0) + 3cb6: 8522 mv a0,s0 + 3cb8: a37ff0ef jal ra,36ee + 3cbc: 8556 mv a0,s5 + 3cbe: bfc9 j 3c90 + 3cc0: 14a1 addi s1,s1,-24 + 3cc2: 4929 li s2,10 + 3cc4: 01848793 addi a5,s1,24 + 3cc8: 00fa1763 bne s4,a5,3cd6 + 3ccc: fd397de3 bgeu s2,s3,3ca6 + 3cd0: 05340c23 sb s3,88(s0) + 3cd4: bfd1 j 3ca8 + 3cd6: 00448513 addi a0,s1,4 + 3cda: 9e5ff0ef jal ra,36be + 3cde: 87aa mv a5,a0 + 3ce0: 00a97363 bgeu s2,a0,3ce6 + 3ce4: 87ca mv a5,s2 + 3ce6: 4c84 lw s1,24(s1) + 3ce8: 0ff7f913 andi s2,a5,255 + 3cec: 14a1 addi s1,s1,-24 + 3cee: bfd9 j 3cc4 + 3cf0: 0017f713 andi a4,a5,1 + 3cf4: c701 beqz a4,3cfc + 3cf6: 032400a3 sb s2,33(s0) + 3cfa: b7c9 j 3cbc + 3cfc: f3e1 bnez a5,3cbc + 3cfe: 8522 mv a0,s0 + 3d00: b77ff0ef jal ra,3876 + 3d04: 8522 mv a0,s0 + 3d06: 032400a3 sb s2,33(s0) + 3d0a: cf7ff0ef jal ra,3a00 + 3d0e: c509 beqz a0,3d18 + 3d10: 8522 mv a0,s0 + 3d12: ac3ff0ef jal ra,37d4 + 3d16: b75d j 3cbc + 3d18: 8522 mv a0,s0 + 3d1a: afbff0ef jal ra,3814 + 3d1e: bf79 j 3cbc + 3d20: 19000513 li a0,400 + 3d24: bf95 j 3c98 + +00003d26 : + 3d26: e16fc2ef jal t0,33c <__riscv_save_4> + 3d2a: 842a mv s0,a0 + 3d2c: 84ae mv s1,a1 + 3d2e: cb9ff0ef jal ra,39e6 + 3d32: 19000793 li a5,400 + 3d36: ed01 bnez a0,3d4e + 3d38: ca5ff0ef jal ra,39dc + 3d3c: 6a400793 li a5,1700 + 3d40: e519 bnez a0,3d4e + 3d42: 009467b3 or a5,s0,s1 + 3d46: e799 bnez a5,3d54 + 3d48: ef5ff0ef jal ra,3c3c + 3d4c: 4781 li a5,0 + 3d4e: 853e mv a0,a5 + 3d50: e20fc06f j 370 <__riscv_restore_4> + 3d54: 57fd li a5,-1 + 3d56: 00f41663 bne s0,a5,3d62 + 3d5a: 06500793 li a5,101 + 3d5e: fe8488e3 beq s1,s0,3d4e + 3d62: 2e99 jal 40b8 + 3d64: 89aa mv s3,a0 + 3d66: 8541a503 lw a0,-1964(gp) # 20000234 + 3d6a: 85a2 mv a1,s0 + 3d6c: 8626 mv a2,s1 + 3d6e: 2811 jal 3d82 + 3d70: 8541a503 lw a0,-1964(gp) # 20000234 + 3d74: b03ff0ef jal ra,3876 + 3d78: 854e mv a0,s3 + 3d7a: 26a9 jal 40c4 + 3d7c: c1fff0ef jal ra,399a + 3d80: b7f1 j 3d4c + +00003d82 : + 3d82: dd4fc2ef jal t0,356 <__riscv_save_0> + 3d86: 1141 addi sp,sp,-16 + 3d88: 842a mv s0,a0 + 3d8a: c62e sw a1,12(sp) + 3d8c: c432 sw a2,8(sp) + 3d8e: 262d jal 40b8 + 3d90: 8181a783 lw a5,-2024(gp) # 200001f8 + 3d94: 45b2 lw a1,12(sp) + 3d96: 4622 lw a2,8(sp) + 3d98: fc078793 addi a5,a5,-64 + 3d9c: dc0c sw a1,56(s0) + 3d9e: dc50 sw a2,60(s0) + 3da0: 4681 li a3,0 + 3da2: 4701 li a4,0 + 3da4: 81818313 addi t1,gp,-2024 # 200001f8 + 3da8: 04078e13 addi t3,a5,64 + 3dac: 066e1163 bne t3,t1,3e0e + 3db0: 40d588b3 sub a7,a1,a3 + 3db4: 0115beb3 sltu t4,a1,a7 + 3db8: 40e60833 sub a6,a2,a4 + 3dbc: 41d80833 sub a6,a6,t4 + 3dc0: 03142c23 sw a7,56(s0) + 3dc4: 03042e23 sw a6,60(s0) + 3dc8: 026e0163 beq t3,t1,3dea + 3dcc: 40b685b3 sub a1,a3,a1 + 3dd0: 00b6b6b3 sltu a3,a3,a1 + 3dd4: 8f11 sub a4,a4,a2 + 3dd6: 8f15 sub a4,a4,a3 + 3dd8: 5f94 lw a3,56(a5) + 3dda: 5fd0 lw a2,60(a5) + 3ddc: 95b6 add a1,a1,a3 + 3dde: 00d5b6b3 sltu a3,a1,a3 + 3de2: 9732 add a4,a4,a2 + 3de4: 9736 add a4,a4,a3 + 3de6: df8c sw a1,56(a5) + 3de8: dfd8 sw a4,60(a5) + 3dea: 43f8 lw a4,68(a5) + 3dec: 04040693 addi a3,s0,64 + 3df0: c3f4 sw a3,68(a5) + 3df2: 05c42023 sw t3,64(s0) + 3df6: c078 sw a4,68(s0) + 3df8: c314 sw a3,0(a4) + 3dfa: 24e9 jal 40c4 + 3dfc: 02044783 lbu a5,32(s0) + 3e00: 0017e793 ori a5,a5,1 + 3e04: 02f40023 sb a5,32(s0) + 3e08: 0141 addi sp,sp,16 + 3e0a: d70fc06f j 37a <__riscv_restore_0> + 3e0e: 0387a883 lw a7,56(a5) + 3e12: 03c7ae83 lw t4,60(a5) + 3e16: 98b6 add a7,a7,a3 + 3e18: 00d8b833 sltu a6,a7,a3 + 3e1c: 9eba add t4,t4,a4 + 3e1e: 9876 add a6,a6,t4 + 3e20: f90668e3 bltu a2,a6,3db0 + 3e24: 00c81463 bne a6,a2,3e2c + 3e28: f915e4e3 bltu a1,a7,3db0 + 3e2c: 01159a63 bne a1,a7,3e40 + 3e30: 01061863 bne a2,a6,3e40 + 3e34: 02144f03 lbu t5,33(s0) + 3e38: 0217ce83 lbu t4,33(a5) + 3e3c: f7df6ae3 bltu t5,t4,3db0 + 3e40: 43bc lw a5,64(a5) + 3e42: 86c6 mv a3,a7 + 3e44: 8742 mv a4,a6 + 3e46: fc078793 addi a5,a5,-64 + 3e4a: bfb9 j 3da8 + +00003e4c : + 3e4c: d0afc2ef jal t0,356 <__riscv_save_0> + 3e50: 842a mv s0,a0 + 3e52: 249d jal 40b8 + 3e54: 403c lw a5,64(s0) + 3e56: 04040713 addi a4,s0,64 + 3e5a: 04e78863 beq a5,a4,3eaa + 3e5e: fc078713 addi a4,a5,-64 + 3e62: c721 beqz a4,3eaa + 3e64: 81818713 addi a4,gp,-2024 # 200001f8 + 3e68: 04e78163 beq a5,a4,3eaa + 3e6c: 5c14 lw a3,56(s0) + 3e6e: 03c42883 lw a7,60(s0) + 3e72: 55f9 li a1,-2 + 3e74: 40d58333 sub t1,a1,a3 + 3e78: ffc7a603 lw a2,-4(a5) + 3e7c: 0065b833 sltu a6,a1,t1 + 3e80: fff8c593 not a1,a7 + 3e84: 410585b3 sub a1,a1,a6 + 3e88: ff87a703 lw a4,-8(a5) + 3e8c: 02c5ea63 bltu a1,a2,3ec0 + 3e90: 00b61463 bne a2,a1,3e98 + 3e94: 02e36663 bltu t1,a4,3ec0 + 3e98: 96ba add a3,a3,a4 + 3e9a: 00e6b733 sltu a4,a3,a4 + 3e9e: 9646 add a2,a2,a7 + 3ea0: 9732 add a4,a4,a2 + 3ea2: fed7ac23 sw a3,-8(a5) + 3ea6: fee7ae23 sw a4,-4(a5) + 3eaa: 4078 lw a4,68(s0) + 3eac: c3d8 sw a4,4(a5) + 3eae: c31c sw a5,0(a4) + 3eb0: 2c11 jal 40c4 + 3eb2: 02044783 lbu a5,32(s0) + 3eb6: 9bf9 andi a5,a5,-2 + 3eb8: 02f40023 sb a5,32(s0) + 3ebc: cbefc06f j 37a <__riscv_restore_0> + 3ec0: 5679 li a2,-2 + 3ec2: 56fd li a3,-1 + 3ec4: fec7ac23 sw a2,-8(a5) + 3ec8: fed7ae23 sw a3,-4(a5) + 3ecc: bff9 j 3eaa + +00003ece : + 3ece: c88fc2ef jal t0,356 <__riscv_save_0> + 3ed2: 1141 addi sp,sp,-16 + 3ed4: 842a mv s0,a0 + 3ed6: c62e sw a1,12(sp) + 3ed8: 22c5 jal 40b8 + 3eda: 8681a783 lw a5,-1944(gp) # 20000248 + 3ede: 86c1a683 lw a3,-1940(gp) # 2000024c + 3ee2: 45b2 lw a1,12(sp) + 3ee4: 00878633 add a2,a5,s0 + 3ee8: 00f637b3 sltu a5,a2,a5 + 3eec: 96ae add a3,a3,a1 + 3eee: 97b6 add a5,a5,a3 + 3ef0: 86f1a623 sw a5,-1940(gp) # 2000024c + 3ef4: 8181a783 lw a5,-2024(gp) # 200001f8 + 3ef8: 86c1a423 sw a2,-1944(gp) # 20000248 + 3efc: 81818493 addi s1,gp,-2024 # 200001f8 + 3f00: 00979663 bne a5,s1,3f0c + 3f04: 22c1 jal 40c4 + 3f06: 0141 addi sp,sp,16 + 3f08: c72fc06f j 37a <__riscv_restore_0> + 3f0c: ffc7a703 lw a4,-4(a5) + 3f10: 892a mv s2,a0 + 3f12: ff87a683 lw a3,-8(a5) + 3f16: fc078513 addi a0,a5,-64 + 3f1a: 02e5ef63 bltu a1,a4,3f58 + 3f1e: 00b71463 bne a4,a1,3f26 + 3f22: 02d46b63 bltu s0,a3,3f58 + 3f26: 4380 lw s0,0(a5) + 3f28: 4681 li a3,0 + 3f2a: 4701 li a4,0 + 3f2c: fed7ac23 sw a3,-8(a5) + 3f30: fee7ae23 sw a4,-4(a5) + 3f34: fc040413 addi s0,s0,-64 + 3f38: 04050793 addi a5,a0,64 + 3f3c: 02978863 beq a5,s1,3f6c + 3f40: 5d1c lw a5,56(a0) + 3f42: 5d58 lw a4,60(a0) + 3f44: 8fd9 or a5,a5,a4 + 3f46: e39d bnez a5,3f6c + 3f48: 4589 li a1,2 + 3f4a: fbaff0ef jal ra,3704 + 3f4e: 403c lw a5,64(s0) + 3f50: 8522 mv a0,s0 + 3f52: fc078413 addi s0,a5,-64 + 3f56: b7cd j 3f38 + 3f58: 40868433 sub s0,a3,s0 + 3f5c: 0086b6b3 sltu a3,a3,s0 + 3f60: 8f0d sub a4,a4,a1 + 3f62: 8f15 sub a4,a4,a3 + 3f64: fe87ac23 sw s0,-8(a5) + 3f68: fee7ae23 sw a4,-4(a5) + 3f6c: 854a mv a0,s2 + 3f6e: bf59 j 3f04 + +00003f70 : + 3f70: be6fc2ef jal t0,356 <__riscv_save_0> + 3f74: a1bff0ef jal ra,398e + 3f78: c509 beqz a0,3f82 + 3f7a: 4505 li a0,1 + 3f7c: 4581 li a1,0 + 3f7e: f51ff0ef jal ra,3ece + 3f82: bf8fc06f j 37a <__riscv_restore_0> + +00003f86 : + 3f86: 6521 lui a0,0x8 + 3f88: 80050513 addi a0,a0,-2048 # 7800 <_scanf_float+0x2da> + 3f8c: 30051573 csrrw a0,mstatus,a0 + 3f90: 8082 ret + +00003f92 : + 3f92: 30051073 csrw mstatus,a0 + 3f96: 8082 ret + +00003f98 : + 3f98: e000f737 lui a4,0xe000f + 3f9c: 431c lw a5,0(a4) + 3f9e: 0786 slli a5,a5,0x1 + 3fa0: 8385 srli a5,a5,0x1 + 3fa2: c31c sw a5,0(a4) + 3fa4: 8082 ret + +00003fa6 : + 3fa6: e000f737 lui a4,0xe000f + 3faa: 431c lw a5,0(a4) + 3fac: 800006b7 lui a3,0x80000 + 3fb0: 8fd5 or a5,a5,a3 + 3fb2: c31c sw a5,0(a4) + 3fb4: 8082 ret + +00003fb6 : + 3fb6: ba0fc2ef jal t0,356 <__riscv_save_0> + 3fba: fedff0ef jal ra,3fa6 + 3fbe: bbcfc06f j 37a <__riscv_restore_0> + +00003fc2 : + 3fc2: e000f7b7 lui a5,0xe000f + 3fc6: 0007a023 sw zero,0(a5) # e000f000 <_eusrstack+0xbffff000> + 3fca: 0007a223 sw zero,4(a5) + 3fce: 4681 li a3,0 + 3fd0: c794 sw a3,8(a5) + 3fd2: 4701 li a4,0 + 3fd4: c7d8 sw a4,12(a5) + 3fd6: fff50613 addi a2,a0,-1 + 3fda: cb90 sw a2,16(a5) + 3fdc: 4681 li a3,0 + 3fde: cbd4 sw a3,20(a5) + 3fe0: 473d li a4,15 + 3fe2: c398 sw a4,0(a5) + 3fe4: 8082 ret + +00003fe6 : + 3fe6: 0ff57513 andi a0,a0,255 + 3fea: e000e7b7 lui a5,0xe000e + 3fee: 40a78623 sb a0,1036(a5) # e000e40c <_eusrstack+0xbfffe40c> + 3ff2: 8082 ret + +00003ff4 : + 3ff4: e000e7b7 lui a5,0xe000e + 3ff8: 5741 li a4,-16 + 3ffa: 40e78723 sb a4,1038(a5) # e000e40e <_eusrstack+0xbfffe40e> + 3ffe: 6705 lui a4,0x1 + 4000: 10e7a023 sw a4,256(a5) + 4004: 6711 lui a4,0x4 + 4006: 10e7a023 sw a4,256(a5) + 400a: 8082 ret + +0000400c : + 400c: 7119 addi sp,sp,-128 + 400e: fe82 fsw ft0,124(sp) + 4010: fc86 fsw ft1,120(sp) + 4012: fa8a fsw ft2,116(sp) + 4014: f88e fsw ft3,112(sp) + 4016: f692 fsw ft4,108(sp) + 4018: f496 fsw ft5,104(sp) + 401a: f29a fsw ft6,100(sp) + 401c: f09e fsw ft7,96(sp) + 401e: eea2 fsw fs0,92(sp) + 4020: eca6 fsw fs1,88(sp) + 4022: eaaa fsw fa0,84(sp) + 4024: e8ae fsw fa1,80(sp) + 4026: e6b2 fsw fa2,76(sp) + 4028: e4b6 fsw fa3,72(sp) + 402a: e2ba fsw fa4,68(sp) + 402c: e0be fsw fa5,64(sp) + 402e: fe42 fsw fa6,60(sp) + 4030: fc46 fsw fa7,56(sp) + 4032: fa4a fsw fs2,52(sp) + 4034: f84e fsw fs3,48(sp) + 4036: f652 fsw fs4,44(sp) + 4038: f456 fsw fs5,40(sp) + 403a: f25a fsw fs6,36(sp) + 403c: f05e fsw fs7,32(sp) + 403e: ee62 fsw fs8,28(sp) + 4040: ec66 fsw fs9,24(sp) + 4042: ea6a fsw fs10,20(sp) + 4044: e86e fsw fs11,16(sp) + 4046: e672 fsw ft8,12(sp) + 4048: e476 fsw ft9,8(sp) + 404a: e27a fsw ft10,4(sp) + 404c: e07e fsw ft11,0(sp) + 404e: 828a mv t0,sp + 4050: 8201a103 lw sp,-2016(gp) # 20000200 + 4054: c016 sw t0,0(sp) + 4056: 939ff0ef jal ra,398e + 405a: c919 beqz a0,4070 + 405c: 899ff0ef jal ra,38f4 + 4060: e000f7b7 lui a5,0xe000f + 4064: 0007a223 sw zero,4(a5) # e000f004 <_eusrstack+0xbffff004> + 4068: f09ff0ef jal ra,3f70 + 406c: 8a7ff0ef jal ra,3912 + 4070: 4102 lw sp,0(sp) + 4072: 7076 flw ft0,124(sp) + 4074: 70e6 flw ft1,120(sp) + 4076: 7156 flw ft2,116(sp) + 4078: 71c6 flw ft3,112(sp) + 407a: 7236 flw ft4,108(sp) + 407c: 72a6 flw ft5,104(sp) + 407e: 7316 flw ft6,100(sp) + 4080: 7386 flw ft7,96(sp) + 4082: 6476 flw fs0,92(sp) + 4084: 64e6 flw fs1,88(sp) + 4086: 6556 flw fa0,84(sp) + 4088: 65c6 flw fa1,80(sp) + 408a: 6636 flw fa2,76(sp) + 408c: 66a6 flw fa3,72(sp) + 408e: 6716 flw fa4,68(sp) + 4090: 6786 flw fa5,64(sp) + 4092: 7872 flw fa6,60(sp) + 4094: 78e2 flw fa7,56(sp) + 4096: 7952 flw fs2,52(sp) + 4098: 79c2 flw fs3,48(sp) + 409a: 7a32 flw fs4,44(sp) + 409c: 7aa2 flw fs5,40(sp) + 409e: 7b12 flw fs6,36(sp) + 40a0: 7b82 flw fs7,32(sp) + 40a2: 6c72 flw fs8,28(sp) + 40a4: 6ce2 flw fs9,24(sp) + 40a6: 6d52 flw fs10,20(sp) + 40a8: 6dc2 flw fs11,16(sp) + 40aa: 6e32 flw ft8,12(sp) + 40ac: 6ea2 flw ft9,8(sp) + 40ae: 6f12 flw ft10,4(sp) + 40b0: 6f82 flw ft11,0(sp) + 40b2: 6109 addi sp,sp,128 + 40b4: 30200073 mret + +000040b8 : + 40b8: a9efc2ef jal t0,356 <__riscv_save_0> + 40bc: ecbff0ef jal ra,3f86 + 40c0: abafc06f j 37a <__riscv_restore_0> + +000040c4 : + 40c4: a92fc2ef jal t0,356 <__riscv_save_0> + 40c8: ecbff0ef jal ra,3f92 + 40cc: aaefc06f j 37a <__riscv_restore_0> + +000040d0 : + 40d0: a86fc2ef jal t0,356 <__riscv_save_0> + 40d4: ed3ff0ef jal ra,3fa6 + 40d8: aa2fc06f j 37a <__riscv_restore_0> + +000040dc : + 40dc: a7afc2ef jal t0,356 <__riscv_save_0> + 40e0: ed7ff0ef jal ra,3fb6 + 40e4: a96fc06f j 37a <__riscv_restore_0> + +000040e8 : + 40e8: a6efc2ef jal t0,356 <__riscv_save_0> + 40ec: 914fc0ef jal ra,200 + +000040f0 : + 40f0: a66fc2ef jal t0,356 <__riscv_save_0> + 40f4: 842a mv s0,a0 + 40f6: 0f000513 li a0,240 + 40fa: eedff0ef jal ra,3fe6 + 40fe: 8522 mv a0,s0 + 4100: ec3ff0ef jal ra,3fc2 + 4104: a76fc06f j 37a <__riscv_restore_0> + +00004108 : + 4108: a4efc2ef jal t0,356 <__riscv_save_0> + 410c: 82018713 addi a4,gp,-2016 # 20000200 + 4110: 431c lw a5,0(a4) + 4112: 4581 li a1,0 + 4114: 17f1 addi a5,a5,-4 + 4116: 9bf1 andi a5,a5,-4 + 4118: c31c sw a5,0(a4) + 411a: 200007b7 lui a5,0x20000 + 411e: 1e87a603 lw a2,488(a5) # 200001e8 + 4122: 80c1a683 lw a3,-2036(gp) # 200001ec + 4126: 200007b7 lui a5,0x20000 + 412a: 1e07a503 lw a0,480(a5) # 200001e0 + 412e: 2349 jal 46b0 <__udivdi3> + 4130: 84a1a823 sw a0,-1968(gp) # 20000230 <_edata> + 4134: fbdff0ef jal ra,40f0 + 4138: ebdff0ef jal ra,3ff4 + 413c: a3efc06f j 37a <__riscv_restore_0> + +00004140 : + 4140: 9736 add a4,a4,a3 + 4142: 9b71 andi a4,a4,-4 + 4144: aceae8b7 lui a7,0xaceae + 4148: 8e2a mv t3,a0 + 414a: f8470813 addi a6,a4,-124 # 3f84 + 414e: f8070513 addi a0,a4,-128 + 4152: 4685 li a3,1 + 4154: 4329 li t1,10 + 4156: d0088893 addi a7,a7,-768 # aceadd00 <_eusrstack+0x8ce9dd00> + 415a: 02000e93 li t4,32 + 415e: 0266c7b3 div a5,a3,t1 + 4162: 0811 addi a6,a6,4 + 4164: 0266ef33 rem t5,a3,t1 + 4168: 0792 slli a5,a5,0x4 + 416a: 0685 addi a3,a3,1 + 416c: 01e7e7b3 or a5,a5,t5 + 4170: 0117e7b3 or a5,a5,a7 + 4174: fef82e23 sw a5,-4(a6) + 4178: ffd693e3 bne a3,t4,415e + 417c: 878e mv a5,gp + 417e: f8f72623 sw a5,-116(a4) + 4182: 67a1 lui a5,0x8 + 4184: 88078793 addi a5,a5,-1920 # 7880 <_scanf_float+0x35a> + 4188: fab72423 sw a1,-88(a4) + 418c: f8c72423 sw a2,-120(a4) + 4190: f8f72223 sw a5,-124(a4) + 4194: f9c72023 sw t3,-128(a4) + 4198: 8082 ret + +0000419a : + 419a: 7741 lui a4,0xffff0 + 419c: 8f69 and a4,a4,a0 + 419e: 87aa mv a5,a0 + 41a0: 4501 li a0,0 + 41a2: e319 bnez a4,41a8 + 41a4: 07c2 slli a5,a5,0x10 + 41a6: 4541 li a0,16 + 41a8: ff000737 lui a4,0xff000 + 41ac: 8f7d and a4,a4,a5 + 41ae: e319 bnez a4,41b4 + 41b0: 07a2 slli a5,a5,0x8 + 41b2: 0521 addi a0,a0,8 + 41b4: f0000737 lui a4,0xf0000 + 41b8: 8f7d and a4,a4,a5 + 41ba: e319 bnez a4,41c0 + 41bc: 0792 slli a5,a5,0x4 + 41be: 0511 addi a0,a0,4 + 41c0: c0000737 lui a4,0xc0000 + 41c4: 8f7d and a4,a4,a5 + 41c6: e319 bnez a4,41cc + 41c8: 078a slli a5,a5,0x2 + 41ca: 0509 addi a0,a0,2 + 41cc: 0007c663 bltz a5,41d8 + 41d0: c399 beqz a5,41d6 + 41d2: 0505 addi a0,a0,1 + 41d4: 8082 ret + 41d6: 0509 addi a0,a0,2 + 41d8: 8082 ret + 41da: a001 j 41da + 41dc: a001 j 41dc + +000041de : + 41de: a001 j 41de + +000041e0 : + 41e0: a001 j 41e0 + +000041e2 : + 41e2: a001 j 41e2 + 41e4: a001 j 41e4 + 41e6: a001 j 41e6 + +000041e8 : + 41e8: a001 j 41e8 + +000041ea : + 41ea: a001 j 41ea + +000041ec : + 41ec: a001 j 41ec + +000041ee : + 41ee: a001 j 41ee + +000041f0 : + 41f0: a001 j 41f0 + +000041f2 : + 41f2: a001 j 41f2 + +000041f4 : + 41f4: a001 j 41f4 + +000041f6 : + 41f6: a001 j 41f6 + +000041f8 : + 41f8: a001 j 41f8 + +000041fa : + 41fa: a001 j 41fa + +000041fc : + 41fc: a001 j 41fc + +000041fe : + 41fe: a001 j 41fe + +00004200 : + 4200: a001 j 4200 + +00004202 : + 4202: a001 j 4202 + +00004204 : + 4204: a001 j 4204 + +00004206 : + 4206: a001 j 4206 + +00004208 : + 4208: a001 j 4208 + +0000420a : + 420a: a001 j 420a + +0000420c : + 420c: a001 j 420c + +0000420e : + 420e: a001 j 420e + +00004210 : + 4210: a001 j 4210 + +00004212 : + 4212: a001 j 4212 + +00004214 : + 4214: a001 j 4214 + +00004216 : + 4216: a001 j 4216 + +00004218 : + 4218: a001 j 4218 + +0000421a : + 421a: a001 j 421a + +0000421c : + 421c: a001 j 421c + +0000421e : + 421e: a001 j 421e + +00004220 : + 4220: a001 j 4220 + +00004222 : + 4222: a001 j 4222 + +00004224 : + 4224: a001 j 4224 + +00004226 : + 4226: a001 j 4226 + +00004228 : + 4228: a001 j 4228 + +0000422a : + 422a: a001 j 422a + +0000422c : + 422c: a001 j 422c + +0000422e : + 422e: a001 j 422e + +00004230 : + 4230: a001 j 4230 + +00004232 : + 4232: a001 j 4232 + +00004234 : + 4234: a001 j 4234 + +00004236 : + 4236: a001 j 4236 + +00004238 : + 4238: a001 j 4238 + +0000423a : + 423a: a001 j 423a + +0000423c : + 423c: a001 j 423c + +0000423e : + 423e: a001 j 423e + +00004240 : + 4240: a001 j 4240 + +00004242 : + 4242: a001 j 4242 + +00004244 : + 4244: a001 j 4244 + +00004246 : + 4246: a001 j 4246 + +00004248 : + 4248: a001 j 4248 + +0000424a : + 424a: a001 j 424a + +0000424c : + 424c: a001 j 424c + +0000424e : + 424e: a001 j 424e + +00004250 : + 4250: a001 j 4250 + +00004252 : + 4252: a001 j 4252 + +00004254 : + 4254: a001 j 4254 + +00004256 : + 4256: a001 j 4256 + +00004258 : + 4258: a001 j 4258 + +0000425a : + 425a: a001 j 425a + +0000425c : + 425c: a001 j 425c + +0000425e : + 425e: a001 j 425e + +00004260 : + 4260: a001 j 4260 + +00004262 : + 4262: a001 j 4262 + +00004264 : + 4264: a001 j 4264 + +00004266 : + 4266: a001 j 4266 + +00004268 : + 4268: a001 j 4268 + +0000426a : + 426a: a001 j 426a + +0000426c : + 426c: a001 j 426c + +0000426e : + 426e: a001 j 426e + +00004270 : + 4270: a001 j 4270 + +00004272 : + 4272: a001 j 4272 + +00004274 : + 4274: a001 j 4274 + +00004276 : + 4276: a001 j 4276 + +00004278 : + 4278: a001 j 4278 + +0000427a : + 427a: a001 j 427a + +0000427c : + 427c: a001 j 427c + +0000427e : + 427e: a001 j 427e + +00004280 : + 4280: a001 j 4280 + +00004282 : + 4282: a001 j 4282 + +00004284 : + 4284: a001 j 4284 + +00004286 : + 4286: a001 j 4286 + +00004288 : + 4288: a001 j 4288 + +0000428a : + 428a: a001 j 428a + +0000428c : + 428c: a001 j 428c + +0000428e : + 428e: a001 j 428e + +00004290 : + 4290: a001 j 4290 + +00004292 : + 4292: a001 j 4292 + +00004294 : + 4294: a001 j 4294 + +00004296 : + 4296: a001 j 4296 + +00004298 : + 4298: 1fffc197 auipc gp,0x1fffc + 429c: 74818193 addi gp,gp,1864 # 200009e0 <__global_pointer$> + 42a0: 2000c117 auipc sp,0x2000c + 42a4: d6010113 addi sp,sp,-672 # 20010000 <_eusrstack> + 42a8: 00008517 auipc a0,0x8 + 42ac: 7f050513 addi a0,a0,2032 # ca98 <_data_lma> + 42b0: 1fffc597 auipc a1,0x1fffc + 42b4: d5058593 addi a1,a1,-688 # 20000000 <_data_vma> + 42b8: 85018613 addi a2,gp,-1968 # 20000230 <_edata> + 42bc: 00c5fa63 bgeu a1,a2,42d0 + 42c0: 00052283 lw t0,0(a0) + 42c4: 0055a023 sw t0,0(a1) + 42c8: 0511 addi a0,a0,4 + 42ca: 0591 addi a1,a1,4 + 42cc: fec5eae3 bltu a1,a2,42c0 + 42d0: 85018513 addi a0,gp,-1968 # 20000230 <_edata> + 42d4: 20006597 auipc a1,0x20006 + 42d8: 9a058593 addi a1,a1,-1632 # 20009c74 <_ebss> + 42dc: 00b57763 bgeu a0,a1,42ea + 42e0: 00052023 sw zero,0(a0) + 42e4: 0511 addi a0,a0,4 + 42e6: feb56de3 bltu a0,a1,42e0 + 42ea: 42fd li t0,31 + 42ec: bc029073 csrw 0xbc0,t0 + 42f0: 42fd li t0,31 + 42f2: 80429073 csrw 0x804,t0 + 42f6: 000082b7 lui t0,0x8 + 42fa: 80028293 addi t0,t0,-2048 # 7800 <_scanf_float+0x2da> + 42fe: 3002a073 csrs mstatus,t0 + 4302: ffffc297 auipc t0,0xffffc + 4306: d3628293 addi t0,t0,-714 # 38 <_einit> + 430a: 0032e293 ori t0,t0,3 + 430e: 30529073 csrw mtvec,t0 + 4312: aa8fc0ef jal ra,5ba + 4316: ffffc297 auipc t0,0xffffc + 431a: 1f828293 addi t0,t0,504 # 50e
+ 431e: 34129073 csrw mepc,t0 + 4322: 30200073 mret + +00004326 : + 4326: 459c lw a5,8(a1) + 4328: 0107f713 andi a4,a5,16 + 432c: 00f7f813 andi a6,a5,15 + 4330: c701 beqz a4,4338 + 4332: 41d8 lw a4,4(a1) + 4334: 00e86833 or a6,a6,a4 + 4338: 218e lhu a1,0(a1) + 433a: 0ff5f713 andi a4,a1,255 + 433e: c339 beqz a4,4384 + 4340: 4118 lw a4,0(a0) + 4342: 4681 li a3,0 + 4344: 4e85 li t4,1 + 4346: 4f3d li t5,15 + 4348: 02800f93 li t6,40 + 434c: 04800293 li t0,72 + 4350: 4e21 li t3,8 + 4352: 00de9633 sll a2,t4,a3 + 4356: 00c5f8b3 and a7,a1,a2 + 435a: 03161163 bne a2,a7,437c + 435e: 00269893 slli a7,a3,0x2 + 4362: 011f1333 sll t1,t5,a7 + 4366: fff34313 not t1,t1 + 436a: 00e37733 and a4,t1,a4 + 436e: 011818b3 sll a7,a6,a7 + 4372: 00e8e733 or a4,a7,a4 + 4376: 05f79f63 bne a5,t6,43d4 + 437a: c950 sw a2,20(a0) + 437c: 0685 addi a3,a3,1 + 437e: fdc69ae3 bne a3,t3,4352 + 4382: c118 sw a4,0(a0) + 4384: 0ff00713 li a4,255 + 4388: 04b77563 bgeu a4,a1,43d2 + 438c: 4154 lw a3,4(a0) + 438e: 4621 li a2,8 + 4390: 4e85 li t4,1 + 4392: 4f3d li t5,15 + 4394: 02800f93 li t6,40 + 4398: 04800293 li t0,72 + 439c: 4e41 li t3,16 + 439e: 00ce98b3 sll a7,t4,a2 + 43a2: 0115f733 and a4,a1,a7 + 43a6: 02e89263 bne a7,a4,43ca + 43aa: 00261713 slli a4,a2,0x2 + 43ae: 1701 addi a4,a4,-32 + 43b0: 00ef1333 sll t1,t5,a4 + 43b4: fff34313 not t1,t1 + 43b8: 00d376b3 and a3,t1,a3 + 43bc: 00e81733 sll a4,a6,a4 + 43c0: 8ed9 or a3,a3,a4 + 43c2: 01f79d63 bne a5,t6,43dc + 43c6: 01152a23 sw a7,20(a0) + 43ca: 0605 addi a2,a2,1 + 43cc: fdc619e3 bne a2,t3,439e + 43d0: c154 sw a3,4(a0) + 43d2: 8082 ret + 43d4: fa5794e3 bne a5,t0,437c + 43d8: c910 sw a2,16(a0) + 43da: b74d j 437c + 43dc: fe5797e3 bne a5,t0,43ca + 43e0: 01152823 sw a7,16(a0) + 43e4: b7dd j 43ca + +000043e6 : + 43e6: 40021737 lui a4,0x40021 + 43ea: 435c lw a5,4(a4) + 43ec: 4691 li a3,4 + 43ee: 8bb1 andi a5,a5,12 + 43f0: 00d78563 beq a5,a3,43fa + 43f4: 46a1 li a3,8 + 43f6: 06d78263 beq a5,a3,445a + 43fa: 007a17b7 lui a5,0x7a1 + 43fe: 20078793 addi a5,a5,512 # 7a1200 <_data_lma+0x794768> + 4402: c11c sw a5,0(a0) + 4404: 40021637 lui a2,0x40021 + 4408: 425c lw a5,4(a2) + 440a: 20000737 lui a4,0x20000 + 440e: 00070713 mv a4,a4 + 4412: 8391 srli a5,a5,0x4 + 4414: 8bbd andi a5,a5,15 + 4416: 97ba add a5,a5,a4 + 4418: 2394 lbu a3,0(a5) + 441a: 411c lw a5,0(a0) + 441c: 00d7d7b3 srl a5,a5,a3 + 4420: c15c sw a5,4(a0) + 4422: 4254 lw a3,4(a2) + 4424: 82a1 srli a3,a3,0x8 + 4426: 8a9d andi a3,a3,7 + 4428: 96ba add a3,a3,a4 + 442a: 2294 lbu a3,0(a3) + 442c: 00d7d6b3 srl a3,a5,a3 + 4430: c514 sw a3,8(a0) + 4432: 4254 lw a3,4(a2) + 4434: 82ad srli a3,a3,0xb + 4436: 8a9d andi a3,a3,7 + 4438: 9736 add a4,a4,a3 + 443a: 2318 lbu a4,0(a4) + 443c: 00e7d7b3 srl a5,a5,a4 + 4440: c55c sw a5,12(a0) + 4442: 4258 lw a4,4(a2) + 4444: 8339 srli a4,a4,0xe + 4446: 00377693 andi a3,a4,3 + 444a: 82418713 addi a4,gp,-2012 # 20000204 + 444e: 9736 add a4,a4,a3 + 4450: 2318 lbu a4,0(a4) + 4452: 02e7d7b3 divu a5,a5,a4 + 4456: c91c sw a5,16(a0) + 4458: 8082 ret + 445a: 435c lw a5,4(a4) + 445c: 4354 lw a3,4(a4) + 445e: 6741 lui a4,0x10 + 4460: 83c9 srli a5,a5,0x12 + 4462: 8ef9 and a3,a3,a4 + 4464: 1ffff737 lui a4,0x1ffff + 4468: 70c72703 lw a4,1804(a4) # 1ffff70c <_data_lma+0x1fff2c74> + 446c: 8bbd andi a5,a5,15 + 446e: 0789 addi a5,a5,2 + 4470: 01171613 slli a2,a4,0x11 + 4474: 00064863 bltz a2,4484 + 4478: 4645 li a2,17 + 447a: 4701 li a4,0 + 447c: 02c79263 bne a5,a2,44a0 + 4480: 47c9 li a5,18 + 4482: a839 j 44a0 + 4484: 4709 li a4,2 + 4486: 02e78963 beq a5,a4,44b8 + 448a: 473d li a4,15 + 448c: 02e78863 beq a5,a4,44bc + 4490: 4741 li a4,16 + 4492: 02e78863 beq a5,a4,44c2 + 4496: 4645 li a2,17 + 4498: 4701 li a4,0 + 449a: 00c79363 bne a5,a2,44a0 + 449e: 47c1 li a5,16 + 44a0: e685 bnez a3,44c8 + 44a2: 400246b7 lui a3,0x40024 + 44a6: 8006a683 lw a3,-2048(a3) # 40023800 <_eusrstack+0x20013800> + 44aa: 8ac1 andi a3,a3,16 + 44ac: c68d beqz a3,44d6 + 44ae: 007a16b7 lui a3,0x7a1 + 44b2: 20068693 addi a3,a3,512 # 7a1200 <_data_lma+0x794768> + 44b6: a025 j 44de + 44b8: 4701 li a4,0 + 44ba: b7d9 j 4480 + 44bc: 4705 li a4,1 + 44be: 47b5 li a5,13 + 44c0: b7c5 j 44a0 + 44c2: 4701 li a4,0 + 44c4: 47bd li a5,15 + 44c6: bfe9 j 44a0 + 44c8: 400216b7 lui a3,0x40021 + 44cc: 42d4 lw a3,4(a3) + 44ce: 00e69613 slli a2,a3,0xe + 44d2: fc065ee3 bgez a2,44ae + 44d6: 003d16b7 lui a3,0x3d1 + 44da: 90068693 addi a3,a3,-1792 # 3d0900 <_data_lma+0x3c3e68> + 44de: 02d787b3 mul a5,a5,a3 + 44e2: c11c sw a5,0(a0) + 44e4: d305 beqz a4,4404 + 44e6: 411c lw a5,0(a0) + 44e8: 8385 srli a5,a5,0x1 + 44ea: bf21 j 4402 + +000044ec : + 44ec: c599 beqz a1,44fa + 44ee: 40021737 lui a4,0x40021 + 44f2: 4f1c lw a5,24(a4) + 44f4: 8d5d or a0,a0,a5 + 44f6: cf08 sw a0,24(a4) + 44f8: 8082 ret + 44fa: 400217b7 lui a5,0x40021 + 44fe: 4f98 lw a4,24(a5) + 4500: fff54513 not a0,a0 + 4504: 8d79 and a0,a0,a4 + 4506: cf88 sw a0,24(a5) + 4508: 8082 ret + +0000450a : + 450a: e4dfb2ef jal t0,356 <__riscv_save_0> + 450e: 2916 lhu a3,16(a0) + 4510: 77f5 lui a5,0xffffd + 4512: 17fd addi a5,a5,-1 + 4514: 8ff5 and a5,a5,a3 + 4516: 21f6 lhu a3,6(a1) + 4518: 25da lhu a4,12(a1) + 451a: 7179 addi sp,sp,-48 + 451c: 8fd5 or a5,a5,a3 + 451e: a91e sh a5,16(a0) + 4520: 2556 lhu a3,12(a0) + 4522: 77fd lui a5,0xfffff + 4524: 9f378793 addi a5,a5,-1549 # ffffe9f3 <_eusrstack+0xdffee9f3> + 4528: 8ff5 and a5,a5,a3 + 452a: 21d6 lhu a3,4(a1) + 452c: 842a mv s0,a0 + 452e: c62e sw a1,12(sp) + 4530: 8fd5 or a5,a5,a3 + 4532: 2596 lhu a3,8(a1) + 4534: 8fd5 or a5,a5,a3 + 4536: 25b6 lhu a3,10(a1) + 4538: 8fd5 or a5,a5,a3 + 453a: a55e sh a5,12(a0) + 453c: 295e lhu a5,20(a0) + 453e: 07c2 slli a5,a5,0x10 + 4540: 83c1 srli a5,a5,0x10 + 4542: cff7f793 andi a5,a5,-769 + 4546: 8fd9 or a5,a5,a4 + 4548: a95e sh a5,20(a0) + 454a: 0868 addi a0,sp,28 + 454c: e9bff0ef jal ra,43e6 + 4550: 400147b7 lui a5,0x40014 + 4554: 80078793 addi a5,a5,-2048 # 40013800 <_eusrstack+0x20003800> + 4558: 45b2 lw a1,12(sp) + 455a: 04f41a63 bne s0,a5,45ae + 455e: 57a2 lw a5,40(sp) + 4560: 2456 lhu a3,12(s0) + 4562: 4765 li a4,25 + 4564: 02e787b3 mul a5,a5,a4 + 4568: 06c2 slli a3,a3,0x10 + 456a: 86c1 srai a3,a3,0x10 + 456c: 4198 lw a4,0(a1) + 456e: 0406d263 bgez a3,45b2 + 4572: 0706 slli a4,a4,0x1 + 4574: 2452 lhu a2,12(s0) + 4576: 0642 slli a2,a2,0x10 + 4578: 02e7d7b3 divu a5,a5,a4 + 457c: 06400713 li a4,100 + 4580: 8641 srai a2,a2,0x10 + 4582: 02e7d6b3 divu a3,a5,a4 + 4586: 02e7f7b3 remu a5,a5,a4 + 458a: 0692 slli a3,a3,0x4 + 458c: 02065563 bgez a2,45b6 + 4590: 078e slli a5,a5,0x3 + 4592: 03278793 addi a5,a5,50 + 4596: 02e7d7b3 divu a5,a5,a4 + 459a: 0077f713 andi a4,a5,7 + 459e: 00d767b3 or a5,a4,a3 + 45a2: 07c2 slli a5,a5,0x10 + 45a4: 83c1 srli a5,a5,0x10 + 45a6: a41e sh a5,8(s0) + 45a8: 6145 addi sp,sp,48 + 45aa: dd1fb06f j 37a <__riscv_restore_0> + 45ae: 5792 lw a5,36(sp) + 45b0: bf45 j 4560 + 45b2: 070a slli a4,a4,0x2 + 45b4: b7c1 j 4574 + 45b6: 0792 slli a5,a5,0x4 + 45b8: 03278793 addi a5,a5,50 + 45bc: 02e7d7b3 divu a5,a5,a4 + 45c0: 8bbd andi a5,a5,15 + 45c2: 8fd5 or a5,a5,a3 + 45c4: bff9 j 45a2 + +000045c6 : + 45c6: c591 beqz a1,45d2 + 45c8: 255e lhu a5,12(a0) + 45ca: 6709 lui a4,0x2 + 45cc: 8fd9 or a5,a5,a4 + 45ce: a55e sh a5,12(a0) + 45d0: 8082 ret + 45d2: 255a lhu a4,12(a0) + 45d4: 77f9 lui a5,0xffffe + 45d6: 17fd addi a5,a5,-1 + 45d8: 8ff9 and a5,a5,a4 + 45da: bfd5 j 45ce + +000045dc : + 45dc: 1ff5f593 andi a1,a1,511 + 45e0: a14e sh a1,4(a0) + 45e2: 8082 ret + +000045e4 : + 45e4: 210a lhu a0,0(a0) + 45e6: 8d6d and a0,a0,a1 + 45e8: 00a03533 snez a0,a0 + 45ec: 8082 ret + +000045ee : + 45ee: d69fb2ef jal t0,356 <__riscv_save_0> + 45f2: 842a mv s0,a0 + 45f4: 6511 lui a0,0x4 + 45f6: 1101 addi sp,sp,-32 + 45f8: 4585 li a1,1 + 45fa: 0511 addi a0,a0,4 + 45fc: ef1ff0ef jal ra,44ec + 4600: 20000793 li a5,512 + 4604: 827c sh a5,4(sp) + 4606: 40011537 lui a0,0x40011 + 460a: 478d li a5,3 + 460c: c43e sw a5,8(sp) + 460e: 004c addi a1,sp,4 + 4610: 47e1 li a5,24 + 4612: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20000800> + 4616: c63e sw a5,12(sp) + 4618: d0fff0ef jal ra,4326 + 461c: c822 sw s0,16(sp) + 461e: 40014437 lui s0,0x40014 + 4622: 000807b7 lui a5,0x80 + 4626: 080c addi a1,sp,16 + 4628: 80040513 addi a0,s0,-2048 # 40013800 <_eusrstack+0x20003800> + 462c: cc3e sw a5,24(sp) + 462e: ca02 sw zero,20(sp) + 4630: 00011e23 sh zero,28(sp) + 4634: ed7ff0ef jal ra,450a + 4638: 4585 li a1,1 + 463a: 80040513 addi a0,s0,-2048 + 463e: f89ff0ef jal ra,45c6 + 4642: 6105 addi sp,sp,32 + 4644: d37fb06f j 37a <__riscv_restore_0> + +00004648 <_write>: + 4648: cf5fb2ef jal t0,33c <__riscv_save_4> + 464c: 400144b7 lui s1,0x40014 + 4650: 89ae mv s3,a1 + 4652: 8932 mv s2,a2 + 4654: 4401 li s0,0 + 4656: 80048493 addi s1,s1,-2048 # 40013800 <_eusrstack+0x20003800> + 465a: 01244563 blt s0,s2,4664 <_write+0x1c> + 465e: 854a mv a0,s2 + 4660: d11fb06f j 370 <__riscv_restore_4> + 4664: 04000593 li a1,64 + 4668: 8526 mv a0,s1 + 466a: f7bff0ef jal ra,45e4 + 466e: d97d beqz a0,4664 <_write+0x1c> + 4670: 008987b3 add a5,s3,s0 + 4674: 00078583 lb a1,0(a5) # 80000 <_data_lma+0x73568> + 4678: 8526 mv a0,s1 + 467a: 0405 addi s0,s0,1 + 467c: 05c2 slli a1,a1,0x10 + 467e: 81c1 srli a1,a1,0x10 + 4680: f5dff0ef jal ra,45dc + 4684: bfd9 j 465a <_write+0x12> + +00004686 <_sbrk>: + 4686: 82818713 addi a4,gp,-2008 # 20000208 + 468a: 431c lw a5,0(a4) + 468c: 2000a6b7 lui a3,0x2000a + 4690: c7468693 addi a3,a3,-908 # 20009c74 <_ebss> + 4694: 953e add a0,a0,a5 + 4696: 00d56b63 bltu a0,a3,46ac <_sbrk+0x26> + 469a: 2000b6b7 lui a3,0x2000b + 469e: 00068693 mv a3,a3 + 46a2: 00a6e563 bltu a3,a0,46ac <_sbrk+0x26> + 46a6: c308 sw a0,0(a4) + 46a8: 853e mv a0,a5 + 46aa: 8082 ret + 46ac: 57fd li a5,-1 + 46ae: bfed j 46a8 <_sbrk+0x22> + +000046b0 <__udivdi3>: + 46b0: 87b6 mv a5,a3 + 46b2: 88b2 mv a7,a2 + 46b4: 832a mv t1,a0 + 46b6: 882e mv a6,a1 + 46b8: 14069d63 bnez a3,4812 <__udivdi3+0x162> + 46bc: 0ac5f963 bgeu a1,a2,476e <__udivdi3+0xbe> + 46c0: 6741 lui a4,0x10 + 46c2: 1ae66e63 bltu a2,a4,487e <__udivdi3+0x1ce> + 46c6: 010007b7 lui a5,0x1000 + 46ca: 34f66363 bltu a2,a5,4a10 <__udivdi3+0x360> + 46ce: 01865693 srli a3,a2,0x18 + 46d2: 47e1 li a5,24 + 46d4: 00008717 auipc a4,0x8 + 46d8: ebc70713 addi a4,a4,-324 # c590 <__clz_tab> + 46dc: 9736 add a4,a4,a3 + 46de: 00074703 lbu a4,0(a4) + 46e2: 97ba add a5,a5,a4 + 46e4: 02000713 li a4,32 + 46e8: 8f1d sub a4,a4,a5 + 46ea: cb19 beqz a4,4700 <__udivdi3+0x50> + 46ec: 00e59833 sll a6,a1,a4 + 46f0: 00f557b3 srl a5,a0,a5 + 46f4: 00e618b3 sll a7,a2,a4 + 46f8: 0107e833 or a6,a5,a6 + 46fc: 00e51333 sll t1,a0,a4 + 4700: 0108d613 srli a2,a7,0x10 + 4704: 02c85533 divu a0,a6,a2 + 4708: 01089693 slli a3,a7,0x10 + 470c: 82c1 srli a3,a3,0x10 + 470e: 01035793 srli a5,t1,0x10 + 4712: 02c87733 remu a4,a6,a2 + 4716: 02a685b3 mul a1,a3,a0 + 471a: 0742 slli a4,a4,0x10 + 471c: 00f76833 or a6,a4,a5 + 4720: 00b87a63 bgeu a6,a1,4734 <__udivdi3+0x84> + 4724: 9846 add a6,a6,a7 + 4726: fff50793 addi a5,a0,-1 + 472a: 01186463 bltu a6,a7,4732 <__udivdi3+0x82> + 472e: 30b86763 bltu a6,a1,4a3c <__udivdi3+0x38c> + 4732: 853e mv a0,a5 + 4734: 40b80833 sub a6,a6,a1 + 4738: 02c85733 divu a4,a6,a2 + 473c: 0342 slli t1,t1,0x10 + 473e: 01035313 srli t1,t1,0x10 + 4742: 02c87833 remu a6,a6,a2 + 4746: 02e686b3 mul a3,a3,a4 + 474a: 0842 slli a6,a6,0x10 + 474c: 00686833 or a6,a6,t1 + 4750: 00d87b63 bgeu a6,a3,4766 <__udivdi3+0xb6> + 4754: 9846 add a6,a6,a7 + 4756: fff70793 addi a5,a4,-1 + 475a: 01186563 bltu a6,a7,4764 <__udivdi3+0xb4> + 475e: 1779 addi a4,a4,-2 + 4760: 00d86363 bltu a6,a3,4766 <__udivdi3+0xb6> + 4764: 873e mv a4,a5 + 4766: 0542 slli a0,a0,0x10 + 4768: 8d59 or a0,a0,a4 + 476a: 4581 li a1,0 + 476c: 8082 ret + 476e: e601 bnez a2,4776 <__udivdi3+0xc6> + 4770: 4705 li a4,1 + 4772: 02c758b3 divu a7,a4,a2 + 4776: 6741 lui a4,0x10 + 4778: 0ee8ea63 bltu a7,a4,486c <__udivdi3+0x1bc> + 477c: 010007b7 lui a5,0x1000 + 4780: 28f8ec63 bltu a7,a5,4a18 <__udivdi3+0x368> + 4784: 0188d693 srli a3,a7,0x18 + 4788: 47e1 li a5,24 + 478a: 00008717 auipc a4,0x8 + 478e: e0670713 addi a4,a4,-506 # c590 <__clz_tab> + 4792: 9736 add a4,a4,a3 + 4794: 00074683 lbu a3,0(a4) + 4798: 96be add a3,a3,a5 + 479a: 02000793 li a5,32 + 479e: 8f95 sub a5,a5,a3 + 47a0: ebe5 bnez a5,4890 <__udivdi3+0x1e0> + 47a2: 01089e93 slli t4,a7,0x10 + 47a6: 41158733 sub a4,a1,a7 + 47aa: 0108df13 srli t5,a7,0x10 + 47ae: 010ede93 srli t4,t4,0x10 + 47b2: 4585 li a1,1 + 47b4: 01035793 srli a5,t1,0x10 + 47b8: 03e75533 divu a0,a4,t5 + 47bc: 03e77733 remu a4,a4,t5 + 47c0: 03d506b3 mul a3,a0,t4 + 47c4: 0742 slli a4,a4,0x10 + 47c6: 8fd9 or a5,a5,a4 + 47c8: 00d7fa63 bgeu a5,a3,47dc <__udivdi3+0x12c> + 47cc: 97c6 add a5,a5,a7 + 47ce: fff50713 addi a4,a0,-1 + 47d2: 0117e463 bltu a5,a7,47da <__udivdi3+0x12a> + 47d6: 26d7e663 bltu a5,a3,4a42 <__udivdi3+0x392> + 47da: 853a mv a0,a4 + 47dc: 8f95 sub a5,a5,a3 + 47de: 03e7d733 divu a4,a5,t5 + 47e2: 0342 slli t1,t1,0x10 + 47e4: 01035313 srli t1,t1,0x10 + 47e8: 03e7f7b3 remu a5,a5,t5 + 47ec: 03d70eb3 mul t4,a4,t4 + 47f0: 07c2 slli a5,a5,0x10 + 47f2: 0067e7b3 or a5,a5,t1 + 47f6: 01d7fb63 bgeu a5,t4,480c <__udivdi3+0x15c> + 47fa: 97c6 add a5,a5,a7 + 47fc: fff70693 addi a3,a4,-1 + 4800: 0117e563 bltu a5,a7,480a <__udivdi3+0x15a> + 4804: 1779 addi a4,a4,-2 + 4806: 01d7e363 bltu a5,t4,480c <__udivdi3+0x15c> + 480a: 8736 mv a4,a3 + 480c: 0542 slli a0,a0,0x10 + 480e: 8d59 or a0,a0,a4 + 4810: 8082 ret + 4812: 04d5e263 bltu a1,a3,4856 <__udivdi3+0x1a6> + 4816: 67c1 lui a5,0x10 + 4818: 04f6e263 bltu a3,a5,485c <__udivdi3+0x1ac> + 481c: 010007b7 lui a5,0x1000 + 4820: 1ef6e463 bltu a3,a5,4a08 <__udivdi3+0x358> + 4824: 0186d713 srli a4,a3,0x18 + 4828: 4861 li a6,24 + 482a: 00008797 auipc a5,0x8 + 482e: d6678793 addi a5,a5,-666 # c590 <__clz_tab> + 4832: 97ba add a5,a5,a4 + 4834: 0007c703 lbu a4,0(a5) + 4838: 02000e13 li t3,32 + 483c: 9742 add a4,a4,a6 + 483e: 40ee0e33 sub t3,t3,a4 + 4842: 0c0e1a63 bnez t3,4916 <__udivdi3+0x266> + 4846: 1cb6ed63 bltu a3,a1,4a20 <__udivdi3+0x370> + 484a: 00c53533 sltu a0,a0,a2 + 484e: 00154513 xori a0,a0,1 + 4852: 4581 li a1,0 + 4854: 8082 ret + 4856: 4581 li a1,0 + 4858: 4501 li a0,0 + 485a: 8082 ret + 485c: 0ff00793 li a5,255 + 4860: 1cd7f363 bgeu a5,a3,4a26 <__udivdi3+0x376> + 4864: 0086d713 srli a4,a3,0x8 + 4868: 4821 li a6,8 + 486a: b7c1 j 482a <__udivdi3+0x17a> + 486c: 0ff00713 li a4,255 + 4870: 86c6 mv a3,a7 + 4872: f1177ce3 bgeu a4,a7,478a <__udivdi3+0xda> + 4876: 0088d693 srli a3,a7,0x8 + 487a: 47a1 li a5,8 + 487c: b739 j 478a <__udivdi3+0xda> + 487e: 0ff00713 li a4,255 + 4882: 86b2 mv a3,a2 + 4884: e4c778e3 bgeu a4,a2,46d4 <__udivdi3+0x24> + 4888: 00865693 srli a3,a2,0x8 + 488c: 47a1 li a5,8 + 488e: b599 j 46d4 <__udivdi3+0x24> + 4890: 00f898b3 sll a7,a7,a5 + 4894: 00d5d633 srl a2,a1,a3 + 4898: 0108df13 srli t5,a7,0x10 + 489c: 03e65e33 divu t3,a2,t5 + 48a0: 00f59733 sll a4,a1,a5 + 48a4: 00d556b3 srl a3,a0,a3 + 48a8: 8f55 or a4,a4,a3 + 48aa: 01089e93 slli t4,a7,0x10 + 48ae: 010ede93 srli t4,t4,0x10 + 48b2: 00f51333 sll t1,a0,a5 + 48b6: 01075593 srli a1,a4,0x10 + 48ba: 03e676b3 remu a3,a2,t5 + 48be: 03ce87b3 mul a5,t4,t3 + 48c2: 06c2 slli a3,a3,0x10 + 48c4: 8ecd or a3,a3,a1 + 48c6: 00f6fb63 bgeu a3,a5,48dc <__udivdi3+0x22c> + 48ca: 96c6 add a3,a3,a7 + 48cc: fffe0613 addi a2,t3,-1 + 48d0: 1716e463 bltu a3,a7,4a38 <__udivdi3+0x388> + 48d4: 16f6f263 bgeu a3,a5,4a38 <__udivdi3+0x388> + 48d8: 1e79 addi t3,t3,-2 + 48da: 96c6 add a3,a3,a7 + 48dc: 8e9d sub a3,a3,a5 + 48de: 03e6d633 divu a2,a3,t5 + 48e2: 01071793 slli a5,a4,0x10 + 48e6: 83c1 srli a5,a5,0x10 + 48e8: 03e6f6b3 remu a3,a3,t5 + 48ec: 02ce8533 mul a0,t4,a2 + 48f0: 01069713 slli a4,a3,0x10 + 48f4: 8f5d or a4,a4,a5 + 48f6: 00a77b63 bgeu a4,a0,490c <__udivdi3+0x25c> + 48fa: 9746 add a4,a4,a7 + 48fc: fff60793 addi a5,a2,-1 # 40020fff <_eusrstack+0x20010fff> + 4900: 13176863 bltu a4,a7,4a30 <__udivdi3+0x380> + 4904: 12a77663 bgeu a4,a0,4a30 <__udivdi3+0x380> + 4908: 1679 addi a2,a2,-2 + 490a: 9746 add a4,a4,a7 + 490c: 010e1593 slli a1,t3,0x10 + 4910: 8f09 sub a4,a4,a0 + 4912: 8dd1 or a1,a1,a2 + 4914: b545 j 47b4 <__udivdi3+0x104> + 4916: 00e657b3 srl a5,a2,a4 + 491a: 01c696b3 sll a3,a3,t3 + 491e: 8edd or a3,a3,a5 + 4920: 00e5d333 srl t1,a1,a4 + 4924: 0106df13 srli t5,a3,0x10 + 4928: 03e357b3 divu a5,t1,t5 + 492c: 01069e93 slli t4,a3,0x10 + 4930: 010ede93 srli t4,t4,0x10 + 4934: 01c59833 sll a6,a1,t3 + 4938: 00e55733 srl a4,a0,a4 + 493c: 01076833 or a6,a4,a6 + 4940: 01085893 srli a7,a6,0x10 + 4944: 01c61633 sll a2,a2,t3 + 4948: 03e37333 remu t1,t1,t5 + 494c: 02fe85b3 mul a1,t4,a5 + 4950: 0342 slli t1,t1,0x10 + 4952: 011368b3 or a7,t1,a7 + 4956: 00b8fb63 bgeu a7,a1,496c <__udivdi3+0x2bc> + 495a: 98b6 add a7,a7,a3 + 495c: fff78713 addi a4,a5,-1 + 4960: 0cd8ea63 bltu a7,a3,4a34 <__udivdi3+0x384> + 4964: 0cb8f863 bgeu a7,a1,4a34 <__udivdi3+0x384> + 4968: 17f9 addi a5,a5,-2 + 496a: 98b6 add a7,a7,a3 + 496c: 40b888b3 sub a7,a7,a1 + 4970: 03e8d733 divu a4,a7,t5 + 4974: 0842 slli a6,a6,0x10 + 4976: 01085813 srli a6,a6,0x10 + 497a: 03e8f8b3 remu a7,a7,t5 + 497e: 02ee8333 mul t1,t4,a4 + 4982: 08c2 slli a7,a7,0x10 + 4984: 0108e5b3 or a1,a7,a6 + 4988: 0065fb63 bgeu a1,t1,499e <__udivdi3+0x2ee> + 498c: 95b6 add a1,a1,a3 + 498e: fff70813 addi a6,a4,-1 + 4992: 08d5ed63 bltu a1,a3,4a2c <__udivdi3+0x37c> + 4996: 0865fb63 bgeu a1,t1,4a2c <__udivdi3+0x37c> + 499a: 1779 addi a4,a4,-2 + 499c: 95b6 add a1,a1,a3 + 499e: 07c2 slli a5,a5,0x10 + 49a0: 6f41 lui t5,0x10 + 49a2: 8fd9 or a5,a5,a4 + 49a4: ffff0713 addi a4,t5,-1 # ffff <_data_lma+0x3567> + 49a8: 00e7f6b3 and a3,a5,a4 + 49ac: 0107d893 srli a7,a5,0x10 + 49b0: 8f71 and a4,a4,a2 + 49b2: 8241 srli a2,a2,0x10 + 49b4: 02e68eb3 mul t4,a3,a4 + 49b8: 406585b3 sub a1,a1,t1 + 49bc: 02c686b3 mul a3,a3,a2 + 49c0: 010ed813 srli a6,t4,0x10 + 49c4: 02e88733 mul a4,a7,a4 + 49c8: 96ba add a3,a3,a4 + 49ca: 96c2 add a3,a3,a6 + 49cc: 02c88633 mul a2,a7,a2 + 49d0: 00e6f363 bgeu a3,a4,49d6 <__udivdi3+0x326> + 49d4: 967a add a2,a2,t5 + 49d6: 0106d893 srli a7,a3,0x10 + 49da: 9646 add a2,a2,a7 + 49dc: 02c5e263 bltu a1,a2,4a00 <__udivdi3+0x350> + 49e0: 00c58563 beq a1,a2,49ea <__udivdi3+0x33a> + 49e4: 853e mv a0,a5 + 49e6: 4581 li a1,0 + 49e8: 8082 ret + 49ea: 6741 lui a4,0x10 + 49ec: 177d addi a4,a4,-1 + 49ee: 8ef9 and a3,a3,a4 + 49f0: 06c2 slli a3,a3,0x10 + 49f2: 00eefeb3 and t4,t4,a4 + 49f6: 01c51533 sll a0,a0,t3 + 49fa: 96f6 add a3,a3,t4 + 49fc: fed574e3 bgeu a0,a3,49e4 <__udivdi3+0x334> + 4a00: fff78513 addi a0,a5,-1 + 4a04: 4581 li a1,0 + 4a06: 8082 ret + 4a08: 0106d713 srli a4,a3,0x10 + 4a0c: 4841 li a6,16 + 4a0e: bd31 j 482a <__udivdi3+0x17a> + 4a10: 01065693 srli a3,a2,0x10 + 4a14: 47c1 li a5,16 + 4a16: b97d j 46d4 <__udivdi3+0x24> + 4a18: 0108d693 srli a3,a7,0x10 + 4a1c: 47c1 li a5,16 + 4a1e: b3b5 j 478a <__udivdi3+0xda> + 4a20: 4581 li a1,0 + 4a22: 4505 li a0,1 + 4a24: 8082 ret + 4a26: 8736 mv a4,a3 + 4a28: 4801 li a6,0 + 4a2a: b501 j 482a <__udivdi3+0x17a> + 4a2c: 8742 mv a4,a6 + 4a2e: bf85 j 499e <__udivdi3+0x2ee> + 4a30: 863e mv a2,a5 + 4a32: bde9 j 490c <__udivdi3+0x25c> + 4a34: 87ba mv a5,a4 + 4a36: bf1d j 496c <__udivdi3+0x2bc> + 4a38: 8e32 mv t3,a2 + 4a3a: b54d j 48dc <__udivdi3+0x22c> + 4a3c: 1579 addi a0,a0,-2 + 4a3e: 9846 add a6,a6,a7 + 4a40: b9d5 j 4734 <__udivdi3+0x84> + 4a42: 1579 addi a0,a0,-2 + 4a44: 97c6 add a5,a5,a7 + 4a46: bb59 j 47dc <__udivdi3+0x12c> + +00004a48 <__adddf3>: + 4a48: 00100837 lui a6,0x100 + 4a4c: 1101 addi sp,sp,-32 + 4a4e: 187d addi a6,a6,-1 + 4a50: 00b87733 and a4,a6,a1 + 4a54: ca26 sw s1,20(sp) + 4a56: 00d87833 and a6,a6,a3 + 4a5a: 0145d493 srli s1,a1,0x14 + 4a5e: 0146d313 srli t1,a3,0x14 + 4a62: 00371e13 slli t3,a4,0x3 + 4a66: c64e sw s3,12(sp) + 4a68: 01d55713 srli a4,a0,0x1d + 4a6c: 080e slli a6,a6,0x3 + 4a6e: 01d65793 srli a5,a2,0x1d + 4a72: 7ff4f493 andi s1,s1,2047 + 4a76: 7ff37313 andi t1,t1,2047 + 4a7a: ce06 sw ra,28(sp) + 4a7c: cc22 sw s0,24(sp) + 4a7e: c84a sw s2,16(sp) + 4a80: 01f5d993 srli s3,a1,0x1f + 4a84: 01f6de93 srli t4,a3,0x1f + 4a88: 01c76733 or a4,a4,t3 + 4a8c: 00351f13 slli t5,a0,0x3 + 4a90: 0107e833 or a6,a5,a6 + 4a94: 00361f93 slli t6,a2,0x3 + 4a98: 40648e33 sub t3,s1,t1 + 4a9c: 19d98063 beq s3,t4,4c1c <__adddf3+0x1d4> + 4aa0: 13c05663 blez t3,4bcc <__adddf3+0x184> + 4aa4: 1c030463 beqz t1,4c6c <__adddf3+0x224> + 4aa8: 008006b7 lui a3,0x800 + 4aac: 7ff00793 li a5,2047 + 4ab0: 00d86833 or a6,a6,a3 + 4ab4: 36f48f63 beq s1,a5,4e32 <__adddf3+0x3ea> + 4ab8: 03800793 li a5,56 + 4abc: 35c7c063 blt a5,t3,4dfc <__adddf3+0x3b4> + 4ac0: 47fd li a5,31 + 4ac2: 47c7cd63 blt a5,t3,4f3c <__adddf3+0x4f4> + 4ac6: 02000513 li a0,32 + 4aca: 41c50533 sub a0,a0,t3 + 4ace: 01cfd7b3 srl a5,t6,t3 + 4ad2: 00a816b3 sll a3,a6,a0 + 4ad6: 00af9933 sll s2,t6,a0 + 4ada: 8edd or a3,a3,a5 + 4adc: 01203933 snez s2,s2 + 4ae0: 01c857b3 srl a5,a6,t3 + 4ae4: 0126e933 or s2,a3,s2 + 4ae8: 8f1d sub a4,a4,a5 + 4aea: 412f0933 sub s2,t5,s2 + 4aee: 012f37b3 sltu a5,t5,s2 + 4af2: 40f70633 sub a2,a4,a5 + 4af6: 00861793 slli a5,a2,0x8 + 4afa: 2407d463 bgez a5,4d42 <__adddf3+0x2fa> + 4afe: 00800737 lui a4,0x800 + 4b02: 177d addi a4,a4,-1 + 4b04: 00e67433 and s0,a2,a4 + 4b08: 2c040c63 beqz s0,4de0 <__adddf3+0x398> + 4b0c: 8522 mv a0,s0 + 4b0e: 31d010ef jal ra,662a <__clzsi2> + 4b12: ff850713 addi a4,a0,-8 + 4b16: 02000793 li a5,32 + 4b1a: 8f99 sub a5,a5,a4 + 4b1c: 00f957b3 srl a5,s2,a5 + 4b20: 00e41633 sll a2,s0,a4 + 4b24: 8fd1 or a5,a5,a2 + 4b26: 00e91933 sll s2,s2,a4 + 4b2a: 2a974163 blt a4,s1,4dcc <__adddf3+0x384> + 4b2e: 40970533 sub a0,a4,s1 + 4b32: 00150613 addi a2,a0,1 + 4b36: 477d li a4,31 + 4b38: 38c74d63 blt a4,a2,4ed2 <__adddf3+0x48a> + 4b3c: 02000713 li a4,32 + 4b40: 8f11 sub a4,a4,a2 + 4b42: 00c956b3 srl a3,s2,a2 + 4b46: 00e91933 sll s2,s2,a4 + 4b4a: 00e79733 sll a4,a5,a4 + 4b4e: 8f55 or a4,a4,a3 + 4b50: 01203933 snez s2,s2 + 4b54: 01276933 or s2,a4,s2 + 4b58: 00c7d633 srl a2,a5,a2 + 4b5c: 4481 li s1,0 + 4b5e: 00797793 andi a5,s2,7 + 4b62: cf81 beqz a5,4b7a <__adddf3+0x132> + 4b64: 00f97713 andi a4,s2,15 + 4b68: 4791 li a5,4 + 4b6a: 00f70863 beq a4,a5,4b7a <__adddf3+0x132> + 4b6e: 00490713 addi a4,s2,4 + 4b72: 01273933 sltu s2,a4,s2 + 4b76: 964a add a2,a2,s2 + 4b78: 893a mv s2,a4 + 4b7a: 00861793 slli a5,a2,0x8 + 4b7e: 1c07d663 bgez a5,4d4a <__adddf3+0x302> + 4b82: 00148513 addi a0,s1,1 + 4b86: 7ff00793 li a5,2047 + 4b8a: 85ce mv a1,s3 + 4b8c: 20f50463 beq a0,a5,4d94 <__adddf3+0x34c> + 4b90: ff8007b7 lui a5,0xff800 + 4b94: 17fd addi a5,a5,-1 + 4b96: 8ff1 and a5,a5,a2 + 4b98: 01d79893 slli a7,a5,0x1d + 4b9c: 00395913 srli s2,s2,0x3 + 4ba0: 07a6 slli a5,a5,0x9 + 4ba2: 0128e8b3 or a7,a7,s2 + 4ba6: 83b1 srli a5,a5,0xc + 4ba8: 7ff57513 andi a0,a0,2047 + 4bac: 00c79693 slli a3,a5,0xc + 4bb0: 0552 slli a0,a0,0x14 + 4bb2: 40f2 lw ra,28(sp) + 4bb4: 4462 lw s0,24(sp) + 4bb6: 82b1 srli a3,a3,0xc + 4bb8: 05fe slli a1,a1,0x1f + 4bba: 8ec9 or a3,a3,a0 + 4bbc: 8ecd or a3,a3,a1 + 4bbe: 44d2 lw s1,20(sp) + 4bc0: 4942 lw s2,16(sp) + 4bc2: 49b2 lw s3,12(sp) + 4bc4: 8546 mv a0,a7 + 4bc6: 85b6 mv a1,a3 + 4bc8: 6105 addi sp,sp,32 + 4bca: 8082 ret + 4bcc: 0a0e1e63 bnez t3,4c88 <__adddf3+0x240> + 4bd0: 00148313 addi t1,s1,1 + 4bd4: 7fe37313 andi t1,t1,2046 + 4bd8: 22031763 bnez t1,4e06 <__adddf3+0x3be> + 4bdc: 01e767b3 or a5,a4,t5 + 4be0: 01f868b3 or a7,a6,t6 + 4be4: 1a049d63 bnez s1,4d9e <__adddf3+0x356> + 4be8: 40078763 beqz a5,4ff6 <__adddf3+0x5ae> + 4bec: 44088663 beqz a7,5038 <__stack_size+0x38> + 4bf0: 41ff0933 sub s2,t5,t6 + 4bf4: 410707b3 sub a5,a4,a6 + 4bf8: 012f3633 sltu a2,t5,s2 + 4bfc: 40c78633 sub a2,a5,a2 + 4c00: 00861793 slli a5,a2,0x8 + 4c04: 4c07d663 bgez a5,50d0 <__stack_size+0xd0> + 4c08: 41ef8933 sub s2,t6,t5 + 4c0c: 40e807b3 sub a5,a6,a4 + 4c10: 012fb633 sltu a2,t6,s2 + 4c14: 40c78633 sub a2,a5,a2 + 4c18: 89f6 mv s3,t4 + 4c1a: b791 j 4b5e <__adddf3+0x116> + 4c1c: 0fc05063 blez t3,4cfc <__adddf3+0x2b4> + 4c20: 0c030063 beqz t1,4ce0 <__adddf3+0x298> + 4c24: 008006b7 lui a3,0x800 + 4c28: 7ff00793 li a5,2047 + 4c2c: 00d86833 or a6,a6,a3 + 4c30: 3af48a63 beq s1,a5,4fe4 <__adddf3+0x59c> + 4c34: 03800793 li a5,56 + 4c38: 13c7cb63 blt a5,t3,4d6e <__adddf3+0x326> + 4c3c: 47fd li a5,31 + 4c3e: 35c7df63 bge a5,t3,4f9c <__adddf3+0x554> + 4c42: fe0e0913 addi s2,t3,-32 + 4c46: 02000793 li a5,32 + 4c4a: 012856b3 srl a3,a6,s2 + 4c4e: 00fe0a63 beq t3,a5,4c62 <__adddf3+0x21a> + 4c52: 04000913 li s2,64 + 4c56: 41c90933 sub s2,s2,t3 + 4c5a: 01281933 sll s2,a6,s2 + 4c5e: 012fefb3 or t6,t6,s2 + 4c62: 01f03933 snez s2,t6 + 4c66: 00d96933 or s2,s2,a3 + 4c6a: a231 j 4d76 <__adddf3+0x32e> + 4c6c: 01f867b3 or a5,a6,t6 + 4c70: 1c078a63 beqz a5,4e44 <__adddf3+0x3fc> + 4c74: fffe0793 addi a5,t3,-1 + 4c78: 38078c63 beqz a5,5010 <__stack_size+0x10> + 4c7c: 7ff00693 li a3,2047 + 4c80: 1ade0963 beq t3,a3,4e32 <__adddf3+0x3ea> + 4c84: 8e3e mv t3,a5 + 4c86: bd0d j 4ab8 <__adddf3+0x70> + 4c88: 409305b3 sub a1,t1,s1 + 4c8c: 22049163 bnez s1,4eae <__adddf3+0x466> + 4c90: 01e767b3 or a5,a4,t5 + 4c94: 32078763 beqz a5,4fc2 <__adddf3+0x57a> + 4c98: fff58793 addi a5,a1,-1 + 4c9c: 44078163 beqz a5,50de <__stack_size+0xde> + 4ca0: 7ff00693 li a3,2047 + 4ca4: 20d58c63 beq a1,a3,4ebc <__adddf3+0x474> + 4ca8: 85be mv a1,a5 + 4caa: 03800793 li a5,56 + 4cae: 2ab7cc63 blt a5,a1,4f66 <__adddf3+0x51e> + 4cb2: 47fd li a5,31 + 4cb4: 3cb7cf63 blt a5,a1,5092 <__stack_size+0x92> + 4cb8: 02000793 li a5,32 + 4cbc: 8f8d sub a5,a5,a1 + 4cbe: 00f71933 sll s2,a4,a5 + 4cc2: 00bf56b3 srl a3,t5,a1 + 4cc6: 00ff17b3 sll a5,t5,a5 + 4cca: 00d96933 or s2,s2,a3 + 4cce: 00f037b3 snez a5,a5 + 4cd2: 00b75733 srl a4,a4,a1 + 4cd6: 00f96933 or s2,s2,a5 + 4cda: 40e80833 sub a6,a6,a4 + 4cde: ac41 j 4f6e <__adddf3+0x526> + 4ce0: 01f867b3 or a5,a6,t6 + 4ce4: 34078063 beqz a5,5024 <__stack_size+0x24> + 4ce8: fffe0793 addi a5,t3,-1 + 4cec: 20078a63 beqz a5,4f00 <__adddf3+0x4b8> + 4cf0: 7ff00693 li a3,2047 + 4cf4: 2ede0863 beq t3,a3,4fe4 <__adddf3+0x59c> + 4cf8: 8e3e mv t3,a5 + 4cfa: bf2d j 4c34 <__adddf3+0x1ec> + 4cfc: 140e1e63 bnez t3,4e58 <__adddf3+0x410> + 4d00: 00148693 addi a3,s1,1 + 4d04: 7fe6f793 andi a5,a3,2046 + 4d08: 34079163 bnez a5,504a <__stack_size+0x4a> + 4d0c: 01e767b3 or a5,a4,t5 + 4d10: 2c049563 bnez s1,4fda <__adddf3+0x592> + 4d14: 3e078063 beqz a5,50f4 <__stack_size+0xf4> + 4d18: 01f867b3 or a5,a6,t6 + 4d1c: 30078e63 beqz a5,5038 <__stack_size+0x38> + 4d20: 01ff0933 add s2,t5,t6 + 4d24: 010707b3 add a5,a4,a6 + 4d28: 01e93f33 sltu t5,s2,t5 + 4d2c: 01e78633 add a2,a5,t5 + 4d30: 00861793 slli a5,a2,0x8 + 4d34: 0007d763 bgez a5,4d42 <__adddf3+0x2fa> + 4d38: ff8007b7 lui a5,0xff800 + 4d3c: 17fd addi a5,a5,-1 + 4d3e: 8e7d and a2,a2,a5 + 4d40: 4485 li s1,1 + 4d42: 00797793 andi a5,s2,7 + 4d46: e0079fe3 bnez a5,4b64 <__adddf3+0x11c> + 4d4a: 01d61793 slli a5,a2,0x1d + 4d4e: 00395893 srli a7,s2,0x3 + 4d52: 00f8e8b3 or a7,a7,a5 + 4d56: 00365793 srli a5,a2,0x3 + 4d5a: 7ff00713 li a4,2047 + 4d5e: 04e48d63 beq s1,a4,4db8 <__adddf3+0x370> + 4d62: 07b2 slli a5,a5,0xc + 4d64: 83b1 srli a5,a5,0xc + 4d66: 7ff4f513 andi a0,s1,2047 + 4d6a: 85ce mv a1,s3 + 4d6c: b581 j 4bac <__adddf3+0x164> + 4d6e: 01f86933 or s2,a6,t6 + 4d72: 01203933 snez s2,s2 + 4d76: 997a add s2,s2,t5 + 4d78: 01e937b3 sltu a5,s2,t5 + 4d7c: 00e78633 add a2,a5,a4 + 4d80: 00861793 slli a5,a2,0x8 + 4d84: fa07dfe3 bgez a5,4d42 <__adddf3+0x2fa> + 4d88: 0485 addi s1,s1,1 + 4d8a: 7ff00793 li a5,2047 + 4d8e: 18f49663 bne s1,a5,4f1a <__adddf3+0x4d2> + 4d92: 85ce mv a1,s3 + 4d94: 7ff00513 li a0,2047 + 4d98: 4781 li a5,0 + 4d9a: 4881 li a7,0 + 4d9c: bd01 j 4bac <__adddf3+0x164> + 4d9e: ebc1 bnez a5,4e2e <__adddf3+0x3e6> + 4da0: 3a088463 beqz a7,5148 <__stack_size+0x148> + 4da4: 00361693 slli a3,a2,0x3 + 4da8: 01d81793 slli a5,a6,0x1d + 4dac: 828d srli a3,a3,0x3 + 4dae: 00d7e8b3 or a7,a5,a3 + 4db2: 89f6 mv s3,t4 + 4db4: 00385793 srli a5,a6,0x3 + 4db8: 00f8e7b3 or a5,a7,a5 + 4dbc: dbf9 beqz a5,4d92 <__adddf3+0x34a> + 4dbe: 4581 li a1,0 + 4dc0: 7ff00513 li a0,2047 + 4dc4: 000807b7 lui a5,0x80 + 4dc8: 4881 li a7,0 + 4dca: b3cd j 4bac <__adddf3+0x164> + 4dcc: ff800637 lui a2,0xff800 + 4dd0: 167d addi a2,a2,-1 + 4dd2: 8e7d and a2,a2,a5 + 4dd4: 00797793 andi a5,s2,7 + 4dd8: 8c99 sub s1,s1,a4 + 4dda: d80795e3 bnez a5,4b64 <__adddf3+0x11c> + 4dde: b7b5 j 4d4a <__adddf3+0x302> + 4de0: 854a mv a0,s2 + 4de2: 049010ef jal ra,662a <__clzsi2> + 4de6: 01850713 addi a4,a0,24 + 4dea: 47fd li a5,31 + 4dec: d2e7d5e3 bge a5,a4,4b16 <__adddf3+0xce> + 4df0: ff850613 addi a2,a0,-8 + 4df4: 00c917b3 sll a5,s2,a2 + 4df8: 4901 li s2,0 + 4dfa: bb05 j 4b2a <__adddf3+0xe2> + 4dfc: 01f86933 or s2,a6,t6 + 4e00: 01203933 snez s2,s2 + 4e04: b1dd j 4aea <__adddf3+0xa2> + 4e06: 41ff0933 sub s2,t5,t6 + 4e0a: 41070633 sub a2,a4,a6 + 4e0e: 012f3433 sltu s0,t5,s2 + 4e12: 40860433 sub s0,a2,s0 + 4e16: 00841793 slli a5,s0,0x8 + 4e1a: 2407cd63 bltz a5,5074 <__stack_size+0x74> + 4e1e: 008968b3 or a7,s2,s0 + 4e22: ce0893e3 bnez a7,4b08 <__adddf3+0xc0> + 4e26: 4781 li a5,0 + 4e28: 4981 li s3,0 + 4e2a: 4481 li s1,0 + 4e2c: bf1d j 4d62 <__adddf3+0x31a> + 4e2e: f80898e3 bnez a7,4dbe <__adddf3+0x376> + 4e32: 050e slli a0,a0,0x3 + 4e34: 01d71793 slli a5,a4,0x1d + 4e38: 810d srli a0,a0,0x3 + 4e3a: 00a7e8b3 or a7,a5,a0 + 4e3e: 00375793 srli a5,a4,0x3 + 4e42: bf9d j 4db8 <__adddf3+0x370> + 4e44: 050e slli a0,a0,0x3 + 4e46: 01d71793 slli a5,a4,0x1d + 4e4a: 810d srli a0,a0,0x3 + 4e4c: 00a7e8b3 or a7,a5,a0 + 4e50: 84f2 mv s1,t3 + 4e52: 00375793 srli a5,a4,0x3 + 4e56: b711 j 4d5a <__adddf3+0x312> + 4e58: 40930533 sub a0,t1,s1 + 4e5c: 12048263 beqz s1,4f80 <__adddf3+0x538> + 4e60: 008006b7 lui a3,0x800 + 4e64: 7ff00793 li a5,2047 + 4e68: 8f55 or a4,a4,a3 + 4e6a: 2ef30d63 beq t1,a5,5164 <__stack_size+0x164> + 4e6e: 03800793 li a5,56 + 4e72: 20a7cb63 blt a5,a0,5088 <__stack_size+0x88> + 4e76: 47fd li a5,31 + 4e78: 2aa7c363 blt a5,a0,511e <__stack_size+0x11e> + 4e7c: 02000793 li a5,32 + 4e80: 8f89 sub a5,a5,a0 + 4e82: 00f71933 sll s2,a4,a5 + 4e86: 00af56b3 srl a3,t5,a0 + 4e8a: 00ff17b3 sll a5,t5,a5 + 4e8e: 00d96933 or s2,s2,a3 + 4e92: 00f037b3 snez a5,a5 + 4e96: 00a75733 srl a4,a4,a0 + 4e9a: 00f96933 or s2,s2,a5 + 4e9e: 983a add a6,a6,a4 + 4ea0: 997e add s2,s2,t6 + 4ea2: 01f937b3 sltu a5,s2,t6 + 4ea6: 01078633 add a2,a5,a6 + 4eaa: 849a mv s1,t1 + 4eac: bdd1 j 4d80 <__adddf3+0x338> + 4eae: 008006b7 lui a3,0x800 + 4eb2: 7ff00793 li a5,2047 + 4eb6: 8f55 or a4,a4,a3 + 4eb8: def319e3 bne t1,a5,4caa <__adddf3+0x262> + 4ebc: 00361793 slli a5,a2,0x3 + 4ec0: 838d srli a5,a5,0x3 + 4ec2: 01d81893 slli a7,a6,0x1d + 4ec6: 0117e8b3 or a7,a5,a7 + 4eca: 89f6 mv s3,t4 + 4ecc: 00385793 srli a5,a6,0x3 + 4ed0: b5e5 j 4db8 <__adddf3+0x370> + 4ed2: fe150713 addi a4,a0,-31 + 4ed6: 02000693 li a3,32 + 4eda: 00e7d733 srl a4,a5,a4 + 4ede: 00d60a63 beq a2,a3,4ef2 <__adddf3+0x4aa> + 4ee2: 04000693 li a3,64 + 4ee6: 40c68633 sub a2,a3,a2 + 4eea: 00c79633 sll a2,a5,a2 + 4eee: 00c96933 or s2,s2,a2 + 4ef2: 01203933 snez s2,s2 + 4ef6: 00e96933 or s2,s2,a4 + 4efa: 4601 li a2,0 + 4efc: 4481 li s1,0 + 4efe: b591 j 4d42 <__adddf3+0x2fa> + 4f00: 01ff0933 add s2,t5,t6 + 4f04: 010707b3 add a5,a4,a6 + 4f08: 01e93633 sltu a2,s2,t5 + 4f0c: 963e add a2,a2,a5 + 4f0e: 00861793 slli a5,a2,0x8 + 4f12: 4485 li s1,1 + 4f14: e207d7e3 bgez a5,4d42 <__adddf3+0x2fa> + 4f18: 4489 li s1,2 + 4f1a: ff8007b7 lui a5,0xff800 + 4f1e: 17fd addi a5,a5,-1 + 4f20: 8ff1 and a5,a5,a2 + 4f22: 00195713 srli a4,s2,0x1 + 4f26: 00197913 andi s2,s2,1 + 4f2a: 01276933 or s2,a4,s2 + 4f2e: 01f79893 slli a7,a5,0x1f + 4f32: 0128e933 or s2,a7,s2 + 4f36: 0017d613 srli a2,a5,0x1 + 4f3a: b115 j 4b5e <__adddf3+0x116> + 4f3c: fe0e0913 addi s2,t3,-32 + 4f40: 02000793 li a5,32 + 4f44: 012856b3 srl a3,a6,s2 + 4f48: 00fe0a63 beq t3,a5,4f5c <__adddf3+0x514> + 4f4c: 04000913 li s2,64 + 4f50: 41c90933 sub s2,s2,t3 + 4f54: 01281933 sll s2,a6,s2 + 4f58: 012fefb3 or t6,t6,s2 + 4f5c: 01f03933 snez s2,t6 + 4f60: 00d96933 or s2,s2,a3 + 4f64: b659 j 4aea <__adddf3+0xa2> + 4f66: 01e76933 or s2,a4,t5 + 4f6a: 01203933 snez s2,s2 + 4f6e: 412f8933 sub s2,t6,s2 + 4f72: 012fb7b3 sltu a5,t6,s2 + 4f76: 40f80633 sub a2,a6,a5 + 4f7a: 849a mv s1,t1 + 4f7c: 89f6 mv s3,t4 + 4f7e: bea5 j 4af6 <__adddf3+0xae> + 4f80: 01e767b3 or a5,a4,t5 + 4f84: 18078263 beqz a5,5108 <__stack_size+0x108> + 4f88: fff50793 addi a5,a0,-1 + 4f8c: 1c078463 beqz a5,5154 <__stack_size+0x154> + 4f90: 7ff00693 li a3,2047 + 4f94: 12d50463 beq a0,a3,50bc <__stack_size+0xbc> + 4f98: 853e mv a0,a5 + 4f9a: bdd1 j 4e6e <__adddf3+0x426> + 4f9c: 02000793 li a5,32 + 4fa0: 41c787b3 sub a5,a5,t3 + 4fa4: 00f816b3 sll a3,a6,a5 + 4fa8: 00ff9933 sll s2,t6,a5 + 4fac: 01cfd633 srl a2,t6,t3 + 4fb0: 8ed1 or a3,a3,a2 + 4fb2: 01203933 snez s2,s2 + 4fb6: 01c857b3 srl a5,a6,t3 + 4fba: 0126e933 or s2,a3,s2 + 4fbe: 973e add a4,a4,a5 + 4fc0: bb5d j 4d76 <__adddf3+0x32e> + 4fc2: 00361793 slli a5,a2,0x3 + 4fc6: 838d srli a5,a5,0x3 + 4fc8: 01d81893 slli a7,a6,0x1d + 4fcc: 0117e8b3 or a7,a5,a7 + 4fd0: 84ae mv s1,a1 + 4fd2: 00385793 srli a5,a6,0x3 + 4fd6: 89f6 mv s3,t4 + 4fd8: b349 j 4d5a <__adddf3+0x312> + 4fda: c3ed beqz a5,50bc <__stack_size+0xbc> + 4fdc: 01f86933 or s2,a6,t6 + 4fe0: dc091fe3 bnez s2,4dbe <__adddf3+0x376> + 4fe4: 050e slli a0,a0,0x3 + 4fe6: 01d71793 slli a5,a4,0x1d + 4fea: 810d srli a0,a0,0x3 + 4fec: 00f568b3 or a7,a0,a5 + 4ff0: 00375793 srli a5,a4,0x3 + 4ff4: b3d1 j 4db8 <__adddf3+0x370> + 4ff6: 0e088163 beqz a7,50d8 <__stack_size+0xd8> + 4ffa: 00361693 slli a3,a2,0x3 + 4ffe: 01d81793 slli a5,a6,0x1d + 5002: 828d srli a3,a3,0x3 + 5004: 00d7e8b3 or a7,a5,a3 + 5008: 89f6 mv s3,t4 + 500a: 00385793 srli a5,a6,0x3 + 500e: bb91 j 4d62 <__adddf3+0x31a> + 5010: 41ff0933 sub s2,t5,t6 + 5014: 410707b3 sub a5,a4,a6 + 5018: 012f3f33 sltu t5,t5,s2 + 501c: 41e78633 sub a2,a5,t5 + 5020: 4485 li s1,1 + 5022: bcd1 j 4af6 <__adddf3+0xae> + 5024: 050e slli a0,a0,0x3 + 5026: 01d71793 slli a5,a4,0x1d + 502a: 810d srli a0,a0,0x3 + 502c: 00f568b3 or a7,a0,a5 + 5030: 84f2 mv s1,t3 + 5032: 00375793 srli a5,a4,0x3 + 5036: b315 j 4d5a <__adddf3+0x312> + 5038: 050e slli a0,a0,0x3 + 503a: 01d71793 slli a5,a4,0x1d + 503e: 810d srli a0,a0,0x3 + 5040: 00a7e8b3 or a7,a5,a0 + 5044: 00375793 srli a5,a4,0x3 + 5048: bb29 j 4d62 <__adddf3+0x31a> + 504a: 7ff00793 li a5,2047 + 504e: d4f682e3 beq a3,a5,4d92 <__adddf3+0x34a> + 5052: 01ff0933 add s2,t5,t6 + 5056: 01e93633 sltu a2,s2,t5 + 505a: 010707b3 add a5,a4,a6 + 505e: 97b2 add a5,a5,a2 + 5060: 01f79893 slli a7,a5,0x1f + 5064: 00195913 srli s2,s2,0x1 + 5068: 0128e933 or s2,a7,s2 + 506c: 0017d613 srli a2,a5,0x1 + 5070: 84b6 mv s1,a3 + 5072: b9c1 j 4d42 <__adddf3+0x2fa> + 5074: 41ef8933 sub s2,t6,t5 + 5078: 40e80733 sub a4,a6,a4 + 507c: 012fb633 sltu a2,t6,s2 + 5080: 40c70433 sub s0,a4,a2 + 5084: 89f6 mv s3,t4 + 5086: b449 j 4b08 <__adddf3+0xc0> + 5088: 01e76933 or s2,a4,t5 + 508c: 01203933 snez s2,s2 + 5090: bd01 j 4ea0 <__adddf3+0x458> + 5092: fe058793 addi a5,a1,-32 + 5096: 02000693 li a3,32 + 509a: 00f757b3 srl a5,a4,a5 + 509e: 00d58a63 beq a1,a3,50b2 <__stack_size+0xb2> + 50a2: 04000693 li a3,64 + 50a6: 40b685b3 sub a1,a3,a1 + 50aa: 00b71733 sll a4,a4,a1 + 50ae: 00ef6f33 or t5,t5,a4 + 50b2: 01e03933 snez s2,t5 + 50b6: 00f96933 or s2,s2,a5 + 50ba: bd55 j 4f6e <__adddf3+0x526> + 50bc: 00361793 slli a5,a2,0x3 + 50c0: 838d srli a5,a5,0x3 + 50c2: 01d81893 slli a7,a6,0x1d + 50c6: 0117e8b3 or a7,a5,a7 + 50ca: 00385793 srli a5,a6,0x3 + 50ce: b1ed j 4db8 <__adddf3+0x370> + 50d0: 00c968b3 or a7,s2,a2 + 50d4: c60897e3 bnez a7,4d42 <__adddf3+0x2fa> + 50d8: 4781 li a5,0 + 50da: 4981 li s3,0 + 50dc: b159 j 4d62 <__adddf3+0x31a> + 50de: 41ef8933 sub s2,t6,t5 + 50e2: 40e807b3 sub a5,a6,a4 + 50e6: 012fb633 sltu a2,t6,s2 + 50ea: 40c78633 sub a2,a5,a2 + 50ee: 89f6 mv s3,t4 + 50f0: 4485 li s1,1 + 50f2: b411 j 4af6 <__adddf3+0xae> + 50f4: 00361693 slli a3,a2,0x3 + 50f8: 01d81793 slli a5,a6,0x1d + 50fc: 828d srli a3,a3,0x3 + 50fe: 00d7e8b3 or a7,a5,a3 + 5102: 00385793 srli a5,a6,0x3 + 5106: b9b1 j 4d62 <__adddf3+0x31a> + 5108: 00361693 slli a3,a2,0x3 + 510c: 01d81793 slli a5,a6,0x1d + 5110: 828d srli a3,a3,0x3 + 5112: 00d7e8b3 or a7,a5,a3 + 5116: 84aa mv s1,a0 + 5118: 00385793 srli a5,a6,0x3 + 511c: b93d j 4d5a <__adddf3+0x312> + 511e: fe050793 addi a5,a0,-32 + 5122: 02000693 li a3,32 + 5126: 00f757b3 srl a5,a4,a5 + 512a: 00d50a63 beq a0,a3,513e <__stack_size+0x13e> + 512e: 04000693 li a3,64 + 5132: 40a68533 sub a0,a3,a0 + 5136: 00a71733 sll a4,a4,a0 + 513a: 00ef6f33 or t5,t5,a4 + 513e: 01e03933 snez s2,t5 + 5142: 00f96933 or s2,s2,a5 + 5146: bba9 j 4ea0 <__adddf3+0x458> + 5148: 4581 li a1,0 + 514a: 7ff00513 li a0,2047 + 514e: 000807b7 lui a5,0x80 + 5152: bca9 j 4bac <__adddf3+0x164> + 5154: 01ff0933 add s2,t5,t6 + 5158: 010707b3 add a5,a4,a6 + 515c: 01f93633 sltu a2,s2,t6 + 5160: 963e add a2,a2,a5 + 5162: b375 j 4f0e <__adddf3+0x4c6> + 5164: 00361693 slli a3,a2,0x3 + 5168: 01d81793 slli a5,a6,0x1d + 516c: 828d srli a3,a3,0x3 + 516e: 00d7e8b3 or a7,a5,a3 + 5172: 00385793 srli a5,a6,0x3 + 5176: b189 j 4db8 <__adddf3+0x370> + +00005178 <__divdf3>: + 5178: 7139 addi sp,sp,-64 + 517a: 0145d793 srli a5,a1,0x14 + 517e: dc22 sw s0,56(sp) + 5180: d84a sw s2,48(sp) + 5182: d256 sw s5,36(sp) + 5184: 892a mv s2,a0 + 5186: 00c59413 slli s0,a1,0xc + 518a: de06 sw ra,60(sp) + 518c: da26 sw s1,52(sp) + 518e: d64e sw s3,44(sp) + 5190: d452 sw s4,40(sp) + 5192: d05a sw s6,32(sp) + 5194: ce5e sw s7,28(sp) + 5196: 7ff7f513 andi a0,a5,2047 + 519a: 8031 srli s0,s0,0xc + 519c: 01f5da93 srli s5,a1,0x1f + 51a0: 10050b63 beqz a0,52b6 <__divdf3+0x13e> + 51a4: 7ff00793 li a5,2047 + 51a8: 14f50b63 beq a0,a5,52fe <__divdf3+0x186> + 51ac: 01d95a13 srli s4,s2,0x1d + 51b0: 040e slli s0,s0,0x3 + 51b2: 008a6433 or s0,s4,s0 + 51b6: 00800a37 lui s4,0x800 + 51ba: 01446a33 or s4,s0,s4 + 51be: 00391b13 slli s6,s2,0x3 + 51c2: c0150493 addi s1,a0,-1023 + 51c6: 4401 li s0,0 + 51c8: 4b81 li s7,0 + 51ca: 0146d813 srli a6,a3,0x14 + 51ce: 00c69913 slli s2,a3,0xc + 51d2: 7ff87813 andi a6,a6,2047 + 51d6: 88b2 mv a7,a2 + 51d8: 00c95913 srli s2,s2,0xc + 51dc: 01f6d993 srli s3,a3,0x1f + 51e0: 08080e63 beqz a6,527c <__divdf3+0x104> + 51e4: 7ff00793 li a5,2047 + 51e8: 04f80063 beq a6,a5,5228 <__divdf3+0xb0> + 51ec: 01d65713 srli a4,a2,0x1d + 51f0: 090e slli s2,s2,0x3 + 51f2: 01276933 or s2,a4,s2 + 51f6: c0180813 addi a6,a6,-1023 # ffc01 <_data_lma+0xf3169> + 51fa: 008007b7 lui a5,0x800 + 51fe: 00f96733 or a4,s2,a5 + 5202: 00361893 slli a7,a2,0x3 + 5206: 410484b3 sub s1,s1,a6 + 520a: 4581 li a1,0 + 520c: 47bd li a5,15 + 520e: 013ac833 xor a6,s5,s3 + 5212: 1a87e463 bltu a5,s0,53ba <__divdf3+0x242> + 5216: 00007797 auipc a5,0x7 + 521a: 2fa78793 addi a5,a5,762 # c510 <_exit+0x500> + 521e: 040a slli s0,s0,0x2 + 5220: 943e add s0,s0,a5 + 5222: 4010 lw a2,0(s0) + 5224: 963e add a2,a2,a5 + 5226: 8602 jr a2 + 5228: 00c96733 or a4,s2,a2 + 522c: 80148493 addi s1,s1,-2047 + 5230: 10071263 bnez a4,5334 <__divdf3+0x1bc> + 5234: 00246413 ori s0,s0,2 + 5238: 4881 li a7,0 + 523a: 4589 li a1,2 + 523c: bfc1 j 520c <__divdf3+0x94> + 523e: 7ff00613 li a2,2047 + 5242: 4781 li a5,0 + 5244: 4701 li a4,0 + 5246: 07b2 slli a5,a5,0xc + 5248: 50f2 lw ra,60(sp) + 524a: 5462 lw s0,56(sp) + 524c: 0652 slli a2,a2,0x14 + 524e: 83b1 srli a5,a5,0xc + 5250: 087e slli a6,a6,0x1f + 5252: 8fd1 or a5,a5,a2 + 5254: 0107e7b3 or a5,a5,a6 + 5258: 54d2 lw s1,52(sp) + 525a: 5942 lw s2,48(sp) + 525c: 59b2 lw s3,44(sp) + 525e: 5a22 lw s4,40(sp) + 5260: 5a92 lw s5,36(sp) + 5262: 5b02 lw s6,32(sp) + 5264: 4bf2 lw s7,28(sp) + 5266: 853a mv a0,a4 + 5268: 85be mv a1,a5 + 526a: 6121 addi sp,sp,64 + 526c: 8082 ret + 526e: 4801 li a6,0 + 5270: 7ff00613 li a2,2047 + 5274: 000807b7 lui a5,0x80 + 5278: 4701 li a4,0 + 527a: b7f1 j 5246 <__divdf3+0xce> + 527c: 00c96733 or a4,s2,a2 + 5280: c74d beqz a4,532a <__divdf3+0x1b2> + 5282: 30090863 beqz s2,5592 <__divdf3+0x41a> + 5286: 854a mv a0,s2 + 5288: c432 sw a2,8(sp) + 528a: 3a0010ef jal ra,662a <__clzsi2> + 528e: 4622 lw a2,8(sp) + 5290: ff550713 addi a4,a0,-11 + 5294: 47f5 li a5,29 + 5296: ff850693 addi a3,a0,-8 + 529a: 8f99 sub a5,a5,a4 + 529c: 00d91933 sll s2,s2,a3 + 52a0: 00f657b3 srl a5,a2,a5 + 52a4: 0127e733 or a4,a5,s2 + 52a8: 00d618b3 sll a7,a2,a3 + 52ac: 9526 add a0,a0,s1 + 52ae: 3f350493 addi s1,a0,1011 + 52b2: 4581 li a1,0 + 52b4: bfa1 j 520c <__divdf3+0x94> + 52b6: 01246a33 or s4,s0,s2 + 52ba: 060a0363 beqz s4,5320 <__divdf3+0x1a8> + 52be: c636 sw a3,12(sp) + 52c0: c432 sw a2,8(sp) + 52c2: 2a040663 beqz s0,556e <__divdf3+0x3f6> + 52c6: 8522 mv a0,s0 + 52c8: 362010ef jal ra,662a <__clzsi2> + 52cc: 4622 lw a2,8(sp) + 52ce: 46b2 lw a3,12(sp) + 52d0: 84aa mv s1,a0 + 52d2: ff550713 addi a4,a0,-11 + 52d6: 4a75 li s4,29 + 52d8: ff848b13 addi s6,s1,-8 + 52dc: 40ea0a33 sub s4,s4,a4 + 52e0: 01641433 sll s0,s0,s6 + 52e4: 01495a33 srl s4,s2,s4 + 52e8: 008a6a33 or s4,s4,s0 + 52ec: 01691b33 sll s6,s2,s6 + 52f0: c0d00513 li a0,-1011 + 52f4: 409504b3 sub s1,a0,s1 + 52f8: 4401 li s0,0 + 52fa: 4b81 li s7,0 + 52fc: b5f9 j 51ca <__divdf3+0x52> + 52fe: 01246a33 or s4,s0,s2 + 5302: 000a1863 bnez s4,5312 <__divdf3+0x19a> + 5306: 4421 li s0,8 + 5308: 4b01 li s6,0 + 530a: 7ff00493 li s1,2047 + 530e: 4b89 li s7,2 + 5310: bd6d j 51ca <__divdf3+0x52> + 5312: 8a22 mv s4,s0 + 5314: 8b4a mv s6,s2 + 5316: 4431 li s0,12 + 5318: 7ff00493 li s1,2047 + 531c: 4b8d li s7,3 + 531e: b575 j 51ca <__divdf3+0x52> + 5320: 4411 li s0,4 + 5322: 4b01 li s6,0 + 5324: 4481 li s1,0 + 5326: 4b85 li s7,1 + 5328: b54d j 51ca <__divdf3+0x52> + 532a: 00146413 ori s0,s0,1 + 532e: 4881 li a7,0 + 5330: 4585 li a1,1 + 5332: bde9 j 520c <__divdf3+0x94> + 5334: 00346413 ori s0,s0,3 + 5338: 874a mv a4,s2 + 533a: 458d li a1,3 + 533c: bdc1 j 520c <__divdf3+0x94> + 533e: 2e050a63 beqz a0,5632 <__divdf3+0x4ba> + 5342: 4785 li a5,1 + 5344: 8f89 sub a5,a5,a0 + 5346: 03800693 li a3,56 + 534a: 32f6dd63 bge a3,a5,5684 <__divdf3+0x50c> + 534e: 4601 li a2,0 + 5350: 4781 li a5,0 + 5352: 4701 li a4,0 + 5354: bdcd j 5246 <__divdf3+0xce> + 5356: 86ce mv a3,s3 + 5358: 4789 li a5,2 + 535a: 3af58d63 beq a1,a5,5714 <__divdf3+0x59c> + 535e: 478d li a5,3 + 5360: f0f587e3 beq a1,a5,526e <__divdf3+0xf6> + 5364: 4785 li a5,1 + 5366: 8836 mv a6,a3 + 5368: fef583e3 beq a1,a5,534e <__divdf3+0x1d6> + 536c: 3ff48513 addi a0,s1,1023 + 5370: fca057e3 blez a0,533e <__divdf3+0x1c6> + 5374: 0078f793 andi a5,a7,7 + 5378: 28079663 bnez a5,5604 <__divdf3+0x48c> + 537c: 0038d693 srli a3,a7,0x3 + 5380: 00771793 slli a5,a4,0x7 + 5384: 0007d863 bgez a5,5394 <__divdf3+0x21c> + 5388: ff0007b7 lui a5,0xff000 + 538c: 17fd addi a5,a5,-1 + 538e: 8f7d and a4,a4,a5 + 5390: 40048513 addi a0,s1,1024 + 5394: 7fe00793 li a5,2046 + 5398: eaa7c3e3 blt a5,a0,523e <__divdf3+0xc6> + 539c: 01d71613 slli a2,a4,0x1d + 53a0: 00971793 slli a5,a4,0x9 + 53a4: 83b1 srli a5,a5,0xc + 53a6: 00d66733 or a4,a2,a3 + 53aa: 7ff57613 andi a2,a0,2047 + 53ae: bd61 j 5246 <__divdf3+0xce> + 53b0: 86d6 mv a3,s5 + 53b2: 8752 mv a4,s4 + 53b4: 88da mv a7,s6 + 53b6: 85de mv a1,s7 + 53b8: b745 j 5358 <__divdf3+0x1e0> + 53ba: 23476163 bltu a4,s4,55dc <__divdf3+0x464> + 53be: 20ea0d63 beq s4,a4,55d8 <__divdf3+0x460> + 53c2: 86da mv a3,s6 + 53c4: 14fd addi s1,s1,-1 + 53c6: 8452 mv s0,s4 + 53c8: 4b01 li s6,0 + 53ca: 00871793 slli a5,a4,0x8 + 53ce: 0188d313 srli t1,a7,0x18 + 53d2: 00f36333 or t1,t1,a5 + 53d6: 01035e93 srli t4,t1,0x10 + 53da: 03d457b3 divu a5,s0,t4 + 53de: 01031f13 slli t5,t1,0x10 + 53e2: 010f5f13 srli t5,t5,0x10 + 53e6: 0106d593 srli a1,a3,0x10 + 53ea: 00889e13 slli t3,a7,0x8 + 53ee: 03d47433 remu s0,s0,t4 + 53f2: 02ff0733 mul a4,t5,a5 + 53f6: 0442 slli s0,s0,0x10 + 53f8: 8dc1 or a1,a1,s0 + 53fa: 00e5fb63 bgeu a1,a4,5410 <__divdf3+0x298> + 53fe: 959a add a1,a1,t1 + 5400: fff78613 addi a2,a5,-1 # feffffff <_eusrstack+0xdefeffff> + 5404: 2665ee63 bltu a1,t1,5680 <__divdf3+0x508> + 5408: 26e5fc63 bgeu a1,a4,5680 <__divdf3+0x508> + 540c: 17f9 addi a5,a5,-2 + 540e: 959a add a1,a1,t1 + 5410: 8d99 sub a1,a1,a4 + 5412: 03d5d733 divu a4,a1,t4 + 5416: 06c2 slli a3,a3,0x10 + 5418: 82c1 srli a3,a3,0x10 + 541a: 03d5f5b3 remu a1,a1,t4 + 541e: 02ef0633 mul a2,t5,a4 + 5422: 05c2 slli a1,a1,0x10 + 5424: 8dd5 or a1,a1,a3 + 5426: 00c5fb63 bgeu a1,a2,543c <__divdf3+0x2c4> + 542a: 959a add a1,a1,t1 + 542c: fff70693 addi a3,a4,-1 # 7fffff <_data_lma+0x7f3567> + 5430: 2465e663 bltu a1,t1,567c <__divdf3+0x504> + 5434: 24c5f463 bgeu a1,a2,567c <__divdf3+0x504> + 5438: 1779 addi a4,a4,-2 + 543a: 959a add a1,a1,t1 + 543c: 07c2 slli a5,a5,0x10 + 543e: 6441 lui s0,0x10 + 5440: 8f5d or a4,a4,a5 + 5442: fff40793 addi a5,s0,-1 # ffff <_data_lma+0x3567> + 5446: 00f77533 and a0,a4,a5 + 544a: 01075893 srli a7,a4,0x10 + 544e: 010e5f93 srli t6,t3,0x10 + 5452: 00fe77b3 and a5,t3,a5 + 5456: 02f502b3 mul t0,a0,a5 + 545a: 40c586b3 sub a3,a1,a2 + 545e: 02f883b3 mul t2,a7,a5 + 5462: 0102d593 srli a1,t0,0x10 + 5466: 02af8633 mul a2,t6,a0 + 546a: 961e add a2,a2,t2 + 546c: 962e add a2,a2,a1 + 546e: 03f88533 mul a0,a7,t6 + 5472: 00767363 bgeu a2,t2,5478 <__divdf3+0x300> + 5476: 9522 add a0,a0,s0 + 5478: 68c1 lui a7,0x10 + 547a: 18fd addi a7,a7,-1 + 547c: 01065593 srli a1,a2,0x10 + 5480: 01167633 and a2,a2,a7 + 5484: 0642 slli a2,a2,0x10 + 5486: 0112f8b3 and a7,t0,a7 + 548a: 95aa add a1,a1,a0 + 548c: 9646 add a2,a2,a7 + 548e: 12b6e663 bltu a3,a1,55ba <__divdf3+0x442> + 5492: 12b68263 beq a3,a1,55b6 <__divdf3+0x43e> + 5496: 40cb0633 sub a2,s6,a2 + 549a: 8e8d sub a3,a3,a1 + 549c: 00cb3b33 sltu s6,s6,a2 + 54a0: 41668b33 sub s6,a3,s6 + 54a4: 3ff48513 addi a0,s1,1023 + 54a8: 17630c63 beq t1,s6,5620 <__divdf3+0x4a8> + 54ac: 03db58b3 divu a7,s6,t4 + 54b0: 01065593 srli a1,a2,0x10 + 54b4: 03db7b33 remu s6,s6,t4 + 54b8: 031f06b3 mul a3,t5,a7 + 54bc: 0b42 slli s6,s6,0x10 + 54be: 0165eb33 or s6,a1,s6 + 54c2: 00db7b63 bgeu s6,a3,54d8 <__divdf3+0x360> + 54c6: 9b1a add s6,s6,t1 + 54c8: fff88593 addi a1,a7,-1 # ffff <_data_lma+0x3567> + 54cc: 206b6d63 bltu s6,t1,56e6 <__divdf3+0x56e> + 54d0: 20db7b63 bgeu s6,a3,56e6 <__divdf3+0x56e> + 54d4: 18f9 addi a7,a7,-2 + 54d6: 9b1a add s6,s6,t1 + 54d8: 40db0b33 sub s6,s6,a3 + 54dc: 03db56b3 divu a3,s6,t4 + 54e0: 0642 slli a2,a2,0x10 + 54e2: 8241 srli a2,a2,0x10 + 54e4: 03db7b33 remu s6,s6,t4 + 54e8: 02df0f33 mul t5,t5,a3 + 54ec: 0b42 slli s6,s6,0x10 + 54ee: 01666633 or a2,a2,s6 + 54f2: 01e67b63 bgeu a2,t5,5508 <__divdf3+0x390> + 54f6: 961a add a2,a2,t1 + 54f8: fff68593 addi a1,a3,-1 # 7fffff <_data_lma+0x7f3567> + 54fc: 1e666763 bltu a2,t1,56ea <__divdf3+0x572> + 5500: 1fe67563 bgeu a2,t5,56ea <__divdf3+0x572> + 5504: 16f9 addi a3,a3,-2 + 5506: 961a add a2,a2,t1 + 5508: 08c2 slli a7,a7,0x10 + 550a: 00d8e8b3 or a7,a7,a3 + 550e: 01089593 slli a1,a7,0x10 + 5512: 0108d293 srli t0,a7,0x10 + 5516: 81c1 srli a1,a1,0x10 + 5518: 02f58eb3 mul t4,a1,a5 + 551c: 41e60633 sub a2,a2,t5 + 5520: 02bf85b3 mul a1,t6,a1 + 5524: 010ed693 srli a3,t4,0x10 + 5528: 02f287b3 mul a5,t0,a5 + 552c: 95be add a1,a1,a5 + 552e: 96ae add a3,a3,a1 + 5530: 025f8fb3 mul t6,t6,t0 + 5534: 00f6f463 bgeu a3,a5,553c <__divdf3+0x3c4> + 5538: 67c1 lui a5,0x10 + 553a: 9fbe add t6,t6,a5 + 553c: 65c1 lui a1,0x10 + 553e: 15fd addi a1,a1,-1 + 5540: 0106d793 srli a5,a3,0x10 + 5544: 8eed and a3,a3,a1 + 5546: 06c2 slli a3,a3,0x10 + 5548: 00befeb3 and t4,t4,a1 + 554c: 9fbe add t6,t6,a5 + 554e: 96f6 add a3,a3,t4 + 5550: 09f67f63 bgeu a2,t6,55ee <__divdf3+0x476> + 5554: 961a add a2,a2,t1 + 5556: fff88793 addi a5,a7,-1 + 555a: 1a666963 bltu a2,t1,570c <__divdf3+0x594> + 555e: 19f66863 bltu a2,t6,56ee <__divdf3+0x576> + 5562: 1bf60f63 beq a2,t6,5720 <__divdf3+0x5a8> + 5566: 88be mv a7,a5 + 5568: 0018e893 ori a7,a7,1 + 556c: b511 j 5370 <__divdf3+0x1f8> + 556e: 854a mv a0,s2 + 5570: 0ba010ef jal ra,662a <__clzsi2> + 5574: 01550713 addi a4,a0,21 + 5578: 45f1 li a1,28 + 557a: 02050493 addi s1,a0,32 + 557e: 4622 lw a2,8(sp) + 5580: 46b2 lw a3,12(sp) + 5582: d4e5dae3 bge a1,a4,52d6 <__divdf3+0x15e> + 5586: ff850413 addi s0,a0,-8 + 558a: 00891a33 sll s4,s2,s0 + 558e: 4b01 li s6,0 + 5590: b385 j 52f0 <__divdf3+0x178> + 5592: 8532 mv a0,a2 + 5594: c432 sw a2,8(sp) + 5596: 094010ef jal ra,662a <__clzsi2> + 559a: 01550713 addi a4,a0,21 + 559e: 46f1 li a3,28 + 55a0: 87aa mv a5,a0 + 55a2: 4622 lw a2,8(sp) + 55a4: 02050513 addi a0,a0,32 + 55a8: cee6d6e3 bge a3,a4,5294 <__divdf3+0x11c> + 55ac: 17e1 addi a5,a5,-8 + 55ae: 00f61733 sll a4,a2,a5 + 55b2: 4881 li a7,0 + 55b4: b9e5 j 52ac <__divdf3+0x134> + 55b6: eecb70e3 bgeu s6,a2,5496 <__divdf3+0x31e> + 55ba: 9b72 add s6,s6,t3 + 55bc: 01cb3533 sltu a0,s6,t3 + 55c0: 951a add a0,a0,t1 + 55c2: 96aa add a3,a3,a0 + 55c4: fff70513 addi a0,a4,-1 + 55c8: 02d37863 bgeu t1,a3,55f8 <__divdf3+0x480> + 55cc: 10b6e663 bltu a3,a1,56d8 <__divdf3+0x560> + 55d0: 10d58263 beq a1,a3,56d4 <__divdf3+0x55c> + 55d4: 872a mv a4,a0 + 55d6: b5c1 j 5496 <__divdf3+0x31e> + 55d8: df1b65e3 bltu s6,a7,53c2 <__divdf3+0x24a> + 55dc: 001b5593 srli a1,s6,0x1 + 55e0: 01fa1693 slli a3,s4,0x1f + 55e4: 001a5413 srli s0,s4,0x1 + 55e8: 8ecd or a3,a3,a1 + 55ea: 0b7e slli s6,s6,0x1f + 55ec: bbf9 j 53ca <__divdf3+0x252> + 55ee: f7f61de3 bne a2,t6,5568 <__divdf3+0x3f0> + 55f2: d6068fe3 beqz a3,5370 <__divdf3+0x1f8> + 55f6: bfb9 j 5554 <__divdf3+0x3dc> + 55f8: fcd31ee3 bne t1,a3,55d4 <__divdf3+0x45c> + 55fc: fdcb78e3 bgeu s6,t3,55cc <__divdf3+0x454> + 5600: 872a mv a4,a0 + 5602: bd51 j 5496 <__divdf3+0x31e> + 5604: 00f8f793 andi a5,a7,15 + 5608: 4691 li a3,4 + 560a: d6d789e3 beq a5,a3,537c <__divdf3+0x204> + 560e: ffc8b793 sltiu a5,a7,-4 + 5612: 00488693 addi a3,a7,4 + 5616: 0017c793 xori a5,a5,1 + 561a: 828d srli a3,a3,0x3 + 561c: 973e add a4,a4,a5 + 561e: b38d j 5380 <__divdf3+0x208> + 5620: 4681 li a3,0 + 5622: 4785 li a5,1 + 5624: fea04ce3 bgtz a0,561c <__divdf3+0x4a4> + 5628: 58fd li a7,-1 + 562a: d0051ce3 bnez a0,5342 <__divdf3+0x1ca> + 562e: c0100493 li s1,-1023 + 5632: 4785 li a5,1 + 5634: 41e48513 addi a0,s1,1054 + 5638: 00a716b3 sll a3,a4,a0 + 563c: 00f8d633 srl a2,a7,a5 + 5640: 00a89533 sll a0,a7,a0 + 5644: 8ed1 or a3,a3,a2 + 5646: 00a03533 snez a0,a0 + 564a: 8ec9 or a3,a3,a0 + 564c: 0076f613 andi a2,a3,7 + 5650: 00f75733 srl a4,a4,a5 + 5654: ce01 beqz a2,566c <__divdf3+0x4f4> + 5656: 00f6f793 andi a5,a3,15 + 565a: 4611 li a2,4 + 565c: 00c78863 beq a5,a2,566c <__divdf3+0x4f4> + 5660: 00468793 addi a5,a3,4 + 5664: 00d7b6b3 sltu a3,a5,a3 + 5668: 9736 add a4,a4,a3 + 566a: 86be mv a3,a5 + 566c: 00871793 slli a5,a4,0x8 + 5670: 0407d863 bgez a5,56c0 <__divdf3+0x548> + 5674: 4605 li a2,1 + 5676: 4781 li a5,0 + 5678: 4701 li a4,0 + 567a: b6f1 j 5246 <__divdf3+0xce> + 567c: 8736 mv a4,a3 + 567e: bb7d j 543c <__divdf3+0x2c4> + 5680: 87b2 mv a5,a2 + 5682: b379 j 5410 <__divdf3+0x298> + 5684: 46fd li a3,31 + 5686: faf6d7e3 bge a3,a5,5634 <__divdf3+0x4bc> + 568a: 5605 li a2,-31 + 568c: 8e09 sub a2,a2,a0 + 568e: 02000693 li a3,32 + 5692: 00c75633 srl a2,a4,a2 + 5696: 00d78863 beq a5,a3,56a6 <__divdf3+0x52e> + 569a: 43e48793 addi a5,s1,1086 + 569e: 00f717b3 sll a5,a4,a5 + 56a2: 00f8e8b3 or a7,a7,a5 + 56a6: 011036b3 snez a3,a7 + 56aa: 8ed1 or a3,a3,a2 + 56ac: 0076f613 andi a2,a3,7 + 56b0: 4781 li a5,0 + 56b2: ce01 beqz a2,56ca <__divdf3+0x552> + 56b4: 00f6f793 andi a5,a3,15 + 56b8: 4611 li a2,4 + 56ba: 4701 li a4,0 + 56bc: fac792e3 bne a5,a2,5660 <__divdf3+0x4e8> + 56c0: 00971793 slli a5,a4,0x9 + 56c4: 01d71613 slli a2,a4,0x1d + 56c8: 83b1 srli a5,a5,0xc + 56ca: 0036d713 srli a4,a3,0x3 + 56ce: 8f51 or a4,a4,a2 + 56d0: 4601 li a2,0 + 56d2: be95 j 5246 <__divdf3+0xce> + 56d4: f0cb70e3 bgeu s6,a2,55d4 <__divdf3+0x45c> + 56d8: 9b72 add s6,s6,t3 + 56da: 01cb3533 sltu a0,s6,t3 + 56de: 951a add a0,a0,t1 + 56e0: 1779 addi a4,a4,-2 + 56e2: 96aa add a3,a3,a0 + 56e4: bb4d j 5496 <__divdf3+0x31e> + 56e6: 88ae mv a7,a1 + 56e8: bbc5 j 54d8 <__divdf3+0x360> + 56ea: 86ae mv a3,a1 + 56ec: bd31 j 5508 <__divdf3+0x390> + 56ee: 001e1793 slli a5,t3,0x1 + 56f2: 01c7be33 sltu t3,a5,t3 + 56f6: 9372 add t1,t1,t3 + 56f8: 961a add a2,a2,t1 + 56fa: 18f9 addi a7,a7,-2 + 56fc: 8e3e mv t3,a5 + 56fe: e7f615e3 bne a2,t6,5568 <__divdf3+0x3f0> + 5702: c6de07e3 beq t3,a3,5370 <__divdf3+0x1f8> + 5706: 0018e893 ori a7,a7,1 + 570a: b19d j 5370 <__divdf3+0x1f8> + 570c: 88be mv a7,a5 + 570e: fff60ae3 beq a2,t6,5702 <__divdf3+0x58a> + 5712: bd99 j 5568 <__divdf3+0x3f0> + 5714: 8836 mv a6,a3 + 5716: 7ff00613 li a2,2047 + 571a: 4781 li a5,0 + 571c: 4701 li a4,0 + 571e: b625 j 5246 <__divdf3+0xce> + 5720: fcde67e3 bltu t3,a3,56ee <__divdf3+0x576> + 5724: 88be mv a7,a5 + 5726: fede10e3 bne t3,a3,5706 <__divdf3+0x58e> + 572a: b199 j 5370 <__divdf3+0x1f8> + +0000572c <__eqdf2>: + 572c: 0145d713 srli a4,a1,0x14 + 5730: 001007b7 lui a5,0x100 + 5734: 17fd addi a5,a5,-1 + 5736: 0146d813 srli a6,a3,0x14 + 573a: 7ff77713 andi a4,a4,2047 + 573e: 7ff00893 li a7,2047 + 5742: 00b7fe33 and t3,a5,a1 + 5746: 8eaa mv t4,a0 + 5748: 8ff5 and a5,a5,a3 + 574a: 81fd srli a1,a1,0x1f + 574c: 8f32 mv t5,a2 + 574e: 7ff87813 andi a6,a6,2047 + 5752: 82fd srli a3,a3,0x1f + 5754: 01170b63 beq a4,a7,576a <__eqdf2+0x3e> + 5758: 4305 li t1,1 + 575a: 01180663 beq a6,a7,5766 <__eqdf2+0x3a> + 575e: 01071463 bne a4,a6,5766 <__eqdf2+0x3a> + 5762: 00fe0d63 beq t3,a5,577c <__eqdf2+0x50> + 5766: 851a mv a0,t1 + 5768: 8082 ret + 576a: 00ae68b3 or a7,t3,a0 + 576e: 4305 li t1,1 + 5770: fe089be3 bnez a7,5766 <__eqdf2+0x3a> + 5774: fee819e3 bne a6,a4,5766 <__eqdf2+0x3a> + 5778: 8fd1 or a5,a5,a2 + 577a: f7f5 bnez a5,5766 <__eqdf2+0x3a> + 577c: 4305 li t1,1 + 577e: ffee94e3 bne t4,t5,5766 <__eqdf2+0x3a> + 5782: 4301 li t1,0 + 5784: fed581e3 beq a1,a3,5766 <__eqdf2+0x3a> + 5788: 4305 li t1,1 + 578a: ff71 bnez a4,5766 <__eqdf2+0x3a> + 578c: 00ae6533 or a0,t3,a0 + 5790: 00a03333 snez t1,a0 + 5794: bfc9 j 5766 <__eqdf2+0x3a> + +00005796 <__gedf2>: + 5796: 0145d713 srli a4,a1,0x14 + 579a: 001007b7 lui a5,0x100 + 579e: 17fd addi a5,a5,-1 + 57a0: 0146d813 srli a6,a3,0x14 + 57a4: 7ff77713 andi a4,a4,2047 + 57a8: 7ff00893 li a7,2047 + 57ac: 00b7f333 and t1,a5,a1 + 57b0: 8e2a mv t3,a0 + 57b2: 8ff5 and a5,a5,a3 + 57b4: 81fd srli a1,a1,0x1f + 57b6: 8eb2 mv t4,a2 + 57b8: 7ff87813 andi a6,a6,2047 + 57bc: 82fd srli a3,a3,0x1f + 57be: 03170863 beq a4,a7,57ee <__gedf2+0x58> + 57c2: 03180063 beq a6,a7,57e2 <__gedf2+0x4c> + 57c6: eb0d bnez a4,57f8 <__gedf2+0x62> + 57c8: 00a368b3 or a7,t1,a0 + 57cc: 00081463 bnez a6,57d4 <__gedf2+0x3e> + 57d0: 8e5d or a2,a2,a5 + 57d2: ca29 beqz a2,5824 <__gedf2+0x8e> + 57d4: 04088563 beqz a7,581e <__gedf2+0x88> + 57d8: 02d58863 beq a1,a3,5808 <__gedf2+0x72> + 57dc: 4505 li a0,1 + 57de: ed95 bnez a1,581a <__gedf2+0x84> + 57e0: 8082 ret + 57e2: 00c7e8b3 or a7,a5,a2 + 57e6: fe0880e3 beqz a7,57c6 <__gedf2+0x30> + 57ea: 5579 li a0,-2 + 57ec: 8082 ret + 57ee: 00a36533 or a0,t1,a0 + 57f2: fd65 bnez a0,57ea <__gedf2+0x54> + 57f4: 02e80c63 beq a6,a4,582c <__gedf2+0x96> + 57f8: 00081463 bnez a6,5800 <__gedf2+0x6a> + 57fc: 8e5d or a2,a2,a5 + 57fe: de79 beqz a2,57dc <__gedf2+0x46> + 5800: fcd59ee3 bne a1,a3,57dc <__gedf2+0x46> + 5804: fce84ce3 blt a6,a4,57dc <__gedf2+0x46> + 5808: 01074863 blt a4,a6,5818 <__gedf2+0x82> + 580c: fc67e8e3 bltu a5,t1,57dc <__gedf2+0x46> + 5810: 02f30363 beq t1,a5,5836 <__gedf2+0xa0> + 5814: 00f37f63 bgeu t1,a5,5832 <__gedf2+0x9c> + 5818: e581 bnez a1,5820 <__gedf2+0x8a> + 581a: 557d li a0,-1 + 581c: 8082 ret + 581e: def5 beqz a3,581a <__gedf2+0x84> + 5820: 4505 li a0,1 + 5822: 8082 ret + 5824: 4501 li a0,0 + 5826: fa089be3 bnez a7,57dc <__gedf2+0x46> + 582a: 8082 ret + 582c: 8e5d or a2,a2,a5 + 582e: da69 beqz a2,5800 <__gedf2+0x6a> + 5830: bf6d j 57ea <__gedf2+0x54> + 5832: 4501 li a0,0 + 5834: 8082 ret + 5836: fbcee3e3 bltu t4,t3,57dc <__gedf2+0x46> + 583a: 4501 li a0,0 + 583c: fbde72e3 bgeu t3,t4,57e0 <__gedf2+0x4a> + 5840: f1e5 bnez a1,5820 <__gedf2+0x8a> + 5842: bfe1 j 581a <__gedf2+0x84> + +00005844 <__ledf2>: + 5844: 0145d713 srli a4,a1,0x14 + 5848: 001007b7 lui a5,0x100 + 584c: 17fd addi a5,a5,-1 + 584e: 0146d813 srli a6,a3,0x14 + 5852: 7ff77713 andi a4,a4,2047 + 5856: 7ff00893 li a7,2047 + 585a: 00b7fe33 and t3,a5,a1 + 585e: 8eaa mv t4,a0 + 5860: 8ff5 and a5,a5,a3 + 5862: 81fd srli a1,a1,0x1f + 5864: 8f32 mv t5,a2 + 5866: 7ff87813 andi a6,a6,2047 + 586a: 82fd srli a3,a3,0x1f + 586c: 03170e63 beq a4,a7,58a8 <__ledf2+0x64> + 5870: 01180d63 beq a6,a7,588a <__ledf2+0x46> + 5874: e329 bnez a4,58b6 <__ledf2+0x72> + 5876: 00ae68b3 or a7,t3,a0 + 587a: 00081f63 bnez a6,5898 <__ledf2+0x54> + 587e: 8e5d or a2,a2,a5 + 5880: ee01 bnez a2,5898 <__ledf2+0x54> + 5882: 4301 li t1,0 + 5884: 04088c63 beqz a7,58dc <__ledf2+0x98> + 5888: a821 j 58a0 <__ledf2+0x5c> + 588a: 00c7e8b3 or a7,a5,a2 + 588e: 4309 li t1,2 + 5890: 04089663 bnez a7,58dc <__ledf2+0x98> + 5894: d36d beqz a4,5876 <__ledf2+0x32> + 5896: a005 j 58b6 <__ledf2+0x72> + 5898: 04088463 beqz a7,58e0 <__ledf2+0x9c> + 589c: 02d58563 beq a1,a3,58c6 <__ledf2+0x82> + 58a0: 4305 li t1,1 + 58a2: cd8d beqz a1,58dc <__ledf2+0x98> + 58a4: 537d li t1,-1 + 58a6: a81d j 58dc <__ledf2+0x98> + 58a8: 00ae68b3 or a7,t3,a0 + 58ac: 4309 li t1,2 + 58ae: 02089763 bnez a7,58dc <__ledf2+0x98> + 58b2: 02e80a63 beq a6,a4,58e6 <__ledf2+0xa2> + 58b6: 00081463 bnez a6,58be <__ledf2+0x7a> + 58ba: 8e5d or a2,a2,a5 + 58bc: d275 beqz a2,58a0 <__ledf2+0x5c> + 58be: fed591e3 bne a1,a3,58a0 <__ledf2+0x5c> + 58c2: fce84fe3 blt a6,a4,58a0 <__ledf2+0x5c> + 58c6: 01074963 blt a4,a6,58d8 <__ledf2+0x94> + 58ca: fdc7ebe3 bltu a5,t3,58a0 <__ledf2+0x5c> + 58ce: 00fe0f63 beq t3,a5,58ec <__ledf2+0xa8> + 58d2: 4301 li t1,0 + 58d4: 00fe7463 bgeu t3,a5,58dc <__ledf2+0x98> + 58d8: d5f1 beqz a1,58a4 <__ledf2+0x60> + 58da: 4305 li t1,1 + 58dc: 851a mv a0,t1 + 58de: 8082 ret + 58e0: feed bnez a3,58da <__ledf2+0x96> + 58e2: 537d li t1,-1 + 58e4: bfe5 j 58dc <__ledf2+0x98> + 58e6: 8e5d or a2,a2,a5 + 58e8: da79 beqz a2,58be <__ledf2+0x7a> + 58ea: bfcd j 58dc <__ledf2+0x98> + 58ec: fbdf6ae3 bltu t5,t4,58a0 <__ledf2+0x5c> + 58f0: 4301 li t1,0 + 58f2: ffeef5e3 bgeu t4,t5,58dc <__ledf2+0x98> + 58f6: f1f5 bnez a1,58da <__ledf2+0x96> + 58f8: b775 j 58a4 <__ledf2+0x60> + +000058fa <__muldf3>: + 58fa: 7139 addi sp,sp,-64 + 58fc: d84a sw s2,48(sp) + 58fe: 0145d913 srli s2,a1,0x14 + 5902: d64e sw s3,44(sp) + 5904: d452 sw s4,40(sp) + 5906: d256 sw s5,36(sp) + 5908: 00c59993 slli s3,a1,0xc + 590c: de06 sw ra,60(sp) + 590e: dc22 sw s0,56(sp) + 5910: da26 sw s1,52(sp) + 5912: d05a sw s6,32(sp) + 5914: ce5e sw s7,28(sp) + 5916: 7ff97913 andi s2,s2,2047 + 591a: 8a2a mv s4,a0 + 591c: 00c9d993 srli s3,s3,0xc + 5920: 01f5da93 srli s5,a1,0x1f + 5924: 0e090d63 beqz s2,5a1e <__muldf3+0x124> + 5928: 7ff00793 li a5,2047 + 592c: 18f90663 beq s2,a5,5ab8 <__muldf3+0x1be> + 5930: 01d55413 srli s0,a0,0x1d + 5934: 098e slli s3,s3,0x3 + 5936: 013469b3 or s3,s0,s3 + 593a: 00800437 lui s0,0x800 + 593e: 0089e433 or s0,s3,s0 + 5942: 00351493 slli s1,a0,0x3 + 5946: c0190913 addi s2,s2,-1023 + 594a: 4981 li s3,0 + 594c: 4b81 li s7,0 + 594e: 0146d713 srli a4,a3,0x14 + 5952: 00c69a13 slli s4,a3,0xc + 5956: 7ff77713 andi a4,a4,2047 + 595a: 85b2 mv a1,a2 + 595c: 00ca5a13 srli s4,s4,0xc + 5960: 01f6db13 srli s6,a3,0x1f + 5964: 10070b63 beqz a4,5a7a <__muldf3+0x180> + 5968: 7ff00793 li a5,2047 + 596c: 04f70363 beq a4,a5,59b2 <__muldf3+0xb8> + 5970: 01d65793 srli a5,a2,0x1d + 5974: 0a0e slli s4,s4,0x3 + 5976: 0147ea33 or s4,a5,s4 + 597a: c0170713 addi a4,a4,-1023 + 597e: 008007b7 lui a5,0x800 + 5982: 00fa67b3 or a5,s4,a5 + 5986: 00361593 slli a1,a2,0x3 + 598a: 993a add s2,s2,a4 + 598c: 4881 li a7,0 + 598e: 016ac733 xor a4,s5,s6 + 5992: 46bd li a3,15 + 5994: 853a mv a0,a4 + 5996: 00190813 addi a6,s2,1 + 599a: 1736e863 bltu a3,s3,5b0a <__muldf3+0x210> + 599e: 00007617 auipc a2,0x7 + 59a2: bb260613 addi a2,a2,-1102 # c550 <_exit+0x540> + 59a6: 098a slli s3,s3,0x2 + 59a8: 99b2 add s3,s3,a2 + 59aa: 0009a683 lw a3,0(s3) # 7ff80000 <_eusrstack+0x5ff70000> + 59ae: 96b2 add a3,a3,a2 + 59b0: 8682 jr a3 + 59b2: 00ca67b3 or a5,s4,a2 + 59b6: 7ff90913 addi s2,s2,2047 + 59ba: 12079963 bnez a5,5aec <__muldf3+0x1f2> + 59be: 0029e993 ori s3,s3,2 + 59c2: 4581 li a1,0 + 59c4: 4889 li a7,2 + 59c6: b7e1 j 598e <__muldf3+0x94> + 59c8: 4701 li a4,0 + 59ca: 7ff00793 li a5,2047 + 59ce: 00080437 lui s0,0x80 + 59d2: 4481 li s1,0 + 59d4: 0432 slli s0,s0,0xc + 59d6: 07d2 slli a5,a5,0x14 + 59d8: 8031 srli s0,s0,0xc + 59da: 077e slli a4,a4,0x1f + 59dc: 8c5d or s0,s0,a5 + 59de: 8c59 or s0,s0,a4 + 59e0: 85a2 mv a1,s0 + 59e2: 50f2 lw ra,60(sp) + 59e4: 5462 lw s0,56(sp) + 59e6: 8526 mv a0,s1 + 59e8: 5942 lw s2,48(sp) + 59ea: 54d2 lw s1,52(sp) + 59ec: 59b2 lw s3,44(sp) + 59ee: 5a22 lw s4,40(sp) + 59f0: 5a92 lw s5,36(sp) + 59f2: 5b02 lw s6,32(sp) + 59f4: 4bf2 lw s7,28(sp) + 59f6: 6121 addi sp,sp,64 + 59f8: 8082 ret + 59fa: 855a mv a0,s6 + 59fc: 843e mv s0,a5 + 59fe: 84ae mv s1,a1 + 5a00: 8bc6 mv s7,a7 + 5a02: 4789 li a5,2 + 5a04: 0efb8d63 beq s7,a5,5afe <__muldf3+0x204> + 5a08: 478d li a5,3 + 5a0a: fafb8fe3 beq s7,a5,59c8 <__muldf3+0xce> + 5a0e: 4785 li a5,1 + 5a10: 872a mv a4,a0 + 5a12: 38fb9e63 bne s7,a5,5dae <__muldf3+0x4b4> + 5a16: 4781 li a5,0 + 5a18: 4401 li s0,0 + 5a1a: 4481 li s1,0 + 5a1c: bf65 j 59d4 <__muldf3+0xda> + 5a1e: 00a9e433 or s0,s3,a0 + 5a22: c061 beqz s0,5ae2 <__muldf3+0x1e8> + 5a24: c636 sw a3,12(sp) + 5a26: c432 sw a2,8(sp) + 5a28: 2a098c63 beqz s3,5ce0 <__muldf3+0x3e6> + 5a2c: 854e mv a0,s3 + 5a2e: 3fd000ef jal ra,662a <__clzsi2> + 5a32: 4622 lw a2,8(sp) + 5a34: 46b2 lw a3,12(sp) + 5a36: 87aa mv a5,a0 + 5a38: ff550713 addi a4,a0,-11 + 5a3c: 4475 li s0,29 + 5a3e: ff878493 addi s1,a5,-8 # 7ffff8 <_data_lma+0x7f3560> + 5a42: 8c19 sub s0,s0,a4 + 5a44: 009999b3 sll s3,s3,s1 + 5a48: 008a5433 srl s0,s4,s0 + 5a4c: 01346433 or s0,s0,s3 + 5a50: 009a14b3 sll s1,s4,s1 + 5a54: 0146d713 srli a4,a3,0x14 + 5a58: c0d00913 li s2,-1011 + 5a5c: 00c69a13 slli s4,a3,0xc + 5a60: 7ff77713 andi a4,a4,2047 + 5a64: 40f90933 sub s2,s2,a5 + 5a68: 4981 li s3,0 + 5a6a: 4b81 li s7,0 + 5a6c: 85b2 mv a1,a2 + 5a6e: 00ca5a13 srli s4,s4,0xc + 5a72: 01f6db13 srli s6,a3,0x1f + 5a76: ee0719e3 bnez a4,5968 <__muldf3+0x6e> + 5a7a: 00ca67b3 or a5,s4,a2 + 5a7e: c7b1 beqz a5,5aca <__muldf3+0x1d0> + 5a80: 220a0f63 beqz s4,5cbe <__muldf3+0x3c4> + 5a84: 8552 mv a0,s4 + 5a86: c432 sw a2,8(sp) + 5a88: 3a3000ef jal ra,662a <__clzsi2> + 5a8c: 4622 lw a2,8(sp) + 5a8e: 872a mv a4,a0 + 5a90: ff550693 addi a3,a0,-11 + 5a94: 47f5 li a5,29 + 5a96: ff870593 addi a1,a4,-8 + 5a9a: 8f95 sub a5,a5,a3 + 5a9c: 00ba1a33 sll s4,s4,a1 + 5aa0: 00f657b3 srl a5,a2,a5 + 5aa4: 0147e7b3 or a5,a5,s4 + 5aa8: 00b615b3 sll a1,a2,a1 + 5aac: 40e90933 sub s2,s2,a4 + 5ab0: c0d90913 addi s2,s2,-1011 + 5ab4: 4881 li a7,0 + 5ab6: bde1 j 598e <__muldf3+0x94> + 5ab8: 00a9e433 or s0,s3,a0 + 5abc: ec01 bnez s0,5ad4 <__muldf3+0x1da> + 5abe: 49a1 li s3,8 + 5ac0: 4481 li s1,0 + 5ac2: 7ff00913 li s2,2047 + 5ac6: 4b89 li s7,2 + 5ac8: b559 j 594e <__muldf3+0x54> + 5aca: 0019e993 ori s3,s3,1 + 5ace: 4581 li a1,0 + 5ad0: 4885 li a7,1 + 5ad2: bd75 j 598e <__muldf3+0x94> + 5ad4: 844e mv s0,s3 + 5ad6: 84aa mv s1,a0 + 5ad8: 49b1 li s3,12 + 5ada: 7ff00913 li s2,2047 + 5ade: 4b8d li s7,3 + 5ae0: b5bd j 594e <__muldf3+0x54> + 5ae2: 4991 li s3,4 + 5ae4: 4481 li s1,0 + 5ae6: 4901 li s2,0 + 5ae8: 4b85 li s7,1 + 5aea: b595 j 594e <__muldf3+0x54> + 5aec: 0039e993 ori s3,s3,3 + 5af0: 87d2 mv a5,s4 + 5af2: 488d li a7,3 + 5af4: bd69 j 598e <__muldf3+0x94> + 5af6: 4789 li a5,2 + 5af8: 8556 mv a0,s5 + 5afa: f0fb97e3 bne s7,a5,5a08 <__muldf3+0x10e> + 5afe: 872a mv a4,a0 + 5b00: 7ff00793 li a5,2047 + 5b04: 4401 li s0,0 + 5b06: 4481 li s1,0 + 5b08: b5f1 j 59d4 <__muldf3+0xda> + 5b0a: 6ec1 lui t4,0x10 + 5b0c: fffe8613 addi a2,t4,-1 # ffff <_data_lma+0x3567> + 5b10: 0104d693 srli a3,s1,0x10 + 5b14: 0105de13 srli t3,a1,0x10 + 5b18: 8cf1 and s1,s1,a2 + 5b1a: 8df1 and a1,a1,a2 + 5b1c: 02958633 mul a2,a1,s1 + 5b20: 02b68333 mul t1,a3,a1 + 5b24: 01065893 srli a7,a2,0x10 + 5b28: 029e0533 mul a0,t3,s1 + 5b2c: 951a add a0,a0,t1 + 5b2e: 98aa add a7,a7,a0 + 5b30: 03c682b3 mul t0,a3,t3 + 5b34: 0068f363 bgeu a7,t1,5b3a <__muldf3+0x240> + 5b38: 92f6 add t0,t0,t4 + 5b3a: 6fc1 lui t6,0x10 + 5b3c: ffff8313 addi t1,t6,-1 # ffff <_data_lma+0x3567> + 5b40: 0067f533 and a0,a5,t1 + 5b44: 0107d393 srli t2,a5,0x10 + 5b48: 0068f7b3 and a5,a7,t1 + 5b4c: 07c2 slli a5,a5,0x10 + 5b4e: 00667333 and t1,a2,t1 + 5b52: 933e add t1,t1,a5 + 5b54: 02950633 mul a2,a0,s1 + 5b58: 0108d893 srli a7,a7,0x10 + 5b5c: 02a687b3 mul a5,a3,a0 + 5b60: 01065f13 srli t5,a2,0x10 + 5b64: 029384b3 mul s1,t2,s1 + 5b68: 94be add s1,s1,a5 + 5b6a: 94fa add s1,s1,t5 + 5b6c: 02768eb3 mul t4,a3,t2 + 5b70: 00f4f363 bgeu s1,a5,5b76 <__muldf3+0x27c> + 5b74: 9efe add t4,t4,t6 + 5b76: 6a41 lui s4,0x10 + 5b78: fffa0793 addi a5,s4,-1 # ffff <_data_lma+0x3567> + 5b7c: 01045f93 srli t6,s0,0x10 + 5b80: 00f476b3 and a3,s0,a5 + 5b84: 00f4f9b3 and s3,s1,a5 + 5b88: 8e7d and a2,a2,a5 + 5b8a: 80c1 srli s1,s1,0x10 + 5b8c: 02d58433 mul s0,a1,a3 + 5b90: 09c2 slli s3,s3,0x10 + 5b92: 01d48f33 add t5,s1,t4 + 5b96: 99b2 add s3,s3,a2 + 5b98: 98ce add a7,a7,s3 + 5b9a: 02de07b3 mul a5,t3,a3 + 5b9e: 01045e93 srli t4,s0,0x10 + 5ba2: 02bf85b3 mul a1,t6,a1 + 5ba6: 97ae add a5,a5,a1 + 5ba8: 9ebe add t4,t4,a5 + 5baa: 03fe0e33 mul t3,t3,t6 + 5bae: 00bef363 bgeu t4,a1,5bb4 <__muldf3+0x2ba> + 5bb2: 9e52 add t3,t3,s4 + 5bb4: 67c1 lui a5,0x10 + 5bb6: fff78593 addi a1,a5,-1 # ffff <_data_lma+0x3567> + 5bba: 00bef633 and a2,t4,a1 + 5bbe: 8c6d and s0,s0,a1 + 5bc0: 0642 slli a2,a2,0x10 + 5bc2: 9622 add a2,a2,s0 + 5bc4: 010ede93 srli t4,t4,0x10 + 5bc8: 02d505b3 mul a1,a0,a3 + 5bcc: 9e76 add t3,t3,t4 + 5bce: 02af8533 mul a0,t6,a0 + 5bd2: 0105d413 srli s0,a1,0x10 + 5bd6: 02d386b3 mul a3,t2,a3 + 5bda: 96aa add a3,a3,a0 + 5bdc: 96a2 add a3,a3,s0 + 5bde: 03f38fb3 mul t6,t2,t6 + 5be2: 00a6f363 bgeu a3,a0,5be8 <__muldf3+0x2ee> + 5be6: 9fbe add t6,t6,a5 + 5be8: 6541 lui a0,0x10 + 5bea: 157d addi a0,a0,-1 + 5bec: 00a6f7b3 and a5,a3,a0 + 5bf0: 07c2 slli a5,a5,0x10 + 5bf2: 8d6d and a0,a0,a1 + 5bf4: 97aa add a5,a5,a0 + 5bf6: 005885b3 add a1,a7,t0 + 5bfa: 0135b9b3 sltu s3,a1,s3 + 5bfe: 97fa add a5,a5,t5 + 5c00: 95b2 add a1,a1,a2 + 5c02: 01378433 add s0,a5,s3 + 5c06: 00c5b633 sltu a2,a1,a2 + 5c0a: 01c40eb3 add t4,s0,t3 + 5c0e: 00ce8533 add a0,t4,a2 + 5c12: 01343433 sltu s0,s0,s3 + 5c16: 01e7b7b3 sltu a5,a5,t5 + 5c1a: 8fc1 or a5,a5,s0 + 5c1c: 01cebe33 sltu t3,t4,t3 + 5c20: 0106d413 srli s0,a3,0x10 + 5c24: 00c53633 sltu a2,a0,a2 + 5c28: 943e add s0,s0,a5 + 5c2a: 00ce6633 or a2,t3,a2 + 5c2e: 00959493 slli s1,a1,0x9 + 5c32: 9432 add s0,s0,a2 + 5c34: 947e add s0,s0,t6 + 5c36: 0064e4b3 or s1,s1,t1 + 5c3a: 0426 slli s0,s0,0x9 + 5c3c: 01755693 srli a3,a0,0x17 + 5c40: 009034b3 snez s1,s1 + 5c44: 81dd srli a1,a1,0x17 + 5c46: 00951793 slli a5,a0,0x9 + 5c4a: 8ccd or s1,s1,a1 + 5c4c: 8c55 or s0,s0,a3 + 5c4e: 8cdd or s1,s1,a5 + 5c50: 00741793 slli a5,s0,0x7 + 5c54: 0007db63 bgez a5,5c6a <__muldf3+0x370> + 5c58: 0014d793 srli a5,s1,0x1 + 5c5c: 8885 andi s1,s1,1 + 5c5e: 01f41693 slli a3,s0,0x1f + 5c62: 8cdd or s1,s1,a5 + 5c64: 8cd5 or s1,s1,a3 + 5c66: 8005 srli s0,s0,0x1 + 5c68: 8942 mv s2,a6 + 5c6a: 3ff90793 addi a5,s2,1023 + 5c6e: 08f05963 blez a5,5d00 <__muldf3+0x406> + 5c72: 0074f693 andi a3,s1,7 + 5c76: ce81 beqz a3,5c8e <__muldf3+0x394> + 5c78: 00f4f693 andi a3,s1,15 + 5c7c: 4611 li a2,4 + 5c7e: 00c68863 beq a3,a2,5c8e <__muldf3+0x394> + 5c82: 00448693 addi a3,s1,4 + 5c86: 0096b4b3 sltu s1,a3,s1 + 5c8a: 9426 add s0,s0,s1 + 5c8c: 84b6 mv s1,a3 + 5c8e: 00741693 slli a3,s0,0x7 + 5c92: 0006d863 bgez a3,5ca2 <__muldf3+0x3a8> + 5c96: ff0007b7 lui a5,0xff000 + 5c9a: 17fd addi a5,a5,-1 + 5c9c: 8c7d and s0,s0,a5 + 5c9e: 40090793 addi a5,s2,1024 + 5ca2: 7fe00693 li a3,2046 + 5ca6: 0ef6cf63 blt a3,a5,5da4 <__muldf3+0x4aa> + 5caa: 0034d693 srli a3,s1,0x3 + 5cae: 01d41493 slli s1,s0,0x1d + 5cb2: 0426 slli s0,s0,0x9 + 5cb4: 8cd5 or s1,s1,a3 + 5cb6: 8031 srli s0,s0,0xc + 5cb8: 7ff7f793 andi a5,a5,2047 + 5cbc: bb21 j 59d4 <__muldf3+0xda> + 5cbe: 8532 mv a0,a2 + 5cc0: c432 sw a2,8(sp) + 5cc2: 169000ef jal ra,662a <__clzsi2> + 5cc6: 01550693 addi a3,a0,21 # 10015 <_data_lma+0x357d> + 5cca: 47f1 li a5,28 + 5ccc: 02050713 addi a4,a0,32 + 5cd0: 4622 lw a2,8(sp) + 5cd2: dcd7d1e3 bge a5,a3,5a94 <__muldf3+0x19a> + 5cd6: 1561 addi a0,a0,-8 + 5cd8: 00a617b3 sll a5,a2,a0 + 5cdc: 4581 li a1,0 + 5cde: b3f9 j 5aac <__muldf3+0x1b2> + 5ce0: 14b000ef jal ra,662a <__clzsi2> + 5ce4: 01550713 addi a4,a0,21 + 5ce8: 45f1 li a1,28 + 5cea: 02050793 addi a5,a0,32 + 5cee: 4622 lw a2,8(sp) + 5cf0: 46b2 lw a3,12(sp) + 5cf2: d4e5d5e3 bge a1,a4,5a3c <__muldf3+0x142> + 5cf6: 1561 addi a0,a0,-8 + 5cf8: 00aa1433 sll s0,s4,a0 + 5cfc: 4481 li s1,0 + 5cfe: bb99 j 5a54 <__muldf3+0x15a> + 5d00: 4685 li a3,1 + 5d02: 8e9d sub a3,a3,a5 + 5d04: e7b1 bnez a5,5d50 <__muldf3+0x456> + 5d06: 41e90913 addi s2,s2,1054 + 5d0a: 012497b3 sll a5,s1,s2 + 5d0e: 00d4d4b3 srl s1,s1,a3 + 5d12: 01241933 sll s2,s0,s2 + 5d16: 00f037b3 snez a5,a5 + 5d1a: 009964b3 or s1,s2,s1 + 5d1e: 8cdd or s1,s1,a5 + 5d20: 0074f793 andi a5,s1,7 + 5d24: 00d456b3 srl a3,s0,a3 + 5d28: cf81 beqz a5,5d40 <__muldf3+0x446> + 5d2a: 00f4f793 andi a5,s1,15 + 5d2e: 4611 li a2,4 + 5d30: 00c78863 beq a5,a2,5d40 <__muldf3+0x446> + 5d34: 00448793 addi a5,s1,4 + 5d38: 0097b4b3 sltu s1,a5,s1 + 5d3c: 96a6 add a3,a3,s1 + 5d3e: 84be mv s1,a5 + 5d40: 00869793 slli a5,a3,0x8 + 5d44: 0407d863 bgez a5,5d94 <__muldf3+0x49a> + 5d48: 4785 li a5,1 + 5d4a: 4401 li s0,0 + 5d4c: 4481 li s1,0 + 5d4e: b159 j 59d4 <__muldf3+0xda> + 5d50: 03800613 li a2,56 + 5d54: ccd641e3 blt a2,a3,5a16 <__muldf3+0x11c> + 5d58: 467d li a2,31 + 5d5a: fad656e3 bge a2,a3,5d06 <__muldf3+0x40c> + 5d5e: 5605 li a2,-31 + 5d60: 40f607b3 sub a5,a2,a5 + 5d64: 02000593 li a1,32 + 5d68: 00f45633 srl a2,s0,a5 + 5d6c: 00b68763 beq a3,a1,5d7a <__muldf3+0x480> + 5d70: 43e90913 addi s2,s2,1086 + 5d74: 012417b3 sll a5,s0,s2 + 5d78: 8cdd or s1,s1,a5 + 5d7a: 009034b3 snez s1,s1 + 5d7e: 8cd1 or s1,s1,a2 + 5d80: 0074f693 andi a3,s1,7 + 5d84: 4401 li s0,0 + 5d86: ca99 beqz a3,5d9c <__muldf3+0x4a2> + 5d88: 00f4f793 andi a5,s1,15 + 5d8c: 4611 li a2,4 + 5d8e: 4681 li a3,0 + 5d90: fac792e3 bne a5,a2,5d34 <__muldf3+0x43a> + 5d94: 00969413 slli s0,a3,0x9 + 5d98: 8031 srli s0,s0,0xc + 5d9a: 06f6 slli a3,a3,0x1d + 5d9c: 808d srli s1,s1,0x3 + 5d9e: 8cd5 or s1,s1,a3 + 5da0: 4781 li a5,0 + 5da2: b90d j 59d4 <__muldf3+0xda> + 5da4: 7ff00793 li a5,2047 + 5da8: 4401 li s0,0 + 5daa: 4481 li s1,0 + 5dac: b125 j 59d4 <__muldf3+0xda> + 5dae: 8942 mv s2,a6 + 5db0: bd6d j 5c6a <__muldf3+0x370> + +00005db2 <__subdf3>: + 5db2: 00100737 lui a4,0x100 + 5db6: 177d addi a4,a4,-1 + 5db8: 1101 addi sp,sp,-32 + 5dba: 00b77333 and t1,a4,a1 + 5dbe: 0146d893 srli a7,a3,0x14 + 5dc2: 8f75 and a4,a4,a3 + 5dc4: 01d65e93 srli t4,a2,0x1d + 5dc8: cc22 sw s0,24(sp) + 5dca: ca26 sw s1,20(sp) + 5dcc: 030e slli t1,t1,0x3 + 5dce: 0145d493 srli s1,a1,0x14 + 5dd2: 01d55793 srli a5,a0,0x1d + 5dd6: 070e slli a4,a4,0x3 + 5dd8: ce06 sw ra,28(sp) + 5dda: c84a sw s2,16(sp) + 5ddc: c64e sw s3,12(sp) + 5dde: 7ff8f893 andi a7,a7,2047 + 5de2: 7ff00e13 li t3,2047 + 5de6: 00eee733 or a4,t4,a4 + 5dea: 7ff4f493 andi s1,s1,2047 + 5dee: 01f5d413 srli s0,a1,0x1f + 5df2: 0067e333 or t1,a5,t1 + 5df6: 00351f13 slli t5,a0,0x3 + 5dfa: 82fd srli a3,a3,0x1f + 5dfc: 00361e93 slli t4,a2,0x3 + 5e00: 17c88f63 beq a7,t3,5f7e <__subdf3+0x1cc> + 5e04: 0016c693 xori a3,a3,1 + 5e08: 411485b3 sub a1,s1,a7 + 5e0c: 12d40463 beq s0,a3,5f34 <__subdf3+0x182> + 5e10: 18b05063 blez a1,5f90 <__subdf3+0x1de> + 5e14: 1a088a63 beqz a7,5fc8 <__subdf3+0x216> + 5e18: 008007b7 lui a5,0x800 + 5e1c: 8f5d or a4,a4,a5 + 5e1e: 57c48f63 beq s1,t3,639c <__subdf3+0x5ea> + 5e22: 03800793 li a5,56 + 5e26: 34b7c263 blt a5,a1,616a <__subdf3+0x3b8> + 5e2a: 47fd li a5,31 + 5e2c: 48b7c363 blt a5,a1,62b2 <__subdf3+0x500> + 5e30: 02000793 li a5,32 + 5e34: 8f8d sub a5,a5,a1 + 5e36: 00bed9b3 srl s3,t4,a1 + 5e3a: 00f71833 sll a6,a4,a5 + 5e3e: 00fe9eb3 sll t4,t4,a5 + 5e42: 01386833 or a6,a6,s3 + 5e46: 00b75733 srl a4,a4,a1 + 5e4a: 01d039b3 snez s3,t4 + 5e4e: 01386833 or a6,a6,s3 + 5e52: 40e30333 sub t1,t1,a4 + 5e56: 410f09b3 sub s3,t5,a6 + 5e5a: 013f37b3 sltu a5,t5,s3 + 5e5e: 40f30633 sub a2,t1,a5 + 5e62: 00861793 slli a5,a2,0x8 + 5e66: 2407d263 bgez a5,60aa <__subdf3+0x2f8> + 5e6a: 00800937 lui s2,0x800 + 5e6e: 197d addi s2,s2,-1 + 5e70: 01267933 and s2,a2,s2 + 5e74: 2c090e63 beqz s2,6150 <__subdf3+0x39e> + 5e78: 854a mv a0,s2 + 5e7a: 2f45 jal 662a <__clzsi2> + 5e7c: ff850713 addi a4,a0,-8 + 5e80: 02000793 li a5,32 + 5e84: 8f99 sub a5,a5,a4 + 5e86: 00f9d7b3 srl a5,s3,a5 + 5e8a: 00e91633 sll a2,s2,a4 + 5e8e: 8fd1 or a5,a5,a2 + 5e90: 00e999b3 sll s3,s3,a4 + 5e94: 2a974463 blt a4,s1,613c <__subdf3+0x38a> + 5e98: 8f05 sub a4,a4,s1 + 5e9a: 00170613 addi a2,a4,1 # 100001 <_data_lma+0xf3569> + 5e9e: 46fd li a3,31 + 5ea0: 3ac6c463 blt a3,a2,6248 <__subdf3+0x496> + 5ea4: 02000713 li a4,32 + 5ea8: 8f11 sub a4,a4,a2 + 5eaa: 00c9d6b3 srl a3,s3,a2 + 5eae: 00e99833 sll a6,s3,a4 + 5eb2: 00e79733 sll a4,a5,a4 + 5eb6: 8f55 or a4,a4,a3 + 5eb8: 01003833 snez a6,a6 + 5ebc: 010769b3 or s3,a4,a6 + 5ec0: 00c7d633 srl a2,a5,a2 + 5ec4: 4481 li s1,0 + 5ec6: 0079f793 andi a5,s3,7 + 5eca: cf81 beqz a5,5ee2 <__subdf3+0x130> + 5ecc: 00f9f693 andi a3,s3,15 + 5ed0: 4791 li a5,4 + 5ed2: 00f68863 beq a3,a5,5ee2 <__subdf3+0x130> + 5ed6: 00498693 addi a3,s3,4 + 5eda: 0136b833 sltu a6,a3,s3 + 5ede: 9642 add a2,a2,a6 + 5ee0: 89b6 mv s3,a3 + 5ee2: 00861793 slli a5,a2,0x8 + 5ee6: 1c07d663 bgez a5,60b2 <__subdf3+0x300> + 5eea: 00148713 addi a4,s1,1 + 5eee: 7ff00793 li a5,2047 + 5ef2: 8805 andi s0,s0,1 + 5ef4: 20f70663 beq a4,a5,6100 <__subdf3+0x34e> + 5ef8: ff8007b7 lui a5,0xff800 + 5efc: 17fd addi a5,a5,-1 + 5efe: 8ff1 and a5,a5,a2 + 5f00: 01d79813 slli a6,a5,0x1d + 5f04: 0039d993 srli s3,s3,0x3 + 5f08: 07a6 slli a5,a5,0x9 + 5f0a: 01386833 or a6,a6,s3 + 5f0e: 83b1 srli a5,a5,0xc + 5f10: 7ff77713 andi a4,a4,2047 + 5f14: 00c79693 slli a3,a5,0xc + 5f18: 0752 slli a4,a4,0x14 + 5f1a: 82b1 srli a3,a3,0xc + 5f1c: 047e slli s0,s0,0x1f + 5f1e: 8ed9 or a3,a3,a4 + 5f20: 8ec1 or a3,a3,s0 + 5f22: 40f2 lw ra,28(sp) + 5f24: 4462 lw s0,24(sp) + 5f26: 44d2 lw s1,20(sp) + 5f28: 4942 lw s2,16(sp) + 5f2a: 49b2 lw s3,12(sp) + 5f2c: 8542 mv a0,a6 + 5f2e: 85b6 mv a1,a3 + 5f30: 6105 addi sp,sp,32 + 5f32: 8082 ret + 5f34: 0ab05663 blez a1,5fe0 <__subdf3+0x22e> + 5f38: 12088a63 beqz a7,606c <__subdf3+0x2ba> + 5f3c: 008007b7 lui a5,0x800 + 5f40: 8f5d or a4,a4,a5 + 5f42: 2dc48663 beq s1,t3,620e <__subdf3+0x45c> + 5f46: 03800793 li a5,56 + 5f4a: 18b7c763 blt a5,a1,60d8 <__subdf3+0x326> + 5f4e: 47fd li a5,31 + 5f50: 3cb7d163 bge a5,a1,6312 <__subdf3+0x560> + 5f54: fe058813 addi a6,a1,-32 # ffe0 <_data_lma+0x3548> + 5f58: 02000793 li a5,32 + 5f5c: 010759b3 srl s3,a4,a6 + 5f60: 00f58a63 beq a1,a5,5f74 <__subdf3+0x1c2> + 5f64: 04000793 li a5,64 + 5f68: 40b785b3 sub a1,a5,a1 + 5f6c: 00b71733 sll a4,a4,a1 + 5f70: 00eeeeb3 or t4,t4,a4 + 5f74: 01d03833 snez a6,t4 + 5f78: 01386833 or a6,a6,s3 + 5f7c: a295 j 60e0 <__subdf3+0x32e> + 5f7e: 01d767b3 or a5,a4,t4 + 5f82: 80148593 addi a1,s1,-2047 + 5f86: e399 bnez a5,5f8c <__subdf3+0x1da> + 5f88: 0016c693 xori a3,a3,1 + 5f8c: 04d40a63 beq s0,a3,5fe0 <__subdf3+0x22e> + 5f90: e1d1 bnez a1,6014 <__subdf3+0x262> + 5f92: 00148793 addi a5,s1,1 + 5f96: 7fe7f793 andi a5,a5,2046 + 5f9a: 1e079863 bnez a5,618a <__subdf3+0x3d8> + 5f9e: 01e367b3 or a5,t1,t5 + 5fa2: 01d76833 or a6,a4,t4 + 5fa6: 16049263 bnez s1,610a <__subdf3+0x358> + 5faa: 3c078163 beqz a5,636c <__subdf3+0x5ba> + 5fae: 42081563 bnez a6,63d8 <__subdf3+0x626> + 5fb2: 00351813 slli a6,a0,0x3 + 5fb6: 01d31693 slli a3,t1,0x1d + 5fba: 00385813 srli a6,a6,0x3 + 5fbe: 0106e833 or a6,a3,a6 + 5fc2: 00335793 srli a5,t1,0x3 + 5fc6: a219 j 60cc <__subdf3+0x31a> + 5fc8: 01d767b3 or a5,a4,t4 + 5fcc: 1a078463 beqz a5,6174 <__subdf3+0x3c2> + 5fd0: fff58793 addi a5,a1,-1 + 5fd4: 3a078a63 beqz a5,6388 <__subdf3+0x5d6> + 5fd8: 23c58b63 beq a1,t3,620e <__subdf3+0x45c> + 5fdc: 85be mv a1,a5 + 5fde: b591 j 5e22 <__subdf3+0x70> + 5fe0: 1c059863 bnez a1,61b0 <__subdf3+0x3fe> + 5fe4: 00148693 addi a3,s1,1 + 5fe8: 7fe6f793 andi a5,a3,2046 + 5fec: efc1 bnez a5,6084 <__subdf3+0x2d2> + 5fee: 01e367b3 or a5,t1,t5 + 5ff2: 34049f63 bnez s1,6350 <__subdf3+0x59e> + 5ff6: 44078c63 beqz a5,644e <__subdf3+0x69c> + 5ffa: 01d767b3 or a5,a4,t4 + 5ffe: 46079363 bnez a5,6464 <__subdf3+0x6b2> + 6002: 050e slli a0,a0,0x3 + 6004: 01d31813 slli a6,t1,0x1d + 6008: 810d srli a0,a0,0x3 + 600a: 00a86833 or a6,a6,a0 + 600e: 00335793 srli a5,t1,0x3 + 6012: a86d j 60cc <__subdf3+0x31a> + 6014: 409885b3 sub a1,a7,s1 + 6018: 20049663 bnez s1,6224 <__subdf3+0x472> + 601c: 01e367b3 or a5,t1,t5 + 6020: 30078c63 beqz a5,6338 <__subdf3+0x586> + 6024: fff58793 addi a5,a1,-1 + 6028: 40078863 beqz a5,6438 <__subdf3+0x686> + 602c: 7ff00513 li a0,2047 + 6030: 20a58263 beq a1,a0,6234 <__subdf3+0x482> + 6034: 85be mv a1,a5 + 6036: 03800793 li a5,56 + 603a: 2ab7c163 blt a5,a1,62dc <__subdf3+0x52a> + 603e: 47fd li a5,31 + 6040: 3cb7c763 blt a5,a1,640e <__subdf3+0x65c> + 6044: 02000793 li a5,32 + 6048: 8f8d sub a5,a5,a1 + 604a: 00f31833 sll a6,t1,a5 + 604e: 00bf5633 srl a2,t5,a1 + 6052: 00ff17b3 sll a5,t5,a5 + 6056: 00c86833 or a6,a6,a2 + 605a: 00f039b3 snez s3,a5 + 605e: 00b35333 srl t1,t1,a1 + 6062: 01386833 or a6,a6,s3 + 6066: 40670733 sub a4,a4,t1 + 606a: acad j 62e4 <__subdf3+0x532> + 606c: 01d767b3 or a5,a4,t4 + 6070: 10078263 beqz a5,6174 <__subdf3+0x3c2> + 6074: fff58793 addi a5,a1,-1 + 6078: 1e078e63 beqz a5,6274 <__subdf3+0x4c2> + 607c: 2dc58f63 beq a1,t3,635a <__subdf3+0x5a8> + 6080: 85be mv a1,a5 + 6082: b5d1 j 5f46 <__subdf3+0x194> + 6084: 7ff00793 li a5,2047 + 6088: 06f68b63 beq a3,a5,60fe <__subdf3+0x34c> + 608c: 9efa add t4,t4,t5 + 608e: 01eeb633 sltu a2,t4,t5 + 6092: 00e307b3 add a5,t1,a4 + 6096: 97b2 add a5,a5,a2 + 6098: 01f79813 slli a6,a5,0x1f + 609c: 001ede93 srli t4,t4,0x1 + 60a0: 01d869b3 or s3,a6,t4 + 60a4: 0017d613 srli a2,a5,0x1 + 60a8: 84b6 mv s1,a3 + 60aa: 0079f793 andi a5,s3,7 + 60ae: e0079fe3 bnez a5,5ecc <__subdf3+0x11a> + 60b2: 01d61793 slli a5,a2,0x1d + 60b6: 0039d813 srli a6,s3,0x3 + 60ba: 00f86833 or a6,a6,a5 + 60be: 85a6 mv a1,s1 + 60c0: 00365793 srli a5,a2,0x3 + 60c4: 7ff00713 li a4,2047 + 60c8: 06e58063 beq a1,a4,6128 <__subdf3+0x376> + 60cc: 07b2 slli a5,a5,0xc + 60ce: 83b1 srli a5,a5,0xc + 60d0: 7ff5f713 andi a4,a1,2047 + 60d4: 8805 andi s0,s0,1 + 60d6: bd3d j 5f14 <__subdf3+0x162> + 60d8: 01d76733 or a4,a4,t4 + 60dc: 00e03833 snez a6,a4 + 60e0: 01e809b3 add s3,a6,t5 + 60e4: 01e9b7b3 sltu a5,s3,t5 + 60e8: 00678633 add a2,a5,t1 + 60ec: 00861793 slli a5,a2,0x8 + 60f0: fa07dde3 bgez a5,60aa <__subdf3+0x2f8> + 60f4: 0485 addi s1,s1,1 + 60f6: 7ff00793 li a5,2047 + 60fa: 18f49b63 bne s1,a5,6290 <__subdf3+0x4de> + 60fe: 8805 andi s0,s0,1 + 6100: 7ff00713 li a4,2047 + 6104: 4781 li a5,0 + 6106: 4801 li a6,0 + 6108: b531 j 5f14 <__subdf3+0x162> + 610a: 10079063 bnez a5,620a <__subdf3+0x458> + 610e: 3c080063 beqz a6,64ce <__subdf3+0x71c> + 6112: 00361813 slli a6,a2,0x3 + 6116: 01d71793 slli a5,a4,0x1d + 611a: 00385813 srli a6,a6,0x3 + 611e: 00f86833 or a6,a6,a5 + 6122: 8436 mv s0,a3 + 6124: 00375793 srli a5,a4,0x3 + 6128: 00f867b3 or a5,a6,a5 + 612c: dbe9 beqz a5,60fe <__subdf3+0x34c> + 612e: 4401 li s0,0 + 6130: 7ff00713 li a4,2047 + 6134: 000807b7 lui a5,0x80 + 6138: 4801 li a6,0 + 613a: bbe9 j 5f14 <__subdf3+0x162> + 613c: ff800637 lui a2,0xff800 + 6140: 167d addi a2,a2,-1 + 6142: 8e7d and a2,a2,a5 + 6144: 0079f793 andi a5,s3,7 + 6148: 8c99 sub s1,s1,a4 + 614a: d80791e3 bnez a5,5ecc <__subdf3+0x11a> + 614e: b795 j 60b2 <__subdf3+0x300> + 6150: 854e mv a0,s3 + 6152: 29e1 jal 662a <__clzsi2> + 6154: 01850713 addi a4,a0,24 + 6158: 47fd li a5,31 + 615a: d2e7d3e3 bge a5,a4,5e80 <__subdf3+0xce> + 615e: ff850613 addi a2,a0,-8 + 6162: 00c997b3 sll a5,s3,a2 + 6166: 4981 li s3,0 + 6168: b335 j 5e94 <__subdf3+0xe2> + 616a: 01d76833 or a6,a4,t4 + 616e: 01003833 snez a6,a6 + 6172: b1d5 j 5e56 <__subdf3+0xa4> + 6174: 00351813 slli a6,a0,0x3 + 6178: 01d31793 slli a5,t1,0x1d + 617c: 00385813 srli a6,a6,0x3 + 6180: 00f86833 or a6,a6,a5 + 6184: 00335793 srli a5,t1,0x3 + 6188: bf35 j 60c4 <__subdf3+0x312> + 618a: 41df09b3 sub s3,t5,t4 + 618e: 40e30933 sub s2,t1,a4 + 6192: 013f3633 sltu a2,t5,s3 + 6196: 40c90933 sub s2,s2,a2 + 619a: 00891793 slli a5,s2,0x8 + 619e: 2007ca63 bltz a5,63b2 <__subdf3+0x600> + 61a2: 0129e833 or a6,s3,s2 + 61a6: cc0817e3 bnez a6,5e74 <__subdf3+0xc2> + 61aa: 4781 li a5,0 + 61ac: 4401 li s0,0 + 61ae: bf39 j 60cc <__subdf3+0x31a> + 61b0: 409885b3 sub a1,a7,s1 + 61b4: 14048163 beqz s1,62f6 <__subdf3+0x544> + 61b8: 008006b7 lui a3,0x800 + 61bc: 7ff00793 li a5,2047 + 61c0: 00d36333 or t1,t1,a3 + 61c4: 20f88163 beq a7,a5,63c6 <__subdf3+0x614> + 61c8: 03800793 li a5,56 + 61cc: 22b7cc63 blt a5,a1,6404 <__subdf3+0x652> + 61d0: 47fd li a5,31 + 61d2: 2cb7c963 blt a5,a1,64a4 <__subdf3+0x6f2> + 61d6: 02000793 li a5,32 + 61da: 8f8d sub a5,a5,a1 + 61dc: 00f31833 sll a6,t1,a5 + 61e0: 00bf56b3 srl a3,t5,a1 + 61e4: 00ff17b3 sll a5,t5,a5 + 61e8: 00d86833 or a6,a6,a3 + 61ec: 00f039b3 snez s3,a5 + 61f0: 00b35333 srl t1,t1,a1 + 61f4: 01386833 or a6,a6,s3 + 61f8: 971a add a4,a4,t1 + 61fa: 01d809b3 add s3,a6,t4 + 61fe: 01d9b7b3 sltu a5,s3,t4 + 6202: 00e78633 add a2,a5,a4 + 6206: 84c6 mv s1,a7 + 6208: b5d5 j 60ec <__subdf3+0x33a> + 620a: f20812e3 bnez a6,612e <__subdf3+0x37c> + 620e: 00351813 slli a6,a0,0x3 + 6212: 01d31793 slli a5,t1,0x1d + 6216: 00385813 srli a6,a6,0x3 + 621a: 00f86833 or a6,a6,a5 + 621e: 00335793 srli a5,t1,0x3 + 6222: b719 j 6128 <__subdf3+0x376> + 6224: 00800537 lui a0,0x800 + 6228: 7ff00793 li a5,2047 + 622c: 00a36333 or t1,t1,a0 + 6230: e0f893e3 bne a7,a5,6036 <__subdf3+0x284> + 6234: 060e slli a2,a2,0x3 + 6236: 01d71813 slli a6,a4,0x1d + 623a: 820d srli a2,a2,0x3 + 623c: 00c86833 or a6,a6,a2 + 6240: 00375793 srli a5,a4,0x3 + 6244: 8436 mv s0,a3 + 6246: b5cd j 6128 <__subdf3+0x376> + 6248: 1705 addi a4,a4,-31 + 624a: 02000693 li a3,32 + 624e: 00e7d733 srl a4,a5,a4 + 6252: 00d60a63 beq a2,a3,6266 <__subdf3+0x4b4> + 6256: 04000693 li a3,64 + 625a: 40c68633 sub a2,a3,a2 + 625e: 00c79633 sll a2,a5,a2 + 6262: 00c9e9b3 or s3,s3,a2 + 6266: 01303833 snez a6,s3 + 626a: 00e869b3 or s3,a6,a4 + 626e: 4601 li a2,0 + 6270: 4481 li s1,0 + 6272: bd25 j 60aa <__subdf3+0x2f8> + 6274: 01df09b3 add s3,t5,t4 + 6278: 00e307b3 add a5,t1,a4 + 627c: 01e9bf33 sltu t5,s3,t5 + 6280: 01e78633 add a2,a5,t5 + 6284: 00861793 slli a5,a2,0x8 + 6288: 4485 li s1,1 + 628a: e207d0e3 bgez a5,60aa <__subdf3+0x2f8> + 628e: 4489 li s1,2 + 6290: ff8007b7 lui a5,0xff800 + 6294: 17fd addi a5,a5,-1 + 6296: 8ff1 and a5,a5,a2 + 6298: 0019d713 srli a4,s3,0x1 + 629c: 0019f813 andi a6,s3,1 + 62a0: 01076833 or a6,a4,a6 + 62a4: 01f79993 slli s3,a5,0x1f + 62a8: 0109e9b3 or s3,s3,a6 + 62ac: 0017d613 srli a2,a5,0x1 + 62b0: b919 j 5ec6 <__subdf3+0x114> + 62b2: fe058813 addi a6,a1,-32 + 62b6: 02000793 li a5,32 + 62ba: 010759b3 srl s3,a4,a6 + 62be: 00f58a63 beq a1,a5,62d2 <__subdf3+0x520> + 62c2: 04000793 li a5,64 + 62c6: 40b785b3 sub a1,a5,a1 + 62ca: 00b71733 sll a4,a4,a1 + 62ce: 00eeeeb3 or t4,t4,a4 + 62d2: 01d03833 snez a6,t4 + 62d6: 01386833 or a6,a6,s3 + 62da: beb5 j 5e56 <__subdf3+0xa4> + 62dc: 01e36333 or t1,t1,t5 + 62e0: 00603833 snez a6,t1 + 62e4: 410e89b3 sub s3,t4,a6 + 62e8: 013eb7b3 sltu a5,t4,s3 + 62ec: 40f70633 sub a2,a4,a5 + 62f0: 84c6 mv s1,a7 + 62f2: 8436 mv s0,a3 + 62f4: b6bd j 5e62 <__subdf3+0xb0> + 62f6: 01e367b3 or a5,t1,t5 + 62fa: 18078763 beqz a5,6488 <__subdf3+0x6d6> + 62fe: fff58793 addi a5,a1,-1 + 6302: 1c078c63 beqz a5,64da <__subdf3+0x728> + 6306: 7ff00693 li a3,2047 + 630a: 0ad58e63 beq a1,a3,63c6 <__subdf3+0x614> + 630e: 85be mv a1,a5 + 6310: bd65 j 61c8 <__subdf3+0x416> + 6312: 02000793 li a5,32 + 6316: 8f8d sub a5,a5,a1 + 6318: 00bed9b3 srl s3,t4,a1 + 631c: 00f71833 sll a6,a4,a5 + 6320: 00fe9eb3 sll t4,t4,a5 + 6324: 01386833 or a6,a6,s3 + 6328: 00b75733 srl a4,a4,a1 + 632c: 01d039b3 snez s3,t4 + 6330: 01386833 or a6,a6,s3 + 6334: 933a add t1,t1,a4 + 6336: b36d j 60e0 <__subdf3+0x32e> + 6338: 00361813 slli a6,a2,0x3 + 633c: 01d71793 slli a5,a4,0x1d + 6340: 00385813 srli a6,a6,0x3 + 6344: 0107e833 or a6,a5,a6 + 6348: 8436 mv s0,a3 + 634a: 00375793 srli a5,a4,0x3 + 634e: bb9d j 60c4 <__subdf3+0x312> + 6350: cbbd beqz a5,63c6 <__subdf3+0x614> + 6352: 01d76733 or a4,a4,t4 + 6356: dc071ce3 bnez a4,612e <__subdf3+0x37c> + 635a: 050e slli a0,a0,0x3 + 635c: 01d31813 slli a6,t1,0x1d + 6360: 810d srli a0,a0,0x3 + 6362: 00a86833 or a6,a6,a0 + 6366: 00335793 srli a5,t1,0x3 + 636a: bb7d j 6128 <__subdf3+0x376> + 636c: e2080fe3 beqz a6,61aa <__subdf3+0x3f8> + 6370: 00361813 slli a6,a2,0x3 + 6374: 01d71793 slli a5,a4,0x1d + 6378: 00385813 srli a6,a6,0x3 + 637c: 00f86833 or a6,a6,a5 + 6380: 8436 mv s0,a3 + 6382: 00375793 srli a5,a4,0x3 + 6386: b399 j 60cc <__subdf3+0x31a> + 6388: 41df09b3 sub s3,t5,t4 + 638c: 40e307b3 sub a5,t1,a4 + 6390: 013f3f33 sltu t5,t5,s3 + 6394: 41e78633 sub a2,a5,t5 + 6398: 4485 li s1,1 + 639a: b4e1 j 5e62 <__subdf3+0xb0> + 639c: 00351813 slli a6,a0,0x3 + 63a0: 01d31693 slli a3,t1,0x1d + 63a4: 00385813 srli a6,a6,0x3 + 63a8: 0106e833 or a6,a3,a6 + 63ac: 00335793 srli a5,t1,0x3 + 63b0: bba5 j 6128 <__subdf3+0x376> + 63b2: 41ee89b3 sub s3,t4,t5 + 63b6: 40670633 sub a2,a4,t1 + 63ba: 013eb933 sltu s2,t4,s3 + 63be: 41260933 sub s2,a2,s2 + 63c2: 8436 mv s0,a3 + 63c4: bc45 j 5e74 <__subdf3+0xc2> + 63c6: 060e slli a2,a2,0x3 + 63c8: 01d71813 slli a6,a4,0x1d + 63cc: 820d srli a2,a2,0x3 + 63ce: 00c86833 or a6,a6,a2 + 63d2: 00375793 srli a5,a4,0x3 + 63d6: bb89 j 6128 <__subdf3+0x376> + 63d8: 41df09b3 sub s3,t5,t4 + 63dc: 40e307b3 sub a5,t1,a4 + 63e0: 013f3633 sltu a2,t5,s3 + 63e4: 40c78633 sub a2,a5,a2 + 63e8: 00861793 slli a5,a2,0x8 + 63ec: 0a07d763 bgez a5,649a <__subdf3+0x6e8> + 63f0: 41ee89b3 sub s3,t4,t5 + 63f4: 406707b3 sub a5,a4,t1 + 63f8: 013ebeb3 sltu t4,t4,s3 + 63fc: 41d78633 sub a2,a5,t4 + 6400: 8436 mv s0,a3 + 6402: b4d1 j 5ec6 <__subdf3+0x114> + 6404: 01e36333 or t1,t1,t5 + 6408: 00603833 snez a6,t1 + 640c: b3fd j 61fa <__subdf3+0x448> + 640e: fe058813 addi a6,a1,-32 + 6412: 02000793 li a5,32 + 6416: 010359b3 srl s3,t1,a6 + 641a: 00f58a63 beq a1,a5,642e <__subdf3+0x67c> + 641e: 04000793 li a5,64 + 6422: 40b785b3 sub a1,a5,a1 + 6426: 00b31333 sll t1,t1,a1 + 642a: 006f6f33 or t5,t5,t1 + 642e: 01e03833 snez a6,t5 + 6432: 01386833 or a6,a6,s3 + 6436: b57d j 62e4 <__subdf3+0x532> + 6438: 41ee89b3 sub s3,t4,t5 + 643c: 406707b3 sub a5,a4,t1 + 6440: 013ebeb3 sltu t4,t4,s3 + 6444: 41d78633 sub a2,a5,t4 + 6448: 8436 mv s0,a3 + 644a: 4485 li s1,1 + 644c: bc19 j 5e62 <__subdf3+0xb0> + 644e: 00361813 slli a6,a2,0x3 + 6452: 01d71793 slli a5,a4,0x1d + 6456: 00385813 srli a6,a6,0x3 + 645a: 00f86833 or a6,a6,a5 + 645e: 00375793 srli a5,a4,0x3 + 6462: b1ad j 60cc <__subdf3+0x31a> + 6464: 01df09b3 add s3,t5,t4 + 6468: 00e307b3 add a5,t1,a4 + 646c: 01e9bf33 sltu t5,s3,t5 + 6470: 01e78633 add a2,a5,t5 + 6474: 00861793 slli a5,a2,0x8 + 6478: c207d9e3 bgez a5,60aa <__subdf3+0x2f8> + 647c: ff8007b7 lui a5,0xff800 + 6480: 17fd addi a5,a5,-1 + 6482: 8e7d and a2,a2,a5 + 6484: 4485 li s1,1 + 6486: b115 j 60aa <__subdf3+0x2f8> + 6488: 060e slli a2,a2,0x3 + 648a: 01d71813 slli a6,a4,0x1d + 648e: 820d srli a2,a2,0x3 + 6490: 00c86833 or a6,a6,a2 + 6494: 00375793 srli a5,a4,0x3 + 6498: b135 j 60c4 <__subdf3+0x312> + 649a: 00c9e833 or a6,s3,a2 + 649e: d00806e3 beqz a6,61aa <__subdf3+0x3f8> + 64a2: b121 j 60aa <__subdf3+0x2f8> + 64a4: fe058813 addi a6,a1,-32 + 64a8: 02000793 li a5,32 + 64ac: 010359b3 srl s3,t1,a6 + 64b0: 00f58a63 beq a1,a5,64c4 <__subdf3+0x712> + 64b4: 04000793 li a5,64 + 64b8: 40b785b3 sub a1,a5,a1 + 64bc: 00b31333 sll t1,t1,a1 + 64c0: 006f6f33 or t5,t5,t1 + 64c4: 01e03833 snez a6,t5 + 64c8: 01386833 or a6,a6,s3 + 64cc: b33d j 61fa <__subdf3+0x448> + 64ce: 4401 li s0,0 + 64d0: 7ff00713 li a4,2047 + 64d4: 000807b7 lui a5,0x80 + 64d8: bc35 j 5f14 <__subdf3+0x162> + 64da: 01df09b3 add s3,t5,t4 + 64de: 00e307b3 add a5,t1,a4 + 64e2: 01d9beb3 sltu t4,s3,t4 + 64e6: 01d78633 add a2,a5,t4 + 64ea: bb69 j 6284 <__subdf3+0x4d2> + +000064ec <__fixdfsi>: + 64ec: 0145d793 srli a5,a1,0x14 + 64f0: 001006b7 lui a3,0x100 + 64f4: fff68713 addi a4,a3,-1 # fffff <_data_lma+0xf3567> + 64f8: 7ff7f793 andi a5,a5,2047 + 64fc: 3fe00613 li a2,1022 + 6500: 8f6d and a4,a4,a1 + 6502: 81fd srli a1,a1,0x1f + 6504: 00f65c63 bge a2,a5,651c <__fixdfsi+0x30> + 6508: 41d00613 li a2,1053 + 650c: 00f65a63 bge a2,a5,6520 <__fixdfsi+0x34> + 6510: 80000537 lui a0,0x80000 + 6514: fff54513 not a0,a0 + 6518: 952e add a0,a0,a1 + 651a: 8082 ret + 651c: 4501 li a0,0 + 651e: 8082 ret + 6520: 43300613 li a2,1075 + 6524: 8e1d sub a2,a2,a5 + 6526: 487d li a6,31 + 6528: 8f55 or a4,a4,a3 + 652a: 00c85d63 bge a6,a2,6544 <__fixdfsi+0x58> + 652e: 41300693 li a3,1043 + 6532: 40f687b3 sub a5,a3,a5 + 6536: 00f757b3 srl a5,a4,a5 + 653a: 40f00533 neg a0,a5 + 653e: f1e5 bnez a1,651e <__fixdfsi+0x32> + 6540: 853e mv a0,a5 + 6542: 8082 ret + 6544: bed78793 addi a5,a5,-1043 # 7fbed <_data_lma+0x73155> + 6548: 00f717b3 sll a5,a4,a5 + 654c: 00c55533 srl a0,a0,a2 + 6550: 8fc9 or a5,a5,a0 + 6552: b7e5 j 653a <__fixdfsi+0x4e> + +00006554 <__floatsidf>: + 6554: 1141 addi sp,sp,-16 + 6556: c606 sw ra,12(sp) + 6558: c422 sw s0,8(sp) + 655a: c226 sw s1,4(sp) + 655c: cd05 beqz a0,6594 <__floatsidf+0x40> + 655e: 41f55793 srai a5,a0,0x1f + 6562: 00a7c4b3 xor s1,a5,a0 + 6566: 8c9d sub s1,s1,a5 + 6568: 842a mv s0,a0 + 656a: 8526 mv a0,s1 + 656c: 287d jal 662a <__clzsi2> + 656e: 41e00693 li a3,1054 + 6572: 8e89 sub a3,a3,a0 + 6574: 47a9 li a5,10 + 6576: 807d srli s0,s0,0x1f + 6578: 7ff6f693 andi a3,a3,2047 + 657c: 02a7cd63 blt a5,a0,65b6 <__floatsidf+0x62> + 6580: 472d li a4,11 + 6582: 8f09 sub a4,a4,a0 + 6584: 00e4d7b3 srl a5,s1,a4 + 6588: 0555 addi a0,a0,21 + 658a: 07b2 slli a5,a5,0xc + 658c: 00a494b3 sll s1,s1,a0 + 6590: 83b1 srli a5,a5,0xc + 6592: a029 j 659c <__floatsidf+0x48> + 6594: 4401 li s0,0 + 6596: 4681 li a3,0 + 6598: 4781 li a5,0 + 659a: 4481 li s1,0 + 659c: 07b2 slli a5,a5,0xc + 659e: 06d2 slli a3,a3,0x14 + 65a0: 83b1 srli a5,a5,0xc + 65a2: 047e slli s0,s0,0x1f + 65a4: 8fd5 or a5,a5,a3 + 65a6: 8fc1 or a5,a5,s0 + 65a8: 40b2 lw ra,12(sp) + 65aa: 4422 lw s0,8(sp) + 65ac: 8526 mv a0,s1 + 65ae: 85be mv a1,a5 + 65b0: 4492 lw s1,4(sp) + 65b2: 0141 addi sp,sp,16 + 65b4: 8082 ret + 65b6: 1555 addi a0,a0,-11 + 65b8: 00a497b3 sll a5,s1,a0 + 65bc: 07b2 slli a5,a5,0xc + 65be: 83b1 srli a5,a5,0xc + 65c0: 4481 li s1,0 + 65c2: bfe9 j 659c <__floatsidf+0x48> + +000065c4 <__floatunsidf>: + 65c4: cd15 beqz a0,6600 <__floatunsidf+0x3c> + 65c6: 1141 addi sp,sp,-16 + 65c8: c422 sw s0,8(sp) + 65ca: c606 sw ra,12(sp) + 65cc: 842a mv s0,a0 + 65ce: 28b1 jal 662a <__clzsi2> + 65d0: 41e00693 li a3,1054 + 65d4: 8e89 sub a3,a3,a0 + 65d6: 47a9 li a5,10 + 65d8: 7ff6f693 andi a3,a3,2047 + 65dc: 02a7dc63 bge a5,a0,6614 <__floatunsidf+0x50> + 65e0: 1555 addi a0,a0,-11 + 65e2: 00a417b3 sll a5,s0,a0 + 65e6: 07b2 slli a5,a5,0xc + 65e8: 83b1 srli a5,a5,0xc + 65ea: 4701 li a4,0 + 65ec: 40b2 lw ra,12(sp) + 65ee: 4422 lw s0,8(sp) + 65f0: 07b2 slli a5,a5,0xc + 65f2: 06d2 slli a3,a3,0x14 + 65f4: 83b1 srli a5,a5,0xc + 65f6: 8fd5 or a5,a5,a3 + 65f8: 853a mv a0,a4 + 65fa: 85be mv a1,a5 + 65fc: 0141 addi sp,sp,16 + 65fe: 8082 ret + 6600: 4781 li a5,0 + 6602: 4681 li a3,0 + 6604: 07b2 slli a5,a5,0xc + 6606: 06d2 slli a3,a3,0x14 + 6608: 83b1 srli a5,a5,0xc + 660a: 4701 li a4,0 + 660c: 8fd5 or a5,a5,a3 + 660e: 853a mv a0,a4 + 6610: 85be mv a1,a5 + 6612: 8082 ret + 6614: 472d li a4,11 + 6616: 8f09 sub a4,a4,a0 + 6618: 00e457b3 srl a5,s0,a4 + 661c: 07b2 slli a5,a5,0xc + 661e: 01550713 addi a4,a0,21 # 80000015 <_eusrstack+0x5fff0015> + 6622: 00e41733 sll a4,s0,a4 + 6626: 83b1 srli a5,a5,0xc + 6628: b7d1 j 65ec <__floatunsidf+0x28> + +0000662a <__clzsi2>: + 662a: 67c1 lui a5,0x10 + 662c: 02f57e63 bgeu a0,a5,6668 <__clzsi2+0x3e> + 6630: 0ff00793 li a5,255 + 6634: 02000713 li a4,32 + 6638: 00a7ec63 bltu a5,a0,6650 <__clzsi2+0x26> + 663c: 00006797 auipc a5,0x6 + 6640: f5478793 addi a5,a5,-172 # c590 <__clz_tab> + 6644: 97aa add a5,a5,a0 + 6646: 0007c503 lbu a0,0(a5) + 664a: 40a70533 sub a0,a4,a0 + 664e: 8082 ret + 6650: 8121 srli a0,a0,0x8 + 6652: 00006797 auipc a5,0x6 + 6656: f3e78793 addi a5,a5,-194 # c590 <__clz_tab> + 665a: 97aa add a5,a5,a0 + 665c: 0007c503 lbu a0,0(a5) + 6660: 4761 li a4,24 + 6662: 40a70533 sub a0,a4,a0 + 6666: 8082 ret + 6668: 010007b7 lui a5,0x1000 + 666c: 00f56e63 bltu a0,a5,6688 <__clzsi2+0x5e> + 6670: 8161 srli a0,a0,0x18 + 6672: 00006797 auipc a5,0x6 + 6676: f1e78793 addi a5,a5,-226 # c590 <__clz_tab> + 667a: 97aa add a5,a5,a0 + 667c: 0007c503 lbu a0,0(a5) + 6680: 4721 li a4,8 + 6682: 40a70533 sub a0,a4,a0 + 6686: 8082 ret + 6688: 8141 srli a0,a0,0x10 + 668a: 00006797 auipc a5,0x6 + 668e: f0678793 addi a5,a5,-250 # c590 <__clz_tab> + 6692: 97aa add a5,a5,a0 + 6694: 0007c503 lbu a0,0(a5) + 6698: 4741 li a4,16 + 669a: 40a70533 sub a0,a4,a0 + 669e: 8082 ret + +000066a0 <__assert_func>: + 66a0: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 66a4: 439c lw a5,0(a5) + 66a6: 1141 addi sp,sp,-16 + 66a8: 8832 mv a6,a2 + 66aa: c606 sw ra,12(sp) + 66ac: 88aa mv a7,a0 + 66ae: 872e mv a4,a1 + 66b0: 47c8 lw a0,12(a5) + 66b2: 8636 mv a2,a3 + 66b4: 00006797 auipc a5,0x6 + 66b8: fdc78793 addi a5,a5,-36 # c690 <__clz_tab+0x100> + 66bc: 00081763 bnez a6,66ca <__assert_func+0x2a> + 66c0: 00006797 auipc a5,0x6 + 66c4: 9ec78793 addi a5,a5,-1556 # c0ac <_exit+0x9c> + 66c8: 883e mv a6,a5 + 66ca: 86c6 mv a3,a7 + 66cc: 00006597 auipc a1,0x6 + 66d0: fd458593 addi a1,a1,-44 # c6a0 <__clz_tab+0x110> + 66d4: 2019 jal 66da + 66d6: 666020ef jal ra,8d3c + +000066da : + 66da: 7139 addi sp,sp,-64 + 66dc: d432 sw a2,40(sp) + 66de: d636 sw a3,44(sp) + 66e0: da3e sw a5,52(sp) + 66e2: d83a sw a4,48(sp) + 66e4: dc42 sw a6,56(sp) + 66e6: de46 sw a7,60(sp) + 66e8: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 66ec: 862e mv a2,a1 + 66ee: 85aa mv a1,a0 + 66f0: 4388 lw a0,0(a5) + 66f2: 1034 addi a3,sp,40 + 66f4: ce06 sw ra,28(sp) + 66f6: c636 sw a3,12(sp) + 66f8: 2a71 jal 6894 <_vfiprintf_r> + 66fa: 40f2 lw ra,28(sp) + 66fc: 6121 addi sp,sp,64 + 66fe: 8082 ret + +00006700 : + 6700: 4701 li a4,0 + 6702: 00e61463 bne a2,a4,670a + 6706: 4501 li a0,0 + 6708: 8082 ret + 670a: 00e507b3 add a5,a0,a4 + 670e: 0705 addi a4,a4,1 + 6710: 00e586b3 add a3,a1,a4 + 6714: 0007c783 lbu a5,0(a5) + 6718: fff6c683 lbu a3,-1(a3) + 671c: fed783e3 beq a5,a3,6702 + 6720: 40d78533 sub a0,a5,a3 + 6724: 8082 ret + +00006726 : + 6726: 00a5c7b3 xor a5,a1,a0 + 672a: 8b8d andi a5,a5,3 + 672c: 00c50733 add a4,a0,a2 + 6730: e781 bnez a5,6738 + 6732: 478d li a5,3 + 6734: 00c7ee63 bltu a5,a2,6750 + 6738: 87aa mv a5,a0 + 673a: 0ae57063 bgeu a0,a4,67da + 673e: 0005c683 lbu a3,0(a1) + 6742: 0785 addi a5,a5,1 + 6744: 0585 addi a1,a1,1 + 6746: fed78fa3 sb a3,-1(a5) + 674a: fee7eae3 bltu a5,a4,673e + 674e: 8082 ret + 6750: 00357693 andi a3,a0,3 + 6754: 87aa mv a5,a0 + 6756: ca91 beqz a3,676a + 6758: 0005c683 lbu a3,0(a1) + 675c: 0785 addi a5,a5,1 + 675e: 0585 addi a1,a1,1 + 6760: fed78fa3 sb a3,-1(a5) + 6764: 0037f693 andi a3,a5,3 + 6768: b7fd j 6756 + 676a: ffc77693 andi a3,a4,-4 + 676e: fe068613 addi a2,a3,-32 + 6772: 06c7f063 bgeu a5,a2,67d2 + 6776: 0005a383 lw t2,0(a1) + 677a: 0045a283 lw t0,4(a1) + 677e: 0085af83 lw t6,8(a1) + 6782: 00c5af03 lw t5,12(a1) + 6786: 0105ae83 lw t4,16(a1) + 678a: 0145ae03 lw t3,20(a1) + 678e: 0185a303 lw t1,24(a1) + 6792: 01c5a883 lw a7,28(a1) + 6796: 02458593 addi a1,a1,36 + 679a: 0077a023 sw t2,0(a5) + 679e: ffc5a803 lw a6,-4(a1) + 67a2: 0057a223 sw t0,4(a5) + 67a6: 01f7a423 sw t6,8(a5) + 67aa: 01e7a623 sw t5,12(a5) + 67ae: 01d7a823 sw t4,16(a5) + 67b2: 01c7aa23 sw t3,20(a5) + 67b6: 0067ac23 sw t1,24(a5) + 67ba: 0117ae23 sw a7,28(a5) + 67be: 02478793 addi a5,a5,36 + 67c2: ff07ae23 sw a6,-4(a5) + 67c6: b775 j 6772 + 67c8: 4190 lw a2,0(a1) + 67ca: 0791 addi a5,a5,4 + 67cc: 0591 addi a1,a1,4 + 67ce: fec7ae23 sw a2,-4(a5) + 67d2: fed7ebe3 bltu a5,a3,67c8 + 67d6: f6e7e4e3 bltu a5,a4,673e + 67da: 8082 ret + +000067dc : + 67dc: 04a5f363 bgeu a1,a0,6822 + 67e0: 00c586b3 add a3,a1,a2 + 67e4: 02d57f63 bgeu a0,a3,6822 + 67e8: fff64593 not a1,a2 + 67ec: 4781 li a5,0 + 67ee: 17fd addi a5,a5,-1 + 67f0: 00f59363 bne a1,a5,67f6 + 67f4: 8082 ret + 67f6: 00f68733 add a4,a3,a5 + 67fa: 00074803 lbu a6,0(a4) + 67fe: 00c78733 add a4,a5,a2 + 6802: 972a add a4,a4,a0 + 6804: 01070023 sb a6,0(a4) + 6808: b7dd j 67ee + 680a: 00f58733 add a4,a1,a5 + 680e: 00074683 lbu a3,0(a4) + 6812: 00f50733 add a4,a0,a5 + 6816: 0785 addi a5,a5,1 + 6818: 00d70023 sb a3,0(a4) + 681c: fef617e3 bne a2,a5,680a + 6820: 8082 ret + 6822: 4781 li a5,0 + 6824: bfe5 j 681c + +00006826 <__sfputc_r>: + 6826: 461c lw a5,8(a2) + 6828: 17fd addi a5,a5,-1 + 682a: c61c sw a5,8(a2) + 682c: 0007da63 bgez a5,6840 <__sfputc_r+0x1a> + 6830: 4e18 lw a4,24(a2) + 6832: 00e7c563 blt a5,a4,683c <__sfputc_r+0x16> + 6836: 47a9 li a5,10 + 6838: 00f59463 bne a1,a5,6840 <__sfputc_r+0x1a> + 683c: 3280206f j 8b64 <__swbuf_r> + 6840: 421c lw a5,0(a2) + 6842: 852e mv a0,a1 + 6844: 00178713 addi a4,a5,1 + 6848: c218 sw a4,0(a2) + 684a: 00b78023 sb a1,0(a5) + 684e: 8082 ret + +00006850 <__sfputs_r>: + 6850: 1101 addi sp,sp,-32 + 6852: cc22 sw s0,24(sp) + 6854: ca26 sw s1,20(sp) + 6856: c84a sw s2,16(sp) + 6858: c64e sw s3,12(sp) + 685a: c452 sw s4,8(sp) + 685c: ce06 sw ra,28(sp) + 685e: 892a mv s2,a0 + 6860: 89ae mv s3,a1 + 6862: 8432 mv s0,a2 + 6864: 00d604b3 add s1,a2,a3 + 6868: 5a7d li s4,-1 + 686a: 00941463 bne s0,s1,6872 <__sfputs_r+0x22> + 686e: 4501 li a0,0 + 6870: a811 j 6884 <__sfputs_r+0x34> + 6872: 00044583 lbu a1,0(s0) # 80000 <_data_lma+0x73568> + 6876: 864e mv a2,s3 + 6878: 854a mv a0,s2 + 687a: fadff0ef jal ra,6826 <__sfputc_r> + 687e: 0405 addi s0,s0,1 + 6880: ff4515e3 bne a0,s4,686a <__sfputs_r+0x1a> + 6884: 40f2 lw ra,28(sp) + 6886: 4462 lw s0,24(sp) + 6888: 44d2 lw s1,20(sp) + 688a: 4942 lw s2,16(sp) + 688c: 49b2 lw s3,12(sp) + 688e: 4a22 lw s4,8(sp) + 6890: 6105 addi sp,sp,32 + 6892: 8082 ret + +00006894 <_vfiprintf_r>: + 6894: 7135 addi sp,sp,-160 + 6896: cd22 sw s0,152(sp) + 6898: cb26 sw s1,148(sp) + 689a: c94a sw s2,144(sp) + 689c: c74e sw s3,140(sp) + 689e: cf06 sw ra,156(sp) + 68a0: c552 sw s4,136(sp) + 68a2: c356 sw s5,132(sp) + 68a4: c15a sw s6,128(sp) + 68a6: dede sw s7,124(sp) + 68a8: dce2 sw s8,120(sp) + 68aa: dae6 sw s9,116(sp) + 68ac: 89aa mv s3,a0 + 68ae: 84ae mv s1,a1 + 68b0: 8932 mv s2,a2 + 68b2: 8436 mv s0,a3 + 68b4: c509 beqz a0,68be <_vfiprintf_r+0x2a> + 68b6: 4d1c lw a5,24(a0) + 68b8: e399 bnez a5,68be <_vfiprintf_r+0x2a> + 68ba: 44c030ef jal ra,9d06 <__sinit> + 68be: 00006797 auipc a5,0x6 + 68c2: f8a78793 addi a5,a5,-118 # c848 <__sf_fake_stdin> + 68c6: 0cf49d63 bne s1,a5,69a0 <_vfiprintf_r+0x10c> + 68ca: 0049a483 lw s1,4(s3) + 68ce: 00c4d783 lhu a5,12(s1) + 68d2: 8ba1 andi a5,a5,8 + 68d4: cbe5 beqz a5,69c4 <_vfiprintf_r+0x130> + 68d6: 489c lw a5,16(s1) + 68d8: c7f5 beqz a5,69c4 <_vfiprintf_r+0x130> + 68da: 02000793 li a5,32 + 68de: 02f104a3 sb a5,41(sp) + 68e2: 03000793 li a5,48 + 68e6: d202 sw zero,36(sp) + 68e8: 02f10523 sb a5,42(sp) + 68ec: c622 sw s0,12(sp) + 68ee: 02500b93 li s7,37 + 68f2: 00006a97 auipc s5,0x6 + 68f6: ddea8a93 addi s5,s5,-546 # c6d0 <__clz_tab+0x140> + 68fa: 4c05 li s8,1 + 68fc: 4b29 li s6,10 + 68fe: 844a mv s0,s2 + 6900: 00044783 lbu a5,0(s0) + 6904: c399 beqz a5,690a <_vfiprintf_r+0x76> + 6906: 0f779263 bne a5,s7,69ea <_vfiprintf_r+0x156> + 690a: 41240cb3 sub s9,s0,s2 + 690e: 000c8e63 beqz s9,692a <_vfiprintf_r+0x96> + 6912: 86e6 mv a3,s9 + 6914: 864a mv a2,s2 + 6916: 85a6 mv a1,s1 + 6918: 854e mv a0,s3 + 691a: f37ff0ef jal ra,6850 <__sfputs_r> + 691e: 57fd li a5,-1 + 6920: 1ef50663 beq a0,a5,6b0c <_vfiprintf_r+0x278> + 6924: 5692 lw a3,36(sp) + 6926: 96e6 add a3,a3,s9 + 6928: d236 sw a3,36(sp) + 692a: 00044783 lbu a5,0(s0) + 692e: 1c078f63 beqz a5,6b0c <_vfiprintf_r+0x278> + 6932: 57fd li a5,-1 + 6934: 00140913 addi s2,s0,1 + 6938: c802 sw zero,16(sp) + 693a: ce02 sw zero,28(sp) + 693c: ca3e sw a5,20(sp) + 693e: cc02 sw zero,24(sp) + 6940: 040109a3 sb zero,83(sp) + 6944: d482 sw zero,104(sp) + 6946: 00094583 lbu a1,0(s2) # 800000 <_data_lma+0x7f3568> + 694a: 4615 li a2,5 + 694c: 8556 mv a0,s5 + 694e: 5d7030ef jal ra,a724 + 6952: 00190413 addi s0,s2,1 + 6956: 47c2 lw a5,16(sp) + 6958: e959 bnez a0,69ee <_vfiprintf_r+0x15a> + 695a: 0107f713 andi a4,a5,16 + 695e: c709 beqz a4,6968 <_vfiprintf_r+0xd4> + 6960: 02000713 li a4,32 + 6964: 04e109a3 sb a4,83(sp) + 6968: 0087f713 andi a4,a5,8 + 696c: c709 beqz a4,6976 <_vfiprintf_r+0xe2> + 696e: 02b00713 li a4,43 + 6972: 04e109a3 sb a4,83(sp) + 6976: 00094683 lbu a3,0(s2) + 697a: 02a00713 li a4,42 + 697e: 08e68063 beq a3,a4,69fe <_vfiprintf_r+0x16a> + 6982: 47f2 lw a5,28(sp) + 6984: 844a mv s0,s2 + 6986: 4681 li a3,0 + 6988: 4625 li a2,9 + 698a: 00044703 lbu a4,0(s0) + 698e: 00140593 addi a1,s0,1 + 6992: fd070713 addi a4,a4,-48 + 6996: 0ae67963 bgeu a2,a4,6a48 <_vfiprintf_r+0x1b4> + 699a: cab5 beqz a3,6a0e <_vfiprintf_r+0x17a> + 699c: ce3e sw a5,28(sp) + 699e: a885 j 6a0e <_vfiprintf_r+0x17a> + 69a0: 00006797 auipc a5,0x6 + 69a4: ec878793 addi a5,a5,-312 # c868 <__sf_fake_stdout> + 69a8: 00f49563 bne s1,a5,69b2 <_vfiprintf_r+0x11e> + 69ac: 0089a483 lw s1,8(s3) + 69b0: bf39 j 68ce <_vfiprintf_r+0x3a> + 69b2: 00006797 auipc a5,0x6 + 69b6: e7678793 addi a5,a5,-394 # c828 <__sf_fake_stderr> + 69ba: f0f49ae3 bne s1,a5,68ce <_vfiprintf_r+0x3a> + 69be: 00c9a483 lw s1,12(s3) + 69c2: b731 j 68ce <_vfiprintf_r+0x3a> + 69c4: 85a6 mv a1,s1 + 69c6: 854e mv a0,s3 + 69c8: 262020ef jal ra,8c2a <__swsetup_r> + 69cc: d519 beqz a0,68da <_vfiprintf_r+0x46> + 69ce: 557d li a0,-1 + 69d0: 40fa lw ra,156(sp) + 69d2: 446a lw s0,152(sp) + 69d4: 44da lw s1,148(sp) + 69d6: 494a lw s2,144(sp) + 69d8: 49ba lw s3,140(sp) + 69da: 4a2a lw s4,136(sp) + 69dc: 4a9a lw s5,132(sp) + 69de: 4b0a lw s6,128(sp) + 69e0: 5bf6 lw s7,124(sp) + 69e2: 5c66 lw s8,120(sp) + 69e4: 5cd6 lw s9,116(sp) + 69e6: 610d addi sp,sp,160 + 69e8: 8082 ret + 69ea: 0405 addi s0,s0,1 + 69ec: bf11 j 6900 <_vfiprintf_r+0x6c> + 69ee: 41550533 sub a0,a0,s5 + 69f2: 00ac1533 sll a0,s8,a0 + 69f6: 8fc9 or a5,a5,a0 + 69f8: c83e sw a5,16(sp) + 69fa: 8922 mv s2,s0 + 69fc: b7a9 j 6946 <_vfiprintf_r+0xb2> + 69fe: 4732 lw a4,12(sp) + 6a00: 00470693 addi a3,a4,4 + 6a04: 4318 lw a4,0(a4) + 6a06: c636 sw a3,12(sp) + 6a08: 02074963 bltz a4,6a3a <_vfiprintf_r+0x1a6> + 6a0c: ce3a sw a4,28(sp) + 6a0e: 00044703 lbu a4,0(s0) + 6a12: 02e00793 li a5,46 + 6a16: 04f71f63 bne a4,a5,6a74 <_vfiprintf_r+0x1e0> + 6a1a: 00144703 lbu a4,1(s0) + 6a1e: 02a00793 li a5,42 + 6a22: 02f71b63 bne a4,a5,6a58 <_vfiprintf_r+0x1c4> + 6a26: 47b2 lw a5,12(sp) + 6a28: 0409 addi s0,s0,2 + 6a2a: 00478713 addi a4,a5,4 + 6a2e: 439c lw a5,0(a5) + 6a30: c63a sw a4,12(sp) + 6a32: 0207c163 bltz a5,6a54 <_vfiprintf_r+0x1c0> + 6a36: ca3e sw a5,20(sp) + 6a38: a835 j 6a74 <_vfiprintf_r+0x1e0> + 6a3a: 40e00733 neg a4,a4 + 6a3e: 0027e793 ori a5,a5,2 + 6a42: ce3a sw a4,28(sp) + 6a44: c83e sw a5,16(sp) + 6a46: b7e1 j 6a0e <_vfiprintf_r+0x17a> + 6a48: 036787b3 mul a5,a5,s6 + 6a4c: 4685 li a3,1 + 6a4e: 842e mv s0,a1 + 6a50: 97ba add a5,a5,a4 + 6a52: bf25 j 698a <_vfiprintf_r+0xf6> + 6a54: 57fd li a5,-1 + 6a56: b7c5 j 6a36 <_vfiprintf_r+0x1a2> + 6a58: 0405 addi s0,s0,1 + 6a5a: ca02 sw zero,20(sp) + 6a5c: 4681 li a3,0 + 6a5e: 4781 li a5,0 + 6a60: 4625 li a2,9 + 6a62: 00044703 lbu a4,0(s0) + 6a66: 00140593 addi a1,s0,1 + 6a6a: fd070713 addi a4,a4,-48 + 6a6e: 06e67863 bgeu a2,a4,6ade <_vfiprintf_r+0x24a> + 6a72: f2f1 bnez a3,6a36 <_vfiprintf_r+0x1a2> + 6a74: 00044583 lbu a1,0(s0) + 6a78: 460d li a2,3 + 6a7a: 00006517 auipc a0,0x6 + 6a7e: c5e50513 addi a0,a0,-930 # c6d8 <__clz_tab+0x148> + 6a82: 4a3030ef jal ra,a724 + 6a86: cd11 beqz a0,6aa2 <_vfiprintf_r+0x20e> + 6a88: 00006797 auipc a5,0x6 + 6a8c: c5078793 addi a5,a5,-944 # c6d8 <__clz_tab+0x148> + 6a90: 8d1d sub a0,a0,a5 + 6a92: 04000793 li a5,64 + 6a96: 00a797b3 sll a5,a5,a0 + 6a9a: 4542 lw a0,16(sp) + 6a9c: 0405 addi s0,s0,1 + 6a9e: 8d5d or a0,a0,a5 + 6aa0: c82a sw a0,16(sp) + 6aa2: 00044583 lbu a1,0(s0) + 6aa6: 4619 li a2,6 + 6aa8: 00006517 auipc a0,0x6 + 6aac: c3450513 addi a0,a0,-972 # c6dc <__clz_tab+0x14c> + 6ab0: 00140913 addi s2,s0,1 + 6ab4: 02b10423 sb a1,40(sp) + 6ab8: 46d030ef jal ra,a724 + 6abc: c125 beqz a0,6b1c <_vfiprintf_r+0x288> + 6abe: 00000797 auipc a5,0x0 + 6ac2: 1ec78793 addi a5,a5,492 # 6caa <_printf_float> + 6ac6: e795 bnez a5,6af2 <_vfiprintf_r+0x25e> + 6ac8: 4742 lw a4,16(sp) + 6aca: 47b2 lw a5,12(sp) + 6acc: 10077713 andi a4,a4,256 + 6ad0: cf09 beqz a4,6aea <_vfiprintf_r+0x256> + 6ad2: 0791 addi a5,a5,4 + 6ad4: c63e sw a5,12(sp) + 6ad6: 5792 lw a5,36(sp) + 6ad8: 97d2 add a5,a5,s4 + 6ada: d23e sw a5,36(sp) + 6adc: b50d j 68fe <_vfiprintf_r+0x6a> + 6ade: 036787b3 mul a5,a5,s6 + 6ae2: 4685 li a3,1 + 6ae4: 842e mv s0,a1 + 6ae6: 97ba add a5,a5,a4 + 6ae8: bfad j 6a62 <_vfiprintf_r+0x1ce> + 6aea: 079d addi a5,a5,7 + 6aec: 9be1 andi a5,a5,-8 + 6aee: 07a1 addi a5,a5,8 + 6af0: b7d5 j 6ad4 <_vfiprintf_r+0x240> + 6af2: 0078 addi a4,sp,12 + 6af4: 00000697 auipc a3,0x0 + 6af8: d5c68693 addi a3,a3,-676 # 6850 <__sfputs_r> + 6afc: 8626 mv a2,s1 + 6afe: 080c addi a1,sp,16 + 6b00: 854e mv a0,s3 + 6b02: 2265 jal 6caa <_printf_float> + 6b04: 57fd li a5,-1 + 6b06: 8a2a mv s4,a0 + 6b08: fcf517e3 bne a0,a5,6ad6 <_vfiprintf_r+0x242> + 6b0c: 00c4d783 lhu a5,12(s1) + 6b10: 0407f793 andi a5,a5,64 + 6b14: ea079de3 bnez a5,69ce <_vfiprintf_r+0x13a> + 6b18: 5512 lw a0,36(sp) + 6b1a: bd5d j 69d0 <_vfiprintf_r+0x13c> + 6b1c: 0078 addi a4,sp,12 + 6b1e: 00000697 auipc a3,0x0 + 6b22: d3268693 addi a3,a3,-718 # 6850 <__sfputs_r> + 6b26: 8626 mv a2,s1 + 6b28: 080c addi a1,sp,16 + 6b2a: 854e mv a0,s3 + 6b2c: 27b9 jal 727a <_printf_i> + 6b2e: bfd9 j 6b04 <_vfiprintf_r+0x270> + +00006b30 <__cvt>: + 6b30: 7179 addi sp,sp,-48 + 6b32: d422 sw s0,40(sp) + 6b34: d04a sw s2,32(sp) + 6b36: cc52 sw s4,24(sp) + 6b38: ca56 sw s5,20(sp) + 6b3a: c85a sw s6,16(sp) + 6b3c: d606 sw ra,44(sp) + 6b3e: d226 sw s1,36(sp) + 6b40: ce4e sw s3,28(sp) + 6b42: 8a3a mv s4,a4 + 6b44: 8aae mv s5,a1 + 6b46: 8432 mv s0,a2 + 6b48: 8936 mv s2,a3 + 6b4a: 8b42 mv s6,a6 + 6b4c: 4701 li a4,0 + 6b4e: 00065863 bgez a2,6b5e <__cvt+0x2e> + 6b52: 80000737 lui a4,0x80000 + 6b56: 00c74433 xor s0,a4,a2 + 6b5a: 02d00713 li a4,45 + 6b5e: 00e78023 sb a4,0(a5) + 6b62: fdf8f493 andi s1,a7,-33 + 6b66: 04600793 li a5,70 + 6b6a: 468d li a3,3 + 6b6c: 00f48863 beq s1,a5,6b7c <__cvt+0x4c> + 6b70: 04500793 li a5,69 + 6b74: 4689 li a3,2 + 6b76: 00f49363 bne s1,a5,6b7c <__cvt+0x4c> + 6b7a: 0905 addi s2,s2,1 + 6b7c: 87da mv a5,s6 + 6b7e: 00c10893 addi a7,sp,12 + 6b82: 00810813 addi a6,sp,8 + 6b86: 874a mv a4,s2 + 6b88: 85d6 mv a1,s5 + 6b8a: 8622 mv a2,s0 + 6b8c: 2fa020ef jal ra,8e86 <_dtoa_r> + 6b90: 04700793 li a5,71 + 6b94: 89aa mv s3,a0 + 6b96: 00f49663 bne s1,a5,6ba2 <__cvt+0x72> + 6b9a: 001a7a13 andi s4,s4,1 + 6b9e: 040a0a63 beqz s4,6bf2 <__cvt+0xc2> + 6ba2: 04600793 li a5,70 + 6ba6: 01298a33 add s4,s3,s2 + 6baa: 02f49763 bne s1,a5,6bd8 <__cvt+0xa8> + 6bae: 0009c703 lbu a4,0(s3) + 6bb2: 03000793 li a5,48 + 6bb6: 00f71e63 bne a4,a5,6bd2 <__cvt+0xa2> + 6bba: 4601 li a2,0 + 6bbc: 4681 li a3,0 + 6bbe: 8556 mv a0,s5 + 6bc0: 85a2 mv a1,s0 + 6bc2: b6bfe0ef jal ra,572c <__eqdf2> + 6bc6: c511 beqz a0,6bd2 <__cvt+0xa2> + 6bc8: 4785 li a5,1 + 6bca: 41278933 sub s2,a5,s2 + 6bce: 012b2023 sw s2,0(s6) # 1000000 <_data_lma+0xff3568> + 6bd2: 000b2783 lw a5,0(s6) + 6bd6: 9a3e add s4,s4,a5 + 6bd8: 4601 li a2,0 + 6bda: 4681 li a3,0 + 6bdc: 8556 mv a0,s5 + 6bde: 85a2 mv a1,s0 + 6be0: b4dfe0ef jal ra,572c <__eqdf2> + 6be4: e111 bnez a0,6be8 <__cvt+0xb8> + 6be6: c652 sw s4,12(sp) + 6be8: 03000713 li a4,48 + 6bec: 47b2 lw a5,12(sp) + 6bee: 0347e263 bltu a5,s4,6c12 <__cvt+0xe2> + 6bf2: 47b2 lw a5,12(sp) + 6bf4: 5742 lw a4,48(sp) + 6bf6: 50b2 lw ra,44(sp) + 6bf8: 5422 lw s0,40(sp) + 6bfa: 413787b3 sub a5,a5,s3 + 6bfe: c31c sw a5,0(a4) + 6c00: 854e mv a0,s3 + 6c02: 5492 lw s1,36(sp) + 6c04: 5902 lw s2,32(sp) + 6c06: 49f2 lw s3,28(sp) + 6c08: 4a62 lw s4,24(sp) + 6c0a: 4ad2 lw s5,20(sp) + 6c0c: 4b42 lw s6,16(sp) + 6c0e: 6145 addi sp,sp,48 + 6c10: 8082 ret + 6c12: 00178693 addi a3,a5,1 + 6c16: c636 sw a3,12(sp) + 6c18: 00e78023 sb a4,0(a5) + 6c1c: bfc1 j 6bec <__cvt+0xbc> + +00006c1e <__exponent>: + 6c1e: 00c50023 sb a2,0(a0) + 6c22: 00250713 addi a4,a0,2 + 6c26: 02b00793 li a5,43 + 6c2a: 0005d663 bgez a1,6c36 <__exponent+0x18> + 6c2e: 40b005b3 neg a1,a1 + 6c32: 02d00793 li a5,45 + 6c36: 00f500a3 sb a5,1(a0) + 6c3a: 47a5 li a5,9 + 6c3c: 04b7da63 bge a5,a1,6c90 <__exponent+0x72> + 6c40: 1141 addi sp,sp,-16 + 6c42: 00f10793 addi a5,sp,15 + 6c46: 88be mv a7,a5 + 6c48: 4829 li a6,10 + 6c4a: 06300313 li t1,99 + 6c4e: 0305e6b3 rem a3,a1,a6 + 6c52: fff78613 addi a2,a5,-1 + 6c56: 03068693 addi a3,a3,48 + 6c5a: fed78fa3 sb a3,-1(a5) + 6c5e: 0305c6b3 div a3,a1,a6 + 6c62: 00b34d63 blt t1,a1,6c7c <__exponent+0x5e> + 6c66: 03068693 addi a3,a3,48 + 6c6a: 17f9 addi a5,a5,-2 + 6c6c: fed60fa3 sb a3,-1(a2) # ff7fffff <_eusrstack+0xdf7effff> + 6c70: 0117e963 bltu a5,a7,6c82 <__exponent+0x64> + 6c74: 40a70533 sub a0,a4,a0 + 6c78: 0141 addi sp,sp,16 + 6c7a: 8082 ret + 6c7c: 87b2 mv a5,a2 + 6c7e: 85b6 mv a1,a3 + 6c80: b7f9 j 6c4e <__exponent+0x30> + 6c82: 0785 addi a5,a5,1 + 6c84: fff7c683 lbu a3,-1(a5) + 6c88: 0705 addi a4,a4,1 + 6c8a: fed70fa3 sb a3,-1(a4) # 7fffffff <_eusrstack+0x5ffeffff> + 6c8e: b7cd j 6c70 <__exponent+0x52> + 6c90: 03000793 li a5,48 + 6c94: 00450713 addi a4,a0,4 + 6c98: 03058593 addi a1,a1,48 + 6c9c: 00f50123 sb a5,2(a0) + 6ca0: 00b501a3 sb a1,3(a0) + 6ca4: 40a70533 sub a0,a4,a0 + 6ca8: 8082 ret + +00006caa <_printf_float>: + 6caa: 7119 addi sp,sp,-128 + 6cac: ce3a sw a4,28(sp) + 6cae: de86 sw ra,124(sp) + 6cb0: dca2 sw s0,120(sp) + 6cb2: daa6 sw s1,116(sp) + 6cb4: 842e mv s0,a1 + 6cb6: d8ca sw s2,112(sp) + 6cb8: d6ce sw s3,108(sp) + 6cba: d4d2 sw s4,104(sp) + 6cbc: 89b6 mv s3,a3 + 6cbe: d0da sw s6,96(sp) + 6cc0: cede sw s7,92(sp) + 6cc2: cce2 sw s8,88(sp) + 6cc4: 8932 mv s2,a2 + 6cc6: d2d6 sw s5,100(sp) + 6cc8: cae6 sw s9,84(sp) + 6cca: c8ea sw s10,80(sp) + 6ccc: c6ee sw s11,76(sp) + 6cce: 84aa mv s1,a0 + 6cd0: 0fb030ef jal ra,a5ca <_localeconv_r> + 6cd4: 00052b83 lw s7,0(a0) + 6cd8: 855e mv a0,s7 + 6cda: 78b000ef jal ra,7c64 + 6cde: 00042b03 lw s6,0(s0) + 6ce2: 4772 lw a4,28(sp) + 6ce4: dc02 sw zero,56(sp) + 6ce6: 100b7693 andi a3,s6,256 + 6cea: 8c2a mv s8,a0 + 6cec: 01844a03 lbu s4,24(s0) + 6cf0: 431c lw a5,0(a4) + 6cf2: caf1 beqz a3,6dc6 <_printf_float+0x11c> + 6cf4: 00478693 addi a3,a5,4 + 6cf8: c314 sw a3,0(a4) + 6cfa: 439c lw a5,0(a5) + 6cfc: 1008 addi a0,sp,32 + 6cfe: 4398 lw a4,0(a5) + 6d00: d03a sw a4,32(sp) + 6d02: 43d8 lw a4,4(a5) + 6d04: d23a sw a4,36(sp) + 6d06: 4798 lw a4,8(a5) + 6d08: d43a sw a4,40(sp) + 6d0a: 47dc lw a5,12(a5) + 6d0c: d63e sw a5,44(sp) + 6d0e: 074050ef jal ra,bd82 <__trunctfdf2> + 6d12: c428 sw a0,72(s0) + 6d14: c46c sw a1,76(s0) + 6d16: 04c42c83 lw s9,76(s0) + 6d1a: 00006717 auipc a4,0x6 + 6d1e: 9ce70713 addi a4,a4,-1586 # c6e8 <__clz_tab+0x158> + 6d22: 04842a83 lw s5,72(s0) + 6d26: 00072d03 lw s10,0(a4) + 6d2a: 00472d83 lw s11,4(a4) + 6d2e: 001c9793 slli a5,s9,0x1 + 6d32: 8385 srli a5,a5,0x1 + 6d34: 866a mv a2,s10 + 6d36: 86ee mv a3,s11 + 6d38: 8556 mv a0,s5 + 6d3a: 85be mv a1,a5 + 6d3c: ce3e sw a5,28(sp) + 6d3e: 49f040ef jal ra,b9dc <__unorddf2> + 6d42: ed41 bnez a0,6dda <_printf_float+0x130> + 6d44: 47f2 lw a5,28(sp) + 6d46: 866a mv a2,s10 + 6d48: 86ee mv a3,s11 + 6d4a: 8556 mv a0,s5 + 6d4c: 85be mv a1,a5 + 6d4e: af7fe0ef jal ra,5844 <__ledf2> + 6d52: 08a05463 blez a0,6dda <_printf_float+0x130> + 6d56: 4601 li a2,0 + 6d58: 4681 li a3,0 + 6d5a: 8556 mv a0,s5 + 6d5c: 85e6 mv a1,s9 + 6d5e: ae7fe0ef jal ra,5844 <__ledf2> + 6d62: 00055663 bgez a0,6d6e <_printf_float+0xc4> + 6d66: 02d00793 li a5,45 + 6d6a: 04f401a3 sb a5,67(s0) + 6d6e: 04700793 li a5,71 + 6d72: 00006a97 auipc s5,0x6 + 6d76: 97ea8a93 addi s5,s5,-1666 # c6f0 <__clz_tab+0x160> + 6d7a: 0147f663 bgeu a5,s4,6d86 <_printf_float+0xdc> + 6d7e: 00006a97 auipc s5,0x6 + 6d82: 976a8a93 addi s5,s5,-1674 # c6f4 <__clz_tab+0x164> + 6d86: ffbb7b13 andi s6,s6,-5 + 6d8a: 478d li a5,3 + 6d8c: 01642023 sw s6,0(s0) + 6d90: c81c sw a5,16(s0) + 6d92: 4b01 li s6,0 + 6d94: 874e mv a4,s3 + 6d96: 86ca mv a3,s2 + 6d98: 1870 addi a2,sp,60 + 6d9a: 85a2 mv a1,s0 + 6d9c: 8526 mv a0,s1 + 6d9e: 2ec1 jal 716e <_printf_common> + 6da0: 5cfd li s9,-1 + 6da2: 15951e63 bne a0,s9,6efe <_printf_float+0x254> + 6da6: 557d li a0,-1 + 6da8: 50f6 lw ra,124(sp) + 6daa: 5466 lw s0,120(sp) + 6dac: 54d6 lw s1,116(sp) + 6dae: 5946 lw s2,112(sp) + 6db0: 59b6 lw s3,108(sp) + 6db2: 5a26 lw s4,104(sp) + 6db4: 5a96 lw s5,100(sp) + 6db6: 5b06 lw s6,96(sp) + 6db8: 4bf6 lw s7,92(sp) + 6dba: 4c66 lw s8,88(sp) + 6dbc: 4cd6 lw s9,84(sp) + 6dbe: 4d46 lw s10,80(sp) + 6dc0: 4db6 lw s11,76(sp) + 6dc2: 6109 addi sp,sp,128 + 6dc4: 8082 ret + 6dc6: 079d addi a5,a5,7 + 6dc8: 9be1 andi a5,a5,-8 + 6dca: 00878693 addi a3,a5,8 + 6dce: c314 sw a3,0(a4) + 6dd0: 4398 lw a4,0(a5) + 6dd2: 43dc lw a5,4(a5) + 6dd4: c438 sw a4,72(s0) + 6dd6: c47c sw a5,76(s0) + 6dd8: bf3d j 6d16 <_printf_float+0x6c> + 6dda: 8656 mv a2,s5 + 6ddc: 86e6 mv a3,s9 + 6dde: 8556 mv a0,s5 + 6de0: 85e6 mv a1,s9 + 6de2: 3fb040ef jal ra,b9dc <__unorddf2> + 6de6: cd11 beqz a0,6e02 <_printf_float+0x158> + 6de8: 04700793 li a5,71 + 6dec: 00006a97 auipc s5,0x6 + 6df0: 90ca8a93 addi s5,s5,-1780 # c6f8 <__clz_tab+0x168> + 6df4: f947f9e3 bgeu a5,s4,6d86 <_printf_float+0xdc> + 6df8: 00005a97 auipc s5,0x5 + 6dfc: 6c8a8a93 addi s5,s5,1736 # c4c0 <_exit+0x4b0> + 6e00: b759 j 6d86 <_printf_float+0xdc> + 6e02: 405c lw a5,4(s0) + 6e04: 577d li a4,-1 + 6e06: 0dfa7d13 andi s10,s4,223 + 6e0a: 08e79563 bne a5,a4,6e94 <_printf_float+0x1ea> + 6e0e: 4799 li a5,6 + 6e10: c05c sw a5,4(s0) + 6e12: 4054 lw a3,4(s0) + 6e14: 400b6713 ori a4,s6,1024 + 6e18: 183c addi a5,sp,56 + 6e1a: 85d6 mv a1,s5 + 6e1c: c03e sw a5,0(sp) + 6e1e: c018 sw a4,0(s0) + 6e20: 03310793 addi a5,sp,51 + 6e24: c202 sw zero,4(sp) + 6e26: 88d2 mv a7,s4 + 6e28: 03410813 addi a6,sp,52 + 6e2c: 8666 mv a2,s9 + 6e2e: 8526 mv a0,s1 + 6e30: d01ff0ef jal ra,6b30 <__cvt> + 6e34: 04700793 li a5,71 + 6e38: 8aaa mv s5,a0 + 6e3a: 55d2 lw a1,52(sp) + 6e3c: 00fd1b63 bne s10,a5,6e52 <_printf_float+0x1a8> + 6e40: 57f5 li a5,-3 + 6e42: 00f5c563 blt a1,a5,6e4c <_printf_float+0x1a2> + 6e46: 405c lw a5,4(s0) + 6e48: 08b7d863 bge a5,a1,6ed8 <_printf_float+0x22e> + 6e4c: 1a79 addi s4,s4,-2 + 6e4e: 0ffa7a13 andi s4,s4,255 + 6e52: 06500793 li a5,101 + 6e56: 0547e663 bltu a5,s4,6ea2 <_printf_float+0x1f8> + 6e5a: 15fd addi a1,a1,-1 + 6e5c: 8652 mv a2,s4 + 6e5e: 05040513 addi a0,s0,80 + 6e62: da2e sw a1,52(sp) + 6e64: dbbff0ef jal ra,6c1e <__exponent> + 6e68: 5762 lw a4,56(sp) + 6e6a: 4685 li a3,1 + 6e6c: 8b2a mv s6,a0 + 6e6e: 00a707b3 add a5,a4,a0 + 6e72: c81c sw a5,16(s0) + 6e74: 00e6c563 blt a3,a4,6e7e <_printf_float+0x1d4> + 6e78: 4018 lw a4,0(s0) + 6e7a: 8b05 andi a4,a4,1 + 6e7c: c319 beqz a4,6e82 <_printf_float+0x1d8> + 6e7e: 0785 addi a5,a5,1 + 6e80: c81c sw a5,16(s0) + 6e82: 03314783 lbu a5,51(sp) + 6e86: f00787e3 beqz a5,6d94 <_printf_float+0xea> + 6e8a: 02d00793 li a5,45 + 6e8e: 04f401a3 sb a5,67(s0) + 6e92: b709 j 6d94 <_printf_float+0xea> + 6e94: 04700713 li a4,71 + 6e98: f6ed1de3 bne s10,a4,6e12 <_printf_float+0x168> + 6e9c: fbbd bnez a5,6e12 <_printf_float+0x168> + 6e9e: 4785 li a5,1 + 6ea0: bf85 j 6e10 <_printf_float+0x166> + 6ea2: 06600793 li a5,102 + 6ea6: 02fa1b63 bne s4,a5,6edc <_printf_float+0x232> + 6eaa: 405c lw a5,4(s0) + 6eac: 00b05b63 blez a1,6ec2 <_printf_float+0x218> + 6eb0: c80c sw a1,16(s0) + 6eb2: e781 bnez a5,6eba <_printf_float+0x210> + 6eb4: 4018 lw a4,0(s0) + 6eb6: 8b05 andi a4,a4,1 + 6eb8: cf09 beqz a4,6ed2 <_printf_float+0x228> + 6eba: 0785 addi a5,a5,1 + 6ebc: 97ae add a5,a5,a1 + 6ebe: c81c sw a5,16(s0) + 6ec0: a809 j 6ed2 <_printf_float+0x228> + 6ec2: e789 bnez a5,6ecc <_printf_float+0x222> + 6ec4: 4018 lw a4,0(s0) + 6ec6: 4685 li a3,1 + 6ec8: 8b05 andi a4,a4,1 + 6eca: c319 beqz a4,6ed0 <_printf_float+0x226> + 6ecc: 00278693 addi a3,a5,2 + 6ed0: c814 sw a3,16(s0) + 6ed2: cc2c sw a1,88(s0) + 6ed4: 4b01 li s6,0 + 6ed6: b775 j 6e82 <_printf_float+0x1d8> + 6ed8: 06700a13 li s4,103 + 6edc: 57e2 lw a5,56(sp) + 6ede: 00f5c963 blt a1,a5,6ef0 <_printf_float+0x246> + 6ee2: 401c lw a5,0(s0) + 6ee4: c80c sw a1,16(s0) + 6ee6: 8b85 andi a5,a5,1 + 6ee8: d7ed beqz a5,6ed2 <_printf_float+0x228> + 6eea: 00158793 addi a5,a1,1 + 6eee: bfc1 j 6ebe <_printf_float+0x214> + 6ef0: 4705 li a4,1 + 6ef2: 00b04463 bgtz a1,6efa <_printf_float+0x250> + 6ef6: 4709 li a4,2 + 6ef8: 8f0d sub a4,a4,a1 + 6efa: 97ba add a5,a5,a4 + 6efc: b7c9 j 6ebe <_printf_float+0x214> + 6efe: 401c lw a5,0(s0) + 6f00: 4007f713 andi a4,a5,1024 + 6f04: e315 bnez a4,6f28 <_printf_float+0x27e> + 6f06: 4814 lw a3,16(s0) + 6f08: 8656 mv a2,s5 + 6f0a: 85ca mv a1,s2 + 6f0c: 8526 mv a0,s1 + 6f0e: 9982 jalr s3 + 6f10: e9950be3 beq a0,s9,6da6 <_printf_float+0xfc> + 6f14: 401c lw a5,0(s0) + 6f16: 8b89 andi a5,a5,2 + 6f18: 24079663 bnez a5,7164 <_printf_float+0x4ba> + 6f1c: 57f2 lw a5,60(sp) + 6f1e: 4448 lw a0,12(s0) + 6f20: e8f554e3 bge a0,a5,6da8 <_printf_float+0xfe> + 6f24: 853e mv a0,a5 + 6f26: b549 j 6da8 <_printf_float+0xfe> + 6f28: 06500713 li a4,101 + 6f2c: 19477b63 bgeu a4,s4,70c2 <_printf_float+0x418> + 6f30: 4428 lw a0,72(s0) + 6f32: 446c lw a1,76(s0) + 6f34: 4601 li a2,0 + 6f36: 4681 li a3,0 + 6f38: ff4fe0ef jal ra,572c <__eqdf2> + 6f3c: e939 bnez a0,6f92 <_printf_float+0x2e8> + 6f3e: 4685 li a3,1 + 6f40: 00005617 auipc a2,0x5 + 6f44: 7bc60613 addi a2,a2,1980 # c6fc <__clz_tab+0x16c> + 6f48: 85ca mv a1,s2 + 6f4a: 8526 mv a0,s1 + 6f4c: 9982 jalr s3 + 6f4e: e5950ce3 beq a0,s9,6da6 <_printf_float+0xfc> + 6f52: 5752 lw a4,52(sp) + 6f54: 57e2 lw a5,56(sp) + 6f56: 00f74563 blt a4,a5,6f60 <_printf_float+0x2b6> + 6f5a: 401c lw a5,0(s0) + 6f5c: 8b85 andi a5,a5,1 + 6f5e: dbdd beqz a5,6f14 <_printf_float+0x26a> + 6f60: 86e2 mv a3,s8 + 6f62: 865e mv a2,s7 + 6f64: 85ca mv a1,s2 + 6f66: 8526 mv a0,s1 + 6f68: 9982 jalr s3 + 6f6a: 57fd li a5,-1 + 6f6c: e2f50de3 beq a0,a5,6da6 <_printf_float+0xfc> + 6f70: 4a01 li s4,0 + 6f72: 01a40a93 addi s5,s0,26 + 6f76: 5b7d li s6,-1 + 6f78: 57e2 lw a5,56(sp) + 6f7a: 17fd addi a5,a5,-1 + 6f7c: f8fa5ce3 bge s4,a5,6f14 <_printf_float+0x26a> + 6f80: 4685 li a3,1 + 6f82: 8656 mv a2,s5 + 6f84: 85ca mv a1,s2 + 6f86: 8526 mv a0,s1 + 6f88: 9982 jalr s3 + 6f8a: e1650ee3 beq a0,s6,6da6 <_printf_float+0xfc> + 6f8e: 0a05 addi s4,s4,1 + 6f90: b7e5 j 6f78 <_printf_float+0x2ce> + 6f92: 57d2 lw a5,52(sp) + 6f94: 06f04663 bgtz a5,7000 <_printf_float+0x356> + 6f98: 4685 li a3,1 + 6f9a: 00005617 auipc a2,0x5 + 6f9e: 76260613 addi a2,a2,1890 # c6fc <__clz_tab+0x16c> + 6fa2: 85ca mv a1,s2 + 6fa4: 8526 mv a0,s1 + 6fa6: 9982 jalr s3 + 6fa8: df950fe3 beq a0,s9,6da6 <_printf_float+0xfc> + 6fac: 57d2 lw a5,52(sp) + 6fae: 5762 lw a4,56(sp) + 6fb0: 8fd9 or a5,a5,a4 + 6fb2: e781 bnez a5,6fba <_printf_float+0x310> + 6fb4: 401c lw a5,0(s0) + 6fb6: 8b85 andi a5,a5,1 + 6fb8: dfb1 beqz a5,6f14 <_printf_float+0x26a> + 6fba: 86e2 mv a3,s8 + 6fbc: 865e mv a2,s7 + 6fbe: 85ca mv a1,s2 + 6fc0: 8526 mv a0,s1 + 6fc2: 9982 jalr s3 + 6fc4: 57fd li a5,-1 + 6fc6: def500e3 beq a0,a5,6da6 <_printf_float+0xfc> + 6fca: 4a01 li s4,0 + 6fcc: 01a40b13 addi s6,s0,26 + 6fd0: 5bfd li s7,-1 + 6fd2: 57d2 lw a5,52(sp) + 6fd4: 40f007b3 neg a5,a5 + 6fd8: 00fa4b63 blt s4,a5,6fee <_printf_float+0x344> + 6fdc: 56e2 lw a3,56(sp) + 6fde: 8656 mv a2,s5 + 6fe0: 85ca mv a1,s2 + 6fe2: 8526 mv a0,s1 + 6fe4: 9982 jalr s3 + 6fe6: 57fd li a5,-1 + 6fe8: f2f516e3 bne a0,a5,6f14 <_printf_float+0x26a> + 6fec: bb6d j 6da6 <_printf_float+0xfc> + 6fee: 4685 li a3,1 + 6ff0: 865a mv a2,s6 + 6ff2: 85ca mv a1,s2 + 6ff4: 8526 mv a0,s1 + 6ff6: 9982 jalr s3 + 6ff8: db7507e3 beq a0,s7,6da6 <_printf_float+0xfc> + 6ffc: 0a05 addi s4,s4,1 + 6ffe: bfd1 j 6fd2 <_printf_float+0x328> + 7000: 4c3c lw a5,88(s0) + 7002: 5a62 lw s4,56(sp) + 7004: 0147d363 bge a5,s4,700a <_printf_float+0x360> + 7008: 8a3e mv s4,a5 + 700a: 01405a63 blez s4,701e <_printf_float+0x374> + 700e: 86d2 mv a3,s4 + 7010: 8656 mv a2,s5 + 7012: 85ca mv a1,s2 + 7014: 8526 mv a0,s1 + 7016: 9982 jalr s3 + 7018: 57fd li a5,-1 + 701a: d8f506e3 beq a0,a5,6da6 <_printf_float+0xfc> + 701e: 4c81 li s9,0 + 7020: 01a40d13 addi s10,s0,26 + 7024: 5dfd li s11,-1 + 7026: a809 j 7038 <_printf_float+0x38e> + 7028: 4685 li a3,1 + 702a: 866a mv a2,s10 + 702c: 85ca mv a1,s2 + 702e: 8526 mv a0,s1 + 7030: 9982 jalr s3 + 7032: d7b50ae3 beq a0,s11,6da6 <_printf_float+0xfc> + 7036: 0c85 addi s9,s9,1 + 7038: 05842b03 lw s6,88(s0) + 703c: 87d2 mv a5,s4 + 703e: 000a5363 bgez s4,7044 <_printf_float+0x39a> + 7042: 4781 li a5,0 + 7044: 40fb07b3 sub a5,s6,a5 + 7048: fefcc0e3 blt s9,a5,7028 <_printf_float+0x37e> + 704c: 5752 lw a4,52(sp) + 704e: 57e2 lw a5,56(sp) + 7050: 02f74d63 blt a4,a5,708a <_printf_float+0x3e0> + 7054: 401c lw a5,0(s0) + 7056: 8b85 andi a5,a5,1 + 7058: eb8d bnez a5,708a <_printf_float+0x3e0> + 705a: 57e2 lw a5,56(sp) + 705c: 5752 lw a4,52(sp) + 705e: 40e78a33 sub s4,a5,a4 + 7062: 00eb4463 blt s6,a4,706a <_printf_float+0x3c0> + 7066: 41678a33 sub s4,a5,s6 + 706a: 01405b63 blez s4,7080 <_printf_float+0x3d6> + 706e: 86d2 mv a3,s4 + 7070: 016a8633 add a2,s5,s6 + 7074: 85ca mv a1,s2 + 7076: 8526 mv a0,s1 + 7078: 9982 jalr s3 + 707a: 57fd li a5,-1 + 707c: d2f505e3 beq a0,a5,6da6 <_printf_float+0xfc> + 7080: 4a81 li s5,0 + 7082: 01a40b13 addi s6,s0,26 + 7086: 5bfd li s7,-1 + 7088: a015 j 70ac <_printf_float+0x402> + 708a: 86e2 mv a3,s8 + 708c: 865e mv a2,s7 + 708e: 85ca mv a1,s2 + 7090: 8526 mv a0,s1 + 7092: 9982 jalr s3 + 7094: 57fd li a5,-1 + 7096: fcf512e3 bne a0,a5,705a <_printf_float+0x3b0> + 709a: b331 j 6da6 <_printf_float+0xfc> + 709c: 4685 li a3,1 + 709e: 865a mv a2,s6 + 70a0: 85ca mv a1,s2 + 70a2: 8526 mv a0,s1 + 70a4: 9982 jalr s3 + 70a6: d17500e3 beq a0,s7,6da6 <_printf_float+0xfc> + 70aa: 0a85 addi s5,s5,1 + 70ac: 5752 lw a4,52(sp) + 70ae: 57e2 lw a5,56(sp) + 70b0: 8f99 sub a5,a5,a4 + 70b2: 8752 mv a4,s4 + 70b4: 000a5363 bgez s4,70ba <_printf_float+0x410> + 70b8: 4701 li a4,0 + 70ba: 8f99 sub a5,a5,a4 + 70bc: fefac0e3 blt s5,a5,709c <_printf_float+0x3f2> + 70c0: bd91 j 6f14 <_printf_float+0x26a> + 70c2: 56e2 lw a3,56(sp) + 70c4: 4705 li a4,1 + 70c6: 00d74463 blt a4,a3,70ce <_printf_float+0x424> + 70ca: 8b85 andi a5,a5,1 + 70cc: c7b5 beqz a5,7138 <_printf_float+0x48e> + 70ce: 4685 li a3,1 + 70d0: 8656 mv a2,s5 + 70d2: 85ca mv a1,s2 + 70d4: 8526 mv a0,s1 + 70d6: 9982 jalr s3 + 70d8: 5a7d li s4,-1 + 70da: cd4506e3 beq a0,s4,6da6 <_printf_float+0xfc> + 70de: 86e2 mv a3,s8 + 70e0: 865e mv a2,s7 + 70e2: 85ca mv a1,s2 + 70e4: 8526 mv a0,s1 + 70e6: 9982 jalr s3 + 70e8: cb450fe3 beq a0,s4,6da6 <_printf_float+0xfc> + 70ec: 4428 lw a0,72(s0) + 70ee: 446c lw a1,76(s0) + 70f0: 4601 li a2,0 + 70f2: 4681 li a3,0 + 70f4: e38fe0ef jal ra,572c <__eqdf2> + 70f8: c91d beqz a0,712e <_printf_float+0x484> + 70fa: 56e2 lw a3,56(sp) + 70fc: 001a8613 addi a2,s5,1 + 7100: 85ca mv a1,s2 + 7102: 16fd addi a3,a3,-1 + 7104: 8526 mv a0,s1 + 7106: 9982 jalr s3 + 7108: c9450fe3 beq a0,s4,6da6 <_printf_float+0xfc> + 710c: 86da mv a3,s6 + 710e: 05040613 addi a2,s0,80 + 7112: b5f9 j 6fe0 <_printf_float+0x336> + 7114: 4685 li a3,1 + 7116: 8656 mv a2,s5 + 7118: 85ca mv a1,s2 + 711a: 8526 mv a0,s1 + 711c: 9982 jalr s3 + 711e: c97504e3 beq a0,s7,6da6 <_printf_float+0xfc> + 7122: 0a05 addi s4,s4,1 + 7124: 57e2 lw a5,56(sp) + 7126: 17fd addi a5,a5,-1 + 7128: fefa46e3 blt s4,a5,7114 <_printf_float+0x46a> + 712c: b7c5 j 710c <_printf_float+0x462> + 712e: 4a01 li s4,0 + 7130: 01a40a93 addi s5,s0,26 + 7134: 5bfd li s7,-1 + 7136: b7fd j 7124 <_printf_float+0x47a> + 7138: 4685 li a3,1 + 713a: 8656 mv a2,s5 + 713c: 85ca mv a1,s2 + 713e: 8526 mv a0,s1 + 7140: 9982 jalr s3 + 7142: fd9515e3 bne a0,s9,710c <_printf_float+0x462> + 7146: b185 j 6da6 <_printf_float+0xfc> + 7148: 4685 li a3,1 + 714a: 8656 mv a2,s5 + 714c: 85ca mv a1,s2 + 714e: 8526 mv a0,s1 + 7150: 9982 jalr s3 + 7152: c5650ae3 beq a0,s6,6da6 <_printf_float+0xfc> + 7156: 0a05 addi s4,s4,1 + 7158: 445c lw a5,12(s0) + 715a: 5772 lw a4,60(sp) + 715c: 8f99 sub a5,a5,a4 + 715e: fefa45e3 blt s4,a5,7148 <_printf_float+0x49e> + 7162: bb6d j 6f1c <_printf_float+0x272> + 7164: 4a01 li s4,0 + 7166: 01940a93 addi s5,s0,25 + 716a: 5b7d li s6,-1 + 716c: b7f5 j 7158 <_printf_float+0x4ae> + +0000716e <_printf_common>: + 716e: 7179 addi sp,sp,-48 + 7170: ca56 sw s5,20(sp) + 7172: 499c lw a5,16(a1) + 7174: 8aba mv s5,a4 + 7176: 4598 lw a4,8(a1) + 7178: d422 sw s0,40(sp) + 717a: d226 sw s1,36(sp) + 717c: ce4e sw s3,28(sp) + 717e: cc52 sw s4,24(sp) + 7180: d606 sw ra,44(sp) + 7182: d04a sw s2,32(sp) + 7184: c85a sw s6,16(sp) + 7186: c65e sw s7,12(sp) + 7188: 89aa mv s3,a0 + 718a: 842e mv s0,a1 + 718c: 84b2 mv s1,a2 + 718e: 8a36 mv s4,a3 + 7190: 00e7d363 bge a5,a4,7196 <_printf_common+0x28> + 7194: 87ba mv a5,a4 + 7196: c09c sw a5,0(s1) + 7198: 04344703 lbu a4,67(s0) + 719c: c319 beqz a4,71a2 <_printf_common+0x34> + 719e: 0785 addi a5,a5,1 + 71a0: c09c sw a5,0(s1) + 71a2: 401c lw a5,0(s0) + 71a4: 0207f793 andi a5,a5,32 + 71a8: c781 beqz a5,71b0 <_printf_common+0x42> + 71aa: 409c lw a5,0(s1) + 71ac: 0789 addi a5,a5,2 + 71ae: c09c sw a5,0(s1) + 71b0: 00042903 lw s2,0(s0) + 71b4: 00697913 andi s2,s2,6 + 71b8: 00091a63 bnez s2,71cc <_printf_common+0x5e> + 71bc: 01940b13 addi s6,s0,25 + 71c0: 5bfd li s7,-1 + 71c2: 445c lw a5,12(s0) + 71c4: 4098 lw a4,0(s1) + 71c6: 8f99 sub a5,a5,a4 + 71c8: 04f94c63 blt s2,a5,7220 <_printf_common+0xb2> + 71cc: 401c lw a5,0(s0) + 71ce: 04344683 lbu a3,67(s0) + 71d2: 0207f793 andi a5,a5,32 + 71d6: 00d036b3 snez a3,a3 + 71da: eba5 bnez a5,724a <_printf_common+0xdc> + 71dc: 04340613 addi a2,s0,67 + 71e0: 85d2 mv a1,s4 + 71e2: 854e mv a0,s3 + 71e4: 9a82 jalr s5 + 71e6: 57fd li a5,-1 + 71e8: 04f50363 beq a0,a5,722e <_printf_common+0xc0> + 71ec: 401c lw a5,0(s0) + 71ee: 4611 li a2,4 + 71f0: 4098 lw a4,0(s1) + 71f2: 8b99 andi a5,a5,6 + 71f4: 4454 lw a3,12(s0) + 71f6: 4481 li s1,0 + 71f8: 00c79763 bne a5,a2,7206 <_printf_common+0x98> + 71fc: 40e684b3 sub s1,a3,a4 + 7200: 0004d363 bgez s1,7206 <_printf_common+0x98> + 7204: 4481 li s1,0 + 7206: 441c lw a5,8(s0) + 7208: 4818 lw a4,16(s0) + 720a: 00f75463 bge a4,a5,7212 <_printf_common+0xa4> + 720e: 8f99 sub a5,a5,a4 + 7210: 94be add s1,s1,a5 + 7212: 4901 li s2,0 + 7214: 0469 addi s0,s0,26 + 7216: 5b7d li s6,-1 + 7218: 05249863 bne s1,s2,7268 <_printf_common+0xfa> + 721c: 4501 li a0,0 + 721e: a809 j 7230 <_printf_common+0xc2> + 7220: 4685 li a3,1 + 7222: 865a mv a2,s6 + 7224: 85d2 mv a1,s4 + 7226: 854e mv a0,s3 + 7228: 9a82 jalr s5 + 722a: 01751e63 bne a0,s7,7246 <_printf_common+0xd8> + 722e: 557d li a0,-1 + 7230: 50b2 lw ra,44(sp) + 7232: 5422 lw s0,40(sp) + 7234: 5492 lw s1,36(sp) + 7236: 5902 lw s2,32(sp) + 7238: 49f2 lw s3,28(sp) + 723a: 4a62 lw s4,24(sp) + 723c: 4ad2 lw s5,20(sp) + 723e: 4b42 lw s6,16(sp) + 7240: 4bb2 lw s7,12(sp) + 7242: 6145 addi sp,sp,48 + 7244: 8082 ret + 7246: 0905 addi s2,s2,1 + 7248: bfad j 71c2 <_printf_common+0x54> + 724a: 00d40733 add a4,s0,a3 + 724e: 03000613 li a2,48 + 7252: 04c701a3 sb a2,67(a4) + 7256: 04544703 lbu a4,69(s0) + 725a: 00168793 addi a5,a3,1 + 725e: 97a2 add a5,a5,s0 + 7260: 0689 addi a3,a3,2 + 7262: 04e781a3 sb a4,67(a5) + 7266: bf9d j 71dc <_printf_common+0x6e> + 7268: 4685 li a3,1 + 726a: 8622 mv a2,s0 + 726c: 85d2 mv a1,s4 + 726e: 854e mv a0,s3 + 7270: 9a82 jalr s5 + 7272: fb650ee3 beq a0,s6,722e <_printf_common+0xc0> + 7276: 0905 addi s2,s2,1 + 7278: b745 j 7218 <_printf_common+0xaa> + +0000727a <_printf_i>: + 727a: 7179 addi sp,sp,-48 + 727c: d422 sw s0,40(sp) + 727e: d226 sw s1,36(sp) + 7280: d04a sw s2,32(sp) + 7282: ce4e sw s3,28(sp) + 7284: d606 sw ra,44(sp) + 7286: cc52 sw s4,24(sp) + 7288: ca56 sw s5,20(sp) + 728a: c85a sw s6,16(sp) + 728c: 89b6 mv s3,a3 + 728e: 0185c683 lbu a3,24(a1) + 7292: 06900793 li a5,105 + 7296: 8932 mv s2,a2 + 7298: 84aa mv s1,a0 + 729a: 842e mv s0,a1 + 729c: 04358613 addi a2,a1,67 + 72a0: 02f68d63 beq a3,a5,72da <_printf_i+0x60> + 72a4: 06d7e263 bltu a5,a3,7308 <_printf_i+0x8e> + 72a8: 05800793 li a5,88 + 72ac: 18f68963 beq a3,a5,743e <_printf_i+0x1c4> + 72b0: 00d7ed63 bltu a5,a3,72ca <_printf_i+0x50> + 72b4: 22068263 beqz a3,74d8 <_printf_i+0x25e> + 72b8: 04300793 li a5,67 + 72bc: 0af68f63 beq a3,a5,737a <_printf_i+0x100> + 72c0: 04240a93 addi s5,s0,66 + 72c4: 04d40123 sb a3,66(s0) + 72c8: a0d1 j 738c <_printf_i+0x112> + 72ca: 06300793 li a5,99 + 72ce: 0af68663 beq a3,a5,737a <_printf_i+0x100> + 72d2: 06400793 li a5,100 + 72d6: fef695e3 bne a3,a5,72c0 <_printf_i+0x46> + 72da: 401c lw a5,0(s0) + 72dc: 4308 lw a0,0(a4) + 72de: 0807f693 andi a3,a5,128 + 72e2: 00450593 addi a1,a0,4 + 72e6: c6cd beqz a3,7390 <_printf_i+0x116> + 72e8: 411c lw a5,0(a0) + 72ea: c30c sw a1,0(a4) + 72ec: 0007d863 bgez a5,72fc <_printf_i+0x82> + 72f0: 02d00713 li a4,45 + 72f4: 40f007b3 neg a5,a5 + 72f8: 04e401a3 sb a4,67(s0) + 72fc: 00005697 auipc a3,0x5 + 7300: 40468693 addi a3,a3,1028 # c700 <__clz_tab+0x170> + 7304: 4729 li a4,10 + 7306: a875 j 73c2 <_printf_i+0x148> + 7308: 07000793 li a5,112 + 730c: 16f68563 beq a3,a5,7476 <_printf_i+0x1fc> + 7310: 02d7e563 bltu a5,a3,733a <_printf_i+0xc0> + 7314: 06e00793 li a5,110 + 7318: 18f68c63 beq a3,a5,74b0 <_printf_i+0x236> + 731c: 06f00793 li a5,111 + 7320: faf690e3 bne a3,a5,72c0 <_printf_i+0x46> + 7324: 400c lw a1,0(s0) + 7326: 431c lw a5,0(a4) + 7328: 0805f813 andi a6,a1,128 + 732c: 00478513 addi a0,a5,4 + 7330: 06080863 beqz a6,73a0 <_printf_i+0x126> + 7334: c308 sw a0,0(a4) + 7336: 439c lw a5,0(a5) + 7338: a895 j 73ac <_printf_i+0x132> + 733a: 07500793 li a5,117 + 733e: fef683e3 beq a3,a5,7324 <_printf_i+0xaa> + 7342: 07800793 li a5,120 + 7346: 12f68c63 beq a3,a5,747e <_printf_i+0x204> + 734a: 07300793 li a5,115 + 734e: f6f699e3 bne a3,a5,72c0 <_printf_i+0x46> + 7352: 431c lw a5,0(a4) + 7354: 41d0 lw a2,4(a1) + 7356: 4581 li a1,0 + 7358: 00478693 addi a3,a5,4 + 735c: c314 sw a3,0(a4) + 735e: 0007aa83 lw s5,0(a5) + 7362: 8556 mv a0,s5 + 7364: 3c0030ef jal ra,a724 + 7368: c501 beqz a0,7370 <_printf_i+0xf6> + 736a: 41550533 sub a0,a0,s5 + 736e: c048 sw a0,4(s0) + 7370: 405c lw a5,4(s0) + 7372: c81c sw a5,16(s0) + 7374: 040401a3 sb zero,67(s0) + 7378: a871 j 7414 <_printf_i+0x19a> + 737a: 431c lw a5,0(a4) + 737c: 04240a93 addi s5,s0,66 + 7380: 00478693 addi a3,a5,4 + 7384: 439c lw a5,0(a5) + 7386: c314 sw a3,0(a4) + 7388: 04f40123 sb a5,66(s0) + 738c: 4785 li a5,1 + 738e: b7d5 j 7372 <_printf_i+0xf8> + 7390: 0407f693 andi a3,a5,64 + 7394: 411c lw a5,0(a0) + 7396: c30c sw a1,0(a4) + 7398: dab1 beqz a3,72ec <_printf_i+0x72> + 739a: 07c2 slli a5,a5,0x10 + 739c: 87c1 srai a5,a5,0x10 + 739e: b7b9 j 72ec <_printf_i+0x72> + 73a0: 0405f593 andi a1,a1,64 + 73a4: c308 sw a0,0(a4) + 73a6: d9c1 beqz a1,7336 <_printf_i+0xbc> + 73a8: 0007d783 lhu a5,0(a5) + 73ac: 06f00713 li a4,111 + 73b0: 0ee68863 beq a3,a4,74a0 <_printf_i+0x226> + 73b4: 00005697 auipc a3,0x5 + 73b8: 34c68693 addi a3,a3,844 # c700 <__clz_tab+0x170> + 73bc: 4729 li a4,10 + 73be: 040401a3 sb zero,67(s0) + 73c2: 404c lw a1,4(s0) + 73c4: c40c sw a1,8(s0) + 73c6: 0005c563 bltz a1,73d0 <_printf_i+0x156> + 73ca: 4008 lw a0,0(s0) + 73cc: 996d andi a0,a0,-5 + 73ce: c008 sw a0,0(s0) + 73d0: e399 bnez a5,73d6 <_printf_i+0x15c> + 73d2: 8ab2 mv s5,a2 + 73d4: cd91 beqz a1,73f0 <_printf_i+0x176> + 73d6: 8ab2 mv s5,a2 + 73d8: 02e7f5b3 remu a1,a5,a4 + 73dc: 1afd addi s5,s5,-1 + 73de: 95b6 add a1,a1,a3 + 73e0: 0005c583 lbu a1,0(a1) + 73e4: 00ba8023 sb a1,0(s5) + 73e8: 02e7d5b3 divu a1,a5,a4 + 73ec: 0ce7f063 bgeu a5,a4,74ac <_printf_i+0x232> + 73f0: 47a1 li a5,8 + 73f2: 00f71e63 bne a4,a5,740e <_printf_i+0x194> + 73f6: 401c lw a5,0(s0) + 73f8: 8b85 andi a5,a5,1 + 73fa: cb91 beqz a5,740e <_printf_i+0x194> + 73fc: 4058 lw a4,4(s0) + 73fe: 481c lw a5,16(s0) + 7400: 00e7c763 blt a5,a4,740e <_printf_i+0x194> + 7404: 03000793 li a5,48 + 7408: fefa8fa3 sb a5,-1(s5) + 740c: 1afd addi s5,s5,-1 + 740e: 41560633 sub a2,a2,s5 + 7412: c810 sw a2,16(s0) + 7414: 874e mv a4,s3 + 7416: 86ca mv a3,s2 + 7418: 0070 addi a2,sp,12 + 741a: 85a2 mv a1,s0 + 741c: 8526 mv a0,s1 + 741e: d51ff0ef jal ra,716e <_printf_common> + 7422: 5a7d li s4,-1 + 7424: 0b451e63 bne a0,s4,74e0 <_printf_i+0x266> + 7428: 557d li a0,-1 + 742a: 50b2 lw ra,44(sp) + 742c: 5422 lw s0,40(sp) + 742e: 5492 lw s1,36(sp) + 7430: 5902 lw s2,32(sp) + 7432: 49f2 lw s3,28(sp) + 7434: 4a62 lw s4,24(sp) + 7436: 4ad2 lw s5,20(sp) + 7438: 4b42 lw s6,16(sp) + 743a: 6145 addi sp,sp,48 + 743c: 8082 ret + 743e: 04d582a3 sb a3,69(a1) + 7442: 00005697 auipc a3,0x5 + 7446: 2be68693 addi a3,a3,702 # c700 <__clz_tab+0x170> + 744a: 400c lw a1,0(s0) + 744c: 4308 lw a0,0(a4) + 744e: 0805f813 andi a6,a1,128 + 7452: 411c lw a5,0(a0) + 7454: 0511 addi a0,a0,4 + 7456: 02080d63 beqz a6,7490 <_printf_i+0x216> + 745a: c308 sw a0,0(a4) + 745c: 0015f713 andi a4,a1,1 + 7460: c701 beqz a4,7468 <_printf_i+0x1ee> + 7462: 0205e593 ori a1,a1,32 + 7466: c00c sw a1,0(s0) + 7468: 4741 li a4,16 + 746a: fbb1 bnez a5,73be <_printf_i+0x144> + 746c: 400c lw a1,0(s0) + 746e: fdf5f593 andi a1,a1,-33 + 7472: c00c sw a1,0(s0) + 7474: b7a9 j 73be <_printf_i+0x144> + 7476: 419c lw a5,0(a1) + 7478: 0207e793 ori a5,a5,32 + 747c: c19c sw a5,0(a1) + 747e: 07800793 li a5,120 + 7482: 04f402a3 sb a5,69(s0) + 7486: 00005697 auipc a3,0x5 + 748a: 28e68693 addi a3,a3,654 # c714 <__clz_tab+0x184> + 748e: bf75 j 744a <_printf_i+0x1d0> + 7490: 0405f813 andi a6,a1,64 + 7494: c308 sw a0,0(a4) + 7496: fc0803e3 beqz a6,745c <_printf_i+0x1e2> + 749a: 07c2 slli a5,a5,0x10 + 749c: 83c1 srli a5,a5,0x10 + 749e: bf7d j 745c <_printf_i+0x1e2> + 74a0: 00005697 auipc a3,0x5 + 74a4: 26068693 addi a3,a3,608 # c700 <__clz_tab+0x170> + 74a8: 4721 li a4,8 + 74aa: bf11 j 73be <_printf_i+0x144> + 74ac: 87ae mv a5,a1 + 74ae: b72d j 73d8 <_printf_i+0x15e> + 74b0: 4194 lw a3,0(a1) + 74b2: 431c lw a5,0(a4) + 74b4: 49cc lw a1,20(a1) + 74b6: 0806f813 andi a6,a3,128 + 74ba: 00478513 addi a0,a5,4 + 74be: 00080663 beqz a6,74ca <_printf_i+0x250> + 74c2: c308 sw a0,0(a4) + 74c4: 439c lw a5,0(a5) + 74c6: c38c sw a1,0(a5) + 74c8: a801 j 74d8 <_printf_i+0x25e> + 74ca: c308 sw a0,0(a4) + 74cc: 0406f693 andi a3,a3,64 + 74d0: 439c lw a5,0(a5) + 74d2: daf5 beqz a3,74c6 <_printf_i+0x24c> + 74d4: 00b79023 sh a1,0(a5) + 74d8: 00042823 sw zero,16(s0) + 74dc: 8ab2 mv s5,a2 + 74de: bf1d j 7414 <_printf_i+0x19a> + 74e0: 4814 lw a3,16(s0) + 74e2: 8656 mv a2,s5 + 74e4: 85ca mv a1,s2 + 74e6: 8526 mv a0,s1 + 74e8: 9982 jalr s3 + 74ea: f3450fe3 beq a0,s4,7428 <_printf_i+0x1ae> + 74ee: 401c lw a5,0(s0) + 74f0: 8b89 andi a5,a5,2 + 74f2: e78d bnez a5,751c <_printf_i+0x2a2> + 74f4: 47b2 lw a5,12(sp) + 74f6: 4448 lw a0,12(s0) + 74f8: f2f559e3 bge a0,a5,742a <_printf_i+0x1b0> + 74fc: 853e mv a0,a5 + 74fe: b735 j 742a <_printf_i+0x1b0> + 7500: 4685 li a3,1 + 7502: 8656 mv a2,s5 + 7504: 85ca mv a1,s2 + 7506: 8526 mv a0,s1 + 7508: 9982 jalr s3 + 750a: f1650fe3 beq a0,s6,7428 <_printf_i+0x1ae> + 750e: 0a05 addi s4,s4,1 + 7510: 445c lw a5,12(s0) + 7512: 4732 lw a4,12(sp) + 7514: 8f99 sub a5,a5,a4 + 7516: fefa45e3 blt s4,a5,7500 <_printf_i+0x286> + 751a: bfe9 j 74f4 <_printf_i+0x27a> + 751c: 4a01 li s4,0 + 751e: 01940a93 addi s5,s0,25 + 7522: 5b7d li s6,-1 + 7524: b7f5 j 7510 <_printf_i+0x296> + +00007526 <_scanf_float>: + 7526: 459c lw a5,8(a1) + 7528: 711d addi sp,sp,-96 + 752a: cca2 sw s0,88(sp) + 752c: c6ce sw s3,76(sp) + 752e: c0da sw s6,64(sp) + 7530: da66 sw s9,52(sp) + 7532: ce86 sw ra,92(sp) + 7534: 8cb2 mv s9,a2 + 7536: caa6 sw s1,84(sp) + 7538: c8ca sw s2,80(sp) + 753a: c4d2 sw s4,72(sp) + 753c: c2d6 sw s5,68(sp) + 753e: de5e sw s7,60(sp) + 7540: dc62 sw s8,56(sp) + 7542: d86a sw s10,48(sp) + 7544: d66e sw s11,44(sp) + 7546: fff78613 addi a2,a5,-1 + 754a: 15c00713 li a4,348 + 754e: 8b36 mv s6,a3 + 7550: 89aa mv s3,a0 + 7552: 842e mv s0,a1 + 7554: 4681 li a3,0 + 7556: 00c77763 bgeu a4,a2,7564 <_scanf_float+0x3e> + 755a: ea378693 addi a3,a5,-349 + 755e: 15d00793 li a5,349 + 7562: c59c sw a5,8(a1) + 7564: 401c lw a5,0(s0) + 7566: 01c40a93 addi s5,s0,28 + 756a: 84d6 mv s1,s5 + 756c: 7807e793 ori a5,a5,1920 + 7570: c01c sw a5,0(s0) + 7572: 4901 li s2,0 + 7574: 4d81 li s11,0 + 7576: 4c01 li s8,0 + 7578: 4a01 li s4,0 + 757a: 4d01 li s10,0 + 757c: 4b81 li s7,0 + 757e: 04900613 li a2,73 + 7582: 70000813 li a6,1792 + 7586: 4885 li a7,1 + 7588: 40000e93 li t4,1024 + 758c: 4309 li t1,2 + 758e: 06500e13 li t3,101 + 7592: 4f1d li t5,7 + 7594: 4418 lw a4,8(s0) + 7596: cb1d beqz a4,75cc <_scanf_float+0xa6> + 7598: 000ca783 lw a5,0(s9) + 759c: 0007c783 lbu a5,0(a5) + 75a0: 12c78b63 beq a5,a2,76d6 <_scanf_float+0x1b0> + 75a4: 0cf66863 bltu a2,a5,7674 <_scanf_float+0x14e> + 75a8: 03900593 li a1,57 + 75ac: 0af5e463 bltu a1,a5,7654 <_scanf_float+0x12e> + 75b0: 03100593 li a1,49 + 75b4: 14b7fb63 bgeu a5,a1,770a <_scanf_float+0x1e4> + 75b8: 02d00593 li a1,45 + 75bc: 16b78363 beq a5,a1,7722 <_scanf_float+0x1fc> + 75c0: 04f5e363 bltu a1,a5,7606 <_scanf_float+0xe0> + 75c4: 02b00713 li a4,43 + 75c8: 14e78d63 beq a5,a4,7722 <_scanf_float+0x1fc> + 75cc: 000d0663 beqz s10,75d8 <_scanf_float+0xb2> + 75d0: 401c lw a5,0(s0) + 75d2: eff7f793 andi a5,a5,-257 + 75d6: c01c sw a5,0(s0) + 75d8: 1dfd addi s11,s11,-1 + 75da: 4785 li a5,1 + 75dc: 21b7eb63 bltu a5,s11,77f2 <_scanf_float+0x2cc> + 75e0: 1e9aed63 bltu s5,s1,77da <_scanf_float+0x2b4> + 75e4: 4905 li s2,1 + 75e6: 40f6 lw ra,92(sp) + 75e8: 4466 lw s0,88(sp) + 75ea: 854a mv a0,s2 + 75ec: 44d6 lw s1,84(sp) + 75ee: 4946 lw s2,80(sp) + 75f0: 49b6 lw s3,76(sp) + 75f2: 4a26 lw s4,72(sp) + 75f4: 4a96 lw s5,68(sp) + 75f6: 4b06 lw s6,64(sp) + 75f8: 5bf2 lw s7,60(sp) + 75fa: 5c62 lw s8,56(sp) + 75fc: 5cd2 lw s9,52(sp) + 75fe: 5d42 lw s10,48(sp) + 7600: 5db2 lw s11,44(sp) + 7602: 6125 addi sp,sp,96 + 7604: 8082 ret + 7606: 02e00593 li a1,46 + 760a: 14b78f63 beq a5,a1,7768 <_scanf_float+0x242> + 760e: 03000593 li a1,48 + 7612: fab79de3 bne a5,a1,75cc <_scanf_float+0xa6> + 7616: 400c lw a1,0(s0) + 7618: 1005f513 andi a0,a1,256 + 761c: c57d beqz a0,770a <_scanf_float+0x1e4> + 761e: f7f5f593 andi a1,a1,-129 + 7622: c00c sw a1,0(s0) + 7624: 0d05 addi s10,s10,1 + 7626: c681 beqz a3,762e <_scanf_float+0x108> + 7628: 0705 addi a4,a4,1 + 762a: 16fd addi a3,a3,-1 + 762c: c418 sw a4,8(s0) + 762e: 441c lw a5,8(s0) + 7630: 17fd addi a5,a5,-1 + 7632: c41c sw a5,8(s0) + 7634: 481c lw a5,16(s0) + 7636: 0785 addi a5,a5,1 + 7638: c81c sw a5,16(s0) + 763a: 004ca783 lw a5,4(s9) + 763e: 17fd addi a5,a5,-1 + 7640: 00fca223 sw a5,4(s9) + 7644: 16f05663 blez a5,77b0 <_scanf_float+0x28a> + 7648: 000ca783 lw a5,0(s9) + 764c: 0785 addi a5,a5,1 + 764e: 00fca023 sw a5,0(s9) + 7652: b789 j 7594 <_scanf_float+0x6e> + 7654: 04500713 li a4,69 + 7658: 12e78263 beq a5,a4,777c <_scanf_float+0x256> + 765c: 04600713 li a4,70 + 7660: 0ee78b63 beq a5,a4,7756 <_scanf_float+0x230> + 7664: 04100713 li a4,65 + 7668: f6e792e3 bne a5,a4,75cc <_scanf_float+0xa6> + 766c: f71d90e3 bne s11,a7,75cc <_scanf_float+0xa6> + 7670: 4d89 li s11,2 + 7672: a065 j 771a <_scanf_float+0x1f4> + 7674: 11c78463 beq a5,t3,777c <_scanf_float+0x256> + 7678: 04fe6163 bltu t3,a5,76ba <_scanf_float+0x194> + 767c: 05400713 li a4,84 + 7680: 0ce78f63 beq a5,a4,775e <_scanf_float+0x238> + 7684: 02f76463 bltu a4,a5,76ac <_scanf_float+0x186> + 7688: 04e00713 li a4,78 + 768c: f4e790e3 bne a5,a4,75cc <_scanf_float+0xa6> + 7690: 0a0d9163 bnez s11,7732 <_scanf_float+0x20c> + 7694: 0a0d1163 bnez s10,7736 <_scanf_float+0x210> + 7698: 4018 lw a4,0(s0) + 769a: 70077593 andi a1,a4,1792 + 769e: 09059c63 bne a1,a6,7736 <_scanf_float+0x210> + 76a2: 87f77713 andi a4,a4,-1921 + 76a6: c018 sw a4,0(s0) + 76a8: 4d85 li s11,1 + 76aa: a885 j 771a <_scanf_float+0x1f4> + 76ac: 05900713 li a4,89 + 76b0: 04e78963 beq a5,a4,7702 <_scanf_float+0x1dc> + 76b4: 06100713 li a4,97 + 76b8: bf45 j 7668 <_scanf_float+0x142> + 76ba: 06e00713 li a4,110 + 76be: fce789e3 beq a5,a4,7690 <_scanf_float+0x16a> + 76c2: 02f76863 bltu a4,a5,76f2 <_scanf_float+0x1cc> + 76c6: 06600713 li a4,102 + 76ca: 08e78663 beq a5,a4,7756 <_scanf_float+0x230> + 76ce: 06900713 li a4,105 + 76d2: eee79de3 bne a5,a4,75cc <_scanf_float+0xa6> + 76d6: 06091963 bnez s2,7748 <_scanf_float+0x222> + 76da: ee0d1be3 bnez s10,75d0 <_scanf_float+0xaa> + 76de: 4018 lw a4,0(s0) + 76e0: 70077593 andi a1,a4,1792 + 76e4: ef059ae3 bne a1,a6,75d8 <_scanf_float+0xb2> + 76e8: 87f77713 andi a4,a4,-1921 + 76ec: c018 sw a4,0(s0) + 76ee: 4905 li s2,1 + 76f0: a02d j 771a <_scanf_float+0x1f4> + 76f2: 07400713 li a4,116 + 76f6: 06e78463 beq a5,a4,775e <_scanf_float+0x238> + 76fa: 07900713 li a4,121 + 76fe: ece797e3 bne a5,a4,75cc <_scanf_float+0xa6> + 7702: ede915e3 bne s2,t5,75cc <_scanf_float+0xa6> + 7706: 4921 li s2,8 + 7708: a809 j 771a <_scanf_float+0x1f4> + 770a: 012d8733 add a4,s11,s2 + 770e: ea071fe3 bnez a4,75cc <_scanf_float+0xa6> + 7712: 4018 lw a4,0(s0) + 7714: e7f77713 andi a4,a4,-385 + 7718: c018 sw a4,0(s0) + 771a: 00f48023 sb a5,0(s1) + 771e: 0485 addi s1,s1,1 + 7720: b739 j 762e <_scanf_float+0x108> + 7722: 4018 lw a4,0(s0) + 7724: 08077593 andi a1,a4,128 + 7728: ea0582e3 beqz a1,75cc <_scanf_float+0xa6> + 772c: f7f77713 andi a4,a4,-129 + 7730: b7e5 j 7718 <_scanf_float+0x1f2> + 7732: 066d8d63 beq s11,t1,77ac <_scanf_float+0x286> + 7736: 01190563 beq s2,a7,7740 <_scanf_float+0x21a> + 773a: 4711 li a4,4 + 773c: e8e918e3 bne s2,a4,75cc <_scanf_float+0xa6> + 7740: 0905 addi s2,s2,1 + 7742: 0ff97913 andi s2,s2,255 + 7746: bfd1 j 771a <_scanf_float+0x1f4> + 7748: ffd90713 addi a4,s2,-3 + 774c: 0fd77713 andi a4,a4,253 + 7750: e6071ee3 bnez a4,75cc <_scanf_float+0xa6> + 7754: b7f5 j 7740 <_scanf_float+0x21a> + 7756: e6691be3 bne s2,t1,75cc <_scanf_float+0xa6> + 775a: 490d li s2,3 + 775c: bf7d j 771a <_scanf_float+0x1f4> + 775e: 4719 li a4,6 + 7760: e6e916e3 bne s2,a4,75cc <_scanf_float+0xa6> + 7764: 491d li s2,7 + 7766: bf55 j 771a <_scanf_float+0x1f4> + 7768: 4018 lw a4,0(s0) + 776a: 20077593 andi a1,a4,512 + 776e: e4058fe3 beqz a1,75cc <_scanf_float+0xa6> + 7772: d7f77713 andi a4,a4,-641 + 7776: c018 sw a4,0(s0) + 7778: 8bea mv s7,s10 + 777a: b745 j 771a <_scanf_float+0x1f4> + 777c: 4018 lw a4,0(s0) + 777e: 50077593 andi a1,a4,1280 + 7782: 01d58863 beq a1,t4,7792 <_scanf_float+0x26c> + 7786: 40077593 andi a1,a4,1024 + 778a: e40581e3 beqz a1,75cc <_scanf_float+0xa6> + 778e: e40d05e3 beqz s10,75d8 <_scanf_float+0xb2> + 7792: 20077593 andi a1,a4,512 + 7796: e581 bnez a1,779e <_scanf_float+0x278> + 7798: 417d0a33 sub s4,s10,s7 + 779c: 8c26 mv s8,s1 + 779e: 87f77713 andi a4,a4,-1921 + 77a2: 18076713 ori a4,a4,384 + 77a6: c018 sw a4,0(s0) + 77a8: 4d01 li s10,0 + 77aa: bf85 j 771a <_scanf_float+0x1f4> + 77ac: 4d8d li s11,3 + 77ae: b7b5 j 771a <_scanf_float+0x1f4> + 77b0: 18042783 lw a5,384(s0) + 77b4: 85e6 mv a1,s9 + 77b6: 854e mv a0,s3 + 77b8: c636 sw a3,12(sp) + 77ba: 9782 jalr a5 + 77bc: 46b2 lw a3,12(sp) + 77be: 04900613 li a2,73 + 77c2: 70000813 li a6,1792 + 77c6: 4885 li a7,1 + 77c8: 40000e93 li t4,1024 + 77cc: 4309 li t1,2 + 77ce: 06500e13 li t3,101 + 77d2: 4f1d li t5,7 + 77d4: dc0500e3 beqz a0,7594 <_scanf_float+0x6e> + 77d8: bbd5 j 75cc <_scanf_float+0xa6> + 77da: 14fd addi s1,s1,-1 + 77dc: 17c42783 lw a5,380(s0) + 77e0: 0004c583 lbu a1,0(s1) + 77e4: 8666 mv a2,s9 + 77e6: 854e mv a0,s3 + 77e8: 9782 jalr a5 + 77ea: 481c lw a5,16(s0) + 77ec: 17fd addi a5,a5,-1 + 77ee: c81c sw a5,16(s0) + 77f0: bbc5 j 75e0 <_scanf_float+0xba> + 77f2: fff90793 addi a5,s2,-1 + 77f6: 4719 li a4,6 + 77f8: 02f76663 bltu a4,a5,7824 <_scanf_float+0x2fe> + 77fc: 4789 li a5,2 + 77fe: 8da6 mv s11,s1 + 7800: 0927f163 bgeu a5,s2,7882 <_scanf_float+0x35c> + 7804: 40990733 sub a4,s2,s1 + 7808: 0ff77713 andi a4,a4,255 + 780c: 468d li a3,3 + 780e: 00ed87b3 add a5,s11,a4 + 7812: 0ff7f793 andi a5,a5,255 + 7816: 02f6ec63 bltu a3,a5,784e <_scanf_float+0x328> + 781a: 1975 addi s2,s2,-3 + 781c: 0ff97913 andi s2,s2,255 + 7820: 412484b3 sub s1,s1,s2 + 7824: 401c lw a5,0(s0) + 7826: 1007f713 andi a4,a5,256 + 782a: c345 beqz a4,78ca <_scanf_float+0x3a4> + 782c: 4007f793 andi a5,a5,1024 + 7830: cfa1 beqz a5,7888 <_scanf_float+0x362> + 7832: da9af9e3 bgeu s5,s1,75e4 <_scanf_float+0xbe> + 7836: 14fd addi s1,s1,-1 + 7838: 17c42783 lw a5,380(s0) + 783c: 0004c583 lbu a1,0(s1) + 7840: 8666 mv a2,s9 + 7842: 854e mv a0,s3 + 7844: 9782 jalr a5 + 7846: 481c lw a5,16(s0) + 7848: 17fd addi a5,a5,-1 + 784a: c81c sw a5,16(s0) + 784c: b7dd j 7832 <_scanf_float+0x30c> + 784e: 1dfd addi s11,s11,-1 + 7850: 17c42783 lw a5,380(s0) + 7854: 000dc583 lbu a1,0(s11) # 7ff30000 <_eusrstack+0x5ff20000> + 7858: 8666 mv a2,s9 + 785a: 854e mv a0,s3 + 785c: c63a sw a4,12(sp) + 785e: 9782 jalr a5 + 7860: 481c lw a5,16(s0) + 7862: 468d li a3,3 + 7864: 4732 lw a4,12(sp) + 7866: 17fd addi a5,a5,-1 + 7868: c81c sw a5,16(s0) + 786a: b755 j 780e <_scanf_float+0x2e8> + 786c: 14fd addi s1,s1,-1 + 786e: 17c42783 lw a5,380(s0) + 7872: 0004c583 lbu a1,0(s1) + 7876: 8666 mv a2,s9 + 7878: 854e mv a0,s3 + 787a: 9782 jalr a5 + 787c: 481c lw a5,16(s0) + 787e: 17fd addi a5,a5,-1 + 7880: c81c sw a5,16(s0) + 7882: fe9ae5e3 bltu s5,s1,786c <_scanf_float+0x346> + 7886: bbb9 j 75e4 <_scanf_float+0xbe> + 7888: 481c lw a5,16(s0) + 788a: fff4c583 lbu a1,-1(s1) + 788e: fff48913 addi s2,s1,-1 + 7892: 17fd addi a5,a5,-1 + 7894: c81c sw a5,16(s0) + 7896: 06500793 li a5,101 + 789a: 02f58263 beq a1,a5,78be <_scanf_float+0x398> + 789e: 04500793 li a5,69 + 78a2: 00f58e63 beq a1,a5,78be <_scanf_float+0x398> + 78a6: 17c42783 lw a5,380(s0) + 78aa: 8666 mv a2,s9 + 78ac: 854e mv a0,s3 + 78ae: 9782 jalr a5 + 78b0: 481c lw a5,16(s0) + 78b2: ffe4c583 lbu a1,-2(s1) + 78b6: ffe48913 addi s2,s1,-2 + 78ba: 17fd addi a5,a5,-1 + 78bc: c81c sw a5,16(s0) + 78be: 17c42783 lw a5,380(s0) + 78c2: 8666 mv a2,s9 + 78c4: 854e mv a0,s3 + 78c6: 9782 jalr a5 + 78c8: 84ca mv s1,s2 + 78ca: 00042903 lw s2,0(s0) + 78ce: 01097913 andi s2,s2,16 + 78d2: 0c091363 bnez s2,7998 <_scanf_float+0x472> + 78d6: 00048023 sb zero,0(s1) + 78da: 401c lw a5,0(s0) + 78dc: 40000713 li a4,1024 + 78e0: 6007f793 andi a5,a5,1536 + 78e4: 02e79e63 bne a5,a4,7920 <_scanf_float+0x3fa> + 78e8: 41ab8633 sub a2,s7,s10 + 78ec: 05ab9663 bne s7,s10,7938 <_scanf_float+0x412> + 78f0: 85d6 mv a1,s5 + 78f2: 4601 li a2,0 + 78f4: 854e mv a0,s3 + 78f6: 070010ef jal ra,8966 <_strtod_r> + 78fa: 4018 lw a4,0(s0) + 78fc: 8a2a mv s4,a0 + 78fe: 8aae mv s5,a1 + 7900: 00277693 andi a3,a4,2 + 7904: 000b2783 lw a5,0(s6) + 7908: c6a9 beqz a3,7952 <_scanf_float+0x42c> + 790a: 00478713 addi a4,a5,4 + 790e: 00eb2023 sw a4,0(s6) + 7912: 439c lw a5,0(a5) + 7914: c388 sw a0,0(a5) + 7916: c3cc sw a1,4(a5) + 7918: 445c lw a5,12(s0) + 791a: 0785 addi a5,a5,1 + 791c: c45c sw a5,12(s0) + 791e: b1e1 j 75e6 <_scanf_float+0xc0> + 7920: fc0a08e3 beqz s4,78f0 <_scanf_float+0x3ca> + 7924: 4601 li a2,0 + 7926: 46a9 li a3,10 + 7928: 001c0593 addi a1,s8,1 + 792c: 854e mv a0,s3 + 792e: 1ae010ef jal ra,8adc <_strtol_r> + 7932: 41450633 sub a2,a0,s4 + 7936: 84e2 mv s1,s8 + 7938: 16f40793 addi a5,s0,367 + 793c: 00f4e463 bltu s1,a5,7944 <_scanf_float+0x41e> + 7940: 16e40493 addi s1,s0,366 + 7944: 00005597 auipc a1,0x5 + 7948: de458593 addi a1,a1,-540 # c728 <__clz_tab+0x198> + 794c: 8526 mv a0,s1 + 794e: 2cc1 jal 7c1e + 7950: b745 j 78f0 <_scanf_float+0x3ca> + 7952: 00478693 addi a3,a5,4 + 7956: 00db2023 sw a3,0(s6) + 795a: 8b11 andi a4,a4,4 + 795c: 4384 lw s1,0(a5) + 795e: cf19 beqz a4,797c <_scanf_float+0x456> + 7960: 85aa mv a1,a0 + 7962: 8656 mv a2,s5 + 7964: 0808 addi a0,sp,16 + 7966: 10e040ef jal ra,ba74 <__extenddftf2> + 796a: 46d2 lw a3,20(sp) + 796c: 4762 lw a4,24(sp) + 796e: 47f2 lw a5,28(sp) + 7970: 4642 lw a2,16(sp) + 7972: c0d4 sw a3,4(s1) + 7974: c498 sw a4,8(s1) + 7976: c090 sw a2,0(s1) + 7978: c4dc sw a5,12(s1) + 797a: bf79 j 7918 <_scanf_float+0x3f2> + 797c: 862a mv a2,a0 + 797e: 86ae mv a3,a1 + 7980: 05c040ef jal ra,b9dc <__unorddf2> + 7984: c509 beqz a0,798e <_scanf_float+0x468> + 7986: 4501 li a0,0 + 7988: 2c29 jal 7ba2 + 798a: c088 sw a0,0(s1) + 798c: b771 j 7918 <_scanf_float+0x3f2> + 798e: 8552 mv a0,s4 + 7990: 85d6 mv a1,s5 + 7992: 286040ef jal ra,bc18 <__truncdfsf2> + 7996: bfd5 j 798a <_scanf_float+0x464> + 7998: 4901 li s2,0 + 799a: b1b1 j 75e6 <_scanf_float+0xc0> + +0000799c : + 799c: 7139 addi sp,sp,-64 + 799e: da3e sw a5,52(sp) + 79a0: d22e sw a1,36(sp) + 79a2: d432 sw a2,40(sp) + 79a4: d636 sw a3,44(sp) + 79a6: d83a sw a4,48(sp) + 79a8: dc42 sw a6,56(sp) + 79aa: de46 sw a7,60(sp) + 79ac: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 79b0: cc22 sw s0,24(sp) + 79b2: 4380 lw s0,0(a5) + 79b4: ca26 sw s1,20(sp) + 79b6: ce06 sw ra,28(sp) + 79b8: 84aa mv s1,a0 + 79ba: c411 beqz s0,79c6 + 79bc: 4c1c lw a5,24(s0) + 79be: e781 bnez a5,79c6 + 79c0: 8522 mv a0,s0 + 79c2: 344020ef jal ra,9d06 <__sinit> + 79c6: 440c lw a1,8(s0) + 79c8: 1054 addi a3,sp,36 + 79ca: 8626 mv a2,s1 + 79cc: 8522 mv a0,s0 + 79ce: c636 sw a3,12(sp) + 79d0: ec5fe0ef jal ra,6894 <_vfiprintf_r> + 79d4: 40f2 lw ra,28(sp) + 79d6: 4462 lw s0,24(sp) + 79d8: 44d2 lw s1,20(sp) + 79da: 6121 addi sp,sp,64 + 79dc: 8082 ret + +000079de : + 79de: 1101 addi sp,sp,-32 + 79e0: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 79e4: cc22 sw s0,24(sp) + 79e6: 4380 lw s0,0(a5) + 79e8: ce06 sw ra,28(sp) + 79ea: 85aa mv a1,a0 + 79ec: c801 beqz s0,79fc + 79ee: 4c1c lw a5,24(s0) + 79f0: e791 bnez a5,79fc + 79f2: c62a sw a0,12(sp) + 79f4: 8522 mv a0,s0 + 79f6: 310020ef jal ra,9d06 <__sinit> + 79fa: 45b2 lw a1,12(sp) + 79fc: 4410 lw a2,8(s0) + 79fe: 8522 mv a0,s0 + 7a00: 4462 lw s0,24(sp) + 7a02: 40f2 lw ra,28(sp) + 7a04: 6105 addi sp,sp,32 + 7a06: 42b0306f j b630 <_putc_r> + +00007a0a <_puts_r>: + 7a0a: 1101 addi sp,sp,-32 + 7a0c: ca26 sw s1,20(sp) + 7a0e: c84a sw s2,16(sp) + 7a10: ce06 sw ra,28(sp) + 7a12: cc22 sw s0,24(sp) + 7a14: c64e sw s3,12(sp) + 7a16: c452 sw s4,8(sp) + 7a18: 84aa mv s1,a0 + 7a1a: 892e mv s2,a1 + 7a1c: c509 beqz a0,7a26 <_puts_r+0x1c> + 7a1e: 4d1c lw a5,24(a0) + 7a20: e399 bnez a5,7a26 <_puts_r+0x1c> + 7a22: 2e4020ef jal ra,9d06 <__sinit> + 7a26: 4c9c lw a5,24(s1) + 7a28: 4480 lw s0,8(s1) + 7a2a: e781 bnez a5,7a32 <_puts_r+0x28> + 7a2c: 8526 mv a0,s1 + 7a2e: 2d8020ef jal ra,9d06 <__sinit> + 7a32: 00005797 auipc a5,0x5 + 7a36: e1678793 addi a5,a5,-490 # c848 <__sf_fake_stdin> + 7a3a: 02f41d63 bne s0,a5,7a74 <_puts_r+0x6a> + 7a3e: 40c0 lw s0,4(s1) + 7a40: 00c45783 lhu a5,12(s0) + 7a44: 8ba1 andi a5,a5,8 + 7a46: c7b9 beqz a5,7a94 <_puts_r+0x8a> + 7a48: 481c lw a5,16(s0) + 7a4a: c7a9 beqz a5,7a94 <_puts_r+0x8a> + 7a4c: 59fd li s3,-1 + 7a4e: 4a29 li s4,10 + 7a50: 441c lw a5,8(s0) + 7a52: 00094583 lbu a1,0(s2) + 7a56: 17fd addi a5,a5,-1 + 7a58: eda1 bnez a1,7ab0 <_puts_r+0xa6> + 7a5a: c41c sw a5,8(s0) + 7a5c: 0807d163 bgez a5,7ade <_puts_r+0xd4> + 7a60: 8622 mv a2,s0 + 7a62: 45a9 li a1,10 + 7a64: 8526 mv a0,s1 + 7a66: 0fe010ef jal ra,8b64 <__swbuf_r> + 7a6a: 57fd li a5,-1 + 7a6c: 02f50963 beq a0,a5,7a9e <_puts_r+0x94> + 7a70: 4529 li a0,10 + 7a72: a03d j 7aa0 <_puts_r+0x96> + 7a74: 00005797 auipc a5,0x5 + 7a78: df478793 addi a5,a5,-524 # c868 <__sf_fake_stdout> + 7a7c: 00f41463 bne s0,a5,7a84 <_puts_r+0x7a> + 7a80: 4480 lw s0,8(s1) + 7a82: bf7d j 7a40 <_puts_r+0x36> + 7a84: 00005797 auipc a5,0x5 + 7a88: da478793 addi a5,a5,-604 # c828 <__sf_fake_stderr> + 7a8c: faf41ae3 bne s0,a5,7a40 <_puts_r+0x36> + 7a90: 44c0 lw s0,12(s1) + 7a92: b77d j 7a40 <_puts_r+0x36> + 7a94: 85a2 mv a1,s0 + 7a96: 8526 mv a0,s1 + 7a98: 192010ef jal ra,8c2a <__swsetup_r> + 7a9c: d945 beqz a0,7a4c <_puts_r+0x42> + 7a9e: 557d li a0,-1 + 7aa0: 40f2 lw ra,28(sp) + 7aa2: 4462 lw s0,24(sp) + 7aa4: 44d2 lw s1,20(sp) + 7aa6: 4942 lw s2,16(sp) + 7aa8: 49b2 lw s3,12(sp) + 7aaa: 4a22 lw s4,8(sp) + 7aac: 6105 addi sp,sp,32 + 7aae: 8082 ret + 7ab0: c41c sw a5,8(s0) + 7ab2: 0905 addi s2,s2,1 + 7ab4: 0007d763 bgez a5,7ac2 <_puts_r+0xb8> + 7ab8: 4c18 lw a4,24(s0) + 7aba: 00e7cb63 blt a5,a4,7ad0 <_puts_r+0xc6> + 7abe: 01458963 beq a1,s4,7ad0 <_puts_r+0xc6> + 7ac2: 401c lw a5,0(s0) + 7ac4: 00178713 addi a4,a5,1 + 7ac8: c018 sw a4,0(s0) + 7aca: 00b78023 sb a1,0(a5) + 7ace: b749 j 7a50 <_puts_r+0x46> + 7ad0: 8622 mv a2,s0 + 7ad2: 8526 mv a0,s1 + 7ad4: 090010ef jal ra,8b64 <__swbuf_r> + 7ad8: f7351ce3 bne a0,s3,7a50 <_puts_r+0x46> + 7adc: b7c9 j 7a9e <_puts_r+0x94> + 7ade: 401c lw a5,0(s0) + 7ae0: 00178713 addi a4,a5,1 + 7ae4: c018 sw a4,0(s0) + 7ae6: 4729 li a4,10 + 7ae8: 00e78023 sb a4,0(a5) + 7aec: b751 j 7a70 <_puts_r+0x66> + +00007aee : + 7aee: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 7af2: 85aa mv a1,a0 + 7af4: 4388 lw a0,0(a5) + 7af6: f15ff06f j 7a0a <_puts_r> + +00007afa : + 7afa: 4145d713 srai a4,a1,0x14 + 7afe: 1141 addi sp,sp,-16 + 7b00: 7ff77713 andi a4,a4,2047 + 7b04: c606 sw ra,12(sp) + 7b06: c0170693 addi a3,a4,-1023 + 7b0a: 4e4d li t3,19 + 7b0c: 882a mv a6,a0 + 7b0e: 87ae mv a5,a1 + 7b10: 88ae mv a7,a1 + 7b12: 06de4263 blt t3,a3,7b76 + 7b16: 0006dd63 bgez a3,7b30 + 7b1a: 80000737 lui a4,0x80000 + 7b1e: 4681 li a3,0 + 7b20: 8f6d and a4,a4,a1 + 7b22: c214 sw a3,0(a2) + 7b24: c258 sw a4,4(a2) + 7b26: 40b2 lw ra,12(sp) + 7b28: 8542 mv a0,a6 + 7b2a: 85be mv a1,a5 + 7b2c: 0141 addi sp,sp,16 + 7b2e: 8082 ret + 7b30: 00100737 lui a4,0x100 + 7b34: 177d addi a4,a4,-1 + 7b36: 40d75733 sra a4,a4,a3 + 7b3a: 00e5f6b3 and a3,a1,a4 + 7b3e: 00a6e333 or t1,a3,a0 + 7b42: 00031b63 bnez t1,7b58 + 7b46: c25c sw a5,4(a2) + 7b48: 800007b7 lui a5,0x80000 + 7b4c: 01062023 sw a6,0(a2) + 7b50: 00f8f7b3 and a5,a7,a5 + 7b54: 4801 li a6,0 + 7b56: bfc1 j 7b26 + 7b58: fff74713 not a4,a4 + 7b5c: 4801 li a6,0 + 7b5e: 00b777b3 and a5,a4,a1 + 7b62: 01062023 sw a6,0(a2) + 7b66: c25c sw a5,4(a2) + 7b68: 86be mv a3,a5 + 7b6a: 8642 mv a2,a6 + 7b6c: a46fe0ef jal ra,5db2 <__subdf3> + 7b70: 882a mv a6,a0 + 7b72: 87ae mv a5,a1 + 7b74: bf4d j 7b26 + 7b76: 03300e13 li t3,51 + 7b7a: fcde46e3 blt t3,a3,7b46 + 7b7e: bed70693 addi a3,a4,-1043 # ffbed <_data_lma+0xf3155> + 7b82: 577d li a4,-1 + 7b84: 00d75733 srl a4,a4,a3 + 7b88: 00a776b3 and a3,a4,a0 + 7b8c: decd beqz a3,7b46 + 7b8e: fff74713 not a4,a4 + 7b92: 00a778b3 and a7,a4,a0 + 7b96: 01162023 sw a7,0(a2) + 7b9a: c24c sw a1,4(a2) + 7b9c: 86ae mv a3,a1 + 7b9e: 8646 mv a2,a7 + 7ba0: b7f1 j 7b6c + +00007ba2 : + 7ba2: 00005797 auipc a5,0x5 + 7ba6: b8e78793 addi a5,a5,-1138 # c730 <__clz_tab+0x1a0> + 7baa: 4388 lw a0,0(a5) + 7bac: 8082 ret + +00007bae : + 7bae: 7135 addi sp,sp,-160 + 7bb0: cb3e sw a5,148(sp) + 7bb2: daa6 sw s1,116(sp) + 7bb4: c736 sw a3,140(sp) + 7bb6: c93a sw a4,144(sp) + 7bb8: cd42 sw a6,152(sp) + 7bba: cf46 sw a7,156(sp) + 7bbc: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 7bc0: de86 sw ra,124(sp) + 7bc2: dca2 sw s0,120(sp) + 7bc4: 4384 lw s1,0(a5) + 7bc6: 0005db63 bgez a1,7bdc + 7bca: 08b00793 li a5,139 + 7bce: c09c sw a5,0(s1) + 7bd0: 557d li a0,-1 + 7bd2: 50f6 lw ra,124(sp) + 7bd4: 5466 lw s0,120(sp) + 7bd6: 54d6 lw s1,116(sp) + 7bd8: 610d addi sp,sp,160 + 7bda: 8082 ret + 7bdc: 20800793 li a5,520 + 7be0: 00f11a23 sh a5,20(sp) + 7be4: c42a sw a0,8(sp) + 7be6: cc2a sw a0,24(sp) + 7be8: 4781 li a5,0 + 7bea: c199 beqz a1,7bf0 + 7bec: fff58793 addi a5,a1,-1 + 7bf0: c83e sw a5,16(sp) + 7bf2: ce3e sw a5,28(sp) + 7bf4: 0174 addi a3,sp,140 + 7bf6: 57fd li a5,-1 + 7bf8: 842e mv s0,a1 + 7bfa: 8526 mv a0,s1 + 7bfc: 002c addi a1,sp,8 + 7bfe: 00f11b23 sh a5,22(sp) + 7c02: c236 sw a3,4(sp) + 7c04: 7ae030ef jal ra,b3b2 <_svfiprintf_r> + 7c08: 57fd li a5,-1 + 7c0a: 00f55563 bge a0,a5,7c14 + 7c0e: 08b00793 li a5,139 + 7c12: c09c sw a5,0(s1) + 7c14: dc5d beqz s0,7bd2 + 7c16: 47a2 lw a5,8(sp) + 7c18: 00078023 sb zero,0(a5) + 7c1c: bf5d j 7bd2 + +00007c1e : + 7c1e: 7135 addi sp,sp,-160 + 7c20: cb3e sw a5,148(sp) + 7c22: 800007b7 lui a5,0x80000 + 7c26: fff7c793 not a5,a5 + 7c2a: ce3e sw a5,28(sp) + 7c2c: c83e sw a5,16(sp) + 7c2e: 77c1 lui a5,0xffff0 + 7c30: 20878793 addi a5,a5,520 # ffff0208 <_eusrstack+0xdffe0208> + 7c34: c532 sw a2,136(sp) + 7c36: c736 sw a3,140(sp) + 7c38: c93a sw a4,144(sp) + 7c3a: cd42 sw a6,152(sp) + 7c3c: cf46 sw a7,156(sp) + 7c3e: ca3e sw a5,20(sp) + 7c40: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 7c44: c42a sw a0,8(sp) + 7c46: cc2a sw a0,24(sp) + 7c48: 4388 lw a0,0(a5) + 7c4a: 0134 addi a3,sp,136 + 7c4c: 862e mv a2,a1 + 7c4e: 002c addi a1,sp,8 + 7c50: de86 sw ra,124(sp) + 7c52: c236 sw a3,4(sp) + 7c54: 75e030ef jal ra,b3b2 <_svfiprintf_r> + 7c58: 47a2 lw a5,8(sp) + 7c5a: 00078023 sb zero,0(a5) + 7c5e: 50f6 lw ra,124(sp) + 7c60: 610d addi sp,sp,160 + 7c62: 8082 ret + +00007c64 : + 7c64: 87aa mv a5,a0 + 7c66: 0785 addi a5,a5,1 + 7c68: fff7c703 lbu a4,-1(a5) + 7c6c: ff6d bnez a4,7c66 + 7c6e: 40a78533 sub a0,a5,a0 + 7c72: 157d addi a0,a0,-1 + 7c74: 8082 ret + +00007c76 : + 7c76: 87aa mv a5,a0 + 7c78: ca09 beqz a2,7c8a + 7c7a: 0585 addi a1,a1,1 + 7c7c: fff5c703 lbu a4,-1(a1) + 7c80: 0785 addi a5,a5,1 + 7c82: 167d addi a2,a2,-1 + 7c84: fee78fa3 sb a4,-1(a5) + 7c88: fb65 bnez a4,7c78 + 7c8a: 963e add a2,a2,a5 + 7c8c: 00c79363 bne a5,a2,7c92 + 7c90: 8082 ret + 7c92: 0785 addi a5,a5,1 + 7c94: fe078fa3 sb zero,-1(a5) + 7c98: bfd5 j 7c8c + +00007c9a : + 7c9a: 1101 addi sp,sp,-32 + 7c9c: cc22 sw s0,24(sp) + 7c9e: 872a mv a4,a0 + 7ca0: 842e mv s0,a1 + 7ca2: 853a mv a0,a4 + 7ca4: 85a2 mv a1,s0 + 7ca6: c632 sw a2,12(sp) + 7ca8: ce06 sw ra,28(sp) + 7caa: 162030ef jal ra,ae0c <__ulp> + 7cae: 4632 lw a2,12(sp) + 7cb0: 882a mv a6,a0 + 7cb2: 88ae mv a7,a1 + 7cb4: c605 beqz a2,7cdc + 7cb6: 8051 srli s0,s0,0x14 + 7cb8: 7ff47413 andi s0,s0,2047 + 7cbc: 06b00793 li a5,107 + 7cc0: 8f81 sub a5,a5,s0 + 7cc2: 00f05d63 blez a5,7cdc + 7cc6: 07d2 slli a5,a5,0x14 + 7cc8: 3ff00737 lui a4,0x3ff00 + 7ccc: 4801 li a6,0 + 7cce: 973e add a4,a4,a5 + 7cd0: 8642 mv a2,a6 + 7cd2: 86ba mv a3,a4 + 7cd4: c27fd0ef jal ra,58fa <__muldf3> + 7cd8: 882a mv a6,a0 + 7cda: 88ae mv a7,a1 + 7cdc: 40f2 lw ra,28(sp) + 7cde: 4462 lw s0,24(sp) + 7ce0: 8542 mv a0,a6 + 7ce2: 85c6 mv a1,a7 + 7ce4: 6105 addi sp,sp,32 + 7ce6: 8082 ret + +00007ce8 <_strtod_l>: + 7ce8: 7135 addi sp,sp,-160 + 7cea: c94a sw s2,144(sp) + 7cec: 892a mv s2,a0 + 7cee: 8536 mv a0,a3 + 7cf0: d432 sw a2,40(sp) + 7cf2: c636 sw a3,12(sp) + 7cf4: cf06 sw ra,156(sp) + 7cf6: cd22 sw s0,152(sp) + 7cf8: cb26 sw s1,148(sp) + 7cfa: c74e sw s3,140(sp) + 7cfc: d8ea sw s10,112(sp) + 7cfe: d6ee sw s11,108(sp) + 7d00: 8d2e mv s10,a1 + 7d02: c552 sw s4,136(sp) + 7d04: c356 sw s5,132(sp) + 7d06: c15a sw s6,128(sp) + 7d08: dede sw s7,124(sp) + 7d0a: dce2 sw s8,120(sp) + 7d0c: dae6 sw s9,116(sp) + 7d0e: c882 sw zero,80(sp) + 7d10: 0b5020ef jal ra,a5c4 <__localeconv_l> + 7d14: 8daa mv s11,a0 + 7d16: 4108 lw a0,0(a0) + 7d18: 4481 li s1,0 + 7d1a: 4401 li s0,0 + 7d1c: f49ff0ef jal ra,7c64 + 7d20: 46b2 lw a3,12(sp) + 7d22: 89aa mv s3,a0 + 7d24: c6ea sw s10,76(sp) + 7d26: 4635 li a2,13 + 7d28: 02b00593 li a1,43 + 7d2c: 02d00513 li a0,45 + 7d30: 02000813 li a6,32 + 7d34: 48a5 li a7,9 + 7d36: 47b6 lw a5,76(sp) + 7d38: 0007c703 lbu a4,0(a5) + 7d3c: 08e66b63 bltu a2,a4,7dd2 <_strtod_l+0xea> + 7d40: 09177f63 bgeu a4,a7,7dde <_strtod_l+0xf6> + 7d44: c75d beqz a4,7df2 <_strtod_l+0x10a> + 7d46: c802 sw zero,16(sp) + 7d48: 4a36 lw s4,76(sp) + 7d4a: 03000793 li a5,48 + 7d4e: 4a81 li s5,0 + 7d50: 000a4703 lbu a4,0(s4) + 7d54: 12f71d63 bne a4,a5,7e8e <_strtod_l+0x1a6> + 7d58: 001a4783 lbu a5,1(s4) + 7d5c: 05800713 li a4,88 + 7d60: 00e78863 beq a5,a4,7d70 <_strtod_l+0x88> + 7d64: 07800613 li a2,120 + 7d68: 03000713 li a4,48 + 7d6c: 10c79763 bne a5,a2,7e7a <_strtod_l+0x192> + 7d70: 47c2 lw a5,16(sp) + 7d72: 8836 mv a6,a3 + 7d74: 0898 addi a4,sp,80 + 7d76: 08d4 addi a3,sp,84 + 7d78: 00005617 auipc a2,0x5 + 7d7c: a1860613 addi a2,a2,-1512 # c790 + 7d80: 00ec addi a1,sp,76 + 7d82: 854a mv a0,s2 + 7d84: 1b0020ef jal ra,9f34 <__gethex> + 7d88: 00757993 andi s3,a0,7 + 7d8c: 8aaa mv s5,a0 + 7d8e: 00098863 beqz s3,7d9e <_strtod_l+0xb6> + 7d92: 4799 li a5,6 + 7d94: 06f99863 bne s3,a5,7e04 <_strtod_l+0x11c> + 7d98: 0a05 addi s4,s4,1 + 7d9a: c6d2 sw s4,76(sp) + 7d9c: c802 sw zero,16(sp) + 7d9e: 57a2 lw a5,40(sp) + 7da0: c781 beqz a5,7da8 <_strtod_l+0xc0> + 7da2: 47b6 lw a5,76(sp) + 7da4: 5722 lw a4,40(sp) + 7da6: c31c sw a5,0(a4) + 7da8: 47c2 lw a5,16(sp) + 7daa: cba1 beqz a5,7dfa <_strtod_l+0x112> + 7dac: 800005b7 lui a1,0x80000 + 7db0: 8da1 xor a1,a1,s0 + 7db2: 40fa lw ra,156(sp) + 7db4: 446a lw s0,152(sp) + 7db6: 8526 mv a0,s1 + 7db8: 494a lw s2,144(sp) + 7dba: 44da lw s1,148(sp) + 7dbc: 49ba lw s3,140(sp) + 7dbe: 4a2a lw s4,136(sp) + 7dc0: 4a9a lw s5,132(sp) + 7dc2: 4b0a lw s6,128(sp) + 7dc4: 5bf6 lw s7,124(sp) + 7dc6: 5c66 lw s8,120(sp) + 7dc8: 5cd6 lw s9,116(sp) + 7dca: 5d46 lw s10,112(sp) + 7dcc: 5db6 lw s11,108(sp) + 7dce: 610d addi sp,sp,160 + 7dd0: 8082 ret + 7dd2: 00b70963 beq a4,a1,7de4 <_strtod_l+0xfc> + 7dd6: 02a70463 beq a4,a0,7dfe <_strtod_l+0x116> + 7dda: f70716e3 bne a4,a6,7d46 <_strtod_l+0x5e> + 7dde: 0785 addi a5,a5,1 + 7de0: c6be sw a5,76(sp) + 7de2: bf91 j 7d36 <_strtod_l+0x4e> + 7de4: c802 sw zero,16(sp) + 7de6: 00178713 addi a4,a5,1 + 7dea: c6ba sw a4,76(sp) + 7dec: 0017c783 lbu a5,1(a5) + 7df0: ffa1 bnez a5,7d48 <_strtod_l+0x60> + 7df2: 57a2 lw a5,40(sp) + 7df4: c6ea sw s10,76(sp) + 7df6: c802 sw zero,16(sp) + 7df8: f7cd bnez a5,7da2 <_strtod_l+0xba> + 7dfa: 85a2 mv a1,s0 + 7dfc: bf5d j 7db2 <_strtod_l+0xca> + 7dfe: 4705 li a4,1 + 7e00: c83a sw a4,16(sp) + 7e02: b7d5 j 7de6 <_strtod_l+0xfe> + 7e04: 4646 lw a2,80(sp) + 7e06: ca11 beqz a2,7e1a <_strtod_l+0x132> + 7e08: 03500593 li a1,53 + 7e0c: 08a8 addi a0,sp,88 + 7e0e: 240030ef jal ra,b04e <__copybits> + 7e12: 45c6 lw a1,80(sp) + 7e14: 854a mv a0,s2 + 7e16: 1b5020ef jal ra,a7ca <_Bfree> + 7e1a: 19fd addi s3,s3,-1 + 7e1c: 4791 li a5,4 + 7e1e: 0137ee63 bltu a5,s3,7e3a <_strtod_l+0x152> + 7e22: 00005717 auipc a4,0x5 + 7e26: 91270713 addi a4,a4,-1774 # c734 <__clz_tab+0x1a4> + 7e2a: 098a slli s3,s3,0x2 + 7e2c: 99ba add s3,s3,a4 + 7e2e: 0009a783 lw a5,0(s3) + 7e32: 97ba add a5,a5,a4 + 7e34: 8782 jr a5 + 7e36: 44e6 lw s1,88(sp) + 7e38: 4476 lw s0,92(sp) + 7e3a: 008afa93 andi s5,s5,8 + 7e3e: f60a80e3 beqz s5,7d9e <_strtod_l+0xb6> + 7e42: 800007b7 lui a5,0x80000 + 7e46: 8c5d or s0,s0,a5 + 7e48: bf99 j 7d9e <_strtod_l+0xb6> + 7e4a: 45f6 lw a1,92(sp) + 7e4c: fff00437 lui s0,0xfff00 + 7e50: 147d addi s0,s0,-1 + 7e52: 0085f7b3 and a5,a1,s0 + 7e56: 4456 lw s0,84(sp) + 7e58: 44e6 lw s1,88(sp) + 7e5a: 43340413 addi s0,s0,1075 # fff00433 <_eusrstack+0xdfef0433> + 7e5e: 01441593 slli a1,s0,0x14 + 7e62: 00b7e433 or s0,a5,a1 + 7e66: bfd1 j 7e3a <_strtod_l+0x152> + 7e68: 7ff00437 lui s0,0x7ff00 + 7e6c: b7f9 j 7e3a <_strtod_l+0x152> + 7e6e: 800005b7 lui a1,0x80000 + 7e72: fff5c413 not s0,a1 + 7e76: 54fd li s1,-1 + 7e78: b7c9 j 7e3a <_strtod_l+0x152> + 7e7a: 47b6 lw a5,76(sp) + 7e7c: 00178693 addi a3,a5,1 # 80000001 <_eusrstack+0x5fff0001> + 7e80: c6b6 sw a3,76(sp) + 7e82: 0017c783 lbu a5,1(a5) + 7e86: fee78ae3 beq a5,a4,7e7a <_strtod_l+0x192> + 7e8a: db91 beqz a5,7d9e <_strtod_l+0xb6> + 7e8c: 4a85 li s5,1 + 7e8e: 4cb6 lw s9,76(sp) + 7e90: 4a01 li s4,0 + 7e92: 4b81 li s7,0 + 7e94: 4c01 li s8,0 + 7e96: 46a5 li a3,9 + 7e98: 45a1 li a1,8 + 7e9a: 47a9 li a5,10 + 7e9c: 4536 lw a0,76(sp) + 7e9e: 00054b03 lbu s6,0(a0) + 7ea2: fd0b0713 addi a4,s6,-48 + 7ea6: 0ff77613 andi a2,a4,255 + 7eaa: 04c6fd63 bgeu a3,a2,7f04 <_strtod_l+0x21c> + 7eae: 000da583 lw a1,0(s11) + 7eb2: 864e mv a2,s3 + 7eb4: 195030ef jal ra,b848 + 7eb8: c13d beqz a0,7f1e <_strtod_l+0x236> + 7eba: 87da mv a5,s6 + 7ebc: 8de2 mv s11,s8 + 7ebe: 4681 li a3,0 + 7ec0: 4b01 li s6,0 + 7ec2: 4501 li a0,0 + 7ec4: 06500713 li a4,101 + 7ec8: 00e78763 beq a5,a4,7ed6 <_strtod_l+0x1ee> + 7ecc: 04500713 li a4,69 + 7ed0: 4981 li s3,0 + 7ed2: 16e79963 bne a5,a4,8044 <_strtod_l+0x35c> + 7ed6: 000d9663 bnez s11,7ee2 <_strtod_l+0x1fa> + 7eda: 0156e7b3 or a5,a3,s5 + 7ede: db91 beqz a5,7df2 <_strtod_l+0x10a> + 7ee0: 4d81 li s11,0 + 7ee2: 4d36 lw s10,76(sp) + 7ee4: 02b00713 li a4,43 + 7ee8: 001d0793 addi a5,s10,1 # 7ff30001 <_eusrstack+0x5ff20001> + 7eec: c6be sw a5,76(sp) + 7eee: 001d4783 lbu a5,1(s10) + 7ef2: 0ee78263 beq a5,a4,7fd6 <_strtod_l+0x2ee> + 7ef6: 02d00713 li a4,45 + 7efa: 4801 li a6,0 + 7efc: 0ee79363 bne a5,a4,7fe2 <_strtod_l+0x2fa> + 7f00: 4805 li a6,1 + 7f02: a8d9 j 7fd8 <_strtod_l+0x2f0> + 7f04: 0185c963 blt a1,s8,7f16 <_strtod_l+0x22e> + 7f08: 02fb8bb3 mul s7,s7,a5 + 7f0c: 9bba add s7,s7,a4 + 7f0e: 0505 addi a0,a0,1 + 7f10: 0c05 addi s8,s8,1 + 7f12: c6aa sw a0,76(sp) + 7f14: b761 j 7e9c <_strtod_l+0x1b4> + 7f16: 02fa0a33 mul s4,s4,a5 + 7f1a: 9a3a add s4,s4,a4 + 7f1c: bfcd j 7f0e <_strtod_l+0x226> + 7f1e: 4536 lw a0,76(sp) + 7f20: 4681 li a3,0 + 7f22: 954e add a0,a0,s3 + 7f24: c6aa sw a0,76(sp) + 7f26: 00054783 lbu a5,0(a0) + 7f2a: 060c0d63 beqz s8,7fa4 <_strtod_l+0x2bc> + 7f2e: 4b01 li s6,0 + 7f30: 8de2 mv s11,s8 + 7f32: fd078713 addi a4,a5,-48 + 7f36: 4625 li a2,9 + 7f38: 02e67663 bgeu a2,a4,7f64 <_strtod_l+0x27c> + 7f3c: 4505 li a0,1 + 7f3e: b759 j 7ec4 <_strtod_l+0x1dc> + 7f40: 47b6 lw a5,76(sp) + 7f42: 0685 addi a3,a3,1 + 7f44: 00178613 addi a2,a5,1 + 7f48: c6b2 sw a2,76(sp) + 7f4a: 0017c783 lbu a5,1(a5) + 7f4e: fee789e3 beq a5,a4,7f40 <_strtod_l+0x258> + 7f52: fcf78713 addi a4,a5,-49 + 7f56: 4621 li a2,8 + 7f58: 1ee66ae3 bltu a2,a4,894c <_strtod_l+0xc64> + 7f5c: 4cb6 lw s9,76(sp) + 7f5e: 8b36 mv s6,a3 + 7f60: 4d81 li s11,0 + 7f62: 4681 li a3,0 + 7f64: fd078793 addi a5,a5,-48 + 7f68: 00168713 addi a4,a3,1 + 7f6c: c785 beqz a5,7f94 <_strtod_l+0x2ac> + 7f6e: 9b3a add s6,s6,a4 + 7f70: 01b68533 add a0,a3,s11 + 7f74: 876e mv a4,s11 + 7f76: 4821 li a6,8 + 7f78: 48c1 li a7,16 + 7f7a: 4629 li a2,10 + 7f7c: 02a71763 bne a4,a0,7faa <_strtod_l+0x2c2> + 7f80: 0d85 addi s11,s11,1 + 7f82: 9db6 add s11,s11,a3 + 7f84: 46a1 li a3,8 + 7f86: 02e6cf63 blt a3,a4,7fc4 <_strtod_l+0x2dc> + 7f8a: 4729 li a4,10 + 7f8c: 02eb8bb3 mul s7,s7,a4 + 7f90: 4701 li a4,0 + 7f92: 9bbe add s7,s7,a5 + 7f94: 47b6 lw a5,76(sp) + 7f96: 00178693 addi a3,a5,1 + 7f9a: c6b6 sw a3,76(sp) + 7f9c: 0017c783 lbu a5,1(a5) + 7fa0: 86ba mv a3,a4 + 7fa2: bf41 j 7f32 <_strtod_l+0x24a> + 7fa4: 03000713 li a4,48 + 7fa8: b75d j 7f4e <_strtod_l+0x266> + 7faa: 00170593 addi a1,a4,1 + 7fae: 00e84663 blt a6,a4,7fba <_strtod_l+0x2d2> + 7fb2: 02cb8bb3 mul s7,s7,a2 + 7fb6: 872e mv a4,a1 + 7fb8: b7d1 j 7f7c <_strtod_l+0x294> + 7fba: feb8cee3 blt a7,a1,7fb6 <_strtod_l+0x2ce> + 7fbe: 02ca0a33 mul s4,s4,a2 + 7fc2: bfd5 j 7fb6 <_strtod_l+0x2ce> + 7fc4: 46c1 li a3,16 + 7fc6: 4701 li a4,0 + 7fc8: fdb6c6e3 blt a3,s11,7f94 <_strtod_l+0x2ac> + 7fcc: 46a9 li a3,10 + 7fce: 02da0a33 mul s4,s4,a3 + 7fd2: 9a3e add s4,s4,a5 + 7fd4: b7c1 j 7f94 <_strtod_l+0x2ac> + 7fd6: 4801 li a6,0 + 7fd8: 002d0793 addi a5,s10,2 + 7fdc: c6be sw a5,76(sp) + 7fde: 002d4783 lbu a5,2(s10) + 7fe2: fd078713 addi a4,a5,-48 + 7fe6: 4625 li a2,9 + 7fe8: 0ce66763 bltu a2,a4,80b6 <_strtod_l+0x3ce> + 7fec: 03000713 li a4,48 + 7ff0: 0ae78663 beq a5,a4,809c <_strtod_l+0x3b4> + 7ff4: fcf78713 addi a4,a5,-49 + 7ff8: 4621 li a2,8 + 7ffa: 4981 li s3,0 + 7ffc: 04e66463 bltu a2,a4,8044 <_strtod_l+0x35c> + 8000: 48b6 lw a7,76(sp) + 8002: fd078713 addi a4,a5,-48 + 8006: 4325 li t1,9 + 8008: 4e29 li t3,10 + 800a: 47b6 lw a5,76(sp) + 800c: 00178613 addi a2,a5,1 + 8010: c6b2 sw a2,76(sp) + 8012: 0017c783 lbu a5,1(a5) + 8016: fd078593 addi a1,a5,-48 + 801a: 0ff5f593 andi a1,a1,255 + 801e: 08b37663 bgeu t1,a1,80aa <_strtod_l+0x3c2> + 8022: 6995 lui s3,0x5 + 8024: 41160633 sub a2,a2,a7 + 8028: e1f98993 addi s3,s3,-481 # 4e1f <__adddf3+0x3d7> + 802c: 48a1 li a7,8 + 802e: 85ce mv a1,s3 + 8030: 00c8c663 blt a7,a2,803c <_strtod_l+0x354> + 8034: 89ba mv s3,a4 + 8036: 00e5d363 bge a1,a4,803c <_strtod_l+0x354> + 803a: 89ae mv s3,a1 + 803c: 00080463 beqz a6,8044 <_strtod_l+0x35c> + 8040: 413009b3 neg s3,s3 + 8044: 0c0d9863 bnez s11,8114 <_strtod_l+0x42c> + 8048: 00dae6b3 or a3,s5,a3 + 804c: d40699e3 bnez a3,7d9e <_strtod_l+0xb6> + 8050: da0511e3 bnez a0,7df2 <_strtod_l+0x10a> + 8054: 04e00713 li a4,78 + 8058: 06e78a63 beq a5,a4,80cc <_strtod_l+0x3e4> + 805c: 06f74063 blt a4,a5,80bc <_strtod_l+0x3d4> + 8060: 04900713 li a4,73 + 8064: d8e797e3 bne a5,a4,7df2 <_strtod_l+0x10a> + 8068: 00004597 auipc a1,0x4 + 806c: 71858593 addi a1,a1,1816 # c780 <__clz_tab+0x1f0> + 8070: 00e8 addi a0,sp,76 + 8072: 3bc020ef jal ra,a42e <__match> + 8076: d6050ee3 beqz a0,7df2 <_strtod_l+0x10a> + 807a: 47b6 lw a5,76(sp) + 807c: 00004597 auipc a1,0x4 + 8080: 70858593 addi a1,a1,1800 # c784 <__clz_tab+0x1f4> + 8084: 00e8 addi a0,sp,76 + 8086: 17fd addi a5,a5,-1 + 8088: c6be sw a5,76(sp) + 808a: 3a4020ef jal ra,a42e <__match> + 808e: e501 bnez a0,8096 <_strtod_l+0x3ae> + 8090: 47b6 lw a5,76(sp) + 8092: 0785 addi a5,a5,1 + 8094: c6be sw a5,76(sp) + 8096: 7ff00437 lui s0,0x7ff00 + 809a: b311 j 7d9e <_strtod_l+0xb6> + 809c: 47b6 lw a5,76(sp) + 809e: 00178613 addi a2,a5,1 + 80a2: c6b2 sw a2,76(sp) + 80a4: 0017c783 lbu a5,1(a5) + 80a8: b7a1 j 7ff0 <_strtod_l+0x308> + 80aa: 03c70733 mul a4,a4,t3 + 80ae: 97ba add a5,a5,a4 + 80b0: fd078713 addi a4,a5,-48 + 80b4: bf99 j 800a <_strtod_l+0x322> + 80b6: c6ea sw s10,76(sp) + 80b8: 4981 li s3,0 + 80ba: b769 j 8044 <_strtod_l+0x35c> + 80bc: 06900713 li a4,105 + 80c0: fae784e3 beq a5,a4,8068 <_strtod_l+0x380> + 80c4: 06e00713 li a4,110 + 80c8: d2e795e3 bne a5,a4,7df2 <_strtod_l+0x10a> + 80cc: 00004597 auipc a1,0x4 + 80d0: 6c058593 addi a1,a1,1728 # c78c <__clz_tab+0x1fc> + 80d4: 00e8 addi a0,sp,76 + 80d6: 358020ef jal ra,a42e <__match> + 80da: d0050ce3 beqz a0,7df2 <_strtod_l+0x10a> + 80de: 47b6 lw a5,76(sp) + 80e0: 0007c703 lbu a4,0(a5) + 80e4: 02800793 li a5,40 + 80e8: 02f71363 bne a4,a5,810e <_strtod_l+0x426> + 80ec: 08b0 addi a2,sp,88 + 80ee: 00004597 auipc a1,0x4 + 80f2: 6b658593 addi a1,a1,1718 # c7a4 + 80f6: 00e8 addi a0,sp,76 + 80f8: 366020ef jal ra,a45e <__hexnan> + 80fc: 4795 li a5,5 + 80fe: 00f51863 bne a0,a5,810e <_strtod_l+0x426> + 8102: 45f6 lw a1,92(sp) + 8104: 7ff00437 lui s0,0x7ff00 + 8108: 44e6 lw s1,88(sp) + 810a: 8c4d or s0,s0,a1 + 810c: b949 j 7d9e <_strtod_l+0xb6> + 810e: fff80437 lui s0,0xfff80 + 8112: b171 j 7d9e <_strtod_l+0xb6> + 8114: 41698ab3 sub s5,s3,s6 + 8118: 000c1363 bnez s8,811e <_strtod_l+0x436> + 811c: 8c6e mv s8,s11 + 811e: 47c1 li a5,16 + 8120: 8d6e mv s10,s11 + 8122: 01b7d363 bge a5,s11,8128 <_strtod_l+0x440> + 8126: 4d41 li s10,16 + 8128: 855e mv a0,s7 + 812a: c9afe0ef jal ra,65c4 <__floatunsidf> + 812e: 47a5 li a5,9 + 8130: 84aa mv s1,a0 + 8132: 842e mv s0,a1 + 8134: 03b7dc63 bge a5,s11,816c <_strtod_l+0x484> + 8138: ff7d0793 addi a5,s10,-9 + 813c: 00379713 slli a4,a5,0x3 + 8140: 00004797 auipc a5,0x4 + 8144: 78078793 addi a5,a5,1920 # c8c0 <__mprec_tens> + 8148: 97ba add a5,a5,a4 + 814a: 4390 lw a2,0(a5) + 814c: 43d4 lw a3,4(a5) + 814e: facfd0ef jal ra,58fa <__muldf3> + 8152: 842a mv s0,a0 + 8154: 8552 mv a0,s4 + 8156: 84ae mv s1,a1 + 8158: c6cfe0ef jal ra,65c4 <__floatunsidf> + 815c: 862a mv a2,a0 + 815e: 86ae mv a3,a1 + 8160: 8522 mv a0,s0 + 8162: 85a6 mv a1,s1 + 8164: 8e5fc0ef jal ra,4a48 <__adddf3> + 8168: 84aa mv s1,a0 + 816a: 842e mv s0,a1 + 816c: 47bd li a5,15 + 816e: 09b7cd63 blt a5,s11,8208 <_strtod_l+0x520> + 8172: c20a86e3 beqz s5,7d9e <_strtod_l+0xb6> + 8176: 07505463 blez s5,81de <_strtod_l+0x4f6> + 817a: 4759 li a4,22 + 817c: 03574363 blt a4,s5,81a2 <_strtod_l+0x4ba> + 8180: 0a8e slli s5,s5,0x3 + 8182: 00004797 auipc a5,0x4 + 8186: 73e78793 addi a5,a5,1854 # c8c0 <__mprec_tens> + 818a: 9abe add s5,s5,a5 + 818c: 000aa503 lw a0,0(s5) + 8190: 004aa583 lw a1,4(s5) + 8194: 8626 mv a2,s1 + 8196: 86a2 mv a3,s0 + 8198: f62fd0ef jal ra,58fa <__muldf3> + 819c: 84aa mv s1,a0 + 819e: 842e mv s0,a1 + 81a0: befd j 7d9e <_strtod_l+0xb6> + 81a2: 02500713 li a4,37 + 81a6: 41b70733 sub a4,a4,s11 + 81aa: 05574f63 blt a4,s5,8208 <_strtod_l+0x520> + 81ae: 41b78db3 sub s11,a5,s11 + 81b2: 00004917 auipc s2,0x4 + 81b6: 70e90913 addi s2,s2,1806 # c8c0 <__mprec_tens> + 81ba: 003d9793 slli a5,s11,0x3 + 81be: 97ca add a5,a5,s2 + 81c0: 4388 lw a0,0(a5) + 81c2: 43cc lw a1,4(a5) + 81c4: 41ba8db3 sub s11,s5,s11 + 81c8: 8626 mv a2,s1 + 81ca: 86a2 mv a3,s0 + 81cc: 0d8e slli s11,s11,0x3 + 81ce: f2cfd0ef jal ra,58fa <__muldf3> + 81d2: 9dca add s11,s11,s2 + 81d4: 000da603 lw a2,0(s11) + 81d8: 004da683 lw a3,4(s11) + 81dc: bf75 j 8198 <_strtod_l+0x4b0> + 81de: 57a9 li a5,-22 + 81e0: 02fac463 blt s5,a5,8208 <_strtod_l+0x520> + 81e4: 413b09b3 sub s3,s6,s3 + 81e8: 00399b13 slli s6,s3,0x3 + 81ec: 00004997 auipc s3,0x4 + 81f0: 6d498993 addi s3,s3,1748 # c8c0 <__mprec_tens> + 81f4: 99da add s3,s3,s6 + 81f6: 0009a603 lw a2,0(s3) + 81fa: 0049a683 lw a3,4(s3) + 81fe: 8526 mv a0,s1 + 8200: 85a2 mv a1,s0 + 8202: f77fc0ef jal ra,5178 <__divdf3> + 8206: bf59 j 819c <_strtod_l+0x4b4> + 8208: 41ad8d33 sub s10,s11,s10 + 820c: 9d56 add s10,s10,s5 + 820e: 11a05763 blez s10,831c <_strtod_l+0x634> + 8212: 00fd7793 andi a5,s10,15 + 8216: cf99 beqz a5,8234 <_strtod_l+0x54c> + 8218: 00004717 auipc a4,0x4 + 821c: 6a870713 addi a4,a4,1704 # c8c0 <__mprec_tens> + 8220: 078e slli a5,a5,0x3 + 8222: 97ba add a5,a5,a4 + 8224: 4388 lw a0,0(a5) + 8226: 43cc lw a1,4(a5) + 8228: 8626 mv a2,s1 + 822a: 86a2 mv a3,s0 + 822c: ecefd0ef jal ra,58fa <__muldf3> + 8230: 84aa mv s1,a0 + 8232: 842e mv s0,a1 + 8234: ff0d7d13 andi s10,s10,-16 + 8238: 0a0d0863 beqz s10,82e8 <_strtod_l+0x600> + 823c: 13400793 li a5,308 + 8240: 05a7d563 bge a5,s10,828a <_strtod_l+0x5a2> + 8244: 4b01 li s6,0 + 8246: 4981 li s3,0 + 8248: c602 sw zero,12(sp) + 824a: 4b81 li s7,0 + 824c: 02200793 li a5,34 + 8250: 00f92023 sw a5,0(s2) + 8254: 7ff00437 lui s0,0x7ff00 + 8258: 4481 li s1,0 + 825a: 47b2 lw a5,12(sp) + 825c: b40781e3 beqz a5,7d9e <_strtod_l+0xb6> + 8260: 45c6 lw a1,80(sp) + 8262: 854a mv a0,s2 + 8264: 566020ef jal ra,a7ca <_Bfree> + 8268: 85de mv a1,s7 + 826a: 854a mv a0,s2 + 826c: 55e020ef jal ra,a7ca <_Bfree> + 8270: 85ce mv a1,s3 + 8272: 854a mv a0,s2 + 8274: 556020ef jal ra,a7ca <_Bfree> + 8278: 45b2 lw a1,12(sp) + 827a: 854a mv a0,s2 + 827c: 54e020ef jal ra,a7ca <_Bfree> + 8280: 85da mv a1,s6 + 8282: 854a mv a0,s2 + 8284: 546020ef jal ra,a7ca <_Bfree> + 8288: be19 j 7d9e <_strtod_l+0xb6> + 828a: 404d5d13 srai s10,s10,0x4 + 828e: 8526 mv a0,s1 + 8290: 85a2 mv a1,s0 + 8292: 4781 li a5,0 + 8294: 4a01 li s4,0 + 8296: 4805 li a6,1 + 8298: 00004897 auipc a7,0x4 + 829c: 60088893 addi a7,a7,1536 # c898 <__mprec_bigtens> + 82a0: 05a84663 blt a6,s10,82ec <_strtod_l+0x604> + 82a4: c399 beqz a5,82aa <_strtod_l+0x5c2> + 82a6: 84aa mv s1,a0 + 82a8: 842e mv s0,a1 + 82aa: 00004717 auipc a4,0x4 + 82ae: 5ee70713 addi a4,a4,1518 # c898 <__mprec_bigtens> + 82b2: 003a1793 slli a5,s4,0x3 + 82b6: 97ba add a5,a5,a4 + 82b8: 4388 lw a0,0(a5) + 82ba: 43cc lw a1,4(a5) + 82bc: fcb00737 lui a4,0xfcb00 + 82c0: 9722 add a4,a4,s0 + 82c2: 8626 mv a2,s1 + 82c4: 86ba mv a3,a4 + 82c6: e34fd0ef jal ra,58fa <__muldf3> + 82ca: 7ff00437 lui s0,0x7ff00 + 82ce: 00b477b3 and a5,s0,a1 + 82d2: 7ca00737 lui a4,0x7ca00 + 82d6: 84aa mv s1,a0 + 82d8: f6f766e3 bltu a4,a5,8244 <_strtod_l+0x55c> + 82dc: 7c900737 lui a4,0x7c900 + 82e0: 02f77a63 bgeu a4,a5,8314 <_strtod_l+0x62c> + 82e4: 147d addi s0,s0,-1 + 82e6: 54fd li s1,-1 + 82e8: 4a01 li s4,0 + 82ea: a8dd j 83e0 <_strtod_l+0x6f8> + 82ec: 001d7713 andi a4,s10,1 + 82f0: cf11 beqz a4,830c <_strtod_l+0x624> + 82f2: 003a1713 slli a4,s4,0x3 + 82f6: 9746 add a4,a4,a7 + 82f8: 4310 lw a2,0(a4) + 82fa: 4354 lw a3,4(a4) + 82fc: dfefd0ef jal ra,58fa <__muldf3> + 8300: 4785 li a5,1 + 8302: 4805 li a6,1 + 8304: 00004897 auipc a7,0x4 + 8308: 59488893 addi a7,a7,1428 # c898 <__mprec_bigtens> + 830c: 0a05 addi s4,s4,1 + 830e: 401d5d13 srai s10,s10,0x1 + 8312: b779 j 82a0 <_strtod_l+0x5b8> + 8314: 03500437 lui s0,0x3500 + 8318: 942e add s0,s0,a1 + 831a: b7f9 j 82e8 <_strtod_l+0x600> + 831c: fc0d06e3 beqz s10,82e8 <_strtod_l+0x600> + 8320: 41a00d33 neg s10,s10 + 8324: 00fd7793 andi a5,s10,15 + 8328: cf99 beqz a5,8346 <_strtod_l+0x65e> + 832a: 00004717 auipc a4,0x4 + 832e: 59670713 addi a4,a4,1430 # c8c0 <__mprec_tens> + 8332: 078e slli a5,a5,0x3 + 8334: 97ba add a5,a5,a4 + 8336: 4390 lw a2,0(a5) + 8338: 43d4 lw a3,4(a5) + 833a: 8526 mv a0,s1 + 833c: 85a2 mv a1,s0 + 833e: e3bfc0ef jal ra,5178 <__divdf3> + 8342: 84aa mv s1,a0 + 8344: 842e mv s0,a1 + 8346: 404d5d13 srai s10,s10,0x4 + 834a: f80d0fe3 beqz s10,82e8 <_strtod_l+0x600> + 834e: 47fd li a5,31 + 8350: 01a7dd63 bge a5,s10,836a <_strtod_l+0x682> + 8354: 4b01 li s6,0 + 8356: 4981 li s3,0 + 8358: c602 sw zero,12(sp) + 835a: 4b81 li s7,0 + 835c: 02200793 li a5,34 + 8360: 4481 li s1,0 + 8362: 4401 li s0,0 + 8364: 00f92023 sw a5,0(s2) + 8368: bdcd j 825a <_strtod_l+0x572> + 836a: 010d7a13 andi s4,s10,16 + 836e: 000a0463 beqz s4,8376 <_strtod_l+0x68e> + 8372: 06a00a13 li s4,106 + 8376: 8526 mv a0,s1 + 8378: 85a2 mv a1,s0 + 837a: 00004797 auipc a5,0x4 + 837e: 43e78793 addi a5,a5,1086 # c7b8 + 8382: 4701 li a4,0 + 8384: 001d7693 andi a3,s10,1 + 8388: ca81 beqz a3,8398 <_strtod_l+0x6b0> + 838a: 4390 lw a2,0(a5) + 838c: 43d4 lw a3,4(a5) + 838e: c63e sw a5,12(sp) + 8390: d6afd0ef jal ra,58fa <__muldf3> + 8394: 47b2 lw a5,12(sp) + 8396: 4705 li a4,1 + 8398: 401d5d13 srai s10,s10,0x1 + 839c: 07a1 addi a5,a5,8 + 839e: fe0d13e3 bnez s10,8384 <_strtod_l+0x69c> + 83a2: c319 beqz a4,83a8 <_strtod_l+0x6c0> + 83a4: 84aa mv s1,a0 + 83a6: 842e mv s0,a1 + 83a8: 020a0563 beqz s4,83d2 <_strtod_l+0x6ea> + 83ac: 01445793 srli a5,s0,0x14 + 83b0: 7ff7f713 andi a4,a5,2047 + 83b4: 06b00793 li a5,107 + 83b8: 8f99 sub a5,a5,a4 + 83ba: 00f05c63 blez a5,83d2 <_strtod_l+0x6ea> + 83be: 477d li a4,31 + 83c0: 22f75463 bge a4,a5,85e8 <_strtod_l+0x900> + 83c4: 03400713 li a4,52 + 83c8: 4481 li s1,0 + 83ca: 20f75963 bge a4,a5,85dc <_strtod_l+0x8f4> + 83ce: 03700437 lui s0,0x3700 + 83d2: 4601 li a2,0 + 83d4: 4681 li a3,0 + 83d6: 8526 mv a0,s1 + 83d8: 85a2 mv a1,s0 + 83da: b52fd0ef jal ra,572c <__eqdf2> + 83de: d93d beqz a0,8354 <_strtod_l+0x66c> + 83e0: 875e mv a4,s7 + 83e2: 86ee mv a3,s11 + 83e4: 8662 mv a2,s8 + 83e6: 85e6 mv a1,s9 + 83e8: 854a mv a0,s2 + 83ea: 4bc020ef jal ra,a8a6 <__s2b> + 83ee: c62a sw a0,12(sp) + 83f0: e4050ae3 beqz a0,8244 <_strtod_l+0x55c> + 83f4: 41fad793 srai a5,s5,0x1f + 83f8: 413b09b3 sub s3,s6,s3 + 83fc: 00f9f7b3 and a5,s3,a5 + 8400: d03e sw a5,32(sp) + 8402: ce56 sw s5,28(sp) + 8404: 000ad363 bgez s5,840a <_strtod_l+0x722> + 8408: ce02 sw zero,28(sp) + 840a: 47b2 lw a5,12(sp) + 840c: 4b01 li s6,0 + 840e: 4981 li s3,0 + 8410: 07b1 addi a5,a5,12 + 8412: d83e sw a5,48(sp) + 8414: 001007b7 lui a5,0x100 + 8418: 17fd addi a5,a5,-1 + 841a: d63e sw a5,44(sp) + 841c: 47b2 lw a5,12(sp) + 841e: 854a mv a0,s2 + 8420: 43cc lw a1,4(a5) + 8422: 31c020ef jal ra,a73e <_Balloc> + 8426: 8baa mv s7,a0 + 8428: e20502e3 beqz a0,824c <_strtod_l+0x564> + 842c: 47b2 lw a5,12(sp) + 842e: 55c2 lw a1,48(sp) + 8430: 0531 addi a0,a0,12 + 8432: 4b90 lw a2,16(a5) + 8434: 0609 addi a2,a2,2 + 8436: 060a slli a2,a2,0x2 + 8438: aeefe0ef jal ra,6726 + 843c: 08b8 addi a4,sp,88 + 843e: 08d4 addi a3,sp,84 + 8440: 8622 mv a2,s0 + 8442: 85a6 mv a1,s1 + 8444: 854a mv a0,s2 + 8446: ca26 sw s1,20(sp) + 8448: cc22 sw s0,24(sp) + 844a: 2bd020ef jal ra,af06 <__d2b> + 844e: c8aa sw a0,80(sp) + 8450: de050ee3 beqz a0,824c <_strtod_l+0x564> + 8454: 4585 li a1,1 + 8456: 854a mv a0,s2 + 8458: 5a4020ef jal ra,a9fc <__i2b> + 845c: 89aa mv s3,a0 + 845e: de0507e3 beqz a0,824c <_strtod_l+0x564> + 8462: 47d6 lw a5,84(sp) + 8464: 1807c763 bltz a5,85f2 <_strtod_l+0x90a> + 8468: 5702 lw a4,32(sp) + 846a: 4c72 lw s8,28(sp) + 846c: 00e78d33 add s10,a5,a4 + 8470: 4766 lw a4,88(sp) + 8472: 414787b3 sub a5,a5,s4 + 8476: 03600693 li a3,54 + 847a: 97ba add a5,a5,a4 + 847c: 17fd addi a5,a5,-1 + 847e: c0200d93 li s11,-1022 + 8482: 8e99 sub a3,a3,a4 + 8484: 19b7d663 bge a5,s11,8610 <_strtod_l+0x928> + 8488: 40fd8733 sub a4,s11,a5 + 848c: 467d li a2,31 + 848e: 8e99 sub a3,a3,a4 + 8490: 16e64663 blt a2,a4,85fc <_strtod_l+0x914> + 8494: 4d85 li s11,1 + 8496: 00ed97b3 sll a5,s11,a4 + 849a: d23e sw a5,36(sp) + 849c: 4c81 li s9,0 + 849e: 9c36 add s8,s8,a3 + 84a0: 00dd0db3 add s11,s10,a3 + 84a4: 9c52 add s8,s8,s4 + 84a6: 87ea mv a5,s10 + 84a8: 01add363 bge s11,s10,84ae <_strtod_l+0x7c6> + 84ac: 87ee mv a5,s11 + 84ae: 00fc5363 bge s8,a5,84b4 <_strtod_l+0x7cc> + 84b2: 87e2 mv a5,s8 + 84b4: 00f05863 blez a5,84c4 <_strtod_l+0x7dc> + 84b8: 40fd8db3 sub s11,s11,a5 + 84bc: 40fc0c33 sub s8,s8,a5 + 84c0: 40fd0d33 sub s10,s10,a5 + 84c4: 5782 lw a5,32(sp) + 84c6: 02f05863 blez a5,84f6 <_strtod_l+0x80e> + 84ca: 85ce mv a1,s3 + 84cc: 863e mv a2,a5 + 84ce: 854a mv a0,s2 + 84d0: 68c020ef jal ra,ab5c <__pow5mult> + 84d4: 89aa mv s3,a0 + 84d6: d6050be3 beqz a0,824c <_strtod_l+0x564> + 84da: 4646 lw a2,80(sp) + 84dc: 85aa mv a1,a0 + 84de: 854a mv a0,s2 + 84e0: 538020ef jal ra,aa18 <__multiply> + 84e4: da2a sw a0,52(sp) + 84e6: d60503e3 beqz a0,824c <_strtod_l+0x564> + 84ea: 45c6 lw a1,80(sp) + 84ec: 854a mv a0,s2 + 84ee: 2dc020ef jal ra,a7ca <_Bfree> + 84f2: 57d2 lw a5,52(sp) + 84f4: c8be sw a5,80(sp) + 84f6: 11b04f63 bgtz s11,8614 <_strtod_l+0x92c> + 84fa: 01505a63 blez s5,850e <_strtod_l+0x826> + 84fe: 4672 lw a2,28(sp) + 8500: 85de mv a1,s7 + 8502: 854a mv a0,s2 + 8504: 658020ef jal ra,ab5c <__pow5mult> + 8508: 8baa mv s7,a0 + 850a: d40501e3 beqz a0,824c <_strtod_l+0x564> + 850e: 01805a63 blez s8,8522 <_strtod_l+0x83a> + 8512: 85de mv a1,s7 + 8514: 8662 mv a2,s8 + 8516: 854a mv a0,s2 + 8518: 702020ef jal ra,ac1a <__lshift> + 851c: 8baa mv s7,a0 + 851e: d20507e3 beqz a0,824c <_strtod_l+0x564> + 8522: 01a05a63 blez s10,8536 <_strtod_l+0x84e> + 8526: 85ce mv a1,s3 + 8528: 866a mv a2,s10 + 852a: 854a mv a0,s2 + 852c: 6ee020ef jal ra,ac1a <__lshift> + 8530: 89aa mv s3,a0 + 8532: d0050de3 beqz a0,824c <_strtod_l+0x564> + 8536: 45c6 lw a1,80(sp) + 8538: 865e mv a2,s7 + 853a: 854a mv a0,s2 + 853c: 7de020ef jal ra,ad1a <__mdiff> + 8540: 8b2a mv s6,a0 + 8542: d00505e3 beqz a0,824c <_strtod_l+0x564> + 8546: 00c52c03 lw s8,12(a0) + 854a: 85ce mv a1,s3 + 854c: 00052623 sw zero,12(a0) + 8550: 798020ef jal ra,ace8 <__mcmp> + 8554: 0c055963 bgez a0,8626 <_strtod_l+0x93e> + 8558: 009c6c33 or s8,s8,s1 + 855c: 120c1163 bnez s8,867e <_strtod_l+0x996> + 8560: 00c41793 slli a5,s0,0xc + 8564: 10079d63 bnez a5,867e <_strtod_l+0x996> + 8568: 7ff007b7 lui a5,0x7ff00 + 856c: 8fe1 and a5,a5,s0 + 856e: 06b00737 lui a4,0x6b00 + 8572: 10f77663 bgeu a4,a5,867e <_strtod_l+0x996> + 8576: 014b2783 lw a5,20(s6) + 857a: e791 bnez a5,8586 <_strtod_l+0x89e> + 857c: 010b2703 lw a4,16(s6) + 8580: 4785 li a5,1 + 8582: 0ee7de63 bge a5,a4,867e <_strtod_l+0x996> + 8586: 85da mv a1,s6 + 8588: 4605 li a2,1 + 858a: 854a mv a0,s2 + 858c: 68e020ef jal ra,ac1a <__lshift> + 8590: 85ce mv a1,s3 + 8592: 8b2a mv s6,a0 + 8594: 754020ef jal ra,ace8 <__mcmp> + 8598: 0ea05363 blez a0,867e <_strtod_l+0x996> + 859c: 100a0c63 beqz s4,86b4 <_strtod_l+0x9cc> + 85a0: 7ff007b7 lui a5,0x7ff00 + 85a4: 8fe1 and a5,a5,s0 + 85a6: 06b00737 lui a4,0x6b00 + 85aa: 10f74563 blt a4,a5,86b4 <_strtod_l+0x9cc> + 85ae: 03700737 lui a4,0x3700 + 85b2: daf755e3 bge a4,a5,835c <_strtod_l+0x674> + 85b6: 4701 li a4,0 + 85b8: 395007b7 lui a5,0x39500 + 85bc: 8526 mv a0,s1 + 85be: 85a2 mv a1,s0 + 85c0: 863a mv a2,a4 + 85c2: 86be mv a3,a5 + 85c4: b36fd0ef jal ra,58fa <__muldf3> + 85c8: 842e mv s0,a1 + 85ca: 8dc9 or a1,a1,a0 + 85cc: 84aa mv s1,a0 + 85ce: c80599e3 bnez a1,8260 <_strtod_l+0x578> + 85d2: 02200793 li a5,34 + 85d6: 00f92023 sw a5,0(s2) + 85da: b159 j 8260 <_strtod_l+0x578> + 85dc: 1781 addi a5,a5,-32 + 85de: 577d li a4,-1 + 85e0: 00f717b3 sll a5,a4,a5 + 85e4: 8c7d and s0,s0,a5 + 85e6: b3f5 j 83d2 <_strtod_l+0x6ea> + 85e8: 577d li a4,-1 + 85ea: 00f717b3 sll a5,a4,a5 + 85ee: 8cfd and s1,s1,a5 + 85f0: b3cd j 83d2 <_strtod_l+0x6ea> + 85f2: 4772 lw a4,28(sp) + 85f4: 5d02 lw s10,32(sp) + 85f6: 40f70c33 sub s8,a4,a5 + 85fa: bd9d j 8470 <_strtod_l+0x788> + 85fc: be200c93 li s9,-1054 + 8600: 40fc87b3 sub a5,s9,a5 + 8604: 4c85 li s9,1 + 8606: 00fc9cb3 sll s9,s9,a5 + 860a: 4785 li a5,1 + 860c: d23e sw a5,36(sp) + 860e: bd41 j 849e <_strtod_l+0x7b6> + 8610: 4c81 li s9,0 + 8612: bfe5 j 860a <_strtod_l+0x922> + 8614: 45c6 lw a1,80(sp) + 8616: 866e mv a2,s11 + 8618: 854a mv a0,s2 + 861a: 600020ef jal ra,ac1a <__lshift> + 861e: c8aa sw a0,80(sp) + 8620: ec051de3 bnez a0,84fa <_strtod_l+0x812> + 8624: b125 j 824c <_strtod_l+0x564> + 8626: e969 bnez a0,86f8 <_strtod_l+0xa10> + 8628: 00100737 lui a4,0x100 + 862c: 177d addi a4,a4,-1 + 862e: 00e477b3 and a5,s0,a4 + 8632: 040c0963 beqz s8,8684 <_strtod_l+0x99c> + 8636: 04e79963 bne a5,a4,8688 <_strtod_l+0x9a0> + 863a: 577d li a4,-1 + 863c: 020a0063 beqz s4,865c <_strtod_l+0x974> + 8640: 7ff007b7 lui a5,0x7ff00 + 8644: 8fe1 and a5,a5,s0 + 8646: 06a006b7 lui a3,0x6a00 + 864a: 00f6e963 bltu a3,a5,865c <_strtod_l+0x974> + 864e: 83d1 srli a5,a5,0x14 + 8650: 06b00693 li a3,107 + 8654: 40f687b3 sub a5,a3,a5 + 8658: 00f71733 sll a4,a4,a5 + 865c: 02e49663 bne s1,a4,8688 <_strtod_l+0x9a0> + 8660: 7ff007b7 lui a5,0x7ff00 + 8664: 17fd addi a5,a5,-1 + 8666: 00f41563 bne s0,a5,8670 <_strtod_l+0x988> + 866a: 57fd li a5,-1 + 866c: bef480e3 beq s1,a5,824c <_strtod_l+0x564> + 8670: 7ff005b7 lui a1,0x7ff00 + 8674: 8de1 and a1,a1,s0 + 8676: 00100437 lui s0,0x100 + 867a: 942e add s0,s0,a1 + 867c: 4481 li s1,0 + 867e: f20a1ce3 bnez s4,85b6 <_strtod_l+0x8ce> + 8682: bef9 j 8260 <_strtod_l+0x578> + 8684: 8fc5 or a5,a5,s1 + 8686: db99 beqz a5,859c <_strtod_l+0x8b4> + 8688: 040c8263 beqz s9,86cc <_strtod_l+0x9e4> + 868c: 008cfcb3 and s9,s9,s0 + 8690: fe0c87e3 beqz s9,867e <_strtod_l+0x996> + 8694: 8652 mv a2,s4 + 8696: 8526 mv a0,s1 + 8698: 85a2 mv a1,s0 + 869a: 020c0f63 beqz s8,86d8 <_strtod_l+0x9f0> + 869e: dfcff0ef jal ra,7c9a + 86a2: 862a mv a2,a0 + 86a4: 86ae mv a3,a1 + 86a6: 4552 lw a0,20(sp) + 86a8: 45e2 lw a1,24(sp) + 86aa: b9efc0ef jal ra,4a48 <__adddf3> + 86ae: 84aa mv s1,a0 + 86b0: 842e mv s0,a1 + 86b2: b7f1 j 867e <_strtod_l+0x996> + 86b4: 7ff005b7 lui a1,0x7ff00 + 86b8: 8de1 and a1,a1,s0 + 86ba: fff00437 lui s0,0xfff00 + 86be: 95a2 add a1,a1,s0 + 86c0: 00100437 lui s0,0x100 + 86c4: 147d addi s0,s0,-1 + 86c6: 8c4d or s0,s0,a1 + 86c8: 54fd li s1,-1 + 86ca: bf55 j 867e <_strtod_l+0x996> + 86cc: 5792 lw a5,36(sp) + 86ce: 0097fdb3 and s11,a5,s1 + 86d2: fa0d86e3 beqz s11,867e <_strtod_l+0x996> + 86d6: bf7d j 8694 <_strtod_l+0x9ac> + 86d8: dc2ff0ef jal ra,7c9a + 86dc: 862a mv a2,a0 + 86de: 86ae mv a3,a1 + 86e0: 4552 lw a0,20(sp) + 86e2: 45e2 lw a1,24(sp) + 86e4: ecefd0ef jal ra,5db2 <__subdf3> + 86e8: 4601 li a2,0 + 86ea: 4681 li a3,0 + 86ec: 84aa mv s1,a0 + 86ee: 842e mv s0,a1 + 86f0: 83cfd0ef jal ra,572c <__eqdf2> + 86f4: f549 bnez a0,867e <_strtod_l+0x996> + 86f6: b19d j 835c <_strtod_l+0x674> + 86f8: 85ce mv a1,s3 + 86fa: 855a mv a0,s6 + 86fc: 0df020ef jal ra,afda <__ratio> + 8700: 00004797 auipc a5,0x4 + 8704: 05878793 addi a5,a5,88 # c758 <__clz_tab+0x1c8> + 8708: 4390 lw a2,0(a5) + 870a: 43d4 lw a3,4(a5) + 870c: 8d2a mv s10,a0 + 870e: 8dae mv s11,a1 + 8710: 934fd0ef jal ra,5844 <__ledf2> + 8714: 10a04263 bgtz a0,8818 <_strtod_l+0xb30> + 8718: 0a0c0163 beqz s8,87ba <_strtod_l+0xad2> + 871c: 4d81 li s11,0 + 871e: 3ff00d37 lui s10,0x3ff00 + 8722: 4701 li a4,0 + 8724: 3ff007b7 lui a5,0x3ff00 + 8728: 7ff006b7 lui a3,0x7ff00 + 872c: 00d47cb3 and s9,s0,a3 + 8730: 7fe006b7 lui a3,0x7fe00 + 8734: 16dc9f63 bne s9,a3,88b2 <_strtod_l+0xbca> + 8738: d26a sw s10,36(sp) + 873a: fcb00d37 lui s10,0xfcb00 + 873e: 9d22 add s10,s10,s0 + 8740: 8526 mv a0,s1 + 8742: 85ea mv a1,s10 + 8744: de3e sw a5,60(sp) + 8746: dc3a sw a4,56(sp) + 8748: da6e sw s11,52(sp) + 874a: 6c2020ef jal ra,ae0c <__ulp> + 874e: 58d2 lw a7,52(sp) + 8750: 5812 lw a6,36(sp) + 8752: 862a mv a2,a0 + 8754: 86ae mv a3,a1 + 8756: 8546 mv a0,a7 + 8758: 85c2 mv a1,a6 + 875a: 9a0fd0ef jal ra,58fa <__muldf3> + 875e: 8626 mv a2,s1 + 8760: 86ea mv a3,s10 + 8762: ae6fc0ef jal ra,4a48 <__adddf3> + 8766: 84aa mv s1,a0 + 8768: 7ff00537 lui a0,0x7ff00 + 876c: 00b57633 and a2,a0,a1 + 8770: 7ca006b7 lui a3,0x7ca00 + 8774: 5762 lw a4,56(sp) + 8776: 57f2 lw a5,60(sp) + 8778: 0cd66563 bltu a2,a3,8842 <_strtod_l+0xb5a> + 877c: 4762 lw a4,24(sp) + 877e: fff50793 addi a5,a0,-1 # 7fefffff <_eusrstack+0x5feeffff> + 8782: 00e79663 bne a5,a4,878e <_strtod_l+0xaa6> + 8786: 4752 lw a4,20(sp) + 8788: 57fd li a5,-1 + 878a: ace781e3 beq a5,a4,824c <_strtod_l+0x564> + 878e: 7ff007b7 lui a5,0x7ff00 + 8792: fff78413 addi s0,a5,-1 # 7fefffff <_eusrstack+0x5feeffff> + 8796: 54fd li s1,-1 + 8798: 45c6 lw a1,80(sp) + 879a: 854a mv a0,s2 + 879c: 02e020ef jal ra,a7ca <_Bfree> + 87a0: 85de mv a1,s7 + 87a2: 854a mv a0,s2 + 87a4: 026020ef jal ra,a7ca <_Bfree> + 87a8: 85ce mv a1,s3 + 87aa: 854a mv a0,s2 + 87ac: 01e020ef jal ra,a7ca <_Bfree> + 87b0: 85da mv a1,s6 + 87b2: 854a mv a0,s2 + 87b4: 016020ef jal ra,a7ca <_Bfree> + 87b8: b195 j 841c <_strtod_l+0x734> + 87ba: e0b1 bnez s1,87fe <_strtod_l+0xb16> + 87bc: 57b2 lw a5,44(sp) + 87be: 8fe1 and a5,a5,s0 + 87c0: e7a1 bnez a5,8808 <_strtod_l+0xb20> + 87c2: 00004797 auipc a5,0x4 + 87c6: f8e78793 addi a5,a5,-114 # c750 <__clz_tab+0x1c0> + 87ca: 4390 lw a2,0(a5) + 87cc: 43d4 lw a3,4(a5) + 87ce: 856a mv a0,s10 + 87d0: 85ee mv a1,s11 + 87d2: 872fd0ef jal ra,5844 <__ledf2> + 87d6: 02054d63 bltz a0,8810 <_strtod_l+0xb28> + 87da: 00004797 auipc a5,0x4 + 87de: f6e78793 addi a5,a5,-146 # c748 <__clz_tab+0x1b8> + 87e2: 4390 lw a2,0(a5) + 87e4: 43d4 lw a3,4(a5) + 87e6: 856a mv a0,s10 + 87e8: 85ee mv a1,s11 + 87ea: 910fd0ef jal ra,58fa <__muldf3> + 87ee: 872a mv a4,a0 + 87f0: 87ae mv a5,a1 + 87f2: 80000d37 lui s10,0x80000 + 87f6: 8dba mv s11,a4 + 87f8: 00fd4d33 xor s10,s10,a5 + 87fc: b735 j 8728 <_strtod_l+0xa40> + 87fe: 4785 li a5,1 + 8800: 00f49463 bne s1,a5,8808 <_strtod_l+0xb20> + 8804: b4040ce3 beqz s0,835c <_strtod_l+0x674> + 8808: 4d81 li s11,0 + 880a: bff00d37 lui s10,0xbff00 + 880e: bf11 j 8722 <_strtod_l+0xa3a> + 8810: 4701 li a4,0 + 8812: 3fe007b7 lui a5,0x3fe00 + 8816: bff1 j 87f2 <_strtod_l+0xb0a> + 8818: 00004797 auipc a5,0x4 + 881c: f3078793 addi a5,a5,-208 # c748 <__clz_tab+0x1b8> + 8820: 4390 lw a2,0(a5) + 8822: 43d4 lw a3,4(a5) + 8824: 856a mv a0,s10 + 8826: 85ee mv a1,s11 + 8828: 8d2fd0ef jal ra,58fa <__muldf3> + 882c: 872a mv a4,a0 + 882e: 87ae mv a5,a1 + 8830: 8d2e mv s10,a1 + 8832: 000c1663 bnez s8,883e <_strtod_l+0xb56> + 8836: 80000d37 lui s10,0x80000 + 883a: 00bd4d33 xor s10,s10,a1 + 883e: 8daa mv s11,a0 + 8840: b5e5 j 8728 <_strtod_l+0xa40> + 8842: 03500437 lui s0,0x3500 + 8846: 942e add s0,s0,a1 + 8848: f40a18e3 bnez s4,8798 <_strtod_l+0xab0> + 884c: 7ff006b7 lui a3,0x7ff00 + 8850: 8ee1 and a3,a3,s0 + 8852: f4dc93e3 bne s9,a3,8798 <_strtod_l+0xab0> + 8856: 85be mv a1,a5 + 8858: 853a mv a0,a4 + 885a: 8d3a mv s10,a4 + 885c: 8cbe mv s9,a5 + 885e: c8ffd0ef jal ra,64ec <__fixdfsi> + 8862: cf3fd0ef jal ra,6554 <__floatsidf> + 8866: 862a mv a2,a0 + 8868: 86ae mv a3,a1 + 886a: 856a mv a0,s10 + 886c: 85e6 mv a1,s9 + 886e: d44fd0ef jal ra,5db2 <__subdf3> + 8872: 57b2 lw a5,44(sp) + 8874: 8d2a mv s10,a0 + 8876: 8dae mv s11,a1 + 8878: 8fe1 and a5,a5,s0 + 887a: 8fc5 or a5,a5,s1 + 887c: 0187ec33 or s8,a5,s8 + 8880: 0a0c0b63 beqz s8,8936 <_strtod_l+0xc4e> + 8884: 00004797 auipc a5,0x4 + 8888: ee478793 addi a5,a5,-284 # c768 <__clz_tab+0x1d8> + 888c: 4390 lw a2,0(a5) + 888e: 43d4 lw a3,4(a5) + 8890: fb5fc0ef jal ra,5844 <__ledf2> + 8894: 9c0546e3 bltz a0,8260 <_strtod_l+0x578> + 8898: 00004797 auipc a5,0x4 + 889c: ed878793 addi a5,a5,-296 # c770 <__clz_tab+0x1e0> + 88a0: 4390 lw a2,0(a5) + 88a2: 43d4 lw a3,4(a5) + 88a4: 856a mv a0,s10 + 88a6: 85ee mv a1,s11 + 88a8: eeffc0ef jal ra,5796 <__gedf2> + 88ac: eea056e3 blez a0,8798 <_strtod_l+0xab0> + 88b0: ba45 j 8260 <_strtod_l+0x578> + 88b2: 040a0d63 beqz s4,890c <_strtod_l+0xc24> + 88b6: 06a006b7 lui a3,0x6a00 + 88ba: 0596e963 bltu a3,s9,890c <_strtod_l+0xc24> + 88be: 00004697 auipc a3,0x4 + 88c2: ea268693 addi a3,a3,-350 # c760 <__clz_tab+0x1d0> + 88c6: 4290 lw a2,0(a3) + 88c8: 42d4 lw a3,4(a3) + 88ca: 853a mv a0,a4 + 88cc: 85be mv a1,a5 + 88ce: da3a sw a4,52(sp) + 88d0: d23e sw a5,36(sp) + 88d2: f73fc0ef jal ra,5844 <__ledf2> + 88d6: 5792 lw a5,36(sp) + 88d8: 5752 lw a4,52(sp) + 88da: 02a04463 bgtz a0,8902 <_strtod_l+0xc1a> + 88de: 853a mv a0,a4 + 88e0: 85be mv a1,a5 + 88e2: 136030ef jal ra,ba18 <__fixunsdfsi> + 88e6: e111 bnez a0,88ea <_strtod_l+0xc02> + 88e8: 4505 li a0,1 + 88ea: cdbfd0ef jal ra,65c4 <__floatunsidf> + 88ee: 872a mv a4,a0 + 88f0: 87ae mv a5,a1 + 88f2: 8d2e mv s10,a1 + 88f4: 000c1663 bnez s8,8900 <_strtod_l+0xc18> + 88f8: 80000d37 lui s10,0x80000 + 88fc: 00bd4d33 xor s10,s10,a1 + 8900: 8daa mv s11,a0 + 8902: 06b005b7 lui a1,0x6b00 + 8906: 9d2e add s10,s10,a1 + 8908: 419d0d33 sub s10,s10,s9 + 890c: 4552 lw a0,20(sp) + 890e: 45e2 lw a1,24(sp) + 8910: da3e sw a5,52(sp) + 8912: d23a sw a4,36(sp) + 8914: 4f8020ef jal ra,ae0c <__ulp> + 8918: 862a mv a2,a0 + 891a: 86ae mv a3,a1 + 891c: 856e mv a0,s11 + 891e: 85ea mv a1,s10 + 8920: fdbfc0ef jal ra,58fa <__muldf3> + 8924: 4652 lw a2,20(sp) + 8926: 46e2 lw a3,24(sp) + 8928: 920fc0ef jal ra,4a48 <__adddf3> + 892c: 84aa mv s1,a0 + 892e: 842e mv s0,a1 + 8930: 57d2 lw a5,52(sp) + 8932: 5712 lw a4,36(sp) + 8934: bf11 j 8848 <_strtod_l+0xb60> + 8936: 00004797 auipc a5,0x4 + 893a: e4278793 addi a5,a5,-446 # c778 <__clz_tab+0x1e8> + 893e: 4390 lw a2,0(a5) + 8940: 43d4 lw a3,4(a5) + 8942: f03fc0ef jal ra,5844 <__ledf2> + 8946: e40559e3 bgez a0,8798 <_strtod_l+0xab0> + 894a: ba19 j 8260 <_strtod_l+0x578> + 894c: 06500713 li a4,101 + 8950: 00e78763 beq a5,a4,895e <_strtod_l+0xc76> + 8954: 04500713 li a4,69 + 8958: 4505 li a0,1 + 895a: eee79763 bne a5,a4,8048 <_strtod_l+0x360> + 895e: 4b01 li s6,0 + 8960: 4505 li a0,1 + 8962: d78ff06f j 7eda <_strtod_l+0x1f2> + +00008966 <_strtod_r>: + 8966: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 896a: 439c lw a5,0(a5) + 896c: 5394 lw a3,32(a5) + 896e: e689 bnez a3,8978 <_strtod_r+0x12> + 8970: 1fff7697 auipc a3,0x1fff7 + 8974: 70068693 addi a3,a3,1792 # 20000070 <__global_locale> + 8978: b70ff06f j 7ce8 <_strtod_l> + +0000897c : + 897c: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 8980: 439c lw a5,0(a5) + 8982: 862e mv a2,a1 + 8984: 5394 lw a3,32(a5) + 8986: e689 bnez a3,8990 + 8988: 1fff7697 auipc a3,0x1fff7 + 898c: 6e868693 addi a3,a3,1768 # 20000070 <__global_locale> + 8990: 85aa mv a1,a0 + 8992: 853e mv a0,a5 + 8994: b54ff06f j 7ce8 <_strtod_l> + +00008998 <_strtol_l.isra.0>: + 8998: 7179 addi sp,sp,-48 + 899a: d04a sw s2,32(sp) + 899c: ce4e sw s3,28(sp) + 899e: d606 sw ra,44(sp) + 89a0: d422 sw s0,40(sp) + 89a2: d226 sw s1,36(sp) + 89a4: 89aa mv s3,a0 + 89a6: 892e mv s2,a1 + 89a8: 00190493 addi s1,s2,1 + 89ac: fff4c403 lbu s0,-1(s1) + 89b0: 853a mv a0,a4 + 89b2: c636 sw a3,12(sp) + 89b4: c432 sw a2,8(sp) + 89b6: c22e sw a1,4(sp) + 89b8: c03a sw a4,0(sp) + 89ba: 405010ef jal ra,a5be <__locale_ctype_ptr_l> + 89be: 9522 add a0,a0,s0 + 89c0: 00154783 lbu a5,1(a0) + 89c4: 4702 lw a4,0(sp) + 89c6: 4592 lw a1,4(sp) + 89c8: 8ba1 andi a5,a5,8 + 89ca: 4622 lw a2,8(sp) + 89cc: 46b2 lw a3,12(sp) + 89ce: e7c9 bnez a5,8a58 <_strtol_l.isra.0+0xc0> + 89d0: 02d00793 li a5,45 + 89d4: 08f41463 bne s0,a5,8a5c <_strtol_l.isra.0+0xc4> + 89d8: 0004c783 lbu a5,0(s1) + 89dc: 4305 li t1,1 + 89de: 00290493 addi s1,s2,2 + 89e2: c6fd beqz a3,8ad0 <_strtol_l.isra.0+0x138> + 89e4: 4741 li a4,16 + 89e6: 02e69263 bne a3,a4,8a0a <_strtol_l.isra.0+0x72> + 89ea: 03000713 li a4,48 + 89ee: 00e79e63 bne a5,a4,8a0a <_strtol_l.isra.0+0x72> + 89f2: 0004c783 lbu a5,0(s1) + 89f6: 05800713 li a4,88 + 89fa: 0df7f793 andi a5,a5,223 + 89fe: 0ce79463 bne a5,a4,8ac6 <_strtol_l.isra.0+0x12e> + 8a02: 0014c783 lbu a5,1(s1) + 8a06: 46c1 li a3,16 + 8a08: 0489 addi s1,s1,2 + 8a0a: 800008b7 lui a7,0x80000 + 8a0e: 00031463 bnez t1,8a16 <_strtol_l.isra.0+0x7e> + 8a12: fff8c893 not a7,a7 + 8a16: 02d8ff33 remu t5,a7,a3 + 8a1a: 4801 li a6,0 + 8a1c: 4501 li a0,0 + 8a1e: 4fa5 li t6,9 + 8a20: 4ee5 li t4,25 + 8a22: 52fd li t0,-1 + 8a24: 02d8de33 divu t3,a7,a3 + 8a28: fd078713 addi a4,a5,-48 + 8a2c: 04efe463 bltu t6,a4,8a74 <_strtol_l.isra.0+0xdc> + 8a30: 87ba mv a5,a4 + 8a32: 04d7df63 bge a5,a3,8a90 <_strtol_l.isra.0+0xf8> + 8a36: 00580d63 beq a6,t0,8a50 <_strtol_l.isra.0+0xb8> + 8a3a: 587d li a6,-1 + 8a3c: 00ae6a63 bltu t3,a0,8a50 <_strtol_l.isra.0+0xb8> + 8a40: 00ae1463 bne t3,a0,8a48 <_strtol_l.isra.0+0xb0> + 8a44: 00ff4663 blt t5,a5,8a50 <_strtol_l.isra.0+0xb8> + 8a48: 4805 li a6,1 + 8a4a: 02a68533 mul a0,a3,a0 + 8a4e: 953e add a0,a0,a5 + 8a50: 0485 addi s1,s1,1 + 8a52: fff4c783 lbu a5,-1(s1) + 8a56: bfc9 j 8a28 <_strtol_l.isra.0+0x90> + 8a58: 8926 mv s2,s1 + 8a5a: b7b9 j 89a8 <_strtol_l.isra.0+0x10> + 8a5c: 02b00793 li a5,43 + 8a60: 00f40563 beq s0,a5,8a6a <_strtol_l.isra.0+0xd2> + 8a64: 87a2 mv a5,s0 + 8a66: 4301 li t1,0 + 8a68: bfad j 89e2 <_strtol_l.isra.0+0x4a> + 8a6a: 0004c783 lbu a5,0(s1) + 8a6e: 00290493 addi s1,s2,2 + 8a72: bfd5 j 8a66 <_strtol_l.isra.0+0xce> + 8a74: fbf78713 addi a4,a5,-65 + 8a78: 00eee563 bltu t4,a4,8a82 <_strtol_l.isra.0+0xea> + 8a7c: fc978793 addi a5,a5,-55 + 8a80: bf4d j 8a32 <_strtol_l.isra.0+0x9a> + 8a82: f9f78713 addi a4,a5,-97 + 8a86: 00eee563 bltu t4,a4,8a90 <_strtol_l.isra.0+0xf8> + 8a8a: fa978793 addi a5,a5,-87 + 8a8e: b755 j 8a32 <_strtol_l.isra.0+0x9a> + 8a90: 57fd li a5,-1 + 8a92: 00f81f63 bne a6,a5,8ab0 <_strtol_l.isra.0+0x118> + 8a96: 02200793 li a5,34 + 8a9a: 00f9a023 sw a5,0(s3) + 8a9e: 8546 mv a0,a7 + 8aa0: ee19 bnez a2,8abe <_strtol_l.isra.0+0x126> + 8aa2: 50b2 lw ra,44(sp) + 8aa4: 5422 lw s0,40(sp) + 8aa6: 5492 lw s1,36(sp) + 8aa8: 5902 lw s2,32(sp) + 8aaa: 49f2 lw s3,28(sp) + 8aac: 6145 addi sp,sp,48 + 8aae: 8082 ret + 8ab0: 00030463 beqz t1,8ab8 <_strtol_l.isra.0+0x120> + 8ab4: 40a00533 neg a0,a0 + 8ab8: d66d beqz a2,8aa2 <_strtol_l.isra.0+0x10a> + 8aba: 00080463 beqz a6,8ac2 <_strtol_l.isra.0+0x12a> + 8abe: fff48593 addi a1,s1,-1 + 8ac2: c20c sw a1,0(a2) + 8ac4: bff9 j 8aa2 <_strtol_l.isra.0+0x10a> + 8ac6: 03000793 li a5,48 + 8aca: f2a1 bnez a3,8a0a <_strtol_l.isra.0+0x72> + 8acc: 46a1 li a3,8 + 8ace: bf35 j 8a0a <_strtol_l.isra.0+0x72> + 8ad0: 03000713 li a4,48 + 8ad4: f0e78fe3 beq a5,a4,89f2 <_strtol_l.isra.0+0x5a> + 8ad8: 46a9 li a3,10 + 8ada: bf05 j 8a0a <_strtol_l.isra.0+0x72> + +00008adc <_strtol_r>: + 8adc: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 8ae0: 439c lw a5,0(a5) + 8ae2: 5398 lw a4,32(a5) + 8ae4: e709 bnez a4,8aee <_strtol_r+0x12> + 8ae6: 1fff7717 auipc a4,0x1fff7 + 8aea: 58a70713 addi a4,a4,1418 # 20000070 <__global_locale> + 8aee: eabff06f j 8998 <_strtol_l.isra.0> + +00008af2 <_vsniprintf_r>: + 8af2: 7119 addi sp,sp,-128 + 8af4: dca2 sw s0,120(sp) + 8af6: de86 sw ra,124(sp) + 8af8: daa6 sw s1,116(sp) + 8afa: 8432 mv s0,a2 + 8afc: 00065b63 bgez a2,8b12 <_vsniprintf_r+0x20> + 8b00: 08b00793 li a5,139 + 8b04: c11c sw a5,0(a0) + 8b06: 557d li a0,-1 + 8b08: 50f6 lw ra,124(sp) + 8b0a: 5466 lw s0,120(sp) + 8b0c: 54d6 lw s1,116(sp) + 8b0e: 6109 addi sp,sp,128 + 8b10: 8082 ret + 8b12: 8636 mv a2,a3 + 8b14: 20800693 li a3,520 + 8b18: c42e sw a1,8(sp) + 8b1a: cc2e sw a1,24(sp) + 8b1c: 00d11a23 sh a3,20(sp) + 8b20: 4581 li a1,0 + 8b22: c019 beqz s0,8b28 <_vsniprintf_r+0x36> + 8b24: fff40593 addi a1,s0,-1 # 34fffff <_data_lma+0x34f3567> + 8b28: 57fd li a5,-1 + 8b2a: c82e sw a1,16(sp) + 8b2c: ce2e sw a1,28(sp) + 8b2e: 86ba mv a3,a4 + 8b30: 002c addi a1,sp,8 + 8b32: 00f11b23 sh a5,22(sp) + 8b36: 84aa mv s1,a0 + 8b38: 07b020ef jal ra,b3b2 <_svfiprintf_r> + 8b3c: 57fd li a5,-1 + 8b3e: 00f55563 bge a0,a5,8b48 <_vsniprintf_r+0x56> + 8b42: 08b00793 li a5,139 + 8b46: c09c sw a5,0(s1) + 8b48: d061 beqz s0,8b08 <_vsniprintf_r+0x16> + 8b4a: 47a2 lw a5,8(sp) + 8b4c: 00078023 sb zero,0(a5) + 8b50: bf65 j 8b08 <_vsniprintf_r+0x16> + +00008b52 : + 8b52: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 8b56: 8736 mv a4,a3 + 8b58: 86b2 mv a3,a2 + 8b5a: 862e mv a2,a1 + 8b5c: 85aa mv a1,a0 + 8b5e: 4388 lw a0,0(a5) + 8b60: f93ff06f j 8af2 <_vsniprintf_r> + +00008b64 <__swbuf_r>: + 8b64: 1101 addi sp,sp,-32 + 8b66: cc22 sw s0,24(sp) + 8b68: ca26 sw s1,20(sp) + 8b6a: c84a sw s2,16(sp) + 8b6c: ce06 sw ra,28(sp) + 8b6e: c64e sw s3,12(sp) + 8b70: 84aa mv s1,a0 + 8b72: 892e mv s2,a1 + 8b74: 8432 mv s0,a2 + 8b76: c509 beqz a0,8b80 <__swbuf_r+0x1c> + 8b78: 4d1c lw a5,24(a0) + 8b7a: e399 bnez a5,8b80 <__swbuf_r+0x1c> + 8b7c: 18a010ef jal ra,9d06 <__sinit> + 8b80: 00004797 auipc a5,0x4 + 8b84: cc878793 addi a5,a5,-824 # c848 <__sf_fake_stdin> + 8b88: 06f41b63 bne s0,a5,8bfe <__swbuf_r+0x9a> + 8b8c: 40c0 lw s0,4(s1) + 8b8e: 4c1c lw a5,24(s0) + 8b90: c41c sw a5,8(s0) + 8b92: 00c45783 lhu a5,12(s0) + 8b96: 8ba1 andi a5,a5,8 + 8b98: c3d9 beqz a5,8c1e <__swbuf_r+0xba> + 8b9a: 481c lw a5,16(s0) + 8b9c: c3c9 beqz a5,8c1e <__swbuf_r+0xba> + 8b9e: 481c lw a5,16(s0) + 8ba0: 4008 lw a0,0(s0) + 8ba2: 0ff97993 andi s3,s2,255 + 8ba6: 0ff97913 andi s2,s2,255 + 8baa: 8d1d sub a0,a0,a5 + 8bac: 485c lw a5,20(s0) + 8bae: 00f54763 blt a0,a5,8bbc <__swbuf_r+0x58> + 8bb2: 85a2 mv a1,s0 + 8bb4: 8526 mv a0,s1 + 8bb6: 02e010ef jal ra,9be4 <_fflush_r> + 8bba: e535 bnez a0,8c26 <__swbuf_r+0xc2> + 8bbc: 441c lw a5,8(s0) + 8bbe: 0505 addi a0,a0,1 + 8bc0: 17fd addi a5,a5,-1 + 8bc2: c41c sw a5,8(s0) + 8bc4: 401c lw a5,0(s0) + 8bc6: 00178713 addi a4,a5,1 + 8bca: c018 sw a4,0(s0) + 8bcc: 01378023 sb s3,0(a5) + 8bd0: 485c lw a5,20(s0) + 8bd2: 00a78963 beq a5,a0,8be4 <__swbuf_r+0x80> + 8bd6: 00c45783 lhu a5,12(s0) + 8bda: 8b85 andi a5,a5,1 + 8bdc: cb89 beqz a5,8bee <__swbuf_r+0x8a> + 8bde: 47a9 li a5,10 + 8be0: 00f91763 bne s2,a5,8bee <__swbuf_r+0x8a> + 8be4: 85a2 mv a1,s0 + 8be6: 8526 mv a0,s1 + 8be8: 7fd000ef jal ra,9be4 <_fflush_r> + 8bec: ed0d bnez a0,8c26 <__swbuf_r+0xc2> + 8bee: 40f2 lw ra,28(sp) + 8bf0: 4462 lw s0,24(sp) + 8bf2: 854a mv a0,s2 + 8bf4: 44d2 lw s1,20(sp) + 8bf6: 4942 lw s2,16(sp) + 8bf8: 49b2 lw s3,12(sp) + 8bfa: 6105 addi sp,sp,32 + 8bfc: 8082 ret + 8bfe: 00004797 auipc a5,0x4 + 8c02: c6a78793 addi a5,a5,-918 # c868 <__sf_fake_stdout> + 8c06: 00f41463 bne s0,a5,8c0e <__swbuf_r+0xaa> + 8c0a: 4480 lw s0,8(s1) + 8c0c: b749 j 8b8e <__swbuf_r+0x2a> + 8c0e: 00004797 auipc a5,0x4 + 8c12: c1a78793 addi a5,a5,-998 # c828 <__sf_fake_stderr> + 8c16: f6f41ce3 bne s0,a5,8b8e <__swbuf_r+0x2a> + 8c1a: 44c0 lw s0,12(s1) + 8c1c: bf8d j 8b8e <__swbuf_r+0x2a> + 8c1e: 85a2 mv a1,s0 + 8c20: 8526 mv a0,s1 + 8c22: 2021 jal 8c2a <__swsetup_r> + 8c24: dd2d beqz a0,8b9e <__swbuf_r+0x3a> + 8c26: 597d li s2,-1 + 8c28: b7d9 j 8bee <__swbuf_r+0x8a> + +00008c2a <__swsetup_r>: + 8c2a: 1141 addi sp,sp,-16 + 8c2c: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + 8c30: c226 sw s1,4(sp) + 8c32: 4384 lw s1,0(a5) + 8c34: c422 sw s0,8(sp) + 8c36: c04a sw s2,0(sp) + 8c38: c606 sw ra,12(sp) + 8c3a: 892a mv s2,a0 + 8c3c: 842e mv s0,a1 + 8c3e: c491 beqz s1,8c4a <__swsetup_r+0x20> + 8c40: 4c9c lw a5,24(s1) + 8c42: e781 bnez a5,8c4a <__swsetup_r+0x20> + 8c44: 8526 mv a0,s1 + 8c46: 0c0010ef jal ra,9d06 <__sinit> + 8c4a: 00004797 auipc a5,0x4 + 8c4e: bfe78793 addi a5,a5,-1026 # c848 <__sf_fake_stdin> + 8c52: 02f41c63 bne s0,a5,8c8a <__swsetup_r+0x60> + 8c56: 40c0 lw s0,4(s1) + 8c58: 00c41703 lh a4,12(s0) + 8c5c: 01071793 slli a5,a4,0x10 + 8c60: 83c1 srli a5,a5,0x10 + 8c62: 0087f693 andi a3,a5,8 + 8c66: eebd bnez a3,8ce4 <__swsetup_r+0xba> + 8c68: 0107f693 andi a3,a5,16 + 8c6c: ee9d bnez a3,8caa <__swsetup_r+0x80> + 8c6e: 47a5 li a5,9 + 8c70: 00f92023 sw a5,0(s2) + 8c74: 04076713 ori a4,a4,64 + 8c78: 00e41623 sh a4,12(s0) + 8c7c: 557d li a0,-1 + 8c7e: 40b2 lw ra,12(sp) + 8c80: 4422 lw s0,8(sp) + 8c82: 4492 lw s1,4(sp) + 8c84: 4902 lw s2,0(sp) + 8c86: 0141 addi sp,sp,16 + 8c88: 8082 ret + 8c8a: 00004797 auipc a5,0x4 + 8c8e: bde78793 addi a5,a5,-1058 # c868 <__sf_fake_stdout> + 8c92: 00f41463 bne s0,a5,8c9a <__swsetup_r+0x70> + 8c96: 4480 lw s0,8(s1) + 8c98: b7c1 j 8c58 <__swsetup_r+0x2e> + 8c9a: 00004797 auipc a5,0x4 + 8c9e: b8e78793 addi a5,a5,-1138 # c828 <__sf_fake_stderr> + 8ca2: faf41be3 bne s0,a5,8c58 <__swsetup_r+0x2e> + 8ca6: 44c0 lw s0,12(s1) + 8ca8: bf45 j 8c58 <__swsetup_r+0x2e> + 8caa: 8b91 andi a5,a5,4 + 8cac: c795 beqz a5,8cd8 <__swsetup_r+0xae> + 8cae: 584c lw a1,52(s0) + 8cb0: c991 beqz a1,8cc4 <__swsetup_r+0x9a> + 8cb2: 04440793 addi a5,s0,68 + 8cb6: 00f58563 beq a1,a5,8cc0 <__swsetup_r+0x96> + 8cba: 854a mv a0,s2 + 8cbc: 434020ef jal ra,b0f0 <_free_r> + 8cc0: 02042a23 sw zero,52(s0) + 8cc4: 00c45783 lhu a5,12(s0) + 8cc8: 00042223 sw zero,4(s0) + 8ccc: fdb7f793 andi a5,a5,-37 + 8cd0: 00f41623 sh a5,12(s0) + 8cd4: 481c lw a5,16(s0) + 8cd6: c01c sw a5,0(s0) + 8cd8: 00c45783 lhu a5,12(s0) + 8cdc: 0087e793 ori a5,a5,8 + 8ce0: 00f41623 sh a5,12(s0) + 8ce4: 481c lw a5,16(s0) + 8ce6: ef89 bnez a5,8d00 <__swsetup_r+0xd6> + 8ce8: 00c45783 lhu a5,12(s0) + 8cec: 20000713 li a4,512 + 8cf0: 2807f793 andi a5,a5,640 + 8cf4: 00e78663 beq a5,a4,8d00 <__swsetup_r+0xd6> + 8cf8: 85a2 mv a1,s0 + 8cfa: 854a mv a0,s2 + 8cfc: 141010ef jal ra,a63c <__smakebuf_r> + 8d00: 00c45783 lhu a5,12(s0) + 8d04: 0017f713 andi a4,a5,1 + 8d08: c705 beqz a4,8d30 <__swsetup_r+0x106> + 8d0a: 485c lw a5,20(s0) + 8d0c: 00042423 sw zero,8(s0) + 8d10: 40f007b3 neg a5,a5 + 8d14: cc1c sw a5,24(s0) + 8d16: 481c lw a5,16(s0) + 8d18: 4501 li a0,0 + 8d1a: f3b5 bnez a5,8c7e <__swsetup_r+0x54> + 8d1c: 00c41783 lh a5,12(s0) + 8d20: 0807f713 andi a4,a5,128 + 8d24: df29 beqz a4,8c7e <__swsetup_r+0x54> + 8d26: 0407e793 ori a5,a5,64 + 8d2a: 00f41623 sh a5,12(s0) + 8d2e: b7b9 j 8c7c <__swsetup_r+0x52> + 8d30: 8b89 andi a5,a5,2 + 8d32: 4701 li a4,0 + 8d34: e391 bnez a5,8d38 <__swsetup_r+0x10e> + 8d36: 4858 lw a4,20(s0) + 8d38: c418 sw a4,8(s0) + 8d3a: bff1 j 8d16 <__swsetup_r+0xec> + +00008d3c : + 8d3c: 1141 addi sp,sp,-16 + 8d3e: 4519 li a0,6 + 8d40: c606 sw ra,12(sp) + 8d42: 209020ef jal ra,b74a + 8d46: 4505 li a0,1 + 8d48: 2c8030ef jal ra,c010 <_exit> + +00008d4c : + 8d4c: 1101 addi sp,sp,-32 + 8d4e: cc22 sw s0,24(sp) + 8d50: 491c lw a5,16(a0) + 8d52: 4980 lw s0,16(a1) + 8d54: ce06 sw ra,28(sp) + 8d56: ca26 sw s1,20(sp) + 8d58: c84a sw s2,16(sp) + 8d5a: c64e sw s3,12(sp) + 8d5c: c452 sw s4,8(sp) + 8d5e: c256 sw s5,4(sp) + 8d60: 1287c163 blt a5,s0,8e82 + 8d64: 147d addi s0,s0,-1 + 8d66: 00241813 slli a6,s0,0x2 + 8d6a: 01458993 addi s3,a1,20 # 6b00014 <_data_lma+0x6af357c> + 8d6e: 01098a33 add s4,s3,a6 + 8d72: 01450913 addi s2,a0,20 + 8d76: 984a add a6,a6,s2 + 8d78: 000a2783 lw a5,0(s4) + 8d7c: 00082703 lw a4,0(a6) + 8d80: 0785 addi a5,a5,1 + 8d82: 02f754b3 divu s1,a4,a5 + 8d86: 06f76663 bltu a4,a5,8df2 + 8d8a: 68c1 lui a7,0x10 + 8d8c: 834e mv t1,s3 + 8d8e: 8e4a mv t3,s2 + 8d90: 4e81 li t4,0 + 8d92: 4f01 li t5,0 + 8d94: 18fd addi a7,a7,-1 + 8d96: 0311 addi t1,t1,4 + 8d98: ffc32603 lw a2,-4(t1) + 8d9c: 0e11 addi t3,t3,4 + 8d9e: 01167733 and a4,a2,a7 + 8da2: 8241 srli a2,a2,0x10 + 8da4: 02970733 mul a4,a4,s1 + 8da8: 02960633 mul a2,a2,s1 + 8dac: 9776 add a4,a4,t4 + 8dae: 01075693 srli a3,a4,0x10 + 8db2: 011777b3 and a5,a4,a7 + 8db6: 40ff07b3 sub a5,t5,a5 + 8dba: 9636 add a2,a2,a3 + 8dbc: ffce2683 lw a3,-4(t3) + 8dc0: 01065e93 srli t4,a2,0x10 + 8dc4: 01167633 and a2,a2,a7 + 8dc8: 0116f733 and a4,a3,a7 + 8dcc: 97ba add a5,a5,a4 + 8dce: 82c1 srli a3,a3,0x10 + 8dd0: 4107d713 srai a4,a5,0x10 + 8dd4: 8e91 sub a3,a3,a2 + 8dd6: 96ba add a3,a3,a4 + 8dd8: 4106df13 srai t5,a3,0x10 + 8ddc: 0117f7b3 and a5,a5,a7 + 8de0: 06c2 slli a3,a3,0x10 + 8de2: 8fd5 or a5,a5,a3 + 8de4: fefe2e23 sw a5,-4(t3) + 8de8: fa6a77e3 bgeu s4,t1,8d96 + 8dec: 00082783 lw a5,0(a6) + 8df0: cbbd beqz a5,8e66 + 8df2: 8aaa mv s5,a0 + 8df4: 6f5010ef jal ra,ace8 <__mcmp> + 8df8: 04054963 bltz a0,8e4a + 8dfc: 6641 lui a2,0x10 + 8dfe: 0485 addi s1,s1,1 + 8e00: 85ca mv a1,s2 + 8e02: 4501 li a0,0 + 8e04: 167d addi a2,a2,-1 + 8e06: 0991 addi s3,s3,4 + 8e08: ffc9a803 lw a6,-4(s3) + 8e0c: 4198 lw a4,0(a1) + 8e0e: 0591 addi a1,a1,4 + 8e10: 00c876b3 and a3,a6,a2 + 8e14: 8d15 sub a0,a0,a3 + 8e16: 00c776b3 and a3,a4,a2 + 8e1a: 96aa add a3,a3,a0 + 8e1c: 01075793 srli a5,a4,0x10 + 8e20: 01085813 srli a6,a6,0x10 + 8e24: 4106d713 srai a4,a3,0x10 + 8e28: 410787b3 sub a5,a5,a6 + 8e2c: 97ba add a5,a5,a4 + 8e2e: 4107d513 srai a0,a5,0x10 + 8e32: 8ef1 and a3,a3,a2 + 8e34: 07c2 slli a5,a5,0x10 + 8e36: 8fd5 or a5,a5,a3 + 8e38: fef5ae23 sw a5,-4(a1) + 8e3c: fd3a75e3 bgeu s4,s3,8e06 + 8e40: 00241793 slli a5,s0,0x2 + 8e44: 97ca add a5,a5,s2 + 8e46: 4398 lw a4,0(a5) + 8e48: c71d beqz a4,8e76 + 8e4a: 8526 mv a0,s1 + 8e4c: 40f2 lw ra,28(sp) + 8e4e: 4462 lw s0,24(sp) + 8e50: 44d2 lw s1,20(sp) + 8e52: 4942 lw s2,16(sp) + 8e54: 49b2 lw s3,12(sp) + 8e56: 4a22 lw s4,8(sp) + 8e58: 4a92 lw s5,4(sp) + 8e5a: 6105 addi sp,sp,32 + 8e5c: 8082 ret + 8e5e: 00082783 lw a5,0(a6) + 8e62: e789 bnez a5,8e6c + 8e64: 147d addi s0,s0,-1 + 8e66: 1871 addi a6,a6,-4 + 8e68: ff096be3 bltu s2,a6,8e5e + 8e6c: c900 sw s0,16(a0) + 8e6e: b751 j 8df2 + 8e70: 4398 lw a4,0(a5) + 8e72: e709 bnez a4,8e7c + 8e74: 147d addi s0,s0,-1 + 8e76: 17f1 addi a5,a5,-4 + 8e78: fef96ce3 bltu s2,a5,8e70 + 8e7c: 008aa823 sw s0,16(s5) + 8e80: b7e9 j 8e4a + 8e82: 4501 li a0,0 + 8e84: b7e1 j 8e4c + +00008e86 <_dtoa_r>: + 8e86: 7175 addi sp,sp,-144 + 8e88: d83e sw a5,48(sp) + 8e8a: 515c lw a5,36(a0) + 8e8c: c522 sw s0,136(sp) + 8e8e: c326 sw s1,132(sp) + 8e90: c14a sw s2,128(sp) + 8e92: dece sw s3,124(sp) + 8e94: dcd2 sw s4,120(sp) + 8e96: d4e2 sw s8,104(sp) + 8e98: c706 sw ra,140(sp) + 8e9a: dad6 sw s5,116(sp) + 8e9c: d8da sw s6,112(sp) + 8e9e: d6de sw s7,108(sp) + 8ea0: d2e6 sw s9,100(sp) + 8ea2: d0ea sw s10,96(sp) + 8ea4: ceee sw s11,92(sp) + 8ea6: c236 sw a3,4(sp) + 8ea8: c63a sw a4,12(sp) + 8eaa: ca46 sw a7,20(sp) + 8eac: 84aa mv s1,a0 + 8eae: 842e mv s0,a1 + 8eb0: 8932 mv s2,a2 + 8eb2: 89c2 mv s3,a6 + 8eb4: 8a2e mv s4,a1 + 8eb6: 8c32 mv s8,a2 + 8eb8: ef89 bnez a5,8ed2 <_dtoa_r+0x4c> + 8eba: 4541 li a0,16 + 8ebc: 023010ef jal ra,a6de + 8ec0: d0c8 sw a0,36(s1) + 8ec2: 00052223 sw zero,4(a0) + 8ec6: 00052423 sw zero,8(a0) + 8eca: 00052023 sw zero,0(a0) + 8ece: 00052623 sw zero,12(a0) + 8ed2: 50dc lw a5,36(s1) + 8ed4: 438c lw a1,0(a5) + 8ed6: cd89 beqz a1,8ef0 <_dtoa_r+0x6a> + 8ed8: 43d8 lw a4,4(a5) + 8eda: 4785 li a5,1 + 8edc: 8526 mv a0,s1 + 8ede: 00e797b3 sll a5,a5,a4 + 8ee2: c59c sw a5,8(a1) + 8ee4: c1d8 sw a4,4(a1) + 8ee6: 0e5010ef jal ra,a7ca <_Bfree> + 8eea: 50dc lw a5,36(s1) + 8eec: 0007a023 sw zero,0(a5) + 8ef0: 04095363 bgez s2,8f36 <_dtoa_r+0xb0> + 8ef4: 4785 li a5,1 + 8ef6: 00191c13 slli s8,s2,0x1 + 8efa: 00f9a023 sw a5,0(s3) + 8efe: 001c5c13 srli s8,s8,0x1 + 8f02: 7ff007b7 lui a5,0x7ff00 + 8f06: 00fc7733 and a4,s8,a5 + 8f0a: 06f71463 bne a4,a5,8f72 <_dtoa_r+0xec> + 8f0e: 5742 lw a4,48(sp) + 8f10: 6789 lui a5,0x2 + 8f12: 0c32 slli s8,s8,0xc + 8f14: 70f78793 addi a5,a5,1807 # 270f + 8f18: 00cc5c13 srli s8,s8,0xc + 8f1c: c31c sw a5,0(a4) + 8f1e: 008c6c33 or s8,s8,s0 + 8f22: 320c05e3 beqz s8,9a4c <_dtoa_r+0xbc6> + 8f26: 47d2 lw a5,20(sp) + 8f28: eb91 bnez a5,8f3c <_dtoa_r+0xb6> + 8f2a: 00004797 auipc a5,0x4 + 8f2e: 8fa78793 addi a5,a5,-1798 # c824 + 8f32: c03e sw a5,0(sp) + 8f34: a839 j 8f52 <_dtoa_r+0xcc> + 8f36: 0009a023 sw zero,0(s3) + 8f3a: b7e1 j 8f02 <_dtoa_r+0x7c> + 8f3c: 00004797 auipc a5,0x4 + 8f40: 8e878793 addi a5,a5,-1816 # c824 + 8f44: c03e sw a5,0(sp) + 8f46: 00004797 auipc a5,0x4 + 8f4a: 8e178793 addi a5,a5,-1823 # c827 + 8f4e: 4752 lw a4,20(sp) + 8f50: c31c sw a5,0(a4) + 8f52: 40ba lw ra,140(sp) + 8f54: 442a lw s0,136(sp) + 8f56: 4502 lw a0,0(sp) + 8f58: 449a lw s1,132(sp) + 8f5a: 490a lw s2,128(sp) + 8f5c: 59f6 lw s3,124(sp) + 8f5e: 5a66 lw s4,120(sp) + 8f60: 5ad6 lw s5,116(sp) + 8f62: 5b46 lw s6,112(sp) + 8f64: 5bb6 lw s7,108(sp) + 8f66: 5c26 lw s8,104(sp) + 8f68: 5c96 lw s9,100(sp) + 8f6a: 5d06 lw s10,96(sp) + 8f6c: 4df6 lw s11,92(sp) + 8f6e: 6149 addi sp,sp,144 + 8f70: 8082 ret + 8f72: 4601 li a2,0 + 8f74: 4681 li a3,0 + 8f76: 8522 mv a0,s0 + 8f78: 85e2 mv a1,s8 + 8f7a: ce22 sw s0,28(sp) + 8f7c: d462 sw s8,40(sp) + 8f7e: faefc0ef jal ra,572c <__eqdf2> + 8f82: e105 bnez a0,8fa2 <_dtoa_r+0x11c> + 8f84: 5742 lw a4,48(sp) + 8f86: 4785 li a5,1 + 8f88: c31c sw a5,0(a4) + 8f8a: 00003797 auipc a5,0x3 + 8f8e: 77278793 addi a5,a5,1906 # c6fc <__clz_tab+0x16c> + 8f92: c03e sw a5,0(sp) + 8f94: 47d2 lw a5,20(sp) + 8f96: dfd5 beqz a5,8f52 <_dtoa_r+0xcc> + 8f98: 00003797 auipc a5,0x3 + 8f9c: 76578793 addi a5,a5,1893 # c6fd <__clz_tab+0x16d> + 8fa0: b77d j 8f4e <_dtoa_r+0xc8> + 8fa2: 00b8 addi a4,sp,72 + 8fa4: 00f4 addi a3,sp,76 + 8fa6: 8662 mv a2,s8 + 8fa8: 85a2 mv a1,s0 + 8faa: 8526 mv a0,s1 + 8fac: 014c5913 srli s2,s8,0x14 + 8fb0: 757010ef jal ra,af06 <__d2b> + 8fb4: 7ff97913 andi s2,s2,2047 + 8fb8: 89aa mv s3,a0 + 8fba: 4aa6 lw s5,72(sp) + 8fbc: 10090d63 beqz s2,90d6 <_dtoa_r+0x250> + 8fc0: 57a2 lw a5,40(sp) + 8fc2: 4572 lw a0,28(sp) + 8fc4: c0190913 addi s2,s2,-1023 + 8fc8: 00c79593 slli a1,a5,0xc + 8fcc: 81b1 srli a1,a1,0xc + 8fce: 3ff007b7 lui a5,0x3ff00 + 8fd2: 8ddd or a1,a1,a5 + 8fd4: dc02 sw zero,56(sp) + 8fd6: 00004797 auipc a5,0x4 + 8fda: 80a78793 addi a5,a5,-2038 # c7e0 + 8fde: 4390 lw a2,0(a5) + 8fe0: 43d4 lw a3,4(a5) + 8fe2: dd1fc0ef jal ra,5db2 <__subdf3> + 8fe6: 00004797 auipc a5,0x4 + 8fea: 80278793 addi a5,a5,-2046 # c7e8 + 8fee: 4390 lw a2,0(a5) + 8ff0: 43d4 lw a3,4(a5) + 8ff2: 909fc0ef jal ra,58fa <__muldf3> + 8ff6: 00003797 auipc a5,0x3 + 8ffa: 7fa78793 addi a5,a5,2042 # c7f0 + 8ffe: 4390 lw a2,0(a5) + 9000: 43d4 lw a3,4(a5) + 9002: a47fb0ef jal ra,4a48 <__adddf3> + 9006: 8b2a mv s6,a0 + 9008: 854a mv a0,s2 + 900a: 8bae mv s7,a1 + 900c: d48fd0ef jal ra,6554 <__floatsidf> + 9010: 00003797 auipc a5,0x3 + 9014: 7e878793 addi a5,a5,2024 # c7f8 + 9018: 4390 lw a2,0(a5) + 901a: 43d4 lw a3,4(a5) + 901c: 8dffc0ef jal ra,58fa <__muldf3> + 9020: 862a mv a2,a0 + 9022: 86ae mv a3,a1 + 9024: 855a mv a0,s6 + 9026: 85de mv a1,s7 + 9028: a21fb0ef jal ra,4a48 <__adddf3> + 902c: 8b2a mv s6,a0 + 902e: 8bae mv s7,a1 + 9030: cbcfd0ef jal ra,64ec <__fixdfsi> + 9034: 842a mv s0,a0 + 9036: 4601 li a2,0 + 9038: 4681 li a3,0 + 903a: 855a mv a0,s6 + 903c: 85de mv a1,s7 + 903e: 807fc0ef jal ra,5844 <__ledf2> + 9042: 00055b63 bgez a0,9058 <_dtoa_r+0x1d2> + 9046: 8522 mv a0,s0 + 9048: d0cfd0ef jal ra,6554 <__floatsidf> + 904c: 865a mv a2,s6 + 904e: 86de mv a3,s7 + 9050: edcfc0ef jal ra,572c <__eqdf2> + 9054: c111 beqz a0,9058 <_dtoa_r+0x1d2> + 9056: 147d addi s0,s0,-1 + 9058: 4705 li a4,1 + 905a: 47d9 li a5,22 + 905c: d63a sw a4,44(sp) + 905e: 0287e363 bltu a5,s0,9084 <_dtoa_r+0x1fe> + 9062: 00341713 slli a4,s0,0x3 + 9066: 00004797 auipc a5,0x4 + 906a: 85a78793 addi a5,a5,-1958 # c8c0 <__mprec_tens> + 906e: 97ba add a5,a5,a4 + 9070: 4390 lw a2,0(a5) + 9072: 43d4 lw a3,4(a5) + 9074: 4572 lw a0,28(sp) + 9076: 55a2 lw a1,40(sp) + 9078: fccfc0ef jal ra,5844 <__ledf2> + 907c: 00055363 bgez a0,9082 <_dtoa_r+0x1fc> + 9080: 147d addi s0,s0,-1 + 9082: d602 sw zero,44(sp) + 9084: 412a8933 sub s2,s5,s2 + 9088: fff90b93 addi s7,s2,-1 + 908c: 4b01 li s6,0 + 908e: 000bd663 bgez s7,909a <_dtoa_r+0x214> + 9092: 4b05 li s6,1 + 9094: 412b0b33 sub s6,s6,s2 + 9098: 4b81 li s7,0 + 909a: 06044e63 bltz s0,9116 <_dtoa_r+0x290> + 909e: 9ba2 add s7,s7,s0 + 90a0: cc22 sw s0,24(sp) + 90a2: 4a81 li s5,0 + 90a4: 4712 lw a4,4(sp) + 90a6: 47a5 li a5,9 + 90a8: 14e7e563 bltu a5,a4,91f2 <_dtoa_r+0x36c> + 90ac: 4795 li a5,5 + 90ae: 4c85 li s9,1 + 90b0: 00e7d663 bge a5,a4,90bc <_dtoa_r+0x236> + 90b4: ffc70793 addi a5,a4,-4 + 90b8: c23e sw a5,4(sp) + 90ba: 4c81 li s9,0 + 90bc: 4712 lw a4,4(sp) + 90be: 478d li a5,3 + 90c0: 10f70e63 beq a4,a5,91dc <_dtoa_r+0x356> + 90c4: 04e7cf63 blt a5,a4,9122 <_dtoa_r+0x29c> + 90c8: 4789 li a5,2 + 90ca: c802 sw zero,16(sp) + 90cc: 06f70d63 beq a4,a5,9146 <_dtoa_r+0x2c0> + 90d0: 4785 li a5,1 + 90d2: c83e sw a5,16(sp) + 90d4: a08d j 9136 <_dtoa_r+0x2b0> + 90d6: 4936 lw s2,76(sp) + 90d8: 02000793 li a5,32 + 90dc: 9956 add s2,s2,s5 + 90de: 43290713 addi a4,s2,1074 + 90e2: 02e7d563 bge a5,a4,910c <_dtoa_r+0x286> + 90e6: 04000513 li a0,64 + 90ea: 8d19 sub a0,a0,a4 + 90ec: 41290793 addi a5,s2,1042 + 90f0: 00ac1533 sll a0,s8,a0 + 90f4: 00f45433 srl s0,s0,a5 + 90f8: 8d41 or a0,a0,s0 + 90fa: ccafd0ef jal ra,65c4 <__floatunsidf> + 90fe: fe1007b7 lui a5,0xfe100 + 9102: 95be add a1,a1,a5 + 9104: 4785 li a5,1 + 9106: 197d addi s2,s2,-1 + 9108: dc3e sw a5,56(sp) + 910a: b5f1 j 8fd6 <_dtoa_r+0x150> + 910c: 40e78533 sub a0,a5,a4 + 9110: 00a41533 sll a0,s0,a0 + 9114: b7dd j 90fa <_dtoa_r+0x274> + 9116: 408b0b33 sub s6,s6,s0 + 911a: 40800ab3 neg s5,s0 + 911e: cc02 sw zero,24(sp) + 9120: b751 j 90a4 <_dtoa_r+0x21e> + 9122: 4712 lw a4,4(sp) + 9124: 4791 li a5,4 + 9126: 00f70e63 beq a4,a5,9142 <_dtoa_r+0x2bc> + 912a: 4705 li a4,1 + 912c: c83a sw a4,16(sp) + 912e: 4712 lw a4,4(sp) + 9130: 4795 li a5,5 + 9132: 0af70663 beq a4,a5,91de <_dtoa_r+0x358> + 9136: 57fd li a5,-1 + 9138: c43e sw a5,8(sp) + 913a: 5dfd li s11,-1 + 913c: 47c9 li a5,18 + 913e: c602 sw zero,12(sp) + 9140: a819 j 9156 <_dtoa_r+0x2d0> + 9142: 4785 li a5,1 + 9144: c83e sw a5,16(sp) + 9146: 47b2 lw a5,12(sp) + 9148: 0af04863 bgtz a5,91f8 <_dtoa_r+0x372> + 914c: 4785 li a5,1 + 914e: 4705 li a4,1 + 9150: c43e sw a5,8(sp) + 9152: 4d85 li s11,1 + 9154: c63a sw a4,12(sp) + 9156: 0244a903 lw s2,36(s1) + 915a: 4711 li a4,4 + 915c: 00092223 sw zero,4(s2) + 9160: 01470693 addi a3,a4,20 + 9164: 00492583 lw a1,4(s2) + 9168: 08d7fc63 bgeu a5,a3,9200 <_dtoa_r+0x37a> + 916c: 8526 mv a0,s1 + 916e: 5d0010ef jal ra,a73e <_Balloc> + 9172: 50dc lw a5,36(s1) + 9174: 00a92023 sw a0,0(s2) + 9178: 439c lw a5,0(a5) + 917a: c03e sw a5,0(sp) + 917c: 47b9 li a5,14 + 917e: 1db7e663 bltu a5,s11,934a <_dtoa_r+0x4c4> + 9182: 1c0c8463 beqz s9,934a <_dtoa_r+0x4c4> + 9186: 0a805e63 blez s0,9242 <_dtoa_r+0x3bc> + 918a: 00f47793 andi a5,s0,15 + 918e: 00379713 slli a4,a5,0x3 + 9192: 40445c93 srai s9,s0,0x4 + 9196: 00003797 auipc a5,0x3 + 919a: 72a78793 addi a5,a5,1834 # c8c0 <__mprec_tens> + 919e: 97ba add a5,a5,a4 + 91a0: 010cf693 andi a3,s9,16 + 91a4: 4398 lw a4,0(a5) + 91a6: 4909 li s2,2 + 91a8: 43dc lw a5,4(a5) + 91aa: c685 beqz a3,91d2 <_dtoa_r+0x34c> + 91ac: 00003697 auipc a3,0x3 + 91b0: 6ec68693 addi a3,a3,1772 # c898 <__mprec_bigtens> + 91b4: 5290 lw a2,32(a3) + 91b6: 4572 lw a0,28(sp) + 91b8: 52d4 lw a3,36(a3) + 91ba: 55a2 lw a1,40(sp) + 91bc: d03a sw a4,32(sp) + 91be: d23e sw a5,36(sp) + 91c0: fb9fb0ef jal ra,5178 <__divdf3> + 91c4: 5702 lw a4,32(sp) + 91c6: 5792 lw a5,36(sp) + 91c8: 00fcfc93 andi s9,s9,15 + 91cc: 8a2a mv s4,a0 + 91ce: 8c2e mv s8,a1 + 91d0: 490d li s2,3 + 91d2: 00003d17 auipc s10,0x3 + 91d6: 6c6d0d13 addi s10,s10,1734 # c898 <__mprec_bigtens> + 91da: a889 j 922c <_dtoa_r+0x3a6> + 91dc: c802 sw zero,16(sp) + 91de: 47b2 lw a5,12(sp) + 91e0: 97a2 add a5,a5,s0 + 91e2: c43e sw a5,8(sp) + 91e4: 00178d93 addi s11,a5,1 + 91e8: 87ee mv a5,s11 + 91ea: f7b046e3 bgtz s11,9156 <_dtoa_r+0x2d0> + 91ee: 4785 li a5,1 + 91f0: b79d j 9156 <_dtoa_r+0x2d0> + 91f2: 4c85 li s9,1 + 91f4: c202 sw zero,4(sp) + 91f6: bde9 j 90d0 <_dtoa_r+0x24a> + 91f8: 47b2 lw a5,12(sp) + 91fa: c43e sw a5,8(sp) + 91fc: 8dbe mv s11,a5 + 91fe: bfa1 j 9156 <_dtoa_r+0x2d0> + 9200: 0585 addi a1,a1,1 + 9202: 00b92223 sw a1,4(s2) + 9206: 0706 slli a4,a4,0x1 + 9208: bfa1 j 9160 <_dtoa_r+0x2da> + 920a: 001cf693 andi a3,s9,1 + 920e: ce81 beqz a3,9226 <_dtoa_r+0x3a0> + 9210: 000d2603 lw a2,0(s10) + 9214: 004d2683 lw a3,4(s10) + 9218: 853a mv a0,a4 + 921a: 85be mv a1,a5 + 921c: edefc0ef jal ra,58fa <__muldf3> + 9220: 0905 addi s2,s2,1 + 9222: 872a mv a4,a0 + 9224: 87ae mv a5,a1 + 9226: 401cdc93 srai s9,s9,0x1 + 922a: 0d21 addi s10,s10,8 + 922c: fc0c9fe3 bnez s9,920a <_dtoa_r+0x384> + 9230: 863a mv a2,a4 + 9232: 86be mv a3,a5 + 9234: 8552 mv a0,s4 + 9236: 85e2 mv a1,s8 + 9238: f41fb0ef jal ra,5178 <__divdf3> + 923c: 8a2a mv s4,a0 + 923e: 8c2e mv s8,a1 + 9240: a081 j 9280 <_dtoa_r+0x3fa> + 9242: 4909 li s2,2 + 9244: cc15 beqz s0,9280 <_dtoa_r+0x3fa> + 9246: 40800cb3 neg s9,s0 + 924a: 00fcf793 andi a5,s9,15 + 924e: 00379713 slli a4,a5,0x3 + 9252: 00003797 auipc a5,0x3 + 9256: 66e78793 addi a5,a5,1646 # c8c0 <__mprec_tens> + 925a: 97ba add a5,a5,a4 + 925c: 4390 lw a2,0(a5) + 925e: 43d4 lw a3,4(a5) + 9260: 4572 lw a0,28(sp) + 9262: 55a2 lw a1,40(sp) + 9264: 404cdc93 srai s9,s9,0x4 + 9268: 00003d17 auipc s10,0x3 + 926c: 630d0d13 addi s10,s10,1584 # c898 <__mprec_bigtens> + 9270: e8afc0ef jal ra,58fa <__muldf3> + 9274: 8a2a mv s4,a0 + 9276: 8c2e mv s8,a1 + 9278: 4781 li a5,0 + 927a: 120c9c63 bnez s9,93b2 <_dtoa_r+0x52c> + 927e: ffdd bnez a5,923c <_dtoa_r+0x3b6> + 9280: 57b2 lw a5,44(sp) + 9282: 14078763 beqz a5,93d0 <_dtoa_r+0x54a> + 9286: 00003717 auipc a4,0x3 + 928a: 4ca70713 addi a4,a4,1226 # c750 <__clz_tab+0x1c0> + 928e: 4310 lw a2,0(a4) + 9290: 4354 lw a3,4(a4) + 9292: 8552 mv a0,s4 + 9294: 85e2 mv a1,s8 + 9296: d052 sw s4,32(sp) + 9298: dacfc0ef jal ra,5844 <__ledf2> + 929c: 12055a63 bgez a0,93d0 <_dtoa_r+0x54a> + 92a0: 120d8b63 beqz s11,93d6 <_dtoa_r+0x550> + 92a4: 47a2 lw a5,8(sp) + 92a6: 0af05063 blez a5,9346 <_dtoa_r+0x4c0> + 92aa: 00003717 auipc a4,0x3 + 92ae: 55670713 addi a4,a4,1366 # c800 + 92b2: 5782 lw a5,32(sp) + 92b4: 4310 lw a2,0(a4) + 92b6: 4354 lw a3,4(a4) + 92b8: 853e mv a0,a5 + 92ba: 85e2 mv a1,s8 + 92bc: e3efc0ef jal ra,58fa <__muldf3> + 92c0: 47a2 lw a5,8(sp) + 92c2: fff40d13 addi s10,s0,-1 + 92c6: 8a2a mv s4,a0 + 92c8: 8c2e mv s8,a1 + 92ca: 0905 addi s2,s2,1 + 92cc: 8762 mv a4,s8 + 92ce: 854a mv a0,s2 + 92d0: de3e sw a5,60(sp) + 92d2: da52 sw s4,52(sp) + 92d4: 8cba mv s9,a4 + 92d6: d03a sw a4,32(sp) + 92d8: a7cfd0ef jal ra,6554 <__floatsidf> + 92dc: 5852 lw a6,52(sp) + 92de: 5702 lw a4,32(sp) + 92e0: fcc00937 lui s2,0xfcc00 + 92e4: 8642 mv a2,a6 + 92e6: 86ba mv a3,a4 + 92e8: e12fc0ef jal ra,58fa <__muldf3> + 92ec: 00003697 auipc a3,0x3 + 92f0: 51c68693 addi a3,a3,1308 # c808 + 92f4: 4290 lw a2,0(a3) + 92f6: 42d4 lw a3,4(a3) + 92f8: 8c52 mv s8,s4 + 92fa: f4efb0ef jal ra,4a48 <__adddf3> + 92fe: 57f2 lw a5,60(sp) + 9300: 8a2a mv s4,a0 + 9302: 992e add s2,s2,a1 + 9304: efe1 bnez a5,93dc <_dtoa_r+0x556> + 9306: 00003797 auipc a5,0x3 + 930a: 50a78793 addi a5,a5,1290 # c810 + 930e: 5852 lw a6,52(sp) + 9310: 5702 lw a4,32(sp) + 9312: 4390 lw a2,0(a5) + 9314: 43d4 lw a3,4(a5) + 9316: 8542 mv a0,a6 + 9318: 85ba mv a1,a4 + 931a: a99fc0ef jal ra,5db2 <__subdf3> + 931e: 8652 mv a2,s4 + 9320: 86ca mv a3,s2 + 9322: 8c2a mv s8,a0 + 9324: 8cae mv s9,a1 + 9326: c70fc0ef jal ra,5796 <__gedf2> + 932a: 54a04a63 bgtz a0,987e <_dtoa_r+0x9f8> + 932e: 800007b7 lui a5,0x80000 + 9332: 0127c7b3 xor a5,a5,s2 + 9336: 8652 mv a2,s4 + 9338: 86be mv a3,a5 + 933a: 8562 mv a0,s8 + 933c: 85e6 mv a1,s9 + 933e: d06fc0ef jal ra,5844 <__ledf2> + 9342: 52054b63 bltz a0,9878 <_dtoa_r+0x9f2> + 9346: 4a72 lw s4,28(sp) + 9348: 5c22 lw s8,40(sp) + 934a: 47b6 lw a5,76(sp) + 934c: 3007c763 bltz a5,965a <_dtoa_r+0x7d4> + 9350: 4739 li a4,14 + 9352: 30874463 blt a4,s0,965a <_dtoa_r+0x7d4> + 9356: 00341713 slli a4,s0,0x3 + 935a: 00003797 auipc a5,0x3 + 935e: 56678793 addi a5,a5,1382 # c8c0 <__mprec_tens> + 9362: 97ba add a5,a5,a4 + 9364: 0007ab03 lw s6,0(a5) + 9368: 0047ab83 lw s7,4(a5) + 936c: 47b2 lw a5,12(sp) + 936e: 2007d263 bgez a5,9572 <_dtoa_r+0x6ec> + 9372: 21b04063 bgtz s11,9572 <_dtoa_r+0x6ec> + 9376: 500d9163 bnez s11,9878 <_dtoa_r+0x9f2> + 937a: 00003797 auipc a5,0x3 + 937e: 49678793 addi a5,a5,1174 # c810 + 9382: 4390 lw a2,0(a5) + 9384: 43d4 lw a3,4(a5) + 9386: 855a mv a0,s6 + 9388: 85de mv a1,s7 + 938a: d70fc0ef jal ra,58fa <__muldf3> + 938e: 8652 mv a2,s4 + 9390: 86e2 mv a3,s8 + 9392: c04fc0ef jal ra,5796 <__gedf2> + 9396: 4a81 li s5,0 + 9398: 4901 li s2,0 + 939a: 4a055763 bgez a0,9848 <_dtoa_r+0x9c2> + 939e: 4782 lw a5,0(sp) + 93a0: 4702 lw a4,0(sp) + 93a2: 0405 addi s0,s0,1 + 93a4: 00178a13 addi s4,a5,1 + 93a8: 03100793 li a5,49 + 93ac: 00f70023 sb a5,0(a4) + 93b0: a145 j 9850 <_dtoa_r+0x9ca> + 93b2: 001cf713 andi a4,s9,1 + 93b6: cb09 beqz a4,93c8 <_dtoa_r+0x542> + 93b8: 000d2603 lw a2,0(s10) + 93bc: 004d2683 lw a3,4(s10) + 93c0: 0905 addi s2,s2,1 + 93c2: d38fc0ef jal ra,58fa <__muldf3> + 93c6: 4785 li a5,1 + 93c8: 401cdc93 srai s9,s9,0x1 + 93cc: 0d21 addi s10,s10,8 + 93ce: b575 j 927a <_dtoa_r+0x3f4> + 93d0: 8d22 mv s10,s0 + 93d2: 87ee mv a5,s11 + 93d4: bde5 j 92cc <_dtoa_r+0x446> + 93d6: 8d22 mv s10,s0 + 93d8: 4781 li a5,0 + 93da: bdcd j 92cc <_dtoa_r+0x446> + 93dc: fff78693 addi a3,a5,-1 + 93e0: 00369613 slli a2,a3,0x3 + 93e4: 00003697 auipc a3,0x3 + 93e8: 4dc68693 addi a3,a3,1244 # c8c0 <__mprec_tens> + 93ec: 96b2 add a3,a3,a2 + 93ee: 4288 lw a0,0(a3) + 93f0: 42cc lw a1,4(a3) + 93f2: 4682 lw a3,0(sp) + 93f4: 97b6 add a5,a5,a3 + 93f6: da3e sw a5,52(sp) + 93f8: 47c2 lw a5,16(sp) + 93fa: c3e9 beqz a5,94bc <_dtoa_r+0x636> + 93fc: 00003797 auipc a5,0x3 + 9400: 34c78793 addi a5,a5,844 # c748 <__clz_tab+0x1b8> + 9404: 862a mv a2,a0 + 9406: 86ae mv a3,a1 + 9408: 4388 lw a0,0(a5) + 940a: 43cc lw a1,4(a5) + 940c: de4a sw s2,60(sp) + 940e: d052 sw s4,32(sp) + 9410: d69fb0ef jal ra,5178 <__divdf3> + 9414: 5802 lw a6,32(sp) + 9416: 5772 lw a4,60(sp) + 9418: 00003917 auipc s2,0x3 + 941c: 3e890913 addi s2,s2,1000 # c800 + 9420: 8642 mv a2,a6 + 9422: 86ba mv a3,a4 + 9424: 98ffc0ef jal ra,5db2 <__subdf3> + 9428: 4a02 lw s4,0(sp) + 942a: d02a sw a0,32(sp) + 942c: d22e sw a1,36(sp) + 942e: 85e6 mv a1,s9 + 9430: 8562 mv a0,s8 + 9432: 8bafd0ef jal ra,64ec <__fixdfsi> + 9436: de2a sw a0,60(sp) + 9438: 91cfd0ef jal ra,6554 <__floatsidf> + 943c: 862a mv a2,a0 + 943e: 86ae mv a3,a1 + 9440: 8562 mv a0,s8 + 9442: 85e6 mv a1,s9 + 9444: 96ffc0ef jal ra,5db2 <__subdf3> + 9448: 57f2 lw a5,60(sp) + 944a: 8c2a mv s8,a0 + 944c: 8cae mv s9,a1 + 944e: 862a mv a2,a0 + 9450: 86ae mv a3,a1 + 9452: 5502 lw a0,32(sp) + 9454: 5592 lw a1,36(sp) + 9456: 0a05 addi s4,s4,1 + 9458: 03078793 addi a5,a5,48 + 945c: fefa0fa3 sb a5,-1(s4) + 9460: b36fc0ef jal ra,5796 <__gedf2> + 9464: 0ea04863 bgtz a0,9554 <_dtoa_r+0x6ce> + 9468: 00003797 auipc a5,0x3 + 946c: 2e878793 addi a5,a5,744 # c750 <__clz_tab+0x1c0> + 9470: 4388 lw a0,0(a5) + 9472: 43cc lw a1,4(a5) + 9474: 8662 mv a2,s8 + 9476: 86e6 mv a3,s9 + 9478: 93bfc0ef jal ra,5db2 <__subdf3> + 947c: 862a mv a2,a0 + 947e: 86ae mv a3,a1 + 9480: 5502 lw a0,32(sp) + 9482: 5592 lw a1,36(sp) + 9484: b12fc0ef jal ra,5796 <__gedf2> + 9488: 18a04263 bgtz a0,960c <_dtoa_r+0x786> + 948c: 57d2 lw a5,52(sp) + 948e: eafa0ce3 beq s4,a5,9346 <_dtoa_r+0x4c0> + 9492: 00092603 lw a2,0(s2) + 9496: 00492683 lw a3,4(s2) + 949a: 5502 lw a0,32(sp) + 949c: 5592 lw a1,36(sp) + 949e: c5cfc0ef jal ra,58fa <__muldf3> + 94a2: 00092603 lw a2,0(s2) + 94a6: 00492683 lw a3,4(s2) + 94aa: d02a sw a0,32(sp) + 94ac: d22e sw a1,36(sp) + 94ae: 8562 mv a0,s8 + 94b0: 85e6 mv a1,s9 + 94b2: c48fc0ef jal ra,58fa <__muldf3> + 94b6: 8c2a mv s8,a0 + 94b8: 8cae mv s9,a1 + 94ba: bf95 j 942e <_dtoa_r+0x5a8> + 94bc: 8652 mv a2,s4 + 94be: 86ca mv a3,s2 + 94c0: c3afc0ef jal ra,58fa <__muldf3> + 94c4: 5a52 lw s4,52(sp) + 94c6: 4902 lw s2,0(sp) + 94c8: d02a sw a0,32(sp) + 94ca: d22e sw a1,36(sp) + 94cc: 85e6 mv a1,s9 + 94ce: 8562 mv a0,s8 + 94d0: 81cfd0ef jal ra,64ec <__fixdfsi> + 94d4: de2a sw a0,60(sp) + 94d6: 87efd0ef jal ra,6554 <__floatsidf> + 94da: 862a mv a2,a0 + 94dc: 86ae mv a3,a1 + 94de: 8562 mv a0,s8 + 94e0: 85e6 mv a1,s9 + 94e2: 8d1fc0ef jal ra,5db2 <__subdf3> + 94e6: 5772 lw a4,60(sp) + 94e8: 57d2 lw a5,52(sp) + 94ea: 0905 addi s2,s2,1 + 94ec: 03070713 addi a4,a4,48 + 94f0: fee90fa3 sb a4,-1(s2) + 94f4: 8c2a mv s8,a0 + 94f6: 8cae mv s9,a1 + 94f8: 06f91263 bne s2,a5,955c <_dtoa_r+0x6d6> + 94fc: 00003917 auipc s2,0x3 + 9500: 24c90913 addi s2,s2,588 # c748 <__clz_tab+0x1b8> + 9504: 00092603 lw a2,0(s2) + 9508: 00492683 lw a3,4(s2) + 950c: 5502 lw a0,32(sp) + 950e: 5592 lw a1,36(sp) + 9510: d38fb0ef jal ra,4a48 <__adddf3> + 9514: 862a mv a2,a0 + 9516: 86ae mv a3,a1 + 9518: 8562 mv a0,s8 + 951a: 85e6 mv a1,s9 + 951c: a7afc0ef jal ra,5796 <__gedf2> + 9520: 0ea04663 bgtz a0,960c <_dtoa_r+0x786> + 9524: 5602 lw a2,32(sp) + 9526: 5692 lw a3,36(sp) + 9528: 00092503 lw a0,0(s2) + 952c: 00492583 lw a1,4(s2) + 9530: 883fc0ef jal ra,5db2 <__subdf3> + 9534: 862a mv a2,a0 + 9536: 86ae mv a3,a1 + 9538: 8562 mv a0,s8 + 953a: 85e6 mv a1,s9 + 953c: b08fc0ef jal ra,5844 <__ledf2> + 9540: 03000793 li a5,48 + 9544: e00551e3 bgez a0,9346 <_dtoa_r+0x4c0> + 9548: fffa4703 lbu a4,-1(s4) + 954c: fffa0693 addi a3,s4,-1 + 9550: 00f70463 beq a4,a5,9558 <_dtoa_r+0x6d2> + 9554: 846a mv s0,s10 + 9556: a859 j 95ec <_dtoa_r+0x766> + 9558: 8a36 mv s4,a3 + 955a: b7fd j 9548 <_dtoa_r+0x6c2> + 955c: 00003797 auipc a5,0x3 + 9560: 2a478793 addi a5,a5,676 # c800 + 9564: 4390 lw a2,0(a5) + 9566: 43d4 lw a3,4(a5) + 9568: b92fc0ef jal ra,58fa <__muldf3> + 956c: 8c2a mv s8,a0 + 956e: 8cae mv s9,a1 + 9570: bfb1 j 94cc <_dtoa_r+0x646> + 9572: 87e2 mv a5,s8 + 9574: 8cbe mv s9,a5 + 9576: 4782 lw a5,0(sp) + 9578: 8c52 mv s8,s4 + 957a: 00003a97 auipc s5,0x3 + 957e: 286a8a93 addi s5,s5,646 # c800 + 9582: 00178913 addi s2,a5,1 + 9586: 9dbe add s11,s11,a5 + 9588: 865a mv a2,s6 + 958a: 86de mv a3,s7 + 958c: 8562 mv a0,s8 + 958e: 85e6 mv a1,s9 + 9590: be9fb0ef jal ra,5178 <__divdf3> + 9594: f59fc0ef jal ra,64ec <__fixdfsi> + 9598: 8d2a mv s10,a0 + 959a: fbbfc0ef jal ra,6554 <__floatsidf> + 959e: 865a mv a2,s6 + 95a0: 86de mv a3,s7 + 95a2: b58fc0ef jal ra,58fa <__muldf3> + 95a6: 862a mv a2,a0 + 95a8: 86ae mv a3,a1 + 95aa: 8562 mv a0,s8 + 95ac: 85e6 mv a1,s9 + 95ae: 805fc0ef jal ra,5db2 <__subdf3> + 95b2: 030d0793 addi a5,s10,48 + 95b6: fef90fa3 sb a5,-1(s2) + 95ba: 862a mv a2,a0 + 95bc: 86ae mv a3,a1 + 95be: 8a4a mv s4,s2 + 95c0: 072d9e63 bne s11,s2,963c <_dtoa_r+0x7b6> + 95c4: c84fb0ef jal ra,4a48 <__adddf3> + 95c8: 865a mv a2,s6 + 95ca: 86de mv a3,s7 + 95cc: 8c2a mv s8,a0 + 95ce: 8cae mv s9,a1 + 95d0: 9c6fc0ef jal ra,5796 <__gedf2> + 95d4: 02a04b63 bgtz a0,960a <_dtoa_r+0x784> + 95d8: 865a mv a2,s6 + 95da: 86de mv a3,s7 + 95dc: 8562 mv a0,s8 + 95de: 85e6 mv a1,s9 + 95e0: 94cfc0ef jal ra,572c <__eqdf2> + 95e4: e501 bnez a0,95ec <_dtoa_r+0x766> + 95e6: 001d7793 andi a5,s10,1 + 95ea: e385 bnez a5,960a <_dtoa_r+0x784> + 95ec: 85ce mv a1,s3 + 95ee: 8526 mv a0,s1 + 95f0: 1da010ef jal ra,a7ca <_Bfree> + 95f4: 57c2 lw a5,48(sp) + 95f6: 000a0023 sb zero,0(s4) + 95fa: 0405 addi s0,s0,1 + 95fc: c380 sw s0,0(a5) + 95fe: 47d2 lw a5,20(sp) + 9600: 940789e3 beqz a5,8f52 <_dtoa_r+0xcc> + 9604: 0147a023 sw s4,0(a5) + 9608: b2a9 j 8f52 <_dtoa_r+0xcc> + 960a: 8d22 mv s10,s0 + 960c: 03900713 li a4,57 + 9610: fffa4683 lbu a3,-1(s4) + 9614: fffa0793 addi a5,s4,-1 + 9618: 00e69a63 bne a3,a4,962c <_dtoa_r+0x7a6> + 961c: 4682 lw a3,0(sp) + 961e: 00f69d63 bne a3,a5,9638 <_dtoa_r+0x7b2> + 9622: 03000713 li a4,48 + 9626: 0d05 addi s10,s10,1 + 9628: 00e68023 sb a4,0(a3) + 962c: 0007c703 lbu a4,0(a5) + 9630: 0705 addi a4,a4,1 + 9632: 00e78023 sb a4,0(a5) + 9636: bf39 j 9554 <_dtoa_r+0x6ce> + 9638: 8a3e mv s4,a5 + 963a: bfd9 j 9610 <_dtoa_r+0x78a> + 963c: 000aa603 lw a2,0(s5) + 9640: 004aa683 lw a3,4(s5) + 9644: 0905 addi s2,s2,1 + 9646: ab4fc0ef jal ra,58fa <__muldf3> + 964a: 4601 li a2,0 + 964c: 4681 li a3,0 + 964e: 8c2a mv s8,a0 + 9650: 8cae mv s9,a1 + 9652: 8dafc0ef jal ra,572c <__eqdf2> + 9656: f90d bnez a0,9588 <_dtoa_r+0x702> + 9658: bf51 j 95ec <_dtoa_r+0x766> + 965a: 4742 lw a4,16(sp) + 965c: 10070063 beqz a4,975c <_dtoa_r+0x8d6> + 9660: 4692 lw a3,4(sp) + 9662: 4705 li a4,1 + 9664: 0cd74563 blt a4,a3,972e <_dtoa_r+0x8a8> + 9668: 5762 lw a4,56(sp) + 966a: 43378793 addi a5,a5,1075 + 966e: e709 bnez a4,9678 <_dtoa_r+0x7f2> + 9670: 4726 lw a4,72(sp) + 9672: 03600793 li a5,54 + 9676: 8f99 sub a5,a5,a4 + 9678: 8d56 mv s10,s5 + 967a: 8cda mv s9,s6 + 967c: 4585 li a1,1 + 967e: 8526 mv a0,s1 + 9680: 9b3e add s6,s6,a5 + 9682: 9bbe add s7,s7,a5 + 9684: 378010ef jal ra,a9fc <__i2b> + 9688: 892a mv s2,a0 + 968a: 01905e63 blez s9,96a6 <_dtoa_r+0x820> + 968e: 01705c63 blez s7,96a6 <_dtoa_r+0x820> + 9692: 87e6 mv a5,s9 + 9694: 019bd363 bge s7,s9,969a <_dtoa_r+0x814> + 9698: 87de mv a5,s7 + 969a: 40fb0b33 sub s6,s6,a5 + 969e: 40fc8cb3 sub s9,s9,a5 + 96a2: 40fb8bb3 sub s7,s7,a5 + 96a6: 040a8063 beqz s5,96e6 <_dtoa_r+0x860> + 96aa: 47c2 lw a5,16(sp) + 96ac: cfc5 beqz a5,9764 <_dtoa_r+0x8de> + 96ae: 03a05463 blez s10,96d6 <_dtoa_r+0x850> + 96b2: 85ca mv a1,s2 + 96b4: 866a mv a2,s10 + 96b6: 8526 mv a0,s1 + 96b8: 4a4010ef jal ra,ab5c <__pow5mult> + 96bc: 864e mv a2,s3 + 96be: 85aa mv a1,a0 + 96c0: 892a mv s2,a0 + 96c2: 8526 mv a0,s1 + 96c4: 354010ef jal ra,aa18 <__multiply> + 96c8: ce2a sw a0,28(sp) + 96ca: 85ce mv a1,s3 + 96cc: 8526 mv a0,s1 + 96ce: 0fc010ef jal ra,a7ca <_Bfree> + 96d2: 47f2 lw a5,28(sp) + 96d4: 89be mv s3,a5 + 96d6: 41aa8633 sub a2,s5,s10 + 96da: c611 beqz a2,96e6 <_dtoa_r+0x860> + 96dc: 85ce mv a1,s3 + 96de: 8526 mv a0,s1 + 96e0: 47c010ef jal ra,ab5c <__pow5mult> + 96e4: 89aa mv s3,a0 + 96e6: 4585 li a1,1 + 96e8: 8526 mv a0,s1 + 96ea: 312010ef jal ra,a9fc <__i2b> + 96ee: 47e2 lw a5,24(sp) + 96f0: 8aaa mv s5,a0 + 96f2: 06f05b63 blez a5,9768 <_dtoa_r+0x8e2> + 96f6: 863e mv a2,a5 + 96f8: 85aa mv a1,a0 + 96fa: 8526 mv a0,s1 + 96fc: 460010ef jal ra,ab5c <__pow5mult> + 9700: 4712 lw a4,4(sp) + 9702: 4785 li a5,1 + 9704: 8aaa mv s5,a0 + 9706: 4d01 li s10,0 + 9708: 06e7c863 blt a5,a4,9778 <_dtoa_r+0x8f2> + 970c: 4d01 li s10,0 + 970e: 060a1263 bnez s4,9772 <_dtoa_r+0x8ec> + 9712: 00cc1793 slli a5,s8,0xc + 9716: 8d52 mv s10,s4 + 9718: efa9 bnez a5,9772 <_dtoa_r+0x8ec> + 971a: 7ff005b7 lui a1,0x7ff00 + 971e: 00bc7c33 and s8,s8,a1 + 9722: 040c0863 beqz s8,9772 <_dtoa_r+0x8ec> + 9726: 0b05 addi s6,s6,1 + 9728: 0b85 addi s7,s7,1 + 972a: 4d05 li s10,1 + 972c: a099 j 9772 <_dtoa_r+0x8ec> + 972e: fffd8d13 addi s10,s11,-1 + 9732: 01aaca63 blt s5,s10,9746 <_dtoa_r+0x8c0> + 9736: 41aa8d33 sub s10,s5,s10 + 973a: 000dde63 bgez s11,9756 <_dtoa_r+0x8d0> + 973e: 41bb0cb3 sub s9,s6,s11 + 9742: 4781 li a5,0 + 9744: bf25 j 967c <_dtoa_r+0x7f6> + 9746: 47e2 lw a5,24(sp) + 9748: 415d0ab3 sub s5,s10,s5 + 974c: 97d6 add a5,a5,s5 + 974e: cc3e sw a5,24(sp) + 9750: 8aea mv s5,s10 + 9752: 4d01 li s10,0 + 9754: b7dd j 973a <_dtoa_r+0x8b4> + 9756: 8cda mv s9,s6 + 9758: 87ee mv a5,s11 + 975a: b70d j 967c <_dtoa_r+0x7f6> + 975c: 8d56 mv s10,s5 + 975e: 8cda mv s9,s6 + 9760: 4901 li s2,0 + 9762: b725 j 968a <_dtoa_r+0x804> + 9764: 8656 mv a2,s5 + 9766: bf9d j 96dc <_dtoa_r+0x856> + 9768: 4712 lw a4,4(sp) + 976a: 4785 li a5,1 + 976c: 4d01 li s10,0 + 976e: f8e7dfe3 bge a5,a4,970c <_dtoa_r+0x886> + 9772: 47e2 lw a5,24(sp) + 9774: 4505 li a0,1 + 9776: cf89 beqz a5,9790 <_dtoa_r+0x90a> + 9778: 010aa783 lw a5,16(s5) + 977c: 078d addi a5,a5,3 + 977e: 078a slli a5,a5,0x2 + 9780: 97d6 add a5,a5,s5 + 9782: 43c8 lw a0,4(a5) + 9784: 1c8010ef jal ra,a94c <__hi0bits> + 9788: 02000793 li a5,32 + 978c: 40a78533 sub a0,a5,a0 + 9790: 955e add a0,a0,s7 + 9792: 897d andi a0,a0,31 + 9794: c151 beqz a0,9818 <_dtoa_r+0x992> + 9796: 02000793 li a5,32 + 979a: 8f89 sub a5,a5,a0 + 979c: 4711 li a4,4 + 979e: 06f75a63 bge a4,a5,9812 <_dtoa_r+0x98c> + 97a2: 47f1 li a5,28 + 97a4: 40a78533 sub a0,a5,a0 + 97a8: 9b2a add s6,s6,a0 + 97aa: 9caa add s9,s9,a0 + 97ac: 9baa add s7,s7,a0 + 97ae: 01605863 blez s6,97be <_dtoa_r+0x938> + 97b2: 85ce mv a1,s3 + 97b4: 865a mv a2,s6 + 97b6: 8526 mv a0,s1 + 97b8: 462010ef jal ra,ac1a <__lshift> + 97bc: 89aa mv s3,a0 + 97be: 01705863 blez s7,97ce <_dtoa_r+0x948> + 97c2: 85d6 mv a1,s5 + 97c4: 865e mv a2,s7 + 97c6: 8526 mv a0,s1 + 97c8: 452010ef jal ra,ac1a <__lshift> + 97cc: 8aaa mv s5,a0 + 97ce: 57b2 lw a5,44(sp) + 97d0: c7b1 beqz a5,981c <_dtoa_r+0x996> + 97d2: 85d6 mv a1,s5 + 97d4: 854e mv a0,s3 + 97d6: 512010ef jal ra,ace8 <__mcmp> + 97da: 04055163 bgez a0,981c <_dtoa_r+0x996> + 97de: 85ce mv a1,s3 + 97e0: 4681 li a3,0 + 97e2: 4629 li a2,10 + 97e4: 8526 mv a0,s1 + 97e6: 028010ef jal ra,a80e <__multadd> + 97ea: 47c2 lw a5,16(sp) + 97ec: 147d addi s0,s0,-1 + 97ee: 89aa mv s3,a0 + 97f0: 26078c63 beqz a5,9a68 <_dtoa_r+0xbe2> + 97f4: 85ca mv a1,s2 + 97f6: 4681 li a3,0 + 97f8: 4629 li a2,10 + 97fa: 8526 mv a0,s1 + 97fc: 012010ef jal ra,a80e <__multadd> + 9800: 47a2 lw a5,8(sp) + 9802: 892a mv s2,a0 + 9804: 08f04563 bgtz a5,988e <_dtoa_r+0xa08> + 9808: 4712 lw a4,4(sp) + 980a: 4789 li a5,2 + 980c: 08e7d163 bge a5,a4,988e <_dtoa_r+0xa08> + 9810: a829 j 982a <_dtoa_r+0x9a4> + 9812: f8e78ee3 beq a5,a4,97ae <_dtoa_r+0x928> + 9816: 853e mv a0,a5 + 9818: 0571 addi a0,a0,28 + 981a: b779 j 97a8 <_dtoa_r+0x922> + 981c: 07b04563 bgtz s11,9886 <_dtoa_r+0xa00> + 9820: 4712 lw a4,4(sp) + 9822: 4789 li a5,2 + 9824: 06e7d163 bge a5,a4,9886 <_dtoa_r+0xa00> + 9828: c46e sw s11,8(sp) + 982a: 47a2 lw a5,8(sp) + 982c: ef91 bnez a5,9848 <_dtoa_r+0x9c2> + 982e: 85d6 mv a1,s5 + 9830: 4681 li a3,0 + 9832: 4615 li a2,5 + 9834: 8526 mv a0,s1 + 9836: 7d9000ef jal ra,a80e <__multadd> + 983a: 8aaa mv s5,a0 + 983c: 85aa mv a1,a0 + 983e: 854e mv a0,s3 + 9840: 4a8010ef jal ra,ace8 <__mcmp> + 9844: b4a04de3 bgtz a0,939e <_dtoa_r+0x518> + 9848: 47b2 lw a5,12(sp) + 984a: 4a02 lw s4,0(sp) + 984c: fff7c413 not s0,a5 + 9850: 4b01 li s6,0 + 9852: 85d6 mv a1,s5 + 9854: 8526 mv a0,s1 + 9856: 775000ef jal ra,a7ca <_Bfree> + 985a: d80909e3 beqz s2,95ec <_dtoa_r+0x766> + 985e: 000b0863 beqz s6,986e <_dtoa_r+0x9e8> + 9862: 012b0663 beq s6,s2,986e <_dtoa_r+0x9e8> + 9866: 85da mv a1,s6 + 9868: 8526 mv a0,s1 + 986a: 761000ef jal ra,a7ca <_Bfree> + 986e: 85ca mv a1,s2 + 9870: 8526 mv a0,s1 + 9872: 759000ef jal ra,a7ca <_Bfree> + 9876: bb9d j 95ec <_dtoa_r+0x766> + 9878: 4a81 li s5,0 + 987a: 4901 li s2,0 + 987c: b7f1 j 9848 <_dtoa_r+0x9c2> + 987e: 846a mv s0,s10 + 9880: 4a81 li s5,0 + 9882: 4901 li s2,0 + 9884: be29 j 939e <_dtoa_r+0x518> + 9886: 47c2 lw a5,16(sp) + 9888: c46e sw s11,8(sp) + 988a: 1e078663 beqz a5,9a76 <_dtoa_r+0xbf0> + 988e: 01905863 blez s9,989e <_dtoa_r+0xa18> + 9892: 85ca mv a1,s2 + 9894: 8666 mv a2,s9 + 9896: 8526 mv a0,s1 + 9898: 382010ef jal ra,ac1a <__lshift> + 989c: 892a mv s2,a0 + 989e: 854a mv a0,s2 + 98a0: 020d0663 beqz s10,98cc <_dtoa_r+0xa46> + 98a4: 00492583 lw a1,4(s2) + 98a8: 8526 mv a0,s1 + 98aa: 695000ef jal ra,a73e <_Balloc> + 98ae: 01092603 lw a2,16(s2) + 98b2: 8b2a mv s6,a0 + 98b4: 00c90593 addi a1,s2,12 + 98b8: 0609 addi a2,a2,2 + 98ba: 060a slli a2,a2,0x2 + 98bc: 0531 addi a0,a0,12 + 98be: e69fc0ef jal ra,6726 + 98c2: 4605 li a2,1 + 98c4: 85da mv a1,s6 + 98c6: 8526 mv a0,s1 + 98c8: 352010ef jal ra,ac1a <__lshift> + 98cc: 4782 lw a5,0(sp) + 98ce: 4722 lw a4,8(sp) + 98d0: 8b4a mv s6,s2 + 98d2: 00178c13 addi s8,a5,1 + 98d6: 97ba add a5,a5,a4 + 98d8: c63e sw a5,12(sp) + 98da: 001a7793 andi a5,s4,1 + 98de: 892a mv s2,a0 + 98e0: c43e sw a5,8(sp) + 98e2: 85d6 mv a1,s5 + 98e4: 854e mv a0,s3 + 98e6: c66ff0ef jal ra,8d4c + 98ea: 85da mv a1,s6 + 98ec: 8d2a mv s10,a0 + 98ee: 03050d93 addi s11,a0,48 + 98f2: 854e mv a0,s3 + 98f4: 3f4010ef jal ra,ace8 <__mcmp> + 98f8: 864a mv a2,s2 + 98fa: 8baa mv s7,a0 + 98fc: 85d6 mv a1,s5 + 98fe: 8526 mv a0,s1 + 9900: 41a010ef jal ra,ad1a <__mdiff> + 9904: 4550 lw a2,12(a0) + 9906: fffc0c93 addi s9,s8,-1 + 990a: 8a2a mv s4,a0 + 990c: 4705 li a4,1 + 990e: e611 bnez a2,991a <_dtoa_r+0xa94> + 9910: 85aa mv a1,a0 + 9912: 854e mv a0,s3 + 9914: 3d4010ef jal ra,ace8 <__mcmp> + 9918: 872a mv a4,a0 + 991a: 85d2 mv a1,s4 + 991c: 8526 mv a0,s1 + 991e: c83a sw a4,16(sp) + 9920: 6ab000ef jal ra,a7ca <_Bfree> + 9924: 4792 lw a5,4(sp) + 9926: 4742 lw a4,16(sp) + 9928: 8a62 mv s4,s8 + 992a: 00e7e6b3 or a3,a5,a4 + 992e: 47a2 lw a5,8(sp) + 9930: 8edd or a3,a3,a5 + 9932: ee81 bnez a3,994a <_dtoa_r+0xac4> + 9934: 03900713 li a4,57 + 9938: 04ed8863 beq s11,a4,9988 <_dtoa_r+0xb02> + 993c: 01705463 blez s7,9944 <_dtoa_r+0xabe> + 9940: 031d0d93 addi s11,s10,49 + 9944: 01bc8023 sb s11,0(s9) + 9948: b729 j 9852 <_dtoa_r+0x9cc> + 994a: 000bca63 bltz s7,995e <_dtoa_r+0xad8> + 994e: 4792 lw a5,4(sp) + 9950: 0177ebb3 or s7,a5,s7 + 9954: 47a2 lw a5,8(sp) + 9956: 00fbebb3 or s7,s7,a5 + 995a: 040b9563 bnez s7,99a4 <_dtoa_r+0xb1e> + 995e: fee053e3 blez a4,9944 <_dtoa_r+0xabe> + 9962: 85ce mv a1,s3 + 9964: 4605 li a2,1 + 9966: 8526 mv a0,s1 + 9968: 2b2010ef jal ra,ac1a <__lshift> + 996c: 85d6 mv a1,s5 + 996e: 89aa mv s3,a0 + 9970: 378010ef jal ra,ace8 <__mcmp> + 9974: 00a04663 bgtz a0,9980 <_dtoa_r+0xafa> + 9978: f571 bnez a0,9944 <_dtoa_r+0xabe> + 997a: 001df713 andi a4,s11,1 + 997e: d379 beqz a4,9944 <_dtoa_r+0xabe> + 9980: 03900713 li a4,57 + 9984: faed9ee3 bne s11,a4,9940 <_dtoa_r+0xaba> + 9988: 03900793 li a5,57 + 998c: 00fc8023 sb a5,0(s9) + 9990: 03900693 li a3,57 + 9994: fffa4783 lbu a5,-1(s4) + 9998: fffa0713 addi a4,s4,-1 + 999c: 08d78c63 beq a5,a3,9a34 <_dtoa_r+0xbae> + 99a0: 0785 addi a5,a5,1 + 99a2: a045 j 9a42 <_dtoa_r+0xbbc> + 99a4: 00e05b63 blez a4,99ba <_dtoa_r+0xb34> + 99a8: 03900713 li a4,57 + 99ac: fced8ee3 beq s11,a4,9988 <_dtoa_r+0xb02> + 99b0: 001d8793 addi a5,s11,1 + 99b4: 00fc8023 sb a5,0(s9) + 99b8: bd69 j 9852 <_dtoa_r+0x9cc> + 99ba: 47b2 lw a5,12(sp) + 99bc: ffbc0fa3 sb s11,-1(s8) + 99c0: 05878163 beq a5,s8,9a02 <_dtoa_r+0xb7c> + 99c4: 85ce mv a1,s3 + 99c6: 4681 li a3,0 + 99c8: 4629 li a2,10 + 99ca: 8526 mv a0,s1 + 99cc: 643000ef jal ra,a80e <__multadd> + 99d0: 89aa mv s3,a0 + 99d2: 4681 li a3,0 + 99d4: 4629 li a2,10 + 99d6: 85da mv a1,s6 + 99d8: 8526 mv a0,s1 + 99da: 012b1863 bne s6,s2,99ea <_dtoa_r+0xb64> + 99de: 631000ef jal ra,a80e <__multadd> + 99e2: 8b2a mv s6,a0 + 99e4: 892a mv s2,a0 + 99e6: 0c05 addi s8,s8,1 + 99e8: bded j 98e2 <_dtoa_r+0xa5c> + 99ea: 625000ef jal ra,a80e <__multadd> + 99ee: 85ca mv a1,s2 + 99f0: 8b2a mv s6,a0 + 99f2: 4681 li a3,0 + 99f4: 4629 li a2,10 + 99f6: 8526 mv a0,s1 + 99f8: 617000ef jal ra,a80e <__multadd> + 99fc: 892a mv s2,a0 + 99fe: b7e5 j 99e6 <_dtoa_r+0xb60> + 9a00: 4b01 li s6,0 + 9a02: 85ce mv a1,s3 + 9a04: 4605 li a2,1 + 9a06: 8526 mv a0,s1 + 9a08: 212010ef jal ra,ac1a <__lshift> + 9a0c: 85d6 mv a1,s5 + 9a0e: 89aa mv s3,a0 + 9a10: 2d8010ef jal ra,ace8 <__mcmp> + 9a14: f6a04ee3 bgtz a0,9990 <_dtoa_r+0xb0a> + 9a18: e501 bnez a0,9a20 <_dtoa_r+0xb9a> + 9a1a: 001df793 andi a5,s11,1 + 9a1e: fbad bnez a5,9990 <_dtoa_r+0xb0a> + 9a20: 03000793 li a5,48 + 9a24: fffa4703 lbu a4,-1(s4) + 9a28: fffa0693 addi a3,s4,-1 + 9a2c: e2f713e3 bne a4,a5,9852 <_dtoa_r+0x9cc> + 9a30: 8a36 mv s4,a3 + 9a32: bfcd j 9a24 <_dtoa_r+0xb9e> + 9a34: 4782 lw a5,0(sp) + 9a36: 00e79963 bne a5,a4,9a48 <_dtoa_r+0xbc2> + 9a3a: 4702 lw a4,0(sp) + 9a3c: 0405 addi s0,s0,1 + 9a3e: 03100793 li a5,49 + 9a42: 00f70023 sb a5,0(a4) + 9a46: b531 j 9852 <_dtoa_r+0x9cc> + 9a48: 8a3a mv s4,a4 + 9a4a: b7a9 j 9994 <_dtoa_r+0xb0e> + 9a4c: 4752 lw a4,20(sp) + 9a4e: 00003797 auipc a5,0x3 + 9a52: dca78793 addi a5,a5,-566 # c818 + 9a56: c03e sw a5,0(sp) + 9a58: 00003797 auipc a5,0x3 + 9a5c: dc878793 addi a5,a5,-568 # c820 + 9a60: ce071763 bnez a4,8f4e <_dtoa_r+0xc8> + 9a64: ceeff06f j 8f52 <_dtoa_r+0xcc> + 9a68: 47a2 lw a5,8(sp) + 9a6a: 00f04663 bgtz a5,9a76 <_dtoa_r+0xbf0> + 9a6e: 4712 lw a4,4(sp) + 9a70: 4789 li a5,2 + 9a72: dae7cce3 blt a5,a4,982a <_dtoa_r+0x9a4> + 9a76: 4a02 lw s4,0(sp) + 9a78: 85d6 mv a1,s5 + 9a7a: 854e mv a0,s3 + 9a7c: ad0ff0ef jal ra,8d4c + 9a80: 4782 lw a5,0(sp) + 9a82: 0a05 addi s4,s4,1 + 9a84: 03050d93 addi s11,a0,48 + 9a88: 40fa0733 sub a4,s4,a5 + 9a8c: 47a2 lw a5,8(sp) + 9a8e: ffba0fa3 sb s11,-1(s4) + 9a92: f6f757e3 bge a4,a5,9a00 <_dtoa_r+0xb7a> + 9a96: 85ce mv a1,s3 + 9a98: 4681 li a3,0 + 9a9a: 4629 li a2,10 + 9a9c: 8526 mv a0,s1 + 9a9e: 571000ef jal ra,a80e <__multadd> + 9aa2: 89aa mv s3,a0 + 9aa4: bfd1 j 9a78 <_dtoa_r+0xbf2> + +00009aa6 <__sflush_r>: + 9aa6: 00c5d783 lhu a5,12(a1) # 7ff0000c <_eusrstack+0x5fef000c> + 9aaa: 1101 addi sp,sp,-32 + 9aac: cc22 sw s0,24(sp) + 9aae: ca26 sw s1,20(sp) + 9ab0: ce06 sw ra,28(sp) + 9ab2: c84a sw s2,16(sp) + 9ab4: c64e sw s3,12(sp) + 9ab6: 0087f713 andi a4,a5,8 + 9aba: 84aa mv s1,a0 + 9abc: 842e mv s0,a1 + 9abe: ef79 bnez a4,9b9c <__sflush_r+0xf6> + 9ac0: 41d8 lw a4,4(a1) + 9ac2: 00e04d63 bgtz a4,9adc <__sflush_r+0x36> + 9ac6: 41b8 lw a4,64(a1) + 9ac8: 00e04a63 bgtz a4,9adc <__sflush_r+0x36> + 9acc: 4501 li a0,0 + 9ace: 40f2 lw ra,28(sp) + 9ad0: 4462 lw s0,24(sp) + 9ad2: 44d2 lw s1,20(sp) + 9ad4: 4942 lw s2,16(sp) + 9ad6: 49b2 lw s3,12(sp) + 9ad8: 6105 addi sp,sp,32 + 9ada: 8082 ret + 9adc: 5458 lw a4,44(s0) + 9ade: d77d beqz a4,9acc <__sflush_r+0x26> + 9ae0: 0004a903 lw s2,0(s1) + 9ae4: 01379693 slli a3,a5,0x13 + 9ae8: 0004a023 sw zero,0(s1) + 9aec: 0606de63 bgez a3,9b68 <__sflush_r+0xc2> + 9af0: 4870 lw a2,84(s0) + 9af2: 00c45783 lhu a5,12(s0) + 9af6: 8b91 andi a5,a5,4 + 9af8: c799 beqz a5,9b06 <__sflush_r+0x60> + 9afa: 405c lw a5,4(s0) + 9afc: 8e1d sub a2,a2,a5 + 9afe: 585c lw a5,52(s0) + 9b00: c399 beqz a5,9b06 <__sflush_r+0x60> + 9b02: 403c lw a5,64(s0) + 9b04: 8e1d sub a2,a2,a5 + 9b06: 545c lw a5,44(s0) + 9b08: 500c lw a1,32(s0) + 9b0a: 4681 li a3,0 + 9b0c: 8526 mv a0,s1 + 9b0e: 9782 jalr a5 + 9b10: 57fd li a5,-1 + 9b12: 00c45703 lhu a4,12(s0) + 9b16: 00f51d63 bne a0,a5,9b30 <__sflush_r+0x8a> + 9b1a: 4094 lw a3,0(s1) + 9b1c: 47f5 li a5,29 + 9b1e: 06d7e963 bltu a5,a3,9b90 <__sflush_r+0xea> + 9b22: 204007b7 lui a5,0x20400 + 9b26: 0785 addi a5,a5,1 + 9b28: 00d7d7b3 srl a5,a5,a3 + 9b2c: 8b85 andi a5,a5,1 + 9b2e: c3ad beqz a5,9b90 <__sflush_r+0xea> + 9b30: 481c lw a5,16(s0) + 9b32: 00042223 sw zero,4(s0) + 9b36: c01c sw a5,0(s0) + 9b38: 01371793 slli a5,a4,0x13 + 9b3c: 0007d863 bgez a5,9b4c <__sflush_r+0xa6> + 9b40: 57fd li a5,-1 + 9b42: 00f51463 bne a0,a5,9b4a <__sflush_r+0xa4> + 9b46: 409c lw a5,0(s1) + 9b48: e391 bnez a5,9b4c <__sflush_r+0xa6> + 9b4a: c868 sw a0,84(s0) + 9b4c: 584c lw a1,52(s0) + 9b4e: 0124a023 sw s2,0(s1) + 9b52: ddad beqz a1,9acc <__sflush_r+0x26> + 9b54: 04440793 addi a5,s0,68 + 9b58: 00f58563 beq a1,a5,9b62 <__sflush_r+0xbc> + 9b5c: 8526 mv a0,s1 + 9b5e: 592010ef jal ra,b0f0 <_free_r> + 9b62: 02042a23 sw zero,52(s0) + 9b66: b79d j 9acc <__sflush_r+0x26> + 9b68: 500c lw a1,32(s0) + 9b6a: 4601 li a2,0 + 9b6c: 4685 li a3,1 + 9b6e: 8526 mv a0,s1 + 9b70: 9702 jalr a4 + 9b72: 57fd li a5,-1 + 9b74: 862a mv a2,a0 + 9b76: f6f51ee3 bne a0,a5,9af2 <__sflush_r+0x4c> + 9b7a: 409c lw a5,0(s1) + 9b7c: dbbd beqz a5,9af2 <__sflush_r+0x4c> + 9b7e: 4775 li a4,29 + 9b80: 00e78563 beq a5,a4,9b8a <__sflush_r+0xe4> + 9b84: 4759 li a4,22 + 9b86: 04e79463 bne a5,a4,9bce <__sflush_r+0x128> + 9b8a: 0124a023 sw s2,0(s1) + 9b8e: bf3d j 9acc <__sflush_r+0x26> + 9b90: 04076713 ori a4,a4,64 + 9b94: 00e41623 sh a4,12(s0) + 9b98: 557d li a0,-1 + 9b9a: bf15 j 9ace <__sflush_r+0x28> + 9b9c: 0105a983 lw s3,16(a1) + 9ba0: f20986e3 beqz s3,9acc <__sflush_r+0x26> + 9ba4: 0005a903 lw s2,0(a1) + 9ba8: 8b8d andi a5,a5,3 + 9baa: 0135a023 sw s3,0(a1) + 9bae: 41390933 sub s2,s2,s3 + 9bb2: 4701 li a4,0 + 9bb4: e391 bnez a5,9bb8 <__sflush_r+0x112> + 9bb6: 49d8 lw a4,20(a1) + 9bb8: c418 sw a4,8(s0) + 9bba: f12059e3 blez s2,9acc <__sflush_r+0x26> + 9bbe: 541c lw a5,40(s0) + 9bc0: 500c lw a1,32(s0) + 9bc2: 86ca mv a3,s2 + 9bc4: 864e mv a2,s3 + 9bc6: 8526 mv a0,s1 + 9bc8: 9782 jalr a5 + 9bca: 00a04963 bgtz a0,9bdc <__sflush_r+0x136> + 9bce: 00c45783 lhu a5,12(s0) + 9bd2: 0407e793 ori a5,a5,64 + 9bd6: 00f41623 sh a5,12(s0) + 9bda: bf7d j 9b98 <__sflush_r+0xf2> + 9bdc: 99aa add s3,s3,a0 + 9bde: 40a90933 sub s2,s2,a0 + 9be2: bfe1 j 9bba <__sflush_r+0x114> + +00009be4 <_fflush_r>: + 9be4: 499c lw a5,16(a1) + 9be6: c3a5 beqz a5,9c46 <_fflush_r+0x62> + 9be8: 1101 addi sp,sp,-32 + 9bea: cc22 sw s0,24(sp) + 9bec: ce06 sw ra,28(sp) + 9bee: 842a mv s0,a0 + 9bf0: c511 beqz a0,9bfc <_fflush_r+0x18> + 9bf2: 4d1c lw a5,24(a0) + 9bf4: e781 bnez a5,9bfc <_fflush_r+0x18> + 9bf6: c62e sw a1,12(sp) + 9bf8: 2239 jal 9d06 <__sinit> + 9bfa: 45b2 lw a1,12(sp) + 9bfc: 00003797 auipc a5,0x3 + 9c00: c4c78793 addi a5,a5,-948 # c848 <__sf_fake_stdin> + 9c04: 00f59c63 bne a1,a5,9c1c <_fflush_r+0x38> + 9c08: 404c lw a1,4(s0) + 9c0a: 00c59783 lh a5,12(a1) + 9c0e: c79d beqz a5,9c3c <_fflush_r+0x58> + 9c10: 8522 mv a0,s0 + 9c12: 4462 lw s0,24(sp) + 9c14: 40f2 lw ra,28(sp) + 9c16: 6105 addi sp,sp,32 + 9c18: e8fff06f j 9aa6 <__sflush_r> + 9c1c: 00003797 auipc a5,0x3 + 9c20: c4c78793 addi a5,a5,-948 # c868 <__sf_fake_stdout> + 9c24: 00f59463 bne a1,a5,9c2c <_fflush_r+0x48> + 9c28: 440c lw a1,8(s0) + 9c2a: b7c5 j 9c0a <_fflush_r+0x26> + 9c2c: 00003797 auipc a5,0x3 + 9c30: bfc78793 addi a5,a5,-1028 # c828 <__sf_fake_stderr> + 9c34: fcf59be3 bne a1,a5,9c0a <_fflush_r+0x26> + 9c38: 444c lw a1,12(s0) + 9c3a: bfc1 j 9c0a <_fflush_r+0x26> + 9c3c: 40f2 lw ra,28(sp) + 9c3e: 4462 lw s0,24(sp) + 9c40: 4501 li a0,0 + 9c42: 6105 addi sp,sp,32 + 9c44: 8082 ret + 9c46: 4501 li a0,0 + 9c48: 8082 ret + +00009c4a : + 9c4a: 1141 addi sp,sp,-16 + 9c4c: c422 sw s0,8(sp) + 9c4e: c606 sw ra,12(sp) + 9c50: 842a mv s0,a0 + 9c52: 00b51623 sh a1,12(a0) + 9c56: 00c51723 sh a2,14(a0) + 9c5a: 00052023 sw zero,0(a0) + 9c5e: 00052223 sw zero,4(a0) + 9c62: 00052423 sw zero,8(a0) + 9c66: 06052223 sw zero,100(a0) + 9c6a: 00052823 sw zero,16(a0) + 9c6e: 00052a23 sw zero,20(a0) + 9c72: 00052c23 sw zero,24(a0) + 9c76: 4621 li a2,8 + 9c78: 4581 li a1,0 + 9c7a: 05c50513 addi a0,a0,92 + 9c7e: f08f60ef jal ra,386 + 9c82: 00002797 auipc a5,0x2 + 9c86: b0c78793 addi a5,a5,-1268 # b78e <__sread> + 9c8a: d05c sw a5,36(s0) + 9c8c: 00002797 auipc a5,0x2 + 9c90: b3278793 addi a5,a5,-1230 # b7be <__swrite> + 9c94: d41c sw a5,40(s0) + 9c96: 00002797 auipc a5,0x2 + 9c9a: b7678793 addi a5,a5,-1162 # b80c <__sseek> + 9c9e: d45c sw a5,44(s0) + 9ca0: 00002797 auipc a5,0x2 + 9ca4: ba278793 addi a5,a5,-1118 # b842 <__sclose> + 9ca8: d000 sw s0,32(s0) + 9caa: d81c sw a5,48(s0) + 9cac: 40b2 lw ra,12(sp) + 9cae: 4422 lw s0,8(sp) + 9cb0: 0141 addi sp,sp,16 + 9cb2: 8082 ret + +00009cb4 <_cleanup_r>: + 9cb4: 00000597 auipc a1,0x0 + 9cb8: f3058593 addi a1,a1,-208 # 9be4 <_fflush_r> + 9cbc: aa99 j 9e12 <_fwalk_reent> + +00009cbe <__sfmoreglue>: + 9cbe: 1141 addi sp,sp,-16 + 9cc0: c226 sw s1,4(sp) + 9cc2: 06800613 li a2,104 + 9cc6: fff58493 addi s1,a1,-1 + 9cca: 02c484b3 mul s1,s1,a2 + 9cce: c04a sw s2,0(sp) + 9cd0: 892e mv s2,a1 + 9cd2: c422 sw s0,8(sp) + 9cd4: c606 sw ra,12(sp) + 9cd6: 07448593 addi a1,s1,116 + 9cda: 4be010ef jal ra,b198 <_malloc_r> + 9cde: 842a mv s0,a0 + 9ce0: cd01 beqz a0,9cf8 <__sfmoreglue+0x3a> + 9ce2: 00052023 sw zero,0(a0) + 9ce6: 01252223 sw s2,4(a0) + 9cea: 0531 addi a0,a0,12 + 9cec: c408 sw a0,8(s0) + 9cee: 06848613 addi a2,s1,104 + 9cf2: 4581 li a1,0 + 9cf4: e92f60ef jal ra,386 + 9cf8: 8522 mv a0,s0 + 9cfa: 40b2 lw ra,12(sp) + 9cfc: 4422 lw s0,8(sp) + 9cfe: 4492 lw s1,4(sp) + 9d00: 4902 lw s2,0(sp) + 9d02: 0141 addi sp,sp,16 + 9d04: 8082 ret + +00009d06 <__sinit>: + 9d06: 4d1c lw a5,24(a0) + 9d08: e7a5 bnez a5,9d70 <__sinit+0x6a> + 9d0a: 1141 addi sp,sp,-16 + 9d0c: c606 sw ra,12(sp) + 9d0e: c422 sw s0,8(sp) + 9d10: 00000797 auipc a5,0x0 + 9d14: fa478793 addi a5,a5,-92 # 9cb4 <_cleanup_r> + 9d18: d51c sw a5,40(a0) + 9d1a: 84818793 addi a5,gp,-1976 # 20000228 <_global_impure_ptr> + 9d1e: 439c lw a5,0(a5) + 9d20: 04052423 sw zero,72(a0) + 9d24: 04052623 sw zero,76(a0) + 9d28: 04052823 sw zero,80(a0) + 9d2c: 00f51463 bne a0,a5,9d34 <__sinit+0x2e> + 9d30: 4785 li a5,1 + 9d32: cd1c sw a5,24(a0) + 9d34: 842a mv s0,a0 + 9d36: 2835 jal 9d72 <__sfp> + 9d38: c048 sw a0,4(s0) + 9d3a: 8522 mv a0,s0 + 9d3c: 281d jal 9d72 <__sfp> + 9d3e: c408 sw a0,8(s0) + 9d40: 8522 mv a0,s0 + 9d42: 2805 jal 9d72 <__sfp> + 9d44: c448 sw a0,12(s0) + 9d46: 4048 lw a0,4(s0) + 9d48: 4601 li a2,0 + 9d4a: 4591 li a1,4 + 9d4c: effff0ef jal ra,9c4a + 9d50: 4408 lw a0,8(s0) + 9d52: 4605 li a2,1 + 9d54: 45a5 li a1,9 + 9d56: ef5ff0ef jal ra,9c4a + 9d5a: 4448 lw a0,12(s0) + 9d5c: 4609 li a2,2 + 9d5e: 45c9 li a1,18 + 9d60: eebff0ef jal ra,9c4a + 9d64: 4785 li a5,1 + 9d66: cc1c sw a5,24(s0) + 9d68: 40b2 lw ra,12(sp) + 9d6a: 4422 lw s0,8(sp) + 9d6c: 0141 addi sp,sp,16 + 9d6e: 8082 ret + 9d70: 8082 ret + +00009d72 <__sfp>: + 9d72: 1141 addi sp,sp,-16 + 9d74: 84818793 addi a5,gp,-1976 # 20000228 <_global_impure_ptr> + 9d78: c226 sw s1,4(sp) + 9d7a: 4384 lw s1,0(a5) + 9d7c: c04a sw s2,0(sp) + 9d7e: c606 sw ra,12(sp) + 9d80: 4c9c lw a5,24(s1) + 9d82: c422 sw s0,8(sp) + 9d84: 892a mv s2,a0 + 9d86: e781 bnez a5,9d8e <__sfp+0x1c> + 9d88: 8526 mv a0,s1 + 9d8a: f7dff0ef jal ra,9d06 <__sinit> + 9d8e: 04848493 addi s1,s1,72 + 9d92: 4480 lw s0,8(s1) + 9d94: 40dc lw a5,4(s1) + 9d96: 17fd addi a5,a5,-1 + 9d98: 0007d663 bgez a5,9da4 <__sfp+0x32> + 9d9c: 409c lw a5,0(s1) + 9d9e: cfb9 beqz a5,9dfc <__sfp+0x8a> + 9da0: 4084 lw s1,0(s1) + 9da2: bfc5 j 9d92 <__sfp+0x20> + 9da4: 00c41703 lh a4,12(s0) + 9da8: e739 bnez a4,9df6 <__sfp+0x84> + 9daa: 77c1 lui a5,0xffff0 + 9dac: 0785 addi a5,a5,1 + 9dae: 06042223 sw zero,100(s0) + 9db2: 00042023 sw zero,0(s0) + 9db6: 00042223 sw zero,4(s0) + 9dba: 00042423 sw zero,8(s0) + 9dbe: c45c sw a5,12(s0) + 9dc0: 00042823 sw zero,16(s0) + 9dc4: 00042a23 sw zero,20(s0) + 9dc8: 00042c23 sw zero,24(s0) + 9dcc: 4621 li a2,8 + 9dce: 4581 li a1,0 + 9dd0: 05c40513 addi a0,s0,92 + 9dd4: db2f60ef jal ra,386 + 9dd8: 02042a23 sw zero,52(s0) + 9ddc: 02042c23 sw zero,56(s0) + 9de0: 04042423 sw zero,72(s0) + 9de4: 04042623 sw zero,76(s0) + 9de8: 8522 mv a0,s0 + 9dea: 40b2 lw ra,12(sp) + 9dec: 4422 lw s0,8(sp) + 9dee: 4492 lw s1,4(sp) + 9df0: 4902 lw s2,0(sp) + 9df2: 0141 addi sp,sp,16 + 9df4: 8082 ret + 9df6: 06840413 addi s0,s0,104 + 9dfa: bf71 j 9d96 <__sfp+0x24> + 9dfc: 4591 li a1,4 + 9dfe: 854a mv a0,s2 + 9e00: ebfff0ef jal ra,9cbe <__sfmoreglue> + 9e04: c088 sw a0,0(s1) + 9e06: fd49 bnez a0,9da0 <__sfp+0x2e> + 9e08: 47b1 li a5,12 + 9e0a: 00f92023 sw a5,0(s2) + 9e0e: 4401 li s0,0 + 9e10: bfe1 j 9de8 <__sfp+0x76> + +00009e12 <_fwalk_reent>: + 9e12: 7179 addi sp,sp,-48 + 9e14: d422 sw s0,40(sp) + 9e16: d04a sw s2,32(sp) + 9e18: cc52 sw s4,24(sp) + 9e1a: ca56 sw s5,20(sp) + 9e1c: c85a sw s6,16(sp) + 9e1e: c65e sw s7,12(sp) + 9e20: d606 sw ra,44(sp) + 9e22: d226 sw s1,36(sp) + 9e24: ce4e sw s3,28(sp) + 9e26: 8a2a mv s4,a0 + 9e28: 8aae mv s5,a1 + 9e2a: 04850413 addi s0,a0,72 + 9e2e: 4901 li s2,0 + 9e30: 4b05 li s6,1 + 9e32: 5bfd li s7,-1 + 9e34: ec09 bnez s0,9e4e <_fwalk_reent+0x3c> + 9e36: 50b2 lw ra,44(sp) + 9e38: 5422 lw s0,40(sp) + 9e3a: 854a mv a0,s2 + 9e3c: 5492 lw s1,36(sp) + 9e3e: 5902 lw s2,32(sp) + 9e40: 49f2 lw s3,28(sp) + 9e42: 4a62 lw s4,24(sp) + 9e44: 4ad2 lw s5,20(sp) + 9e46: 4b42 lw s6,16(sp) + 9e48: 4bb2 lw s7,12(sp) + 9e4a: 6145 addi sp,sp,48 + 9e4c: 8082 ret + 9e4e: 4404 lw s1,8(s0) + 9e50: 00442983 lw s3,4(s0) + 9e54: 19fd addi s3,s3,-1 + 9e56: 0009d463 bgez s3,9e5e <_fwalk_reent+0x4c> + 9e5a: 4000 lw s0,0(s0) + 9e5c: bfe1 j 9e34 <_fwalk_reent+0x22> + 9e5e: 00c4d783 lhu a5,12(s1) + 9e62: 00fb7b63 bgeu s6,a5,9e78 <_fwalk_reent+0x66> + 9e66: 00e49783 lh a5,14(s1) + 9e6a: 01778763 beq a5,s7,9e78 <_fwalk_reent+0x66> + 9e6e: 85a6 mv a1,s1 + 9e70: 8552 mv a0,s4 + 9e72: 9a82 jalr s5 + 9e74: 00a96933 or s2,s2,a0 + 9e78: 06848493 addi s1,s1,104 + 9e7c: bfe1 j 9e54 <_fwalk_reent+0x42> + +00009e7e : + 9e7e: 4910 lw a2,16(a0) + 9e80: 01450693 addi a3,a0,20 + 9e84: 4055d713 srai a4,a1,0x5 + 9e88: 87b6 mv a5,a3 + 9e8a: 02c75663 bge a4,a2,9eb6 + 9e8e: 060a slli a2,a2,0x2 + 9e90: 070a slli a4,a4,0x2 + 9e92: 89fd andi a1,a1,31 + 9e94: 9636 add a2,a2,a3 + 9e96: 9736 add a4,a4,a3 + 9e98: c9b9 beqz a1,9eee + 9e9a: 00470813 addi a6,a4,4 + 9e9e: 4318 lw a4,0(a4) + 9ea0: 02000313 li t1,32 + 9ea4: 40b30333 sub t1,t1,a1 + 9ea8: 00b75733 srl a4,a4,a1 + 9eac: 00c86e63 bltu a6,a2,9ec8 + 9eb0: c398 sw a4,0(a5) + 9eb2: c311 beqz a4,9eb6 + 9eb4: 0791 addi a5,a5,4 + 9eb6: 40d78733 sub a4,a5,a3 + 9eba: 8709 srai a4,a4,0x2 + 9ebc: c918 sw a4,16(a0) + 9ebe: 00d79463 bne a5,a3,9ec6 + 9ec2: 00052a23 sw zero,20(a0) + 9ec6: 8082 ret + 9ec8: 00082883 lw a7,0(a6) + 9ecc: 0791 addi a5,a5,4 + 9ece: 0811 addi a6,a6,4 + 9ed0: 006898b3 sll a7,a7,t1 + 9ed4: 00e8e733 or a4,a7,a4 + 9ed8: fee7ae23 sw a4,-4(a5) # fffefffc <_eusrstack+0xdffdfffc> + 9edc: ffc82703 lw a4,-4(a6) + 9ee0: b7e1 j 9ea8 + 9ee2: 0711 addi a4,a4,4 + 9ee4: ffc72583 lw a1,-4(a4) + 9ee8: 0791 addi a5,a5,4 + 9eea: feb7ae23 sw a1,-4(a5) + 9eee: fec76ae3 bltu a4,a2,9ee2 + 9ef2: b7d1 j 9eb6 + +00009ef4 <__hexdig_fun>: + 9ef4: fd050793 addi a5,a0,-48 + 9ef8: 0ff7f793 andi a5,a5,255 + 9efc: 4725 li a4,9 + 9efe: 00f76763 bltu a4,a5,9f0c <__hexdig_fun+0x18> + 9f02: 1501 addi a0,a0,-32 + 9f04: 0ff57793 andi a5,a0,255 + 9f08: 853e mv a0,a5 + 9f0a: 8082 ret + 9f0c: f9f50793 addi a5,a0,-97 + 9f10: 0ff7f793 andi a5,a5,255 + 9f14: 4695 li a3,5 + 9f16: 00f6e563 bltu a3,a5,9f20 <__hexdig_fun+0x2c> + 9f1a: fb950513 addi a0,a0,-71 + 9f1e: b7dd j 9f04 <__hexdig_fun+0x10> + 9f20: fbf50713 addi a4,a0,-65 + 9f24: 0ff77713 andi a4,a4,255 + 9f28: 4781 li a5,0 + 9f2a: fce6efe3 bltu a3,a4,9f08 <__hexdig_fun+0x14> + 9f2e: fd950513 addi a0,a0,-39 + 9f32: bfc9 j 9f04 <__hexdig_fun+0x10> + +00009f34 <__gethex>: + 9f34: 711d addi sp,sp,-96 + 9f36: c2d6 sw s5,68(sp) + 9f38: 8aaa mv s5,a0 + 9f3a: 8542 mv a0,a6 + 9f3c: c636 sw a3,12(sp) + 9f3e: c23a sw a4,4(sp) + 9f40: ce86 sw ra,92(sp) + 9f42: c8ca sw s2,80(sp) + 9f44: c4d2 sw s4,72(sp) + 9f46: c0da sw s6,64(sp) + 9f48: de5e sw s7,60(sp) + 9f4a: 8b3e mv s6,a5 + 9f4c: d66e sw s11,44(sp) + 9f4e: 8932 mv s2,a2 + 9f50: 8dae mv s11,a1 + 9f52: cca2 sw s0,88(sp) + 9f54: caa6 sw s1,84(sp) + 9f56: c6ce sw s3,76(sp) + 9f58: dc62 sw s8,56(sp) + 9f5a: da66 sw s9,52(sp) + 9f5c: d86a sw s10,48(sp) + 9f5e: 259d jal a5c4 <__localeconv_l> + 9f60: 00052b83 lw s7,0(a0) + 9f64: 855e mv a0,s7 + 9f66: cfffd0ef jal ra,7c64 + 9f6a: 00ab87b3 add a5,s7,a0 + 9f6e: 000da683 lw a3,0(s11) + 9f72: fff7c783 lbu a5,-1(a5) + 9f76: 5779 li a4,-2 + 9f78: 8f15 sub a4,a4,a3 + 9f7a: c83e sw a5,16(sp) + 9f7c: 8a2a mv s4,a0 + 9f7e: 00268793 addi a5,a3,2 + 9f82: 03000693 li a3,48 + 9f86: 00f70633 add a2,a4,a5 + 9f8a: 84be mv s1,a5 + 9f8c: 0785 addi a5,a5,1 + 9f8e: fff7c503 lbu a0,-1(a5) + 9f92: c432 sw a2,8(sp) + 9f94: fed509e3 beq a0,a3,9f86 <__gethex+0x52> + 9f98: f5dff0ef jal ra,9ef4 <__hexdig_fun> + 9f9c: 10051f63 bnez a0,a0ba <__gethex+0x186> + 9fa0: 8652 mv a2,s4 + 9fa2: 85de mv a1,s7 + 9fa4: 8526 mv a0,s1 + 9fa6: 0a3010ef jal ra,b848 + 9faa: 10051d63 bnez a0,a0c4 <__gethex+0x190> + 9fae: 01448c33 add s8,s1,s4 + 9fb2: 000c4503 lbu a0,0(s8) + 9fb6: f3fff0ef jal ra,9ef4 <__hexdig_fun> + 9fba: 10050663 beqz a0,a0c6 <__gethex+0x192> + 9fbe: 84e2 mv s1,s8 + 9fc0: 03000793 li a5,48 + 9fc4: 0004c503 lbu a0,0(s1) + 9fc8: 00f50b63 beq a0,a5,9fde <__gethex+0xaa> + 9fcc: f29ff0ef jal ra,9ef4 <__hexdig_fun> + 9fd0: 4785 li a5,1 + 9fd2: 00153993 seqz s3,a0 + 9fd6: 8ce2 mv s9,s8 + 9fd8: c43e sw a5,8(sp) + 9fda: 8c26 mv s8,s1 + 9fdc: a021 j 9fe4 <__gethex+0xb0> + 9fde: 0485 addi s1,s1,1 + 9fe0: b7d5 j 9fc4 <__gethex+0x90> + 9fe2: 0c05 addi s8,s8,1 + 9fe4: 000c4503 lbu a0,0(s8) + 9fe8: f0dff0ef jal ra,9ef4 <__hexdig_fun> + 9fec: f97d bnez a0,9fe2 <__gethex+0xae> + 9fee: 8652 mv a2,s4 + 9ff0: 85de mv a1,s7 + 9ff2: 8562 mv a0,s8 + 9ff4: 055010ef jal ra,b848 + 9ff8: e911 bnez a0,a00c <__gethex+0xd8> + 9ffa: 000c9c63 bnez s9,a012 <__gethex+0xde> + 9ffe: 9c52 add s8,s8,s4 + a000: 8ce2 mv s9,s8 + a002: 000c4503 lbu a0,0(s8) + a006: eefff0ef jal ra,9ef4 <__hexdig_fun> + a00a: e95d bnez a0,a0c0 <__gethex+0x18c> + a00c: 4401 li s0,0 + a00e: 000c8563 beqz s9,a018 <__gethex+0xe4> + a012: 418c8433 sub s0,s9,s8 + a016: 040a slli s0,s0,0x2 + a018: 000c4783 lbu a5,0(s8) + a01c: 05000713 li a4,80 + a020: 00e78763 beq a5,a4,a02e <__gethex+0xfa> + a024: 07000613 li a2,112 + a028: 8ce2 mv s9,s8 + a02a: 06c79063 bne a5,a2,a08a <__gethex+0x156> + a02e: 001c4783 lbu a5,1(s8) + a032: 02b00713 li a4,43 + a036: 08e78b63 beq a5,a4,a0cc <__gethex+0x198> + a03a: 02d00713 li a4,45 + a03e: 08e78b63 beq a5,a4,a0d4 <__gethex+0x1a0> + a042: 001c0c93 addi s9,s8,1 + a046: 4d01 li s10,0 + a048: 000cc503 lbu a0,0(s9) + a04c: ea9ff0ef jal ra,9ef4 <__hexdig_fun> + a050: fff50793 addi a5,a0,-1 + a054: 0ff7f793 andi a5,a5,255 + a058: 45e1 li a1,24 + a05a: 08f5e463 bltu a1,a5,a0e2 <__gethex+0x1ae> + a05e: ff050793 addi a5,a0,-16 + a062: 0c85 addi s9,s9,1 + a064: 000cc503 lbu a0,0(s9) + a068: ca3e sw a5,20(sp) + a06a: e8bff0ef jal ra,9ef4 <__hexdig_fun> + a06e: fff50593 addi a1,a0,-1 + a072: 0ff5f593 andi a1,a1,255 + a076: 4861 li a6,24 + a078: 47d2 lw a5,20(sp) + a07a: 48a9 li a7,10 + a07c: 04b87e63 bgeu a6,a1,a0d8 <__gethex+0x1a4> + a080: 000d0463 beqz s10,a088 <__gethex+0x154> + a084: 40f007b3 neg a5,a5 + a088: 943e add s0,s0,a5 + a08a: 019da023 sw s9,0(s11) + a08e: 04098c63 beqz s3,a0e6 <__gethex+0x1b2> + a092: 47a2 lw a5,8(sp) + a094: 4481 li s1,0 + a096: e391 bnez a5,a09a <__gethex+0x166> + a098: 4499 li s1,6 + a09a: 40f6 lw ra,92(sp) + a09c: 4466 lw s0,88(sp) + a09e: 8526 mv a0,s1 + a0a0: 4946 lw s2,80(sp) + a0a2: 44d6 lw s1,84(sp) + a0a4: 49b6 lw s3,76(sp) + a0a6: 4a26 lw s4,72(sp) + a0a8: 4a96 lw s5,68(sp) + a0aa: 4b06 lw s6,64(sp) + a0ac: 5bf2 lw s7,60(sp) + a0ae: 5c62 lw s8,56(sp) + a0b0: 5cd2 lw s9,52(sp) + a0b2: 5d42 lw s10,48(sp) + a0b4: 5db2 lw s11,44(sp) + a0b6: 6125 addi sp,sp,96 + a0b8: 8082 ret + a0ba: 4981 li s3,0 + a0bc: 4c81 li s9,0 + a0be: bf31 j 9fda <__gethex+0xa6> + a0c0: 0c05 addi s8,s8,1 + a0c2: b781 j a002 <__gethex+0xce> + a0c4: 8c26 mv s8,s1 + a0c6: 4401 li s0,0 + a0c8: 4985 li s3,1 + a0ca: b7b9 j a018 <__gethex+0xe4> + a0cc: 4d01 li s10,0 + a0ce: 002c0c93 addi s9,s8,2 + a0d2: bf9d j a048 <__gethex+0x114> + a0d4: 4d05 li s10,1 + a0d6: bfe5 j a0ce <__gethex+0x19a> + a0d8: 031787b3 mul a5,a5,a7 + a0dc: 97aa add a5,a5,a0 + a0de: 17c1 addi a5,a5,-16 + a0e0: b749 j a062 <__gethex+0x12e> + a0e2: 8ce2 mv s9,s8 + a0e4: b75d j a08a <__gethex+0x156> + a0e6: 409c07b3 sub a5,s8,s1 + a0ea: 17fd addi a5,a5,-1 + a0ec: 4581 li a1,0 + a0ee: 471d li a4,7 + a0f0: 0af74463 blt a4,a5,a198 <__gethex+0x264> + a0f4: 8556 mv a0,s5 + a0f6: 25a1 jal a73e <_Balloc> + a0f8: 4605 li a2,1 + a0fa: 01450993 addi s3,a0,20 + a0fe: 414607b3 sub a5,a2,s4 + a102: 8daa mv s11,a0 + a104: 8d4e mv s10,s3 + a106: 4881 li a7,0 + a108: 4c81 li s9,0 + a10a: ca3e sw a5,20(sp) + a10c: 0984e963 bltu s1,s8,a19e <__gethex+0x26a> + a110: 004d0513 addi a0,s10,4 + a114: 41350533 sub a0,a0,s3 + a118: 8509 srai a0,a0,0x2 + a11a: 019d2023 sw s9,0(s10) + a11e: 00ada823 sw a0,16(s11) + a122: 00551493 slli s1,a0,0x5 + a126: 8566 mv a0,s9 + a128: 025000ef jal ra,a94c <__hi0bits> + a12c: 00092b83 lw s7,0(s2) + a130: 8c89 sub s1,s1,a0 + a132: 0c9bd863 bge s7,s1,a202 <__gethex+0x2ce> + a136: 417484b3 sub s1,s1,s7 + a13a: 85a6 mv a1,s1 + a13c: 856e mv a0,s11 + a13e: 747000ef jal ra,b084 <__any_on> + a142: 8a2a mv s4,a0 + a144: c905 beqz a0,a174 <__gethex+0x240> + a146: fff48613 addi a2,s1,-1 + a14a: 40565693 srai a3,a2,0x5 + a14e: 068a slli a3,a3,0x2 + a150: 96ce add a3,a3,s3 + a152: 4294 lw a3,0(a3) + a154: 4705 li a4,1 + a156: 00c71733 sll a4,a4,a2 + a15a: 8f75 and a4,a4,a3 + a15c: 4a05 li s4,1 + a15e: cb19 beqz a4,a174 <__gethex+0x240> + a160: 00ca5963 bge s4,a2,a172 <__gethex+0x23e> + a164: ffe48593 addi a1,s1,-2 + a168: 856e mv a0,s11 + a16a: 71b000ef jal ra,b084 <__any_on> + a16e: 4a0d li s4,3 + a170: e111 bnez a0,a174 <__gethex+0x240> + a172: 4a09 li s4,2 + a174: 85a6 mv a1,s1 + a176: 856e mv a0,s11 + a178: d07ff0ef jal ra,9e7e + a17c: 9426 add s0,s0,s1 + a17e: 00892703 lw a4,8(s2) + a182: 08875f63 bge a4,s0,a220 <__gethex+0x2ec> + a186: 85ee mv a1,s11 + a188: 8556 mv a0,s5 + a18a: 2581 jal a7ca <_Bfree> + a18c: 4792 lw a5,4(sp) + a18e: 0a300493 li s1,163 + a192: 0007a023 sw zero,0(a5) + a196: b711 j a09a <__gethex+0x166> + a198: 0585 addi a1,a1,1 + a19a: 8785 srai a5,a5,0x1 + a19c: bf91 j a0f0 <__gethex+0x1bc> + a19e: fffc0793 addi a5,s8,-1 + a1a2: c43e sw a5,8(sp) + a1a4: fffc4603 lbu a2,-1(s8) + a1a8: 47c2 lw a5,16(sp) + a1aa: 02f60963 beq a2,a5,a1dc <__gethex+0x2a8> + a1ae: 02000793 li a5,32 + a1b2: 00f89763 bne a7,a5,a1c0 <__gethex+0x28c> + a1b6: 019d2023 sw s9,0(s10) + a1ba: 4881 li a7,0 + a1bc: 0d11 addi s10,s10,4 + a1be: 4c81 li s9,0 + a1c0: fffc4503 lbu a0,-1(s8) + a1c4: cc46 sw a7,24(sp) + a1c6: d2fff0ef jal ra,9ef4 <__hexdig_fun> + a1ca: 48e2 lw a7,24(sp) + a1cc: 893d andi a0,a0,15 + a1ce: 4322 lw t1,8(sp) + a1d0: 01151533 sll a0,a0,a7 + a1d4: 00acecb3 or s9,s9,a0 + a1d8: 0891 addi a7,a7,4 + a1da: a015 j a1fe <__gethex+0x2ca> + a1dc: 4752 lw a4,20(sp) + a1de: fffc0793 addi a5,s8,-1 + a1e2: 00e78333 add t1,a5,a4 + a1e6: fc9364e3 bltu t1,s1,a1ae <__gethex+0x27a> + a1ea: 851a mv a0,t1 + a1ec: 8652 mv a2,s4 + a1ee: 85de mv a1,s7 + a1f0: ce46 sw a7,28(sp) + a1f2: cc1a sw t1,24(sp) + a1f4: 654010ef jal ra,b848 + a1f8: 4362 lw t1,24(sp) + a1fa: 48f2 lw a7,28(sp) + a1fc: f94d bnez a0,a1ae <__gethex+0x27a> + a1fe: 8c1a mv s8,t1 + a200: b731 j a10c <__gethex+0x1d8> + a202: 4a01 li s4,0 + a204: f774dde3 bge s1,s7,a17e <__gethex+0x24a> + a208: 409b84b3 sub s1,s7,s1 + a20c: 85ee mv a1,s11 + a20e: 8626 mv a2,s1 + a210: 8556 mv a0,s5 + a212: 209000ef jal ra,ac1a <__lshift> + a216: 8daa mv s11,a0 + a218: 8c05 sub s0,s0,s1 + a21a: 01450993 addi s3,a0,20 + a21e: b785 j a17e <__gethex+0x24a> + a220: 00492703 lw a4,4(s2) + a224: 0ee45563 bge s0,a4,a30e <__gethex+0x3da> + a228: 40870433 sub s0,a4,s0 + a22c: 07744563 blt s0,s7,a296 <__gethex+0x362> + a230: 00c92703 lw a4,12(s2) + a234: 4689 li a3,2 + a236: 04d70a63 beq a4,a3,a28a <__gethex+0x356> + a23a: 468d li a3,3 + a23c: 04d70a63 beq a4,a3,a290 <__gethex+0x35c> + a240: 4685 li a3,1 + a242: 02d71b63 bne a4,a3,a278 <__gethex+0x344> + a246: 028b9963 bne s7,s0,a278 <__gethex+0x344> + a24a: 02eb9163 bne s7,a4,a26c <__gethex+0x338> + a24e: 00492703 lw a4,4(s2) + a252: 47b2 lw a5,12(sp) + a254: 06200493 li s1,98 + a258: c398 sw a4,0(a5) + a25a: 4705 li a4,1 + a25c: 4792 lw a5,4(sp) + a25e: 00eda823 sw a4,16(s11) + a262: 00e9a023 sw a4,0(s3) + a266: 01b7a023 sw s11,0(a5) + a26a: bd05 j a09a <__gethex+0x166> + a26c: fffb8593 addi a1,s7,-1 + a270: 856e mv a0,s11 + a272: 613000ef jal ra,b084 <__any_on> + a276: fd61 bnez a0,a24e <__gethex+0x31a> + a278: 85ee mv a1,s11 + a27a: 8556 mv a0,s5 + a27c: 23b9 jal a7ca <_Bfree> + a27e: 4792 lw a5,4(sp) + a280: 05000493 li s1,80 + a284: 0007a023 sw zero,0(a5) + a288: bd09 j a09a <__gethex+0x166> + a28a: fe0b17e3 bnez s6,a278 <__gethex+0x344> + a28e: b7c1 j a24e <__gethex+0x31a> + a290: fa0b1fe3 bnez s6,a24e <__gethex+0x31a> + a294: b7d5 j a278 <__gethex+0x344> + a296: fff40493 addi s1,s0,-1 + a29a: 060a1863 bnez s4,a30a <__gethex+0x3d6> + a29e: c491 beqz s1,a2aa <__gethex+0x376> + a2a0: 85a6 mv a1,s1 + a2a2: 856e mv a0,s11 + a2a4: 5e1000ef jal ra,b084 <__any_on> + a2a8: 8a2a mv s4,a0 + a2aa: 4054d713 srai a4,s1,0x5 + a2ae: 070a slli a4,a4,0x2 + a2b0: 974e add a4,a4,s3 + a2b2: 4318 lw a4,0(a4) + a2b4: 4585 li a1,1 + a2b6: 009595b3 sll a1,a1,s1 + a2ba: 8df9 and a1,a1,a4 + a2bc: c199 beqz a1,a2c2 <__gethex+0x38e> + a2be: 002a6a13 ori s4,s4,2 + a2c2: 85a2 mv a1,s0 + a2c4: 856e mv a0,s11 + a2c6: 408b8bb3 sub s7,s7,s0 + a2ca: bb5ff0ef jal ra,9e7e + a2ce: 00492403 lw s0,4(s2) + a2d2: 4489 li s1,2 + a2d4: 080a0b63 beqz s4,a36a <__gethex+0x436> + a2d8: 00c92703 lw a4,12(s2) + a2dc: 4689 li a3,2 + a2de: 02d70a63 beq a4,a3,a312 <__gethex+0x3de> + a2e2: 468d li a3,3 + a2e4: 02d70a63 beq a4,a3,a318 <__gethex+0x3e4> + a2e8: 4685 li a3,1 + a2ea: 00d71d63 bne a4,a3,a304 <__gethex+0x3d0> + a2ee: 002a7713 andi a4,s4,2 + a2f2: cb09 beqz a4,a304 <__gethex+0x3d0> + a2f4: 0009a703 lw a4,0(s3) + a2f8: 00ea6a33 or s4,s4,a4 + a2fc: 001a7a13 andi s4,s4,1 + a300: 000a1e63 bnez s4,a31c <__gethex+0x3e8> + a304: 0104e493 ori s1,s1,16 + a308: a08d j a36a <__gethex+0x436> + a30a: 4a05 li s4,1 + a30c: bf79 j a2aa <__gethex+0x376> + a30e: 4485 li s1,1 + a310: b7d1 j a2d4 <__gethex+0x3a0> + a312: 4705 li a4,1 + a314: 41670b33 sub s6,a4,s6 + a318: fe0b06e3 beqz s6,a304 <__gethex+0x3d0> + a31c: 010da983 lw s3,16(s11) + a320: 014d8713 addi a4,s11,20 + a324: 55fd li a1,-1 + a326: 00299a13 slli s4,s3,0x2 + a32a: 01470633 add a2,a4,s4 + a32e: 4314 lw a3,0(a4) + a330: 04b68363 beq a3,a1,a376 <__gethex+0x442> + a334: 0685 addi a3,a3,1 + a336: c314 sw a3,0(a4) + a338: 4689 li a3,2 + a33a: 014d8713 addi a4,s11,20 + a33e: 08d49463 bne s1,a3,a3c6 <__gethex+0x492> + a342: 00092683 lw a3,0(s2) + a346: 16fd addi a3,a3,-1 + a348: 01769f63 bne a3,s7,a366 <__gethex+0x432> + a34c: 405bd693 srai a3,s7,0x5 + a350: 068a slli a3,a3,0x2 + a352: 9736 add a4,a4,a3 + a354: 4318 lw a4,0(a4) + a356: 4685 li a3,1 + a358: 01769bb3 sll s7,a3,s7 + a35c: 00ebfbb3 and s7,s7,a4 + a360: 000b8363 beqz s7,a366 <__gethex+0x432> + a364: 4485 li s1,1 + a366: 0204e493 ori s1,s1,32 + a36a: 4792 lw a5,4(sp) + a36c: 01b7a023 sw s11,0(a5) + a370: 47b2 lw a5,12(sp) + a372: c380 sw s0,0(a5) + a374: b31d j a09a <__gethex+0x166> + a376: 0711 addi a4,a4,4 + a378: fe072e23 sw zero,-4(a4) + a37c: fac769e3 bltu a4,a2,a32e <__gethex+0x3fa> + a380: 008da703 lw a4,8(s11) + a384: 02e9c563 blt s3,a4,a3ae <__gethex+0x47a> + a388: 004da583 lw a1,4(s11) + a38c: 8556 mv a0,s5 + a38e: 0585 addi a1,a1,1 + a390: 267d jal a73e <_Balloc> + a392: 010da603 lw a2,16(s11) + a396: 00cd8593 addi a1,s11,12 + a39a: 8b2a mv s6,a0 + a39c: 0609 addi a2,a2,2 + a39e: 060a slli a2,a2,0x2 + a3a0: 0531 addi a0,a0,12 + a3a2: b84fc0ef jal ra,6726 + a3a6: 85ee mv a1,s11 + a3a8: 8556 mv a0,s5 + a3aa: 2105 jal a7ca <_Bfree> + a3ac: 8dda mv s11,s6 + a3ae: 010da703 lw a4,16(s11) + a3b2: 00170693 addi a3,a4,1 + a3b6: 0711 addi a4,a4,4 + a3b8: 070a slli a4,a4,0x2 + a3ba: 00dda823 sw a3,16(s11) + a3be: 976e add a4,a4,s11 + a3c0: 4685 li a3,1 + a3c2: c354 sw a3,4(a4) + a3c4: bf95 j a338 <__gethex+0x404> + a3c6: 010da683 lw a3,16(s11) + a3ca: 00d9dc63 bge s3,a3,a3e2 <__gethex+0x4ae> + a3ce: 4585 li a1,1 + a3d0: 856e mv a0,s11 + a3d2: aadff0ef jal ra,9e7e + a3d6: 00892703 lw a4,8(s2) + a3da: 0405 addi s0,s0,1 + a3dc: f88754e3 bge a4,s0,a364 <__gethex+0x430> + a3e0: b35d j a186 <__gethex+0x252> + a3e2: 01fbfb93 andi s7,s7,31 + a3e6: 4485 li s1,1 + a3e8: f60b8fe3 beqz s7,a366 <__gethex+0x432> + a3ec: 9752 add a4,a4,s4 + a3ee: ffc72503 lw a0,-4(a4) + a3f2: 2ba9 jal a94c <__hi0bits> + a3f4: 02000713 li a4,32 + a3f8: 41770bb3 sub s7,a4,s7 + a3fc: fd7549e3 blt a0,s7,a3ce <__gethex+0x49a> + a400: b79d j a366 <__gethex+0x432> + +0000a402 : + a402: 47a1 li a5,8 + a404: 40c78633 sub a2,a5,a2 + a408: 060a slli a2,a2,0x2 + a40a: 02000693 li a3,32 + a40e: 8e91 sub a3,a3,a2 + a410: 415c lw a5,4(a0) + a412: 4118 lw a4,0(a0) + a414: 0511 addi a0,a0,4 + a416: 00d79833 sll a6,a5,a3 + a41a: 01076733 or a4,a4,a6 + a41e: 00c7d7b3 srl a5,a5,a2 + a422: fee52e23 sw a4,-4(a0) + a426: c11c sw a5,0(a0) + a428: feb564e3 bltu a0,a1,a410 + a42c: 8082 ret + +0000a42e <__match>: + a42e: 411c lw a5,0(a0) + a430: 4865 li a6,25 + a432: 0585 addi a1,a1,1 + a434: fff5c603 lbu a2,-1(a1) + a438: 0785 addi a5,a5,1 + a43a: e601 bnez a2,a442 <__match+0x14> + a43c: c11c sw a5,0(a0) + a43e: 4505 li a0,1 + a440: 8082 ret + a442: 0007c703 lbu a4,0(a5) + a446: fbf70693 addi a3,a4,-65 + a44a: 0ff6f693 andi a3,a3,255 + a44e: 00d86463 bltu a6,a3,a456 <__match+0x28> + a452: 02070713 addi a4,a4,32 + a456: fcc70ee3 beq a4,a2,a432 <__match+0x4> + a45a: 4501 li a0,0 + a45c: 8082 ret + +0000a45e <__hexnan>: + a45e: 715d addi sp,sp,-80 + a460: dc52 sw s4,56(sp) + a462: 0005aa03 lw s4,0(a1) + a466: c2a6 sw s1,68(sp) + a468: de4e sw s3,60(sp) + a46a: 405a5493 srai s1,s4,0x5 + a46e: d85a sw s6,48(sp) + a470: 048a slli s1,s1,0x2 + a472: c686 sw ra,76(sp) + a474: c4a2 sw s0,72(sp) + a476: c0ca sw s2,64(sp) + a478: da56 sw s5,52(sp) + a47a: d65e sw s7,44(sp) + a47c: d462 sw s8,40(sp) + a47e: d266 sw s9,36(sp) + a480: d06a sw s10,32(sp) + a482: ce6e sw s11,28(sp) + a484: 01fa7a13 andi s4,s4,31 + a488: 8b2a mv s6,a0 + a48a: 89b2 mv s3,a2 + a48c: 94b2 add s1,s1,a2 + a48e: 000a0363 beqz s4,a494 <__hexnan+0x36> + a492: 0491 addi s1,s1,4 + a494: 000b2783 lw a5,0(s6) + a498: ffc48913 addi s2,s1,-4 + a49c: fe04ae23 sw zero,-4(s1) + a4a0: 8dca mv s11,s2 + a4a2: 844a mv s0,s2 + a4a4: 4601 li a2,0 + a4a6: 4a81 li s5,0 + a4a8: 4b81 li s7,0 + a4aa: 4c21 li s8,8 + a4ac: 02000c93 li s9,32 + a4b0: 4d1d li s10,7 + a4b2: 0017c683 lbu a3,1(a5) + a4b6: 00178713 addi a4,a5,1 + a4ba: c03a sw a4,0(sp) + a4bc: cab1 beqz a3,a510 <__hexnan+0xb2> + a4be: 8536 mv a0,a3 + a4c0: c632 sw a2,12(sp) + a4c2: c43e sw a5,8(sp) + a4c4: c236 sw a3,4(sp) + a4c6: a2fff0ef jal ra,9ef4 <__hexdig_fun> + a4ca: 4632 lw a2,12(sp) + a4cc: e559 bnez a0,a55a <__hexnan+0xfc> + a4ce: 4692 lw a3,4(sp) + a4d0: 47a2 lw a5,8(sp) + a4d2: 02dce863 bltu s9,a3,a502 <__hexnan+0xa4> + a4d6: 037ad463 bge s5,s7,a4fe <__hexnan+0xa0> + a4da: 01b47863 bgeu s0,s11,a4ea <__hexnan+0x8c> + a4de: 00cd4663 blt s10,a2,a4ea <__hexnan+0x8c> + a4e2: 85ee mv a1,s11 + a4e4: 8522 mv a0,s0 + a4e6: f1dff0ef jal ra,a402 + a4ea: 4621 li a2,8 + a4ec: 0089f963 bgeu s3,s0,a4fe <__hexnan+0xa0> + a4f0: ffc40d93 addi s11,s0,-4 + a4f4: fe042e23 sw zero,-4(s0) + a4f8: 8ade mv s5,s7 + a4fa: 846e mv s0,s11 + a4fc: 4601 li a2,0 + a4fe: 4782 lw a5,0(sp) + a500: bf4d j a4b2 <__hexnan+0x54> + a502: 02900593 li a1,41 + a506: 08b69c63 bne a3,a1,a59e <__hexnan+0x140> + a50a: 0789 addi a5,a5,2 + a50c: 00fb2023 sw a5,0(s6) + a510: 080b8763 beqz s7,a59e <__hexnan+0x140> + a514: 01b47963 bgeu s0,s11,a526 <__hexnan+0xc8> + a518: 479d li a5,7 + a51a: 00c7c663 blt a5,a2,a526 <__hexnan+0xc8> + a51e: 85ee mv a1,s11 + a520: 8522 mv a0,s0 + a522: ee1ff0ef jal ra,a402 + a526: 0489fa63 bgeu s3,s0,a57a <__hexnan+0x11c> + a52a: 87ce mv a5,s3 + a52c: 0411 addi s0,s0,4 + a52e: ffc42703 lw a4,-4(s0) + a532: 0791 addi a5,a5,4 + a534: fee7ae23 sw a4,-4(a5) + a538: fe897ae3 bgeu s2,s0,a52c <__hexnan+0xce> + a53c: 0791 addi a5,a5,4 + a53e: fe07ae23 sw zero,-4(a5) + a542: fef97de3 bgeu s2,a5,a53c <__hexnan+0xde> + a546: 00092783 lw a5,0(s2) + a54a: e791 bnez a5,a556 <__hexnan+0xf8> + a54c: 05391763 bne s2,s3,a59a <__hexnan+0x13c> + a550: 4785 li a5,1 + a552: 00f92023 sw a5,0(s2) + a556: 4515 li a0,5 + a558: a0a1 j a5a0 <__hexnan+0x142> + a55a: 0605 addi a2,a2,1 + a55c: 0b85 addi s7,s7,1 + a55e: 00cc5863 bge s8,a2,a56e <__hexnan+0x110> + a562: f889fee3 bgeu s3,s0,a4fe <__hexnan+0xa0> + a566: fe042e23 sw zero,-4(s0) + a56a: 4605 li a2,1 + a56c: 1471 addi s0,s0,-4 + a56e: 401c lw a5,0(s0) + a570: 893d andi a0,a0,15 + a572: 0792 slli a5,a5,0x4 + a574: 8fc9 or a5,a5,a0 + a576: c01c sw a5,0(s0) + a578: b759 j a4fe <__hexnan+0xa0> + a57a: fc0a06e3 beqz s4,a546 <__hexnan+0xe8> + a57e: 02000793 li a5,32 + a582: 414787b3 sub a5,a5,s4 + a586: 5a7d li s4,-1 + a588: 00fa57b3 srl a5,s4,a5 + a58c: ffc4aa03 lw s4,-4(s1) + a590: 00fa7a33 and s4,s4,a5 + a594: ff44ae23 sw s4,-4(s1) + a598: b77d j a546 <__hexnan+0xe8> + a59a: 1971 addi s2,s2,-4 + a59c: b76d j a546 <__hexnan+0xe8> + a59e: 4511 li a0,4 + a5a0: 40b6 lw ra,76(sp) + a5a2: 4426 lw s0,72(sp) + a5a4: 4496 lw s1,68(sp) + a5a6: 4906 lw s2,64(sp) + a5a8: 59f2 lw s3,60(sp) + a5aa: 5a62 lw s4,56(sp) + a5ac: 5ad2 lw s5,52(sp) + a5ae: 5b42 lw s6,48(sp) + a5b0: 5bb2 lw s7,44(sp) + a5b2: 5c22 lw s8,40(sp) + a5b4: 5c92 lw s9,36(sp) + a5b6: 5d02 lw s10,32(sp) + a5b8: 4df2 lw s11,28(sp) + a5ba: 6161 addi sp,sp,80 + a5bc: 8082 ret + +0000a5be <__locale_ctype_ptr_l>: + a5be: 0ec52503 lw a0,236(a0) + a5c2: 8082 ret + +0000a5c4 <__localeconv_l>: + a5c4: 0f050513 addi a0,a0,240 + a5c8: 8082 ret + +0000a5ca <_localeconv_r>: + a5ca: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + a5ce: 439c lw a5,0(a5) + a5d0: 5388 lw a0,32(a5) + a5d2: e509 bnez a0,a5dc <_localeconv_r+0x12> + a5d4: 1fff6517 auipc a0,0x1fff6 + a5d8: a9c50513 addi a0,a0,-1380 # 20000070 <__global_locale> + a5dc: 0f050513 addi a0,a0,240 + a5e0: 8082 ret + +0000a5e2 <__swhatbuf_r>: + a5e2: 7119 addi sp,sp,-128 + a5e4: daa6 sw s1,116(sp) + a5e6: 84ae mv s1,a1 + a5e8: 00e59583 lh a1,14(a1) + a5ec: dca2 sw s0,120(sp) + a5ee: de86 sw ra,124(sp) + a5f0: 8432 mv s0,a2 + a5f2: 0005dc63 bgez a1,a60a <__swhatbuf_r+0x28> + a5f6: 00c4d783 lhu a5,12(s1) + a5fa: 0006a023 sw zero,0(a3) + a5fe: 0807f793 andi a5,a5,128 + a602: e785 bnez a5,a62a <__swhatbuf_r+0x48> + a604: 40000793 li a5,1024 + a608: a01d j a62e <__swhatbuf_r+0x4c> + a60a: 0830 addi a2,sp,24 + a60c: c636 sw a3,12(sp) + a60e: 2ec010ef jal ra,b8fa <_fstat_r> + a612: 46b2 lw a3,12(sp) + a614: fe0541e3 bltz a0,a5f6 <__swhatbuf_r+0x14> + a618: 4772 lw a4,28(sp) + a61a: 67bd lui a5,0xf + a61c: 8ff9 and a5,a5,a4 + a61e: 7779 lui a4,0xffffe + a620: 97ba add a5,a5,a4 + a622: 0017b793 seqz a5,a5 + a626: c29c sw a5,0(a3) + a628: bff1 j a604 <__swhatbuf_r+0x22> + a62a: 04000793 li a5,64 + a62e: c01c sw a5,0(s0) + a630: 50f6 lw ra,124(sp) + a632: 5466 lw s0,120(sp) + a634: 54d6 lw s1,116(sp) + a636: 4501 li a0,0 + a638: 6109 addi sp,sp,128 + a63a: 8082 ret + +0000a63c <__smakebuf_r>: + a63c: 00c5d783 lhu a5,12(a1) + a640: 1101 addi sp,sp,-32 + a642: cc22 sw s0,24(sp) + a644: ce06 sw ra,28(sp) + a646: ca26 sw s1,20(sp) + a648: c84a sw s2,16(sp) + a64a: 8b89 andi a5,a5,2 + a64c: 842e mv s0,a1 + a64e: cf89 beqz a5,a668 <__smakebuf_r+0x2c> + a650: 04740793 addi a5,s0,71 + a654: c01c sw a5,0(s0) + a656: c81c sw a5,16(s0) + a658: 4785 li a5,1 + a65a: c85c sw a5,20(s0) + a65c: 40f2 lw ra,28(sp) + a65e: 4462 lw s0,24(sp) + a660: 44d2 lw s1,20(sp) + a662: 4942 lw s2,16(sp) + a664: 6105 addi sp,sp,32 + a666: 8082 ret + a668: 0074 addi a3,sp,12 + a66a: 0030 addi a2,sp,8 + a66c: 84aa mv s1,a0 + a66e: f75ff0ef jal ra,a5e2 <__swhatbuf_r> + a672: 45a2 lw a1,8(sp) + a674: 892a mv s2,a0 + a676: 8526 mv a0,s1 + a678: 321000ef jal ra,b198 <_malloc_r> + a67c: ed01 bnez a0,a694 <__smakebuf_r+0x58> + a67e: 00c41783 lh a5,12(s0) + a682: 2007f713 andi a4,a5,512 + a686: fb79 bnez a4,a65c <__smakebuf_r+0x20> + a688: 9bf1 andi a5,a5,-4 + a68a: 0027e793 ori a5,a5,2 + a68e: 00f41623 sh a5,12(s0) + a692: bf7d j a650 <__smakebuf_r+0x14> + a694: fffff797 auipc a5,0xfffff + a698: 62078793 addi a5,a5,1568 # 9cb4 <_cleanup_r> + a69c: d49c sw a5,40(s1) + a69e: 00c45783 lhu a5,12(s0) + a6a2: c008 sw a0,0(s0) + a6a4: c808 sw a0,16(s0) + a6a6: 0807e793 ori a5,a5,128 + a6aa: 00f41623 sh a5,12(s0) + a6ae: 47a2 lw a5,8(sp) + a6b0: c85c sw a5,20(s0) + a6b2: 47b2 lw a5,12(sp) + a6b4: cf91 beqz a5,a6d0 <__smakebuf_r+0x94> + a6b6: 00e41583 lh a1,14(s0) + a6ba: 8526 mv a0,s1 + a6bc: 270010ef jal ra,b92c <_isatty_r> + a6c0: c901 beqz a0,a6d0 <__smakebuf_r+0x94> + a6c2: 00c45783 lhu a5,12(s0) + a6c6: 9bf1 andi a5,a5,-4 + a6c8: 0017e793 ori a5,a5,1 + a6cc: 00f41623 sh a5,12(s0) + a6d0: 00c45783 lhu a5,12(s0) + a6d4: 00f96933 or s2,s2,a5 + a6d8: 01241623 sh s2,12(s0) + a6dc: b741 j a65c <__smakebuf_r+0x20> + +0000a6de : + a6de: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + a6e2: 85aa mv a1,a0 + a6e4: 4388 lw a0,0(a5) + a6e6: 2b30006f j b198 <_malloc_r> + +0000a6ea <__ascii_mbtowc>: + a6ea: e185 bnez a1,a70a <__ascii_mbtowc+0x20> + a6ec: 1141 addi sp,sp,-16 + a6ee: 006c addi a1,sp,12 + a6f0: 4501 li a0,0 + a6f2: ca11 beqz a2,a706 <__ascii_mbtowc+0x1c> + a6f4: 5579 li a0,-2 + a6f6: ca81 beqz a3,a706 <__ascii_mbtowc+0x1c> + a6f8: 00064783 lbu a5,0(a2) # 10000 <_data_lma+0x3568> + a6fc: c19c sw a5,0(a1) + a6fe: 00064503 lbu a0,0(a2) + a702: 00a03533 snez a0,a0 + a706: 0141 addi sp,sp,16 + a708: 8082 ret + a70a: 4501 li a0,0 + a70c: ca19 beqz a2,a722 <__ascii_mbtowc+0x38> + a70e: 5579 li a0,-2 + a710: ca89 beqz a3,a722 <__ascii_mbtowc+0x38> + a712: 00064783 lbu a5,0(a2) + a716: c19c sw a5,0(a1) + a718: 00064503 lbu a0,0(a2) + a71c: 00a03533 snez a0,a0 + a720: 8082 ret + a722: 8082 ret + +0000a724 : + a724: 0ff5f593 andi a1,a1,255 + a728: 962a add a2,a2,a0 + a72a: 00c51463 bne a0,a2,a732 + a72e: 4501 li a0,0 + a730: 8082 ret + a732: 00054783 lbu a5,0(a0) + a736: feb78de3 beq a5,a1,a730 + a73a: 0505 addi a0,a0,1 + a73c: b7fd j a72a + +0000a73e <_Balloc>: + a73e: 515c lw a5,36(a0) + a740: 1141 addi sp,sp,-16 + a742: c422 sw s0,8(sp) + a744: c04a sw s2,0(sp) + a746: c606 sw ra,12(sp) + a748: c226 sw s1,4(sp) + a74a: 842a mv s0,a0 + a74c: 892e mv s2,a1 + a74e: ef89 bnez a5,a768 <_Balloc+0x2a> + a750: 4541 li a0,16 + a752: f8dff0ef jal ra,a6de + a756: d048 sw a0,36(s0) + a758: 00052223 sw zero,4(a0) + a75c: 00052423 sw zero,8(a0) + a760: 00052023 sw zero,0(a0) + a764: 00052623 sw zero,12(a0) + a768: 5044 lw s1,36(s0) + a76a: 44dc lw a5,12(s1) + a76c: c79d beqz a5,a79a <_Balloc+0x5c> + a76e: 5058 lw a4,36(s0) + a770: 00291793 slli a5,s2,0x2 + a774: 4758 lw a4,12(a4) + a776: 97ba add a5,a5,a4 + a778: 4388 lw a0,0(a5) + a77a: e129 bnez a0,a7bc <_Balloc+0x7e> + a77c: 4485 li s1,1 + a77e: 012494b3 sll s1,s1,s2 + a782: 00548613 addi a2,s1,5 + a786: 060a slli a2,a2,0x2 + a788: 4585 li a1,1 + a78a: 8522 mv a0,s0 + a78c: 13f000ef jal ra,b0ca <_calloc_r> + a790: cd19 beqz a0,a7ae <_Balloc+0x70> + a792: 01252223 sw s2,4(a0) + a796: c504 sw s1,8(a0) + a798: a025 j a7c0 <_Balloc+0x82> + a79a: 02100613 li a2,33 + a79e: 4591 li a1,4 + a7a0: 8522 mv a0,s0 + a7a2: 129000ef jal ra,b0ca <_calloc_r> + a7a6: 505c lw a5,36(s0) + a7a8: c4c8 sw a0,12(s1) + a7aa: 47dc lw a5,12(a5) + a7ac: f3e9 bnez a5,a76e <_Balloc+0x30> + a7ae: 4501 li a0,0 + a7b0: 40b2 lw ra,12(sp) + a7b2: 4422 lw s0,8(sp) + a7b4: 4492 lw s1,4(sp) + a7b6: 4902 lw s2,0(sp) + a7b8: 0141 addi sp,sp,16 + a7ba: 8082 ret + a7bc: 4118 lw a4,0(a0) + a7be: c398 sw a4,0(a5) + a7c0: 00052823 sw zero,16(a0) + a7c4: 00052623 sw zero,12(a0) + a7c8: b7e5 j a7b0 <_Balloc+0x72> + +0000a7ca <_Bfree>: + a7ca: 515c lw a5,36(a0) + a7cc: 1101 addi sp,sp,-32 + a7ce: cc22 sw s0,24(sp) + a7d0: ce06 sw ra,28(sp) + a7d2: 842a mv s0,a0 + a7d4: ef99 bnez a5,a7f2 <_Bfree+0x28> + a7d6: 4541 li a0,16 + a7d8: c62e sw a1,12(sp) + a7da: f05ff0ef jal ra,a6de + a7de: 45b2 lw a1,12(sp) + a7e0: d048 sw a0,36(s0) + a7e2: 00052223 sw zero,4(a0) + a7e6: 00052423 sw zero,8(a0) + a7ea: 00052023 sw zero,0(a0) + a7ee: 00052623 sw zero,12(a0) + a7f2: c991 beqz a1,a806 <_Bfree+0x3c> + a7f4: 5054 lw a3,36(s0) + a7f6: 41dc lw a5,4(a1) + a7f8: 00279713 slli a4,a5,0x2 + a7fc: 46dc lw a5,12(a3) + a7fe: 97ba add a5,a5,a4 + a800: 4398 lw a4,0(a5) + a802: c198 sw a4,0(a1) + a804: c38c sw a1,0(a5) + a806: 40f2 lw ra,28(sp) + a808: 4462 lw s0,24(sp) + a80a: 6105 addi sp,sp,32 + a80c: 8082 ret + +0000a80e <__multadd>: + a80e: 7179 addi sp,sp,-48 + a810: ce4e sw s3,28(sp) + a812: 89aa mv s3,a0 + a814: 6541 lui a0,0x10 + a816: d422 sw s0,40(sp) + a818: d226 sw s1,36(sp) + a81a: 842e mv s0,a1 + a81c: 4984 lw s1,16(a1) + a81e: d606 sw ra,44(sp) + a820: d04a sw s2,32(sp) + a822: 05d1 addi a1,a1,20 + a824: 4801 li a6,0 + a826: 157d addi a0,a0,-1 + a828: 419c lw a5,0(a1) + a82a: 0591 addi a1,a1,4 + a82c: 0805 addi a6,a6,1 + a82e: 00a7f733 and a4,a5,a0 + a832: 02c70733 mul a4,a4,a2 + a836: 83c1 srli a5,a5,0x10 + a838: 02c787b3 mul a5,a5,a2 + a83c: 9736 add a4,a4,a3 + a83e: 01075693 srli a3,a4,0x10 + a842: 8f69 and a4,a4,a0 + a844: 97b6 add a5,a5,a3 + a846: 0107d693 srli a3,a5,0x10 + a84a: 07c2 slli a5,a5,0x10 + a84c: 97ba add a5,a5,a4 + a84e: fef5ae23 sw a5,-4(a1) + a852: fc984be3 blt a6,s1,a828 <__multadd+0x1a> + a856: c2a1 beqz a3,a896 <__multadd+0x88> + a858: 441c lw a5,8(s0) + a85a: 02f4c763 blt s1,a5,a888 <__multadd+0x7a> + a85e: 404c lw a1,4(s0) + a860: 854e mv a0,s3 + a862: c636 sw a3,12(sp) + a864: 0585 addi a1,a1,1 + a866: ed9ff0ef jal ra,a73e <_Balloc> + a86a: 4810 lw a2,16(s0) + a86c: 00c40593 addi a1,s0,12 + a870: 892a mv s2,a0 + a872: 0609 addi a2,a2,2 + a874: 060a slli a2,a2,0x2 + a876: 0531 addi a0,a0,12 + a878: eaffb0ef jal ra,6726 + a87c: 85a2 mv a1,s0 + a87e: 854e mv a0,s3 + a880: f4bff0ef jal ra,a7ca <_Bfree> + a884: 46b2 lw a3,12(sp) + a886: 844a mv s0,s2 + a888: 00448793 addi a5,s1,4 + a88c: 078a slli a5,a5,0x2 + a88e: 97a2 add a5,a5,s0 + a890: c3d4 sw a3,4(a5) + a892: 0485 addi s1,s1,1 + a894: c804 sw s1,16(s0) + a896: 8522 mv a0,s0 + a898: 50b2 lw ra,44(sp) + a89a: 5422 lw s0,40(sp) + a89c: 5492 lw s1,36(sp) + a89e: 5902 lw s2,32(sp) + a8a0: 49f2 lw s3,28(sp) + a8a2: 6145 addi sp,sp,48 + a8a4: 8082 ret + +0000a8a6 <__s2b>: + a8a6: 7179 addi sp,sp,-48 + a8a8: 00868793 addi a5,a3,8 + a8ac: cc52 sw s4,24(sp) + a8ae: 8a36 mv s4,a3 + a8b0: 46a5 li a3,9 + a8b2: d422 sw s0,40(sp) + a8b4: d226 sw s1,36(sp) + a8b6: ce4e sw s3,28(sp) + a8b8: 842e mv s0,a1 + a8ba: 02d7c7b3 div a5,a5,a3 + a8be: d606 sw ra,44(sp) + a8c0: d04a sw s2,32(sp) + a8c2: ca56 sw s5,20(sp) + a8c4: 89aa mv s3,a0 + a8c6: 84b2 mv s1,a2 + a8c8: 4685 li a3,1 + a8ca: 4581 li a1,0 + a8cc: 04f6cc63 blt a3,a5,a924 <__s2b+0x7e> + a8d0: 854e mv a0,s3 + a8d2: c63a sw a4,12(sp) + a8d4: e6bff0ef jal ra,a73e <_Balloc> + a8d8: 4732 lw a4,12(sp) + a8da: 4785 li a5,1 + a8dc: c91c sw a5,16(a0) + a8de: c958 sw a4,20(a0) + a8e0: 47a5 li a5,9 + a8e2: 0497d463 bge a5,s1,a92a <__s2b+0x84> + a8e6: 00940a93 addi s5,s0,9 + a8ea: 8956 mv s2,s5 + a8ec: 9426 add s0,s0,s1 + a8ee: 0905 addi s2,s2,1 + a8f0: fff94683 lbu a3,-1(s2) + a8f4: 85aa mv a1,a0 + a8f6: 4629 li a2,10 + a8f8: fd068693 addi a3,a3,-48 + a8fc: 854e mv a0,s3 + a8fe: f11ff0ef jal ra,a80e <__multadd> + a902: fe8916e3 bne s2,s0,a8ee <__s2b+0x48> + a906: ff848413 addi s0,s1,-8 + a90a: 9456 add s0,s0,s5 + a90c: 8926 mv s2,s1 + a90e: 03494163 blt s2,s4,a930 <__s2b+0x8a> + a912: 50b2 lw ra,44(sp) + a914: 5422 lw s0,40(sp) + a916: 5492 lw s1,36(sp) + a918: 5902 lw s2,32(sp) + a91a: 49f2 lw s3,28(sp) + a91c: 4a62 lw s4,24(sp) + a91e: 4ad2 lw s5,20(sp) + a920: 6145 addi sp,sp,48 + a922: 8082 ret + a924: 0686 slli a3,a3,0x1 + a926: 0585 addi a1,a1,1 + a928: b755 j a8cc <__s2b+0x26> + a92a: 0429 addi s0,s0,10 + a92c: 44a5 li s1,9 + a92e: bff9 j a90c <__s2b+0x66> + a930: 409907b3 sub a5,s2,s1 + a934: 97a2 add a5,a5,s0 + a936: 0007c683 lbu a3,0(a5) + a93a: 85aa mv a1,a0 + a93c: 4629 li a2,10 + a93e: fd068693 addi a3,a3,-48 + a942: 854e mv a0,s3 + a944: ecbff0ef jal ra,a80e <__multadd> + a948: 0905 addi s2,s2,1 + a94a: b7d1 j a90e <__s2b+0x68> + +0000a94c <__hi0bits>: + a94c: 7741 lui a4,0xffff0 + a94e: 8f69 and a4,a4,a0 + a950: 87aa mv a5,a0 + a952: 4501 li a0,0 + a954: e319 bnez a4,a95a <__hi0bits+0xe> + a956: 07c2 slli a5,a5,0x10 + a958: 4541 li a0,16 + a95a: ff000737 lui a4,0xff000 + a95e: 8f7d and a4,a4,a5 + a960: e319 bnez a4,a966 <__hi0bits+0x1a> + a962: 0521 addi a0,a0,8 + a964: 07a2 slli a5,a5,0x8 + a966: f0000737 lui a4,0xf0000 + a96a: 8f7d and a4,a4,a5 + a96c: e319 bnez a4,a972 <__hi0bits+0x26> + a96e: 0511 addi a0,a0,4 + a970: 0792 slli a5,a5,0x4 + a972: c0000737 lui a4,0xc0000 + a976: 8f7d and a4,a4,a5 + a978: e319 bnez a4,a97e <__hi0bits+0x32> + a97a: 0509 addi a0,a0,2 + a97c: 078a slli a5,a5,0x2 + a97e: 0007c963 bltz a5,a990 <__hi0bits+0x44> + a982: 00179713 slli a4,a5,0x1 + a986: 0505 addi a0,a0,1 + a988: 00074463 bltz a4,a990 <__hi0bits+0x44> + a98c: 02000513 li a0,32 + a990: 8082 ret + +0000a992 <__lo0bits>: + a992: 411c lw a5,0(a0) + a994: 0077f713 andi a4,a5,7 + a998: c30d beqz a4,a9ba <__lo0bits+0x28> + a99a: 0017f693 andi a3,a5,1 + a99e: 4701 li a4,0 + a9a0: e699 bnez a3,a9ae <__lo0bits+0x1c> + a9a2: 0027f713 andi a4,a5,2 + a9a6: c711 beqz a4,a9b2 <__lo0bits+0x20> + a9a8: 8385 srli a5,a5,0x1 + a9aa: c11c sw a5,0(a0) + a9ac: 4705 li a4,1 + a9ae: 853a mv a0,a4 + a9b0: 8082 ret + a9b2: 8389 srli a5,a5,0x2 + a9b4: c11c sw a5,0(a0) + a9b6: 4709 li a4,2 + a9b8: bfdd j a9ae <__lo0bits+0x1c> + a9ba: 01079693 slli a3,a5,0x10 + a9be: 82c1 srli a3,a3,0x10 + a9c0: 4701 li a4,0 + a9c2: e299 bnez a3,a9c8 <__lo0bits+0x36> + a9c4: 83c1 srli a5,a5,0x10 + a9c6: 4741 li a4,16 + a9c8: 0ff7f693 andi a3,a5,255 + a9cc: e299 bnez a3,a9d2 <__lo0bits+0x40> + a9ce: 0721 addi a4,a4,8 + a9d0: 83a1 srli a5,a5,0x8 + a9d2: 00f7f693 andi a3,a5,15 + a9d6: e299 bnez a3,a9dc <__lo0bits+0x4a> + a9d8: 0711 addi a4,a4,4 + a9da: 8391 srli a5,a5,0x4 + a9dc: 0037f693 andi a3,a5,3 + a9e0: e299 bnez a3,a9e6 <__lo0bits+0x54> + a9e2: 0709 addi a4,a4,2 + a9e4: 8389 srli a5,a5,0x2 + a9e6: 0017f693 andi a3,a5,1 + a9ea: e681 bnez a3,a9f2 <__lo0bits+0x60> + a9ec: 8385 srli a5,a5,0x1 + a9ee: 0705 addi a4,a4,1 + a9f0: c399 beqz a5,a9f6 <__lo0bits+0x64> + a9f2: c11c sw a5,0(a0) + a9f4: bf6d j a9ae <__lo0bits+0x1c> + a9f6: 02000713 li a4,32 + a9fa: bf55 j a9ae <__lo0bits+0x1c> + +0000a9fc <__i2b>: + a9fc: 1141 addi sp,sp,-16 + a9fe: c422 sw s0,8(sp) + aa00: 842e mv s0,a1 + aa02: 4585 li a1,1 + aa04: c606 sw ra,12(sp) + aa06: d39ff0ef jal ra,a73e <_Balloc> + aa0a: c940 sw s0,20(a0) + aa0c: 40b2 lw ra,12(sp) + aa0e: 4422 lw s0,8(sp) + aa10: 4705 li a4,1 + aa12: c918 sw a4,16(a0) + aa14: 0141 addi sp,sp,16 + aa16: 8082 ret + +0000aa18 <__multiply>: + aa18: 4998 lw a4,16(a1) + aa1a: 4a1c lw a5,16(a2) + aa1c: 7179 addi sp,sp,-48 + aa1e: d226 sw s1,36(sp) + aa20: d606 sw ra,44(sp) + aa22: d422 sw s0,40(sp) + aa24: d04a sw s2,32(sp) + aa26: ce4e sw s3,28(sp) + aa28: 84ae mv s1,a1 + aa2a: 00f75463 bge a4,a5,aa32 <__multiply+0x1a> + aa2e: 84b2 mv s1,a2 + aa30: 862e mv a2,a1 + aa32: 0104a983 lw s3,16(s1) + aa36: 01062903 lw s2,16(a2) + aa3a: 449c lw a5,8(s1) + aa3c: 40cc lw a1,4(s1) + aa3e: 01298433 add s0,s3,s2 + aa42: 0087d363 bge a5,s0,aa48 <__multiply+0x30> + aa46: 0585 addi a1,a1,1 + aa48: c632 sw a2,12(sp) + aa4a: cf5ff0ef jal ra,a73e <_Balloc> + aa4e: 4632 lw a2,12(sp) + aa50: 01450813 addi a6,a0,20 # 10014 <_data_lma+0x357c> + aa54: 00241313 slli t1,s0,0x2 + aa58: 9342 add t1,t1,a6 + aa5a: 87c2 mv a5,a6 + aa5c: 0267ed63 bltu a5,t1,aa96 <__multiply+0x7e> + aa60: 01448593 addi a1,s1,20 + aa64: 00299893 slli a7,s3,0x2 + aa68: 0651 addi a2,a2,20 + aa6a: 00291e13 slli t3,s2,0x2 + aa6e: 66c1 lui a3,0x10 + aa70: 98ae add a7,a7,a1 + aa72: 9e32 add t3,t3,a2 + aa74: 16fd addi a3,a3,-1 + aa76: 03c66463 bltu a2,t3,aa9e <__multiply+0x86> + aa7a: 00805663 blez s0,aa86 <__multiply+0x6e> + aa7e: 1371 addi t1,t1,-4 + aa80: 00032783 lw a5,0(t1) + aa84: cbf1 beqz a5,ab58 <__multiply+0x140> + aa86: c900 sw s0,16(a0) + aa88: 50b2 lw ra,44(sp) + aa8a: 5422 lw s0,40(sp) + aa8c: 5492 lw s1,36(sp) + aa8e: 5902 lw s2,32(sp) + aa90: 49f2 lw s3,28(sp) + aa92: 6145 addi sp,sp,48 + aa94: 8082 ret + aa96: 0007a023 sw zero,0(a5) + aa9a: 0791 addi a5,a5,4 + aa9c: b7c1 j aa5c <__multiply+0x44> + aa9e: 00062f83 lw t6,0(a2) + aaa2: 00dfffb3 and t6,t6,a3 + aaa6: 040f8a63 beqz t6,aafa <__multiply+0xe2> + aaaa: 8f42 mv t5,a6 + aaac: 82ae mv t0,a1 + aaae: 4481 li s1,0 + aab0: 0002a703 lw a4,0(t0) + aab4: 000f2383 lw t2,0(t5) + aab8: 0f11 addi t5,t5,4 + aaba: 00d77eb3 and t4,a4,a3 + aabe: 03fe8eb3 mul t4,t4,t6 + aac2: 00d3f7b3 and a5,t2,a3 + aac6: 0103d393 srli t2,t2,0x10 + aaca: 0291 addi t0,t0,4 + aacc: 9ebe add t4,t4,a5 + aace: 01075793 srli a5,a4,0x10 + aad2: 03f787b3 mul a5,a5,t6 + aad6: 9ea6 add t4,t4,s1 + aad8: 010ed713 srli a4,t4,0x10 + aadc: 00defeb3 and t4,t4,a3 + aae0: 979e add a5,a5,t2 + aae2: 97ba add a5,a5,a4 + aae4: 0107d493 srli s1,a5,0x10 + aae8: 07c2 slli a5,a5,0x10 + aaea: 01d7e7b3 or a5,a5,t4 + aaee: feff2e23 sw a5,-4(t5) + aaf2: fb12efe3 bltu t0,a7,aab0 <__multiply+0x98> + aaf6: 009f2023 sw s1,0(t5) + aafa: 00265283 lhu t0,2(a2) + aafe: 04028a63 beqz t0,ab52 <__multiply+0x13a> + ab02: 00082783 lw a5,0(a6) + ab06: 8ec2 mv t4,a6 + ab08: 8f2e mv t5,a1 + ab0a: 4f81 li t6,0 + ab0c: 000f2703 lw a4,0(t5) + ab10: 002ed383 lhu t2,2(t4) + ab14: 8ff5 and a5,a5,a3 + ab16: 8f75 and a4,a4,a3 + ab18: 02570733 mul a4,a4,t0 + ab1c: 0e91 addi t4,t4,4 + ab1e: 0f11 addi t5,t5,4 + ab20: 971e add a4,a4,t2 + ab22: 977e add a4,a4,t6 + ab24: 01071f93 slli t6,a4,0x10 + ab28: 00ffe7b3 or a5,t6,a5 + ab2c: fefeae23 sw a5,-4(t4) + ab30: ffef5783 lhu a5,-2(t5) + ab34: 000eaf83 lw t6,0(t4) + ab38: 8341 srli a4,a4,0x10 + ab3a: 025787b3 mul a5,a5,t0 + ab3e: 00dfffb3 and t6,t6,a3 + ab42: 97fe add a5,a5,t6 + ab44: 97ba add a5,a5,a4 + ab46: 0107df93 srli t6,a5,0x10 + ab4a: fd1f61e3 bltu t5,a7,ab0c <__multiply+0xf4> + ab4e: 00fea023 sw a5,0(t4) + ab52: 0611 addi a2,a2,4 + ab54: 0811 addi a6,a6,4 + ab56: b705 j aa76 <__multiply+0x5e> + ab58: 147d addi s0,s0,-1 + ab5a: b705 j aa7a <__multiply+0x62> + +0000ab5c <__pow5mult>: + ab5c: 1101 addi sp,sp,-32 + ab5e: ca26 sw s1,20(sp) + ab60: c84a sw s2,16(sp) + ab62: c64e sw s3,12(sp) + ab64: ce06 sw ra,28(sp) + ab66: cc22 sw s0,24(sp) + ab68: c452 sw s4,8(sp) + ab6a: 00367793 andi a5,a2,3 + ab6e: 892a mv s2,a0 + ab70: 84b2 mv s1,a2 + ab72: 89ae mv s3,a1 + ab74: cf89 beqz a5,ab8e <__pow5mult+0x32> + ab76: 17fd addi a5,a5,-1 + ab78: 00002717 auipc a4,0x2 + ab7c: e1070713 addi a4,a4,-496 # c988 + ab80: 078a slli a5,a5,0x2 + ab82: 97ba add a5,a5,a4 + ab84: 4390 lw a2,0(a5) + ab86: 4681 li a3,0 + ab88: c87ff0ef jal ra,a80e <__multadd> + ab8c: 89aa mv s3,a0 + ab8e: 8489 srai s1,s1,0x2 + ab90: cca5 beqz s1,ac08 <__pow5mult+0xac> + ab92: 02492783 lw a5,36(s2) + ab96: ef91 bnez a5,abb2 <__pow5mult+0x56> + ab98: 4541 li a0,16 + ab9a: b45ff0ef jal ra,a6de + ab9e: 02a92223 sw a0,36(s2) + aba2: 00052223 sw zero,4(a0) + aba6: 00052423 sw zero,8(a0) + abaa: 00052023 sw zero,0(a0) + abae: 00052623 sw zero,12(a0) + abb2: 02492a03 lw s4,36(s2) + abb6: 008a2403 lw s0,8(s4) + abba: e819 bnez s0,abd0 <__pow5mult+0x74> + abbc: 27100593 li a1,625 + abc0: 854a mv a0,s2 + abc2: e3bff0ef jal ra,a9fc <__i2b> + abc6: 00aa2423 sw a0,8(s4) + abca: 842a mv s0,a0 + abcc: 00052023 sw zero,0(a0) + abd0: 0014f793 andi a5,s1,1 + abd4: cf81 beqz a5,abec <__pow5mult+0x90> + abd6: 85ce mv a1,s3 + abd8: 8622 mv a2,s0 + abda: 854a mv a0,s2 + abdc: e3dff0ef jal ra,aa18 <__multiply> + abe0: 8a2a mv s4,a0 + abe2: 85ce mv a1,s3 + abe4: 854a mv a0,s2 + abe6: be5ff0ef jal ra,a7ca <_Bfree> + abea: 89d2 mv s3,s4 + abec: 8485 srai s1,s1,0x1 + abee: cc89 beqz s1,ac08 <__pow5mult+0xac> + abf0: 4008 lw a0,0(s0) + abf2: e909 bnez a0,ac04 <__pow5mult+0xa8> + abf4: 8622 mv a2,s0 + abf6: 85a2 mv a1,s0 + abf8: 854a mv a0,s2 + abfa: e1fff0ef jal ra,aa18 <__multiply> + abfe: c008 sw a0,0(s0) + ac00: 00052023 sw zero,0(a0) + ac04: 842a mv s0,a0 + ac06: b7e9 j abd0 <__pow5mult+0x74> + ac08: 40f2 lw ra,28(sp) + ac0a: 4462 lw s0,24(sp) + ac0c: 854e mv a0,s3 + ac0e: 44d2 lw s1,20(sp) + ac10: 4942 lw s2,16(sp) + ac12: 49b2 lw s3,12(sp) + ac14: 4a22 lw s4,8(sp) + ac16: 6105 addi sp,sp,32 + ac18: 8082 ret + +0000ac1a <__lshift>: + ac1a: 7179 addi sp,sp,-48 + ac1c: d226 sw s1,36(sp) + ac1e: 84ae mv s1,a1 + ac20: ce4e sw s3,28(sp) + ac22: 0104a983 lw s3,16(s1) + ac26: d422 sw s0,40(sp) + ac28: 41cc lw a1,4(a1) + ac2a: 40565413 srai s0,a2,0x5 + ac2e: 449c lw a5,8(s1) + ac30: 99a2 add s3,s3,s0 + ac32: d04a sw s2,32(sp) + ac34: ca56 sw s5,20(sp) + ac36: d606 sw ra,44(sp) + ac38: cc52 sw s4,24(sp) + ac3a: 8aaa mv s5,a0 + ac3c: 00198913 addi s2,s3,1 + ac40: 0927c463 blt a5,s2,acc8 <__lshift+0xae> + ac44: 8556 mv a0,s5 + ac46: c632 sw a2,12(sp) + ac48: af7ff0ef jal ra,a73e <_Balloc> + ac4c: 4632 lw a2,12(sp) + ac4e: 01450793 addi a5,a0,20 + ac52: 8a2a mv s4,a0 + ac54: 86be mv a3,a5 + ac56: 4701 li a4,0 + ac58: 0691 addi a3,a3,4 + ac5a: 06874a63 blt a4,s0,acce <__lshift+0xb4> + ac5e: 00045363 bgez s0,ac64 <__lshift+0x4a> + ac62: 4401 li s0,0 + ac64: 4894 lw a3,16(s1) + ac66: 040a slli s0,s0,0x2 + ac68: 00878733 add a4,a5,s0 + ac6c: 068a slli a3,a3,0x2 + ac6e: 01448793 addi a5,s1,20 + ac72: 8a7d andi a2,a2,31 + ac74: 96be add a3,a3,a5 + ac76: c225 beqz a2,acd6 <__lshift+0xbc> + ac78: 02000813 li a6,32 + ac7c: 40c80833 sub a6,a6,a2 + ac80: 4581 li a1,0 + ac82: 4388 lw a0,0(a5) + ac84: 0711 addi a4,a4,4 + ac86: 0791 addi a5,a5,4 + ac88: 00c51533 sll a0,a0,a2 + ac8c: 8dc9 or a1,a1,a0 + ac8e: feb72e23 sw a1,-4(a4) + ac92: ffc7a583 lw a1,-4(a5) + ac96: 0105d5b3 srl a1,a1,a6 + ac9a: fed7e4e3 bltu a5,a3,ac82 <__lshift+0x68> + ac9e: c30c sw a1,0(a4) + aca0: c199 beqz a1,aca6 <__lshift+0x8c> + aca2: 00298913 addi s2,s3,2 + aca6: 197d addi s2,s2,-1 + aca8: 012a2823 sw s2,16(s4) + acac: 8556 mv a0,s5 + acae: 85a6 mv a1,s1 + acb0: b1bff0ef jal ra,a7ca <_Bfree> + acb4: 50b2 lw ra,44(sp) + acb6: 5422 lw s0,40(sp) + acb8: 8552 mv a0,s4 + acba: 5492 lw s1,36(sp) + acbc: 5902 lw s2,32(sp) + acbe: 49f2 lw s3,28(sp) + acc0: 4a62 lw s4,24(sp) + acc2: 4ad2 lw s5,20(sp) + acc4: 6145 addi sp,sp,48 + acc6: 8082 ret + acc8: 0585 addi a1,a1,1 + acca: 0786 slli a5,a5,0x1 + accc: bf95 j ac40 <__lshift+0x26> + acce: fe06ae23 sw zero,-4(a3) # fffc <_data_lma+0x3564> + acd2: 0705 addi a4,a4,1 + acd4: b751 j ac58 <__lshift+0x3e> + acd6: 0791 addi a5,a5,4 + acd8: ffc7a603 lw a2,-4(a5) + acdc: 0711 addi a4,a4,4 + acde: fec72e23 sw a2,-4(a4) + ace2: fed7eae3 bltu a5,a3,acd6 <__lshift+0xbc> + ace6: b7c1 j aca6 <__lshift+0x8c> + +0000ace8 <__mcmp>: + ace8: 491c lw a5,16(a0) + acea: 4998 lw a4,16(a1) + acec: 8f99 sub a5,a5,a4 + acee: e38d bnez a5,ad10 <__mcmp+0x28> + acf0: 070a slli a4,a4,0x2 + acf2: 0551 addi a0,a0,20 + acf4: 05d1 addi a1,a1,20 + acf6: 00e506b3 add a3,a0,a4 + acfa: 95ba add a1,a1,a4 + acfc: 16f1 addi a3,a3,-4 + acfe: 15f1 addi a1,a1,-4 + ad00: 4290 lw a2,0(a3) + ad02: 4198 lw a4,0(a1) + ad04: 00e60863 beq a2,a4,ad14 <__mcmp+0x2c> + ad08: 57fd li a5,-1 + ad0a: 00e66363 bltu a2,a4,ad10 <__mcmp+0x28> + ad0e: 4785 li a5,1 + ad10: 853e mv a0,a5 + ad12: 8082 ret + ad14: fed564e3 bltu a0,a3,acfc <__mcmp+0x14> + ad18: bfe5 j ad10 <__mcmp+0x28> + +0000ad1a <__mdiff>: + ad1a: 1101 addi sp,sp,-32 + ad1c: ca26 sw s1,20(sp) + ad1e: 84ae mv s1,a1 + ad20: c64e sw s3,12(sp) + ad22: 85b2 mv a1,a2 + ad24: 89aa mv s3,a0 + ad26: 8526 mv a0,s1 + ad28: cc22 sw s0,24(sp) + ad2a: ce06 sw ra,28(sp) + ad2c: c84a sw s2,16(sp) + ad2e: 8432 mv s0,a2 + ad30: fb9ff0ef jal ra,ace8 <__mcmp> + ad34: e105 bnez a0,ad54 <__mdiff+0x3a> + ad36: 4581 li a1,0 + ad38: 854e mv a0,s3 + ad3a: a05ff0ef jal ra,a73e <_Balloc> + ad3e: 4785 li a5,1 + ad40: c91c sw a5,16(a0) + ad42: 00052a23 sw zero,20(a0) + ad46: 40f2 lw ra,28(sp) + ad48: 4462 lw s0,24(sp) + ad4a: 44d2 lw s1,20(sp) + ad4c: 4942 lw s2,16(sp) + ad4e: 49b2 lw s3,12(sp) + ad50: 6105 addi sp,sp,32 + ad52: 8082 ret + ad54: 4905 li s2,1 + ad56: 00054663 bltz a0,ad62 <__mdiff+0x48> + ad5a: 87a2 mv a5,s0 + ad5c: 4901 li s2,0 + ad5e: 8426 mv s0,s1 + ad60: 84be mv s1,a5 + ad62: 404c lw a1,4(s0) + ad64: 854e mv a0,s3 + ad66: 9d9ff0ef jal ra,a73e <_Balloc> + ad6a: 01042303 lw t1,16(s0) + ad6e: 0104a883 lw a7,16(s1) + ad72: 01440613 addi a2,s0,20 + ad76: 00231e13 slli t3,t1,0x2 + ad7a: 01448813 addi a6,s1,20 + ad7e: 088a slli a7,a7,0x2 + ad80: 6ec1 lui t4,0x10 + ad82: 01252623 sw s2,12(a0) + ad86: 9e32 add t3,t3,a2 + ad88: 98c2 add a7,a7,a6 + ad8a: 01450693 addi a3,a0,20 + ad8e: 4f01 li t5,0 + ad90: 1efd addi t4,t4,-1 + ad92: 4218 lw a4,0(a2) + ad94: 00082f83 lw t6,0(a6) + ad98: 0691 addi a3,a3,4 + ad9a: 01d775b3 and a1,a4,t4 + ad9e: 01dff7b3 and a5,t6,t4 + ada2: 95fa add a1,a1,t5 + ada4: 8d9d sub a1,a1,a5 + ada6: 010fdf93 srli t6,t6,0x10 + adaa: 01075793 srli a5,a4,0x10 + adae: 41f787b3 sub a5,a5,t6 + adb2: 4105d713 srai a4,a1,0x10 + adb6: 97ba add a5,a5,a4 + adb8: 4107df13 srai t5,a5,0x10 + adbc: 01d5f5b3 and a1,a1,t4 + adc0: 07c2 slli a5,a5,0x10 + adc2: 8fcd or a5,a5,a1 + adc4: 0811 addi a6,a6,4 + adc6: fef6ae23 sw a5,-4(a3) + adca: 0611 addi a2,a2,4 + adcc: fd1863e3 bltu a6,a7,ad92 <__mdiff+0x78> + add0: 65c1 lui a1,0x10 + add2: 15fd addi a1,a1,-1 + add4: 01c66863 bltu a2,t3,ade4 <__mdiff+0xca> + add8: 16f1 addi a3,a3,-4 + adda: 429c lw a5,0(a3) + addc: c795 beqz a5,ae08 <__mdiff+0xee> + adde: 00652823 sw t1,16(a0) + ade2: b795 j ad46 <__mdiff+0x2c> + ade4: 421c lw a5,0(a2) + ade6: 0691 addi a3,a3,4 + ade8: 0611 addi a2,a2,4 + adea: 00b7f733 and a4,a5,a1 + adee: 977a add a4,a4,t5 + adf0: 41075813 srai a6,a4,0x10 + adf4: 83c1 srli a5,a5,0x10 + adf6: 97c2 add a5,a5,a6 + adf8: 4107df13 srai t5,a5,0x10 + adfc: 8f6d and a4,a4,a1 + adfe: 07c2 slli a5,a5,0x10 + ae00: 8fd9 or a5,a5,a4 + ae02: fef6ae23 sw a5,-4(a3) + ae06: b7f9 j add4 <__mdiff+0xba> + ae08: 137d addi t1,t1,-1 + ae0a: b7f9 j add8 <__mdiff+0xbe> + +0000ae0c <__ulp>: + ae0c: 7ff007b7 lui a5,0x7ff00 + ae10: 8dfd and a1,a1,a5 + ae12: fcc007b7 lui a5,0xfcc00 + ae16: 95be add a1,a1,a5 + ae18: 00b05563 blez a1,ae22 <__ulp+0x16> + ae1c: 4781 li a5,0 + ae1e: 853e mv a0,a5 + ae20: 8082 ret + ae22: 40b005b3 neg a1,a1 + ae26: 4145d793 srai a5,a1,0x14 + ae2a: 474d li a4,19 + ae2c: 00f74763 blt a4,a5,ae3a <__ulp+0x2e> + ae30: 000805b7 lui a1,0x80 + ae34: 40f5d5b3 sra a1,a1,a5 + ae38: b7d5 j ae1c <__ulp+0x10> + ae3a: fec78713 addi a4,a5,-20 # fcbfffec <_eusrstack+0xdcbeffec> + ae3e: 46f9 li a3,30 + ae40: 4581 li a1,0 + ae42: 4785 li a5,1 + ae44: fce6cde3 blt a3,a4,ae1e <__ulp+0x12> + ae48: 800007b7 lui a5,0x80000 + ae4c: 00e7d7b3 srl a5,a5,a4 + ae50: b7f9 j ae1e <__ulp+0x12> + +0000ae52 <__b2d>: + ae52: 7179 addi sp,sp,-48 + ae54: d226 sw s1,36(sp) + ae56: 4904 lw s1,16(a0) + ae58: ce4e sw s3,28(sp) + ae5a: 01450993 addi s3,a0,20 + ae5e: 048a slli s1,s1,0x2 + ae60: 94ce add s1,s1,s3 + ae62: d422 sw s0,40(sp) + ae64: ffc4a403 lw s0,-4(s1) + ae68: d04a sw s2,32(sp) + ae6a: c62e sw a1,12(sp) + ae6c: 8522 mv a0,s0 + ae6e: d606 sw ra,44(sp) + ae70: addff0ef jal ra,a94c <__hi0bits> + ae74: 45b2 lw a1,12(sp) + ae76: 02000793 li a5,32 + ae7a: 8f89 sub a5,a5,a0 + ae7c: c19c sw a5,0(a1) + ae7e: 47a9 li a5,10 + ae80: ffc48913 addi s2,s1,-4 + ae84: 02a7cd63 blt a5,a0,aebe <__b2d+0x6c> + ae88: 47ad li a5,11 + ae8a: 8f89 sub a5,a5,a0 + ae8c: 3ff00737 lui a4,0x3ff00 + ae90: 00f456b3 srl a3,s0,a5 + ae94: 8ed9 or a3,a3,a4 + ae96: 4701 li a4,0 + ae98: 0129f463 bgeu s3,s2,aea0 <__b2d+0x4e> + ae9c: ff84a703 lw a4,-8(s1) + aea0: 0555 addi a0,a0,21 + aea2: 00a41533 sll a0,s0,a0 + aea6: 00f757b3 srl a5,a4,a5 + aeaa: 8fc9 or a5,a5,a0 + aeac: 50b2 lw ra,44(sp) + aeae: 5422 lw s0,40(sp) + aeb0: 5492 lw s1,36(sp) + aeb2: 5902 lw s2,32(sp) + aeb4: 49f2 lw s3,28(sp) + aeb6: 853e mv a0,a5 + aeb8: 85b6 mv a1,a3 + aeba: 6145 addi sp,sp,48 + aebc: 8082 ret + aebe: 4781 li a5,0 + aec0: 0129f663 bgeu s3,s2,aecc <__b2d+0x7a> + aec4: ff84a783 lw a5,-8(s1) + aec8: ff848913 addi s2,s1,-8 + aecc: 1555 addi a0,a0,-11 + aece: c905 beqz a0,aefe <__b2d+0xac> + aed0: 02000713 li a4,32 + aed4: 40a70633 sub a2,a4,a0 + aed8: 00c7d733 srl a4,a5,a2 + aedc: 00a41433 sll s0,s0,a0 + aee0: 8c59 or s0,s0,a4 + aee2: 3ff006b7 lui a3,0x3ff00 + aee6: 8ec1 or a3,a3,s0 + aee8: 4701 li a4,0 + aeea: 0129f463 bgeu s3,s2,aef2 <__b2d+0xa0> + aeee: ffc92703 lw a4,-4(s2) + aef2: 00a797b3 sll a5,a5,a0 + aef6: 00c75733 srl a4,a4,a2 + aefa: 8fd9 or a5,a5,a4 + aefc: bf45 j aeac <__b2d+0x5a> + aefe: 3ff006b7 lui a3,0x3ff00 + af02: 8ec1 or a3,a3,s0 + af04: b765 j aeac <__b2d+0x5a> + +0000af06 <__d2b>: + af06: 7179 addi sp,sp,-48 + af08: d422 sw s0,40(sp) + af0a: 842e mv s0,a1 + af0c: 4585 li a1,1 + af0e: d226 sw s1,36(sp) + af10: d04a sw s2,32(sp) + af12: 84b2 mv s1,a2 + af14: ce4e sw s3,28(sp) + af16: cc52 sw s4,24(sp) + af18: 893a mv s2,a4 + af1a: d606 sw ra,44(sp) + af1c: 8a36 mv s4,a3 + af1e: 821ff0ef jal ra,a73e <_Balloc> + af22: 00100737 lui a4,0x100 + af26: fff70793 addi a5,a4,-1 # fffff <_data_lma+0xf3567> + af2a: 8fe5 and a5,a5,s1 + af2c: 80d1 srli s1,s1,0x14 + af2e: 7ff4f493 andi s1,s1,2047 + af32: 89aa mv s3,a0 + af34: e0b5 bnez s1,af98 <__d2b+0x92> + af36: c63e sw a5,12(sp) + af38: c42d beqz s0,afa2 <__d2b+0x9c> + af3a: 0028 addi a0,sp,8 + af3c: c422 sw s0,8(sp) + af3e: a55ff0ef jal ra,a992 <__lo0bits> + af42: 46a2 lw a3,8(sp) + af44: cd21 beqz a0,af9c <__d2b+0x96> + af46: 4732 lw a4,12(sp) + af48: 02000793 li a5,32 + af4c: 8f89 sub a5,a5,a0 + af4e: 00f717b3 sll a5,a4,a5 + af52: 8fd5 or a5,a5,a3 + af54: 00a75733 srl a4,a4,a0 + af58: 00f9aa23 sw a5,20(s3) + af5c: c63a sw a4,12(sp) + af5e: 4432 lw s0,12(sp) + af60: 0089ac23 sw s0,24(s3) + af64: 00803433 snez s0,s0 + af68: 0405 addi s0,s0,1 + af6a: 0089a823 sw s0,16(s3) + af6e: c4b9 beqz s1,afbc <__d2b+0xb6> + af70: bcd48493 addi s1,s1,-1075 + af74: 94aa add s1,s1,a0 + af76: 03500793 li a5,53 + af7a: 009a2023 sw s1,0(s4) + af7e: 40a78533 sub a0,a5,a0 + af82: 00a92023 sw a0,0(s2) + af86: 50b2 lw ra,44(sp) + af88: 5422 lw s0,40(sp) + af8a: 854e mv a0,s3 + af8c: 5492 lw s1,36(sp) + af8e: 5902 lw s2,32(sp) + af90: 49f2 lw s3,28(sp) + af92: 4a62 lw s4,24(sp) + af94: 6145 addi sp,sp,48 + af96: 8082 ret + af98: 8fd9 or a5,a5,a4 + af9a: bf71 j af36 <__d2b+0x30> + af9c: 00d9aa23 sw a3,20(s3) + afa0: bf7d j af5e <__d2b+0x58> + afa2: 0068 addi a0,sp,12 + afa4: 9efff0ef jal ra,a992 <__lo0bits> + afa8: 47b2 lw a5,12(sp) + afaa: 02050513 addi a0,a0,32 + afae: 4405 li s0,1 + afb0: 00f9aa23 sw a5,20(s3) + afb4: 4785 li a5,1 + afb6: 00f9a823 sw a5,16(s3) + afba: bf55 j af6e <__d2b+0x68> + afbc: 00241793 slli a5,s0,0x2 + afc0: bce50513 addi a0,a0,-1074 + afc4: 97ce add a5,a5,s3 + afc6: 00aa2023 sw a0,0(s4) + afca: 4b88 lw a0,16(a5) + afcc: 0416 slli s0,s0,0x5 + afce: 97fff0ef jal ra,a94c <__hi0bits> + afd2: 8c09 sub s0,s0,a0 + afd4: 00892023 sw s0,0(s2) + afd8: b77d j af86 <__d2b+0x80> + +0000afda <__ratio>: + afda: 7179 addi sp,sp,-48 + afdc: d04a sw s2,32(sp) + afde: 892e mv s2,a1 + afe0: 002c addi a1,sp,8 + afe2: d606 sw ra,44(sp) + afe4: d422 sw s0,40(sp) + afe6: d226 sw s1,36(sp) + afe8: ce4e sw s3,28(sp) + afea: cc52 sw s4,24(sp) + afec: 8a2a mv s4,a0 + afee: e65ff0ef jal ra,ae52 <__b2d> + aff2: 89aa mv s3,a0 + aff4: 84ae mv s1,a1 + aff6: 842e mv s0,a1 + aff8: 854a mv a0,s2 + affa: 006c addi a1,sp,12 + affc: e57ff0ef jal ra,ae52 <__b2d> + b000: 01092783 lw a5,16(s2) + b004: 010a2703 lw a4,16(s4) + b008: 46a2 lw a3,8(sp) + b00a: 8f1d sub a4,a4,a5 + b00c: 47b2 lw a5,12(sp) + b00e: 0716 slli a4,a4,0x5 + b010: 8e9d sub a3,a3,a5 + b012: 00d707b3 add a5,a4,a3 + b016: 02f05563 blez a5,b040 <__ratio+0x66> + b01a: 07d2 slli a5,a5,0x14 + b01c: 862e mv a2,a1 + b01e: 00978433 add s0,a5,s1 + b022: 8732 mv a4,a2 + b024: 85a2 mv a1,s0 + b026: 862a mv a2,a0 + b028: 86ba mv a3,a4 + b02a: 854e mv a0,s3 + b02c: 94cfa0ef jal ra,5178 <__divdf3> + b030: 50b2 lw ra,44(sp) + b032: 5422 lw s0,40(sp) + b034: 5492 lw s1,36(sp) + b036: 5902 lw s2,32(sp) + b038: 49f2 lw s3,28(sp) + b03a: 4a62 lw s4,24(sp) + b03c: 6145 addi sp,sp,48 + b03e: 8082 ret + b040: fff00737 lui a4,0xfff00 + b044: 02e787b3 mul a5,a5,a4 + b048: 00b78633 add a2,a5,a1 + b04c: bfd9 j b022 <__ratio+0x48> + +0000b04e <__copybits>: + b04e: fff58793 addi a5,a1,-1 # 7ffff <_data_lma+0x73567> + b052: 4a18 lw a4,16(a2) + b054: 8795 srai a5,a5,0x5 + b056: 0785 addi a5,a5,1 + b058: 078a slli a5,a5,0x2 + b05a: 01460693 addi a3,a2,20 + b05e: 070a slli a4,a4,0x2 + b060: 97aa add a5,a5,a0 + b062: 9736 add a4,a4,a3 + b064: 00e6e563 bltu a3,a4,b06e <__copybits+0x20> + b068: 00f56a63 bltu a0,a5,b07c <__copybits+0x2e> + b06c: 8082 ret + b06e: 0691 addi a3,a3,4 + b070: ffc6a603 lw a2,-4(a3) # 3feffffc <_eusrstack+0x1feefffc> + b074: 0511 addi a0,a0,4 + b076: fec52e23 sw a2,-4(a0) + b07a: b7ed j b064 <__copybits+0x16> + b07c: 0511 addi a0,a0,4 + b07e: fe052e23 sw zero,-4(a0) + b082: b7dd j b068 <__copybits+0x1a> + +0000b084 <__any_on>: + b084: 4914 lw a3,16(a0) + b086: 4055d793 srai a5,a1,0x5 + b08a: 01450713 addi a4,a0,20 + b08e: 02f6c763 blt a3,a5,b0bc <__any_on+0x38> + b092: 00d7df63 bge a5,a3,b0b0 <__any_on+0x2c> + b096: 89fd andi a1,a1,31 + b098: cd81 beqz a1,b0b0 <__any_on+0x2c> + b09a: 00279693 slli a3,a5,0x2 + b09e: 96ba add a3,a3,a4 + b0a0: 4290 lw a2,0(a3) + b0a2: 4505 li a0,1 + b0a4: 00b656b3 srl a3,a2,a1 + b0a8: 00b695b3 sll a1,a3,a1 + b0ac: 00b61e63 bne a2,a1,b0c8 <__any_on+0x44> + b0b0: 078a slli a5,a5,0x2 + b0b2: 97ba add a5,a5,a4 + b0b4: 00f76663 bltu a4,a5,b0c0 <__any_on+0x3c> + b0b8: 4501 li a0,0 + b0ba: 8082 ret + b0bc: 87b6 mv a5,a3 + b0be: bfcd j b0b0 <__any_on+0x2c> + b0c0: 17f1 addi a5,a5,-4 + b0c2: 4394 lw a3,0(a5) + b0c4: dae5 beqz a3,b0b4 <__any_on+0x30> + b0c6: 4505 li a0,1 + b0c8: 8082 ret + +0000b0ca <_calloc_r>: + b0ca: 02c58633 mul a2,a1,a2 + b0ce: 1101 addi sp,sp,-32 + b0d0: cc22 sw s0,24(sp) + b0d2: ce06 sw ra,28(sp) + b0d4: 85b2 mv a1,a2 + b0d6: c632 sw a2,12(sp) + b0d8: 20c1 jal b198 <_malloc_r> + b0da: 842a mv s0,a0 + b0dc: c509 beqz a0,b0e6 <_calloc_r+0x1c> + b0de: 4632 lw a2,12(sp) + b0e0: 4581 li a1,0 + b0e2: aa4f50ef jal ra,386 + b0e6: 8522 mv a0,s0 + b0e8: 40f2 lw ra,28(sp) + b0ea: 4462 lw s0,24(sp) + b0ec: 6105 addi sp,sp,32 + b0ee: 8082 ret + +0000b0f0 <_free_r>: + b0f0: c1dd beqz a1,b196 <_free_r+0xa6> + b0f2: ffc5a783 lw a5,-4(a1) + b0f6: 1141 addi sp,sp,-16 + b0f8: c422 sw s0,8(sp) + b0fa: c606 sw ra,12(sp) + b0fc: c226 sw s1,4(sp) + b0fe: ffc58413 addi s0,a1,-4 + b102: 0007d363 bgez a5,b108 <_free_r+0x18> + b106: 943e add s0,s0,a5 + b108: 84aa mv s1,a0 + b10a: 087000ef jal ra,b990 <__malloc_lock> + b10e: 87018793 addi a5,gp,-1936 # 20000250 <__malloc_free_list> + b112: 439c lw a5,0(a5) + b114: ef81 bnez a5,b12c <_free_r+0x3c> + b116: 00042223 sw zero,4(s0) + b11a: 8681a823 sw s0,-1936(gp) # 20000250 <__malloc_free_list> + b11e: 4422 lw s0,8(sp) + b120: 40b2 lw ra,12(sp) + b122: 8526 mv a0,s1 + b124: 4492 lw s1,4(sp) + b126: 0141 addi sp,sp,16 + b128: 06b0006f j b992 <__malloc_unlock> + b12c: 00f47e63 bgeu s0,a5,b148 <_free_r+0x58> + b130: 4014 lw a3,0(s0) + b132: 00d40733 add a4,s0,a3 + b136: 00e79663 bne a5,a4,b142 <_free_r+0x52> + b13a: 4398 lw a4,0(a5) + b13c: 43dc lw a5,4(a5) + b13e: 9736 add a4,a4,a3 + b140: c018 sw a4,0(s0) + b142: c05c sw a5,4(s0) + b144: bfd9 j b11a <_free_r+0x2a> + b146: 87ba mv a5,a4 + b148: 43d8 lw a4,4(a5) + b14a: c319 beqz a4,b150 <_free_r+0x60> + b14c: fee47de3 bgeu s0,a4,b146 <_free_r+0x56> + b150: 4394 lw a3,0(a5) + b152: 00d78633 add a2,a5,a3 + b156: 00861f63 bne a2,s0,b174 <_free_r+0x84> + b15a: 4010 lw a2,0(s0) + b15c: 96b2 add a3,a3,a2 + b15e: c394 sw a3,0(a5) + b160: 00d78633 add a2,a5,a3 + b164: fac71de3 bne a4,a2,b11e <_free_r+0x2e> + b168: 4310 lw a2,0(a4) + b16a: 4358 lw a4,4(a4) + b16c: 96b2 add a3,a3,a2 + b16e: c394 sw a3,0(a5) + b170: c3d8 sw a4,4(a5) + b172: b775 j b11e <_free_r+0x2e> + b174: 00c47563 bgeu s0,a2,b17e <_free_r+0x8e> + b178: 47b1 li a5,12 + b17a: c09c sw a5,0(s1) + b17c: b74d j b11e <_free_r+0x2e> + b17e: 4010 lw a2,0(s0) + b180: 00c406b3 add a3,s0,a2 + b184: 00d71663 bne a4,a3,b190 <_free_r+0xa0> + b188: 4314 lw a3,0(a4) + b18a: 4358 lw a4,4(a4) + b18c: 96b2 add a3,a3,a2 + b18e: c014 sw a3,0(s0) + b190: c058 sw a4,4(s0) + b192: c3c0 sw s0,4(a5) + b194: b769 j b11e <_free_r+0x2e> + b196: 8082 ret + +0000b198 <_malloc_r>: + b198: 1101 addi sp,sp,-32 + b19a: ca26 sw s1,20(sp) + b19c: 00358493 addi s1,a1,3 + b1a0: 98f1 andi s1,s1,-4 + b1a2: ce06 sw ra,28(sp) + b1a4: cc22 sw s0,24(sp) + b1a6: c84a sw s2,16(sp) + b1a8: c64e sw s3,12(sp) + b1aa: 04a1 addi s1,s1,8 + b1ac: 47b1 li a5,12 + b1ae: 04f4f363 bgeu s1,a5,b1f4 <_malloc_r+0x5c> + b1b2: 44b1 li s1,12 + b1b4: 04b4e263 bltu s1,a1,b1f8 <_malloc_r+0x60> + b1b8: 892a mv s2,a0 + b1ba: 7d6000ef jal ra,b990 <__malloc_lock> + b1be: 87018793 addi a5,gp,-1936 # 20000250 <__malloc_free_list> + b1c2: 4398 lw a4,0(a5) + b1c4: 843a mv s0,a4 + b1c6: e039 bnez s0,b20c <_malloc_r+0x74> + b1c8: 87418793 addi a5,gp,-1932 # 20000254 <__malloc_sbrk_start> + b1cc: 439c lw a5,0(a5) + b1ce: e791 bnez a5,b1da <_malloc_r+0x42> + b1d0: 4581 li a1,0 + b1d2: 854a mv a0,s2 + b1d4: 21cd jal b6b6 <_sbrk_r> + b1d6: 86a1aa23 sw a0,-1932(gp) # 20000254 <__malloc_sbrk_start> + b1da: 85a6 mv a1,s1 + b1dc: 854a mv a0,s2 + b1de: 29e1 jal b6b6 <_sbrk_r> + b1e0: 59fd li s3,-1 + b1e2: 07351963 bne a0,s3,b254 <_malloc_r+0xbc> + b1e6: 47b1 li a5,12 + b1e8: 00f92023 sw a5,0(s2) + b1ec: 854a mv a0,s2 + b1ee: 7a4000ef jal ra,b992 <__malloc_unlock> + b1f2: a029 j b1fc <_malloc_r+0x64> + b1f4: fc04d0e3 bgez s1,b1b4 <_malloc_r+0x1c> + b1f8: 47b1 li a5,12 + b1fa: c11c sw a5,0(a0) + b1fc: 4501 li a0,0 + b1fe: 40f2 lw ra,28(sp) + b200: 4462 lw s0,24(sp) + b202: 44d2 lw s1,20(sp) + b204: 4942 lw s2,16(sp) + b206: 49b2 lw s3,12(sp) + b208: 6105 addi sp,sp,32 + b20a: 8082 ret + b20c: 401c lw a5,0(s0) + b20e: 8f85 sub a5,a5,s1 + b210: 0207cf63 bltz a5,b24e <_malloc_r+0xb6> + b214: 46ad li a3,11 + b216: 00f6f663 bgeu a3,a5,b222 <_malloc_r+0x8a> + b21a: c01c sw a5,0(s0) + b21c: 943e add s0,s0,a5 + b21e: c004 sw s1,0(s0) + b220: a031 j b22c <_malloc_r+0x94> + b222: 405c lw a5,4(s0) + b224: 02871363 bne a4,s0,b24a <_malloc_r+0xb2> + b228: 86f1a823 sw a5,-1936(gp) # 20000250 <__malloc_free_list> + b22c: 854a mv a0,s2 + b22e: 764000ef jal ra,b992 <__malloc_unlock> + b232: 00b40513 addi a0,s0,11 + b236: 00440793 addi a5,s0,4 + b23a: 9961 andi a0,a0,-8 + b23c: 40f50733 sub a4,a0,a5 + b240: df5d beqz a4,b1fe <_malloc_r+0x66> + b242: 943a add s0,s0,a4 + b244: 8f89 sub a5,a5,a0 + b246: c01c sw a5,0(s0) + b248: bf5d j b1fe <_malloc_r+0x66> + b24a: c35c sw a5,4(a4) + b24c: b7c5 j b22c <_malloc_r+0x94> + b24e: 8722 mv a4,s0 + b250: 4040 lw s0,4(s0) + b252: bf95 j b1c6 <_malloc_r+0x2e> + b254: 00350413 addi s0,a0,3 + b258: 9871 andi s0,s0,-4 + b25a: fc8502e3 beq a0,s0,b21e <_malloc_r+0x86> + b25e: 40a405b3 sub a1,s0,a0 + b262: 854a mv a0,s2 + b264: 2989 jal b6b6 <_sbrk_r> + b266: fb351ce3 bne a0,s3,b21e <_malloc_r+0x86> + b26a: bfb5 j b1e6 <_malloc_r+0x4e> + +0000b26c <_realloc_r>: + b26c: e581 bnez a1,b274 <_realloc_r+0x8> + b26e: 85b2 mv a1,a2 + b270: f29ff06f j b198 <_malloc_r> + b274: 1101 addi sp,sp,-32 + b276: cc22 sw s0,24(sp) + b278: ce06 sw ra,28(sp) + b27a: ca26 sw s1,20(sp) + b27c: c84a sw s2,16(sp) + b27e: c64e sw s3,12(sp) + b280: 8432 mv s0,a2 + b282: ee01 bnez a2,b29a <_realloc_r+0x2e> + b284: e6dff0ef jal ra,b0f0 <_free_r> + b288: 4901 li s2,0 + b28a: 40f2 lw ra,28(sp) + b28c: 4462 lw s0,24(sp) + b28e: 854a mv a0,s2 + b290: 44d2 lw s1,20(sp) + b292: 4942 lw s2,16(sp) + b294: 49b2 lw s3,12(sp) + b296: 6105 addi sp,sp,32 + b298: 8082 ret + b29a: 84ae mv s1,a1 + b29c: 89aa mv s3,a0 + b29e: 2ddd jal b994 <_malloc_usable_size_r> + b2a0: 8926 mv s2,s1 + b2a2: fe8574e3 bgeu a0,s0,b28a <_realloc_r+0x1e> + b2a6: 85a2 mv a1,s0 + b2a8: 854e mv a0,s3 + b2aa: eefff0ef jal ra,b198 <_malloc_r> + b2ae: 892a mv s2,a0 + b2b0: dd69 beqz a0,b28a <_realloc_r+0x1e> + b2b2: 85a6 mv a1,s1 + b2b4: 8622 mv a2,s0 + b2b6: c70fb0ef jal ra,6726 + b2ba: 85a6 mv a1,s1 + b2bc: 854e mv a0,s3 + b2be: e33ff0ef jal ra,b0f0 <_free_r> + b2c2: b7e1 j b28a <_realloc_r+0x1e> + +0000b2c4 <__ssputs_r>: + b2c4: 1101 addi sp,sp,-32 + b2c6: c84a sw s2,16(sp) + b2c8: 0085a903 lw s2,8(a1) + b2cc: cc22 sw s0,24(sp) + b2ce: c452 sw s4,8(sp) + b2d0: c05a sw s6,0(sp) + b2d2: ce06 sw ra,28(sp) + b2d4: ca26 sw s1,20(sp) + b2d6: c64e sw s3,12(sp) + b2d8: c256 sw s5,4(sp) + b2da: 842e mv s0,a1 + b2dc: 8b32 mv s6,a2 + b2de: 8a36 mv s4,a3 + b2e0: 0926ee63 bltu a3,s2,b37c <__ssputs_r+0xb8> + b2e4: 00c5d783 lhu a5,12(a1) + b2e8: 4807f713 andi a4,a5,1152 + b2ec: c751 beqz a4,b378 <__ssputs_r+0xb4> + b2ee: 4004 lw s1,0(s0) + b2f0: 498c lw a1,16(a1) + b2f2: 4858 lw a4,20(s0) + b2f4: 8aaa mv s5,a0 + b2f6: 40b489b3 sub s3,s1,a1 + b2fa: 448d li s1,3 + b2fc: 02e484b3 mul s1,s1,a4 + b300: 4709 li a4,2 + b302: 02e4c4b3 div s1,s1,a4 + b306: 00168713 addi a4,a3,1 + b30a: 974e add a4,a4,s3 + b30c: 00e4f363 bgeu s1,a4,b312 <__ssputs_r+0x4e> + b310: 84ba mv s1,a4 + b312: 4007f793 andi a5,a5,1024 + b316: c3d9 beqz a5,b39c <__ssputs_r+0xd8> + b318: 85a6 mv a1,s1 + b31a: 8556 mv a0,s5 + b31c: e7dff0ef jal ra,b198 <_malloc_r> + b320: 892a mv s2,a0 + b322: e50d bnez a0,b34c <__ssputs_r+0x88> + b324: 47b1 li a5,12 + b326: 00faa023 sw a5,0(s5) + b32a: 00c45783 lhu a5,12(s0) + b32e: 557d li a0,-1 + b330: 0407e793 ori a5,a5,64 + b334: 00f41623 sh a5,12(s0) + b338: 40f2 lw ra,28(sp) + b33a: 4462 lw s0,24(sp) + b33c: 44d2 lw s1,20(sp) + b33e: 4942 lw s2,16(sp) + b340: 49b2 lw s3,12(sp) + b342: 4a22 lw s4,8(sp) + b344: 4a92 lw s5,4(sp) + b346: 4b02 lw s6,0(sp) + b348: 6105 addi sp,sp,32 + b34a: 8082 ret + b34c: 480c lw a1,16(s0) + b34e: 864e mv a2,s3 + b350: bd6fb0ef jal ra,6726 + b354: 00c45783 lhu a5,12(s0) + b358: b7f7f793 andi a5,a5,-1153 + b35c: 0807e793 ori a5,a5,128 + b360: 00f41623 sh a5,12(s0) + b364: 01242823 sw s2,16(s0) + b368: c844 sw s1,20(s0) + b36a: 994e add s2,s2,s3 + b36c: 413484b3 sub s1,s1,s3 + b370: 01242023 sw s2,0(s0) + b374: c404 sw s1,8(s0) + b376: 8952 mv s2,s4 + b378: 012a7363 bgeu s4,s2,b37e <__ssputs_r+0xba> + b37c: 8952 mv s2,s4 + b37e: 4008 lw a0,0(s0) + b380: 864a mv a2,s2 + b382: 85da mv a1,s6 + b384: c58fb0ef jal ra,67dc + b388: 441c lw a5,8(s0) + b38a: 4501 li a0,0 + b38c: 412787b3 sub a5,a5,s2 + b390: c41c sw a5,8(s0) + b392: 401c lw a5,0(s0) + b394: 993e add s2,s2,a5 + b396: 01242023 sw s2,0(s0) + b39a: bf79 j b338 <__ssputs_r+0x74> + b39c: 8626 mv a2,s1 + b39e: 8556 mv a0,s5 + b3a0: ecdff0ef jal ra,b26c <_realloc_r> + b3a4: 892a mv s2,a0 + b3a6: fd5d bnez a0,b364 <__ssputs_r+0xa0> + b3a8: 480c lw a1,16(s0) + b3aa: 8556 mv a0,s5 + b3ac: d45ff0ef jal ra,b0f0 <_free_r> + b3b0: bf95 j b324 <__ssputs_r+0x60> + +0000b3b2 <_svfiprintf_r>: + b3b2: 00c5d783 lhu a5,12(a1) + b3b6: 7171 addi sp,sp,-176 + b3b8: d326 sw s1,164(sp) + b3ba: d14a sw s2,160(sp) + b3bc: cf4e sw s3,156(sp) + b3be: d706 sw ra,172(sp) + b3c0: d522 sw s0,168(sp) + b3c2: cd52 sw s4,152(sp) + b3c4: cb56 sw s5,148(sp) + b3c6: c95a sw s6,144(sp) + b3c8: c75e sw s7,140(sp) + b3ca: c562 sw s8,136(sp) + b3cc: c366 sw s9,132(sp) + b3ce: 0807f793 andi a5,a5,128 + b3d2: 89aa mv s3,a0 + b3d4: 892e mv s2,a1 + b3d6: 84b2 mv s1,a2 + b3d8: c3b9 beqz a5,b41e <_svfiprintf_r+0x6c> + b3da: 499c lw a5,16(a1) + b3dc: e3a9 bnez a5,b41e <_svfiprintf_r+0x6c> + b3de: 04000593 li a1,64 + b3e2: c636 sw a3,12(sp) + b3e4: db5ff0ef jal ra,b198 <_malloc_r> + b3e8: 00a92023 sw a0,0(s2) + b3ec: 00a92823 sw a0,16(s2) + b3f0: 46b2 lw a3,12(sp) + b3f2: e115 bnez a0,b416 <_svfiprintf_r+0x64> + b3f4: 47b1 li a5,12 + b3f6: 00f9a023 sw a5,0(s3) + b3fa: 557d li a0,-1 + b3fc: 50ba lw ra,172(sp) + b3fe: 542a lw s0,168(sp) + b400: 549a lw s1,164(sp) + b402: 590a lw s2,160(sp) + b404: 49fa lw s3,156(sp) + b406: 4a6a lw s4,152(sp) + b408: 4ada lw s5,148(sp) + b40a: 4b4a lw s6,144(sp) + b40c: 4bba lw s7,140(sp) + b40e: 4c2a lw s8,136(sp) + b410: 4c9a lw s9,132(sp) + b412: 614d addi sp,sp,176 + b414: 8082 ret + b416: 04000793 li a5,64 + b41a: 00f92a23 sw a5,20(s2) + b41e: 02000793 li a5,32 + b422: 02f10ca3 sb a5,57(sp) + b426: 03000793 li a5,48 + b42a: da02 sw zero,52(sp) + b42c: 02f10d23 sb a5,58(sp) + b430: ce36 sw a3,28(sp) + b432: 02500b93 li s7,37 + b436: 00001a97 auipc s5,0x1 + b43a: 29aa8a93 addi s5,s5,666 # c6d0 <__clz_tab+0x140> + b43e: 4c05 li s8,1 + b440: 4b29 li s6,10 + b442: 8426 mv s0,s1 + b444: 00044783 lbu a5,0(s0) + b448: c399 beqz a5,b44e <_svfiprintf_r+0x9c> + b44a: 09779d63 bne a5,s7,b4e4 <_svfiprintf_r+0x132> + b44e: 40940cb3 sub s9,s0,s1 + b452: 000c8e63 beqz s9,b46e <_svfiprintf_r+0xbc> + b456: 86e6 mv a3,s9 + b458: 8626 mv a2,s1 + b45a: 85ca mv a1,s2 + b45c: 854e mv a0,s3 + b45e: e67ff0ef jal ra,b2c4 <__ssputs_r> + b462: 57fd li a5,-1 + b464: 1af50263 beq a0,a5,b608 <_svfiprintf_r+0x256> + b468: 56d2 lw a3,52(sp) + b46a: 96e6 add a3,a3,s9 + b46c: da36 sw a3,52(sp) + b46e: 00044783 lbu a5,0(s0) + b472: 18078b63 beqz a5,b608 <_svfiprintf_r+0x256> + b476: 57fd li a5,-1 + b478: 00140493 addi s1,s0,1 + b47c: d002 sw zero,32(sp) + b47e: d602 sw zero,44(sp) + b480: d23e sw a5,36(sp) + b482: d402 sw zero,40(sp) + b484: 060101a3 sb zero,99(sp) + b488: dc82 sw zero,120(sp) + b48a: 0004c583 lbu a1,0(s1) + b48e: 4615 li a2,5 + b490: 8556 mv a0,s5 + b492: a92ff0ef jal ra,a724 + b496: 00148413 addi s0,s1,1 + b49a: 5782 lw a5,32(sp) + b49c: e531 bnez a0,b4e8 <_svfiprintf_r+0x136> + b49e: 0107f713 andi a4,a5,16 + b4a2: c709 beqz a4,b4ac <_svfiprintf_r+0xfa> + b4a4: 02000713 li a4,32 + b4a8: 06e101a3 sb a4,99(sp) + b4ac: 0087f713 andi a4,a5,8 + b4b0: c709 beqz a4,b4ba <_svfiprintf_r+0x108> + b4b2: 02b00713 li a4,43 + b4b6: 06e101a3 sb a4,99(sp) + b4ba: 0004c683 lbu a3,0(s1) + b4be: 02a00713 li a4,42 + b4c2: 02e68b63 beq a3,a4,b4f8 <_svfiprintf_r+0x146> + b4c6: 57b2 lw a5,44(sp) + b4c8: 8426 mv s0,s1 + b4ca: 4681 li a3,0 + b4cc: 4625 li a2,9 + b4ce: 00044703 lbu a4,0(s0) + b4d2: 00140593 addi a1,s0,1 + b4d6: fd070713 addi a4,a4,-48 # ffefffd0 <_eusrstack+0xdfeeffd0> + b4da: 06e67463 bgeu a2,a4,b542 <_svfiprintf_r+0x190> + b4de: c68d beqz a3,b508 <_svfiprintf_r+0x156> + b4e0: d63e sw a5,44(sp) + b4e2: a01d j b508 <_svfiprintf_r+0x156> + b4e4: 0405 addi s0,s0,1 + b4e6: bfb9 j b444 <_svfiprintf_r+0x92> + b4e8: 41550533 sub a0,a0,s5 + b4ec: 00ac1533 sll a0,s8,a0 + b4f0: 8fc9 or a5,a5,a0 + b4f2: d03e sw a5,32(sp) + b4f4: 84a2 mv s1,s0 + b4f6: bf51 j b48a <_svfiprintf_r+0xd8> + b4f8: 4772 lw a4,28(sp) + b4fa: 00470693 addi a3,a4,4 + b4fe: 4318 lw a4,0(a4) + b500: ce36 sw a3,28(sp) + b502: 02074963 bltz a4,b534 <_svfiprintf_r+0x182> + b506: d63a sw a4,44(sp) + b508: 00044703 lbu a4,0(s0) + b50c: 02e00793 li a5,46 + b510: 04f71f63 bne a4,a5,b56e <_svfiprintf_r+0x1bc> + b514: 00144703 lbu a4,1(s0) + b518: 02a00793 li a5,42 + b51c: 02f71b63 bne a4,a5,b552 <_svfiprintf_r+0x1a0> + b520: 47f2 lw a5,28(sp) + b522: 0409 addi s0,s0,2 + b524: 00478713 addi a4,a5,4 # 80000004 <_eusrstack+0x5fff0004> + b528: 439c lw a5,0(a5) + b52a: ce3a sw a4,28(sp) + b52c: 0207c163 bltz a5,b54e <_svfiprintf_r+0x19c> + b530: d23e sw a5,36(sp) + b532: a835 j b56e <_svfiprintf_r+0x1bc> + b534: 40e00733 neg a4,a4 + b538: 0027e793 ori a5,a5,2 + b53c: d63a sw a4,44(sp) + b53e: d03e sw a5,32(sp) + b540: b7e1 j b508 <_svfiprintf_r+0x156> + b542: 036787b3 mul a5,a5,s6 + b546: 4685 li a3,1 + b548: 842e mv s0,a1 + b54a: 97ba add a5,a5,a4 + b54c: b749 j b4ce <_svfiprintf_r+0x11c> + b54e: 57fd li a5,-1 + b550: b7c5 j b530 <_svfiprintf_r+0x17e> + b552: 0405 addi s0,s0,1 + b554: d202 sw zero,36(sp) + b556: 4681 li a3,0 + b558: 4781 li a5,0 + b55a: 4625 li a2,9 + b55c: 00044703 lbu a4,0(s0) + b560: 00140593 addi a1,s0,1 + b564: fd070713 addi a4,a4,-48 + b568: 06e67863 bgeu a2,a4,b5d8 <_svfiprintf_r+0x226> + b56c: f2f1 bnez a3,b530 <_svfiprintf_r+0x17e> + b56e: 00044583 lbu a1,0(s0) + b572: 460d li a2,3 + b574: 00001517 auipc a0,0x1 + b578: 16450513 addi a0,a0,356 # c6d8 <__clz_tab+0x148> + b57c: 9a8ff0ef jal ra,a724 + b580: cd11 beqz a0,b59c <_svfiprintf_r+0x1ea> + b582: 00001797 auipc a5,0x1 + b586: 15678793 addi a5,a5,342 # c6d8 <__clz_tab+0x148> + b58a: 8d1d sub a0,a0,a5 + b58c: 04000793 li a5,64 + b590: 00a797b3 sll a5,a5,a0 + b594: 5502 lw a0,32(sp) + b596: 0405 addi s0,s0,1 + b598: 8d5d or a0,a0,a5 + b59a: d02a sw a0,32(sp) + b59c: 00044583 lbu a1,0(s0) + b5a0: 4619 li a2,6 + b5a2: 00001517 auipc a0,0x1 + b5a6: 13a50513 addi a0,a0,314 # c6dc <__clz_tab+0x14c> + b5aa: 00140493 addi s1,s0,1 + b5ae: 02b10c23 sb a1,56(sp) + b5b2: 972ff0ef jal ra,a724 + b5b6: c135 beqz a0,b61a <_svfiprintf_r+0x268> + b5b8: ffffb797 auipc a5,0xffffb + b5bc: 6f278793 addi a5,a5,1778 # 6caa <_printf_float> + b5c0: e795 bnez a5,b5ec <_svfiprintf_r+0x23a> + b5c2: 5702 lw a4,32(sp) + b5c4: 47f2 lw a5,28(sp) + b5c6: 10077713 andi a4,a4,256 + b5ca: cf09 beqz a4,b5e4 <_svfiprintf_r+0x232> + b5cc: 0791 addi a5,a5,4 + b5ce: ce3e sw a5,28(sp) + b5d0: 57d2 lw a5,52(sp) + b5d2: 97d2 add a5,a5,s4 + b5d4: da3e sw a5,52(sp) + b5d6: b5b5 j b442 <_svfiprintf_r+0x90> + b5d8: 036787b3 mul a5,a5,s6 + b5dc: 4685 li a3,1 + b5de: 842e mv s0,a1 + b5e0: 97ba add a5,a5,a4 + b5e2: bfad j b55c <_svfiprintf_r+0x1aa> + b5e4: 079d addi a5,a5,7 + b5e6: 9be1 andi a5,a5,-8 + b5e8: 07a1 addi a5,a5,8 + b5ea: b7d5 j b5ce <_svfiprintf_r+0x21c> + b5ec: 0878 addi a4,sp,28 + b5ee: 00000697 auipc a3,0x0 + b5f2: cd668693 addi a3,a3,-810 # b2c4 <__ssputs_r> + b5f6: 864a mv a2,s2 + b5f8: 100c addi a1,sp,32 + b5fa: 854e mv a0,s3 + b5fc: eaefb0ef jal ra,6caa <_printf_float> + b600: 57fd li a5,-1 + b602: 8a2a mv s4,a0 + b604: fcf516e3 bne a0,a5,b5d0 <_svfiprintf_r+0x21e> + b608: 00c95783 lhu a5,12(s2) + b60c: 557d li a0,-1 + b60e: 0407f793 andi a5,a5,64 + b612: de0795e3 bnez a5,b3fc <_svfiprintf_r+0x4a> + b616: 5552 lw a0,52(sp) + b618: b3d5 j b3fc <_svfiprintf_r+0x4a> + b61a: 0878 addi a4,sp,28 + b61c: 00000697 auipc a3,0x0 + b620: ca868693 addi a3,a3,-856 # b2c4 <__ssputs_r> + b624: 864a mv a2,s2 + b626: 100c addi a1,sp,32 + b628: 854e mv a0,s3 + b62a: c51fb0ef jal ra,727a <_printf_i> + b62e: bfc9 j b600 <_svfiprintf_r+0x24e> + +0000b630 <_putc_r>: + b630: 1101 addi sp,sp,-32 + b632: cc22 sw s0,24(sp) + b634: ce06 sw ra,28(sp) + b636: 842a mv s0,a0 + b638: c909 beqz a0,b64a <_putc_r+0x1a> + b63a: 4d1c lw a5,24(a0) + b63c: e799 bnez a5,b64a <_putc_r+0x1a> + b63e: c632 sw a2,12(sp) + b640: c42e sw a1,8(sp) + b642: ec4fe0ef jal ra,9d06 <__sinit> + b646: 4632 lw a2,12(sp) + b648: 45a2 lw a1,8(sp) + b64a: 00001797 auipc a5,0x1 + b64e: 1fe78793 addi a5,a5,510 # c848 <__sf_fake_stdin> + b652: 02f61663 bne a2,a5,b67e <_putc_r+0x4e> + b656: 4050 lw a2,4(s0) + b658: 461c lw a5,8(a2) + b65a: 17fd addi a5,a5,-1 + b65c: c61c sw a5,8(a2) + b65e: 0407d063 bgez a5,b69e <_putc_r+0x6e> + b662: 4e18 lw a4,24(a2) + b664: 00e7c763 blt a5,a4,b672 <_putc_r+0x42> + b668: 0ff5f793 andi a5,a1,255 + b66c: 4729 li a4,10 + b66e: 02e79863 bne a5,a4,b69e <_putc_r+0x6e> + b672: 8522 mv a0,s0 + b674: 4462 lw s0,24(sp) + b676: 40f2 lw ra,28(sp) + b678: 6105 addi sp,sp,32 + b67a: ceafd06f j 8b64 <__swbuf_r> + b67e: 00001797 auipc a5,0x1 + b682: 1ea78793 addi a5,a5,490 # c868 <__sf_fake_stdout> + b686: 00f61463 bne a2,a5,b68e <_putc_r+0x5e> + b68a: 4410 lw a2,8(s0) + b68c: b7f1 j b658 <_putc_r+0x28> + b68e: 00001797 auipc a5,0x1 + b692: 19a78793 addi a5,a5,410 # c828 <__sf_fake_stderr> + b696: fcf611e3 bne a2,a5,b658 <_putc_r+0x28> + b69a: 4450 lw a2,12(s0) + b69c: bf75 j b658 <_putc_r+0x28> + b69e: 421c lw a5,0(a2) + b6a0: 0ff5f513 andi a0,a1,255 + b6a4: 00178713 addi a4,a5,1 + b6a8: c218 sw a4,0(a2) + b6aa: 00b78023 sb a1,0(a5) + b6ae: 40f2 lw ra,28(sp) + b6b0: 4462 lw s0,24(sp) + b6b2: 6105 addi sp,sp,32 + b6b4: 8082 ret + +0000b6b6 <_sbrk_r>: + b6b6: 1141 addi sp,sp,-16 + b6b8: c422 sw s0,8(sp) + b6ba: 842a mv s0,a0 + b6bc: 852e mv a0,a1 + b6be: 1fffe797 auipc a5,0x1fffe + b6c2: 5a07a923 sw zero,1458(a5) # 20009c70 + b6c6: c606 sw ra,12(sp) + b6c8: fbff80ef jal ra,4686 <_sbrk> + b6cc: 57fd li a5,-1 + b6ce: 00f51963 bne a0,a5,b6e0 <_sbrk_r+0x2a> + b6d2: 1fffe797 auipc a5,0x1fffe + b6d6: 59e78793 addi a5,a5,1438 # 20009c70 + b6da: 439c lw a5,0(a5) + b6dc: c391 beqz a5,b6e0 <_sbrk_r+0x2a> + b6de: c01c sw a5,0(s0) + b6e0: 40b2 lw ra,12(sp) + b6e2: 4422 lw s0,8(sp) + b6e4: 0141 addi sp,sp,16 + b6e6: 8082 ret + +0000b6e8 <_raise_r>: + b6e8: 47fd li a5,31 + b6ea: 00b7f663 bgeu a5,a1,b6f6 <_raise_r+0xe> + b6ee: 47d9 li a5,22 + b6f0: c11c sw a5,0(a0) + b6f2: 557d li a0,-1 + b6f4: 8082 ret + b6f6: 417c lw a5,68(a0) + b6f8: 1101 addi sp,sp,-32 + b6fa: cc22 sw s0,24(sp) + b6fc: ce06 sw ra,28(sp) + b6fe: 862e mv a2,a1 + b700: 842a mv s0,a0 + b702: c791 beqz a5,b70e <_raise_r+0x26> + b704: 00259713 slli a4,a1,0x2 + b708: 97ba add a5,a5,a4 + b70a: 4398 lw a4,0(a5) + b70c: eb19 bnez a4,b722 <_raise_r+0x3a> + b70e: 8522 mv a0,s0 + b710: c632 sw a2,12(sp) + b712: 28a5 jal b78a <_getpid_r> + b714: 85aa mv a1,a0 + b716: 8522 mv a0,s0 + b718: 4462 lw s0,24(sp) + b71a: 4632 lw a2,12(sp) + b71c: 40f2 lw ra,28(sp) + b71e: 6105 addi sp,sp,32 + b720: a81d j b756 <_kill_r> + b722: 4685 li a3,1 + b724: 4501 li a0,0 + b726: 00d70863 beq a4,a3,b736 <_raise_r+0x4e> + b72a: 56fd li a3,-1 + b72c: 00d71963 bne a4,a3,b73e <_raise_r+0x56> + b730: 47d9 li a5,22 + b732: c01c sw a5,0(s0) + b734: 4505 li a0,1 + b736: 40f2 lw ra,28(sp) + b738: 4462 lw s0,24(sp) + b73a: 6105 addi sp,sp,32 + b73c: 8082 ret + b73e: 852e mv a0,a1 + b740: 0007a023 sw zero,0(a5) + b744: 9702 jalr a4 + b746: 4501 li a0,0 + b748: b7fd j b736 <_raise_r+0x4e> + +0000b74a : + b74a: 82c18793 addi a5,gp,-2004 # 2000020c <_impure_ptr> + b74e: 85aa mv a1,a0 + b750: 4388 lw a0,0(a5) + b752: f97ff06f j b6e8 <_raise_r> + +0000b756 <_kill_r>: + b756: 1141 addi sp,sp,-16 + b758: c422 sw s0,8(sp) + b75a: 842a mv s0,a0 + b75c: 852e mv a0,a1 + b75e: 85b2 mv a1,a2 + b760: 1fffe797 auipc a5,0x1fffe + b764: 5007a823 sw zero,1296(a5) # 20009c70 + b768: c606 sw ra,12(sp) + b76a: 077000ef jal ra,bfe0 <_kill> + b76e: 57fd li a5,-1 + b770: 00f51963 bne a0,a5,b782 <_kill_r+0x2c> + b774: 1fffe797 auipc a5,0x1fffe + b778: 4fc78793 addi a5,a5,1276 # 20009c70 + b77c: 439c lw a5,0(a5) + b77e: c391 beqz a5,b782 <_kill_r+0x2c> + b780: c01c sw a5,0(s0) + b782: 40b2 lw ra,12(sp) + b784: 4422 lw s0,8(sp) + b786: 0141 addi sp,sp,16 + b788: 8082 ret + +0000b78a <_getpid_r>: + b78a: 0370006f j bfc0 <_getpid> + +0000b78e <__sread>: + b78e: 1141 addi sp,sp,-16 + b790: c422 sw s0,8(sp) + b792: 842e mv s0,a1 + b794: 00e59583 lh a1,14(a1) + b798: c606 sw ra,12(sp) + b79a: 2439 jal b9a8 <_read_r> + b79c: 00054963 bltz a0,b7ae <__sread+0x20> + b7a0: 487c lw a5,84(s0) + b7a2: 97aa add a5,a5,a0 + b7a4: c87c sw a5,84(s0) + b7a6: 40b2 lw ra,12(sp) + b7a8: 4422 lw s0,8(sp) + b7aa: 0141 addi sp,sp,16 + b7ac: 8082 ret + b7ae: 00c45783 lhu a5,12(s0) + b7b2: 777d lui a4,0xfffff + b7b4: 177d addi a4,a4,-1 + b7b6: 8ff9 and a5,a5,a4 + b7b8: 00f41623 sh a5,12(s0) + b7bc: b7ed j b7a6 <__sread+0x18> + +0000b7be <__swrite>: + b7be: 00c5d783 lhu a5,12(a1) + b7c2: 1101 addi sp,sp,-32 + b7c4: cc22 sw s0,24(sp) + b7c6: ca26 sw s1,20(sp) + b7c8: c84a sw s2,16(sp) + b7ca: c64e sw s3,12(sp) + b7cc: ce06 sw ra,28(sp) + b7ce: 1007f793 andi a5,a5,256 + b7d2: 84aa mv s1,a0 + b7d4: 842e mv s0,a1 + b7d6: 8932 mv s2,a2 + b7d8: 89b6 mv s3,a3 + b7da: c791 beqz a5,b7e6 <__swrite+0x28> + b7dc: 00e59583 lh a1,14(a1) + b7e0: 4689 li a3,2 + b7e2: 4601 li a2,0 + b7e4: 2aa5 jal b95c <_lseek_r> + b7e6: 00c45783 lhu a5,12(s0) + b7ea: 777d lui a4,0xfffff + b7ec: 177d addi a4,a4,-1 + b7ee: 8ff9 and a5,a5,a4 + b7f0: 00f41623 sh a5,12(s0) + b7f4: 00e41583 lh a1,14(s0) + b7f8: 4462 lw s0,24(sp) + b7fa: 40f2 lw ra,28(sp) + b7fc: 86ce mv a3,s3 + b7fe: 864a mv a2,s2 + b800: 49b2 lw s3,12(sp) + b802: 4942 lw s2,16(sp) + b804: 8526 mv a0,s1 + b806: 44d2 lw s1,20(sp) + b808: 6105 addi sp,sp,32 + b80a: a069 j b894 <_write_r> + +0000b80c <__sseek>: + b80c: 1141 addi sp,sp,-16 + b80e: c422 sw s0,8(sp) + b810: 842e mv s0,a1 + b812: 00e59583 lh a1,14(a1) + b816: c606 sw ra,12(sp) + b818: 2291 jal b95c <_lseek_r> + b81a: 57fd li a5,-1 + b81c: 00c45703 lhu a4,12(s0) + b820: 00f51b63 bne a0,a5,b836 <__sseek+0x2a> + b824: 77fd lui a5,0xfffff + b826: 17fd addi a5,a5,-1 + b828: 8ff9 and a5,a5,a4 + b82a: 00f41623 sh a5,12(s0) + b82e: 40b2 lw ra,12(sp) + b830: 4422 lw s0,8(sp) + b832: 0141 addi sp,sp,16 + b834: 8082 ret + b836: 6785 lui a5,0x1 + b838: 8fd9 or a5,a5,a4 + b83a: 00f41623 sh a5,12(s0) + b83e: c868 sw a0,84(s0) + b840: b7fd j b82e <__sseek+0x22> + +0000b842 <__sclose>: + b842: 00e59583 lh a1,14(a1) + b846: a051 j b8ca <_close_r> + +0000b848 : + b848: c605 beqz a2,b870 + b84a: 167d addi a2,a2,-1 + b84c: 4701 li a4,0 + b84e: 00e507b3 add a5,a0,a4 + b852: 00e586b3 add a3,a1,a4 + b856: 0007c783 lbu a5,0(a5) # 1000 + b85a: 0006c683 lbu a3,0(a3) + b85e: 00d79663 bne a5,a3,b86a + b862: 00c70463 beq a4,a2,b86a + b866: 0705 addi a4,a4,1 + b868: f3fd bnez a5,b84e + b86a: 40d78533 sub a0,a5,a3 + b86e: 8082 ret + b870: 4501 li a0,0 + b872: 8082 ret + +0000b874 <__ascii_wctomb>: + b874: cd91 beqz a1,b890 <__ascii_wctomb+0x1c> + b876: 0ff00793 li a5,255 + b87a: 00c7f763 bgeu a5,a2,b888 <__ascii_wctomb+0x14> + b87e: 08a00793 li a5,138 + b882: c11c sw a5,0(a0) + b884: 557d li a0,-1 + b886: 8082 ret + b888: 00c58023 sb a2,0(a1) + b88c: 4505 li a0,1 + b88e: 8082 ret + b890: 4501 li a0,0 + b892: 8082 ret + +0000b894 <_write_r>: + b894: 1141 addi sp,sp,-16 + b896: c422 sw s0,8(sp) + b898: 842a mv s0,a0 + b89a: 852e mv a0,a1 + b89c: 85b2 mv a1,a2 + b89e: 8636 mv a2,a3 + b8a0: 1fffe797 auipc a5,0x1fffe + b8a4: 3c07a823 sw zero,976(a5) # 20009c70 + b8a8: c606 sw ra,12(sp) + b8aa: d9ff80ef jal ra,4648 <_write> + b8ae: 57fd li a5,-1 + b8b0: 00f51963 bne a0,a5,b8c2 <_write_r+0x2e> + b8b4: 1fffe797 auipc a5,0x1fffe + b8b8: 3bc78793 addi a5,a5,956 # 20009c70 + b8bc: 439c lw a5,0(a5) + b8be: c391 beqz a5,b8c2 <_write_r+0x2e> + b8c0: c01c sw a5,0(s0) + b8c2: 40b2 lw ra,12(sp) + b8c4: 4422 lw s0,8(sp) + b8c6: 0141 addi sp,sp,16 + b8c8: 8082 ret + +0000b8ca <_close_r>: + b8ca: 1141 addi sp,sp,-16 + b8cc: c422 sw s0,8(sp) + b8ce: 842a mv s0,a0 + b8d0: 852e mv a0,a1 + b8d2: 1fffe797 auipc a5,0x1fffe + b8d6: 3807af23 sw zero,926(a5) # 20009c70 + b8da: c606 sw ra,12(sp) + b8dc: 25d1 jal bfa0 <_close> + b8de: 57fd li a5,-1 + b8e0: 00f51963 bne a0,a5,b8f2 <_close_r+0x28> + b8e4: 1fffe797 auipc a5,0x1fffe + b8e8: 38c78793 addi a5,a5,908 # 20009c70 + b8ec: 439c lw a5,0(a5) + b8ee: c391 beqz a5,b8f2 <_close_r+0x28> + b8f0: c01c sw a5,0(s0) + b8f2: 40b2 lw ra,12(sp) + b8f4: 4422 lw s0,8(sp) + b8f6: 0141 addi sp,sp,16 + b8f8: 8082 ret + +0000b8fa <_fstat_r>: + b8fa: 1141 addi sp,sp,-16 + b8fc: c422 sw s0,8(sp) + b8fe: 842a mv s0,a0 + b900: 852e mv a0,a1 + b902: 85b2 mv a1,a2 + b904: 1fffe797 auipc a5,0x1fffe + b908: 3607a623 sw zero,876(a5) # 20009c70 + b90c: c606 sw ra,12(sp) + b90e: 254d jal bfb0 <_fstat> + b910: 57fd li a5,-1 + b912: 00f51963 bne a0,a5,b924 <_fstat_r+0x2a> + b916: 1fffe797 auipc a5,0x1fffe + b91a: 35a78793 addi a5,a5,858 # 20009c70 + b91e: 439c lw a5,0(a5) + b920: c391 beqz a5,b924 <_fstat_r+0x2a> + b922: c01c sw a5,0(s0) + b924: 40b2 lw ra,12(sp) + b926: 4422 lw s0,8(sp) + b928: 0141 addi sp,sp,16 + b92a: 8082 ret + +0000b92c <_isatty_r>: + b92c: 1141 addi sp,sp,-16 + b92e: c422 sw s0,8(sp) + b930: 842a mv s0,a0 + b932: 852e mv a0,a1 + b934: 1fffe797 auipc a5,0x1fffe + b938: 3207ae23 sw zero,828(a5) # 20009c70 + b93c: c606 sw ra,12(sp) + b93e: 2d49 jal bfd0 <_isatty> + b940: 57fd li a5,-1 + b942: 00f51963 bne a0,a5,b954 <_isatty_r+0x28> + b946: 1fffe797 auipc a5,0x1fffe + b94a: 32a78793 addi a5,a5,810 # 20009c70 + b94e: 439c lw a5,0(a5) + b950: c391 beqz a5,b954 <_isatty_r+0x28> + b952: c01c sw a5,0(s0) + b954: 40b2 lw ra,12(sp) + b956: 4422 lw s0,8(sp) + b958: 0141 addi sp,sp,16 + b95a: 8082 ret + +0000b95c <_lseek_r>: + b95c: 1141 addi sp,sp,-16 + b95e: c422 sw s0,8(sp) + b960: 842a mv s0,a0 + b962: 852e mv a0,a1 + b964: 85b2 mv a1,a2 + b966: 8636 mv a2,a3 + b968: 1fffe797 auipc a5,0x1fffe + b96c: 3007a423 sw zero,776(a5) # 20009c70 + b970: c606 sw ra,12(sp) + b972: 2dbd jal bff0 <_lseek> + b974: 57fd li a5,-1 + b976: 00f51963 bne a0,a5,b988 <_lseek_r+0x2c> + b97a: 1fffe797 auipc a5,0x1fffe + b97e: 2f678793 addi a5,a5,758 # 20009c70 + b982: 439c lw a5,0(a5) + b984: c391 beqz a5,b988 <_lseek_r+0x2c> + b986: c01c sw a5,0(s0) + b988: 40b2 lw ra,12(sp) + b98a: 4422 lw s0,8(sp) + b98c: 0141 addi sp,sp,16 + b98e: 8082 ret + +0000b990 <__malloc_lock>: + b990: 8082 ret + +0000b992 <__malloc_unlock>: + b992: 8082 ret + +0000b994 <_malloc_usable_size_r>: + b994: ffc5a783 lw a5,-4(a1) + b998: ffc78513 addi a0,a5,-4 + b99c: 0007d563 bgez a5,b9a6 <_malloc_usable_size_r+0x12> + b9a0: 95aa add a1,a1,a0 + b9a2: 419c lw a5,0(a1) + b9a4: 953e add a0,a0,a5 + b9a6: 8082 ret + +0000b9a8 <_read_r>: + b9a8: 1141 addi sp,sp,-16 + b9aa: c422 sw s0,8(sp) + b9ac: 842a mv s0,a0 + b9ae: 852e mv a0,a1 + b9b0: 85b2 mv a1,a2 + b9b2: 8636 mv a2,a3 + b9b4: 1fffe797 auipc a5,0x1fffe + b9b8: 2a07ae23 sw zero,700(a5) # 20009c70 + b9bc: c606 sw ra,12(sp) + b9be: 2589 jal c000 <_read> + b9c0: 57fd li a5,-1 + b9c2: 00f51963 bne a0,a5,b9d4 <_read_r+0x2c> + b9c6: 1fffe797 auipc a5,0x1fffe + b9ca: 2aa78793 addi a5,a5,682 # 20009c70 + b9ce: 439c lw a5,0(a5) + b9d0: c391 beqz a5,b9d4 <_read_r+0x2c> + b9d2: c01c sw a5,0(s0) + b9d4: 40b2 lw ra,12(sp) + b9d6: 4422 lw s0,8(sp) + b9d8: 0141 addi sp,sp,16 + b9da: 8082 ret + +0000b9dc <__unorddf2>: + b9dc: 0145d713 srli a4,a1,0x14 + b9e0: 001007b7 lui a5,0x100 + b9e4: 17fd addi a5,a5,-1 + b9e6: fff74713 not a4,a4 + b9ea: 0146d813 srli a6,a3,0x14 + b9ee: 8dfd and a1,a1,a5 + b9f0: 8ff5 and a5,a5,a3 + b9f2: 01571693 slli a3,a4,0x15 + b9f6: 7ff87813 andi a6,a6,2047 + b9fa: ca99 beqz a3,ba10 <__unorddf2+0x34> + b9fc: 7ff00713 li a4,2047 + ba00: 4501 li a0,0 + ba02: 00e80363 beq a6,a4,ba08 <__unorddf2+0x2c> + ba06: 8082 ret + ba08: 8fd1 or a5,a5,a2 + ba0a: 00f03533 snez a0,a5 + ba0e: 8082 ret + ba10: 8dc9 or a1,a1,a0 + ba12: 4505 li a0,1 + ba14: d5e5 beqz a1,b9fc <__unorddf2+0x20> + ba16: 8082 ret + +0000ba18 <__fixunsdfsi>: + ba18: 0145d793 srli a5,a1,0x14 + ba1c: 001006b7 lui a3,0x100 + ba20: fff68713 addi a4,a3,-1 # fffff <_data_lma+0xf3567> + ba24: 7ff7f793 andi a5,a5,2047 + ba28: 3fe00613 li a2,1022 + ba2c: 882a mv a6,a0 + ba2e: 8f6d and a4,a4,a1 + ba30: 4501 li a0,0 + ba32: 81fd srli a1,a1,0x1f + ba34: 00f65463 bge a2,a5,ba3c <__fixunsdfsi+0x24> + ba38: c199 beqz a1,ba3e <__fixunsdfsi+0x26> + ba3a: 8082 ret + ba3c: 8082 ret + ba3e: 41e00613 li a2,1054 + ba42: 557d li a0,-1 + ba44: fef64be3 blt a2,a5,ba3a <__fixunsdfsi+0x22> + ba48: 43300513 li a0,1075 + ba4c: 8d1d sub a0,a0,a5 + ba4e: 467d li a2,31 + ba50: 8f55 or a4,a4,a3 + ba52: 00a64a63 blt a2,a0,ba66 <__fixunsdfsi+0x4e> + ba56: bed78793 addi a5,a5,-1043 # ffbed <_data_lma+0xf3155> + ba5a: 00f71733 sll a4,a4,a5 + ba5e: 00a85533 srl a0,a6,a0 + ba62: 8d59 or a0,a0,a4 + ba64: 8082 ret + ba66: 41300513 li a0,1043 + ba6a: 40f507b3 sub a5,a0,a5 + ba6e: 00f75533 srl a0,a4,a5 + ba72: 8082 ret + +0000ba74 <__extenddftf2>: + ba74: 01465793 srli a5,a2,0x14 + ba78: 00c61713 slli a4,a2,0xc + ba7c: 7ff7f793 andi a5,a5,2047 + ba80: 7179 addi sp,sp,-48 + ba82: 8331 srli a4,a4,0xc + ba84: 00178693 addi a3,a5,1 + ba88: d422 sw s0,40(sp) + ba8a: d226 sw s1,36(sp) + ba8c: d606 sw ra,44(sp) + ba8e: d04a sw s2,32(sp) + ba90: c82e sw a1,16(sp) + ba92: ca3a sw a4,20(sp) + ba94: ce02 sw zero,28(sp) + ba96: cc02 sw zero,24(sp) + ba98: 7fe6f693 andi a3,a3,2046 + ba9c: 842a mv s0,a0 + ba9e: 01f65493 srli s1,a2,0x1f + baa2: cea1 beqz a3,bafa <__extenddftf2+0x86> + baa4: 6691 lui a3,0x4 + baa6: c0068693 addi a3,a3,-1024 # 3c00 + baaa: 97b6 add a5,a5,a3 + baac: 0045d613 srli a2,a1,0x4 + bab0: 01c71693 slli a3,a4,0x1c + bab4: 07c6 slli a5,a5,0x11 + bab6: 8ed1 or a3,a3,a2 + bab8: 01c59513 slli a0,a1,0x1c + babc: 8311 srli a4,a4,0x4 + babe: 83c5 srli a5,a5,0x11 + bac0: 4801 li a6,0 + bac2: 00e11623 sh a4,12(sp) + bac6: 4732 lw a4,12(sp) + bac8: 07c6 slli a5,a5,0x11 + baca: 800105b7 lui a1,0x80010 + bace: 83c5 srli a5,a5,0x11 + bad0: 15fd addi a1,a1,-1 + bad2: 07c2 slli a5,a5,0x10 + bad4: 8f6d and a4,a4,a1 + bad6: 8fd9 or a5,a5,a4 + bad8: 0786 slli a5,a5,0x1 + bada: 01f49613 slli a2,s1,0x1f + bade: 8385 srli a5,a5,0x1 + bae0: 8fd1 or a5,a5,a2 + bae2: c048 sw a0,4(s0) + bae4: 01042023 sw a6,0(s0) + bae8: c414 sw a3,8(s0) + baea: c45c sw a5,12(s0) + baec: 8522 mv a0,s0 + baee: 50b2 lw ra,44(sp) + baf0: 5422 lw s0,40(sp) + baf2: 5492 lw s1,36(sp) + baf4: 5902 lw s2,32(sp) + baf6: 6145 addi sp,sp,48 + baf8: 8082 ret + bafa: 00b76533 or a0,a4,a1 + bafe: eba5 bnez a5,bb6e <__extenddftf2+0xfa> + bb00: cd59 beqz a0,bb9e <__extenddftf2+0x12a> + bb02: c35d beqz a4,bba8 <__extenddftf2+0x134> + bb04: 853a mv a0,a4 + bb06: b25fa0ef jal ra,662a <__clzsi2> + bb0a: 03150713 addi a4,a0,49 + bb0e: 01f77813 andi a6,a4,31 + bb12: 8715 srai a4,a4,0x5 + bb14: 0a081e63 bnez a6,bbd0 <__extenddftf2+0x15c> + bb18: 0810 addi a2,sp,16 + bb1a: 00271693 slli a3,a4,0x2 + bb1e: 40d606b3 sub a3,a2,a3 + bb22: 888a mv a7,sp + bb24: 00271813 slli a6,a4,0x2 + bb28: 46cc lw a1,12(a3) + bb2a: 010687b3 add a5,a3,a6 + bb2e: 16f1 addi a3,a3,-4 + bb30: c7cc sw a1,12(a5) + bb32: fed89be3 bne a7,a3,bb28 <__extenddftf2+0xb4> + bb36: 177d addi a4,a4,-1 + bb38: 070a slli a4,a4,0x2 + bb3a: 9732 add a4,a4,a2 + bb3c: 00072023 sw zero,0(a4) # fffff000 <_eusrstack+0xdffef000> + bb40: ffc70693 addi a3,a4,-4 + bb44: 00e60963 beq a2,a4,bb56 <__extenddftf2+0xe2> + bb48: 8736 mv a4,a3 + bb4a: 00072023 sw zero,0(a4) + bb4e: ffc70693 addi a3,a4,-4 + bb52: fee61be3 bne a2,a4,bb48 <__extenddftf2+0xd4> + bb56: 6791 lui a5,0x4 + bb58: c0c78793 addi a5,a5,-1012 # 3c0c + bb5c: 8f89 sub a5,a5,a0 + bb5e: 07c6 slli a5,a5,0x11 + bb60: 4842 lw a6,16(sp) + bb62: 4552 lw a0,20(sp) + bb64: 46e2 lw a3,24(sp) + bb66: 01c15703 lhu a4,28(sp) + bb6a: 83c5 srli a5,a5,0x11 + bb6c: bf99 j bac2 <__extenddftf2+0x4e> + bb6e: c115 beqz a0,bb92 <__extenddftf2+0x11e> + bb70: 67a1 lui a5,0x8 + bb72: 00475513 srli a0,a4,0x4 + bb76: 01c71693 slli a3,a4,0x1c + bb7a: 00f56733 or a4,a0,a5 + bb7e: 0045d613 srli a2,a1,0x4 + bb82: 0742 slli a4,a4,0x10 + bb84: 8ed1 or a3,a3,a2 + bb86: 01c59513 slli a0,a1,0x1c + bb8a: 8341 srli a4,a4,0x10 + bb8c: 17fd addi a5,a5,-1 + bb8e: 4801 li a6,0 + bb90: bf0d j bac2 <__extenddftf2+0x4e> + bb92: 67a1 lui a5,0x8 + bb94: 4681 li a3,0 + bb96: 17fd addi a5,a5,-1 + bb98: 4701 li a4,0 + bb9a: 4801 li a6,0 + bb9c: b71d j bac2 <__extenddftf2+0x4e> + bb9e: 4681 li a3,0 + bba0: 4781 li a5,0 + bba2: 4701 li a4,0 + bba4: 4801 li a6,0 + bba6: bf31 j bac2 <__extenddftf2+0x4e> + bba8: 852e mv a0,a1 + bbaa: 892e mv s2,a1 + bbac: a7ffa0ef jal ra,662a <__clzsi2> + bbb0: 05150713 addi a4,a0,81 + bbb4: 01f77813 andi a6,a4,31 + bbb8: 02050513 addi a0,a0,32 + bbbc: 8715 srai a4,a4,0x5 + bbbe: f4080de3 beqz a6,bb18 <__extenddftf2+0xa4> + bbc2: 4789 li a5,2 + bbc4: 00f70663 beq a4,a5,bbd0 <__extenddftf2+0x15c> + bbc8: 4709 li a4,2 + bbca: 0810 addi a2,sp,16 + bbcc: 48b1 li a7,12 + bbce: a835 j bc0a <__extenddftf2+0x196> + bbd0: 40e006b3 neg a3,a4 + bbd4: 068a slli a3,a3,0x2 + bbd6: 0810 addi a2,sp,16 + bbd8: 06b1 addi a3,a3,12 + bbda: 02000e13 li t3,32 + bbde: 96b2 add a3,a3,a2 + bbe0: 00271893 slli a7,a4,0x2 + bbe4: 410e0e33 sub t3,t3,a6 + bbe8: ffc6a583 lw a1,-4(a3) + bbec: 429c lw a5,0(a3) + bbee: 01168333 add t1,a3,a7 + bbf2: 01c5d5b3 srl a1,a1,t3 + bbf6: 010797b3 sll a5,a5,a6 + bbfa: 8ddd or a1,a1,a5 + bbfc: 00b32023 sw a1,0(t1) + bc00: 16f1 addi a3,a3,-4 + bc02: fed613e3 bne a2,a3,bbe8 <__extenddftf2+0x174> + bc06: 4942 lw s2,16(sp) + bc08: 177d addi a4,a4,-1 + bc0a: 101c addi a5,sp,32 + bc0c: 98be add a7,a7,a5 + bc0e: 01091933 sll s2,s2,a6 + bc12: ff28a823 sw s2,-16(a7) # fff0 <_data_lma+0x3558> + bc16: b70d j bb38 <__extenddftf2+0xc4> + +0000bc18 <__truncdfsf2>: + bc18: 0145d693 srli a3,a1,0x14 + bc1c: 00c59793 slli a5,a1,0xc + bc20: 7ff6f693 andi a3,a3,2047 + bc24: 83b1 srli a5,a5,0xc + bc26: 00168613 addi a2,a3,1 + bc2a: 078e slli a5,a5,0x3 + bc2c: 01d55713 srli a4,a0,0x1d + bc30: 7fe67613 andi a2,a2,2046 + bc34: 81fd srli a1,a1,0x1f + bc36: 8f5d or a4,a4,a5 + bc38: 00351893 slli a7,a0,0x3 + bc3c: ce35 beqz a2,bcb8 <__truncdfsf2+0xa0> + bc3e: c8068813 addi a6,a3,-896 + bc42: 0fe00793 li a5,254 + bc46: 0107dd63 bge a5,a6,bc60 <__truncdfsf2+0x48> + bc4a: 4781 li a5,0 + bc4c: 00979513 slli a0,a5,0x9 + bc50: 0ff00693 li a3,255 + bc54: 06de slli a3,a3,0x17 + bc56: 8125 srli a0,a0,0x9 + bc58: 05fe slli a1,a1,0x1f + bc5a: 8d55 or a0,a0,a3 + bc5c: 8d4d or a0,a0,a1 + bc5e: 8082 ret + bc60: 0b005563 blez a6,bd0a <__truncdfsf2+0xf2> + bc64: 00651793 slli a5,a0,0x6 + bc68: 070e slli a4,a4,0x3 + bc6a: 00f037b3 snez a5,a5 + bc6e: 8fd9 or a5,a5,a4 + bc70: 01d8d893 srli a7,a7,0x1d + bc74: 0117e7b3 or a5,a5,a7 + bc78: 0077f713 andi a4,a5,7 + bc7c: 10070163 beqz a4,bd7e <__truncdfsf2+0x166> + bc80: 00f7f713 andi a4,a5,15 + bc84: 4691 li a3,4 + bc86: 00d70363 beq a4,a3,bc8c <__truncdfsf2+0x74> + bc8a: 0791 addi a5,a5,4 + bc8c: 04000737 lui a4,0x4000 + bc90: 8f7d and a4,a4,a5 + bc92: c775 beqz a4,bd7e <__truncdfsf2+0x166> + bc94: 00180713 addi a4,a6,1 + bc98: 0ff00613 li a2,255 + bc9c: 0ff77693 andi a3,a4,255 + bca0: fac705e3 beq a4,a2,bc4a <__truncdfsf2+0x32> + bca4: 079a slli a5,a5,0x6 + bca6: 83a5 srli a5,a5,0x9 + bca8: 00979513 slli a0,a5,0x9 + bcac: 06de slli a3,a3,0x17 + bcae: 8125 srli a0,a0,0x9 + bcb0: 05fe slli a1,a1,0x1f + bcb2: 8d55 or a0,a0,a3 + bcb4: 8d4d or a0,a0,a1 + bcb6: 8082 ret + bcb8: 011767b3 or a5,a4,a7 + bcbc: ee99 bnez a3,bcda <__truncdfsf2+0xc2> + bcbe: cf85 beqz a5,bcf6 <__truncdfsf2+0xde> + bcc0: 4795 li a5,5 + bcc2: 079a slli a5,a5,0x6 + bcc4: 83a5 srli a5,a5,0x9 + bcc6: 00979513 slli a0,a5,0x9 + bcca: 0ff6f693 andi a3,a3,255 + bcce: 06de slli a3,a3,0x17 + bcd0: 8125 srli a0,a0,0x9 + bcd2: 05fe slli a1,a1,0x1f + bcd4: 8d55 or a0,a0,a3 + bcd6: 8d4d or a0,a0,a1 + bcd8: 8082 ret + bcda: dba5 beqz a5,bc4a <__truncdfsf2+0x32> + bcdc: 004007b7 lui a5,0x400 + bce0: 00979513 slli a0,a5,0x9 + bce4: 0ff00693 li a3,255 + bce8: 06de slli a3,a3,0x17 + bcea: 4581 li a1,0 + bcec: 8125 srli a0,a0,0x9 + bcee: 05fe slli a1,a1,0x1f + bcf0: 8d55 or a0,a0,a3 + bcf2: 8d4d or a0,a0,a1 + bcf4: 8082 ret + bcf6: 4781 li a5,0 + bcf8: 00979513 slli a0,a5,0x9 + bcfc: 4681 li a3,0 + bcfe: 06de slli a3,a3,0x17 + bd00: 8125 srli a0,a0,0x9 + bd02: 05fe slli a1,a1,0x1f + bd04: 8d55 or a0,a0,a3 + bd06: 8d4d or a0,a0,a1 + bd08: 8082 ret + bd0a: 57a5 li a5,-23 + bd0c: 04f84863 blt a6,a5,bd5c <__truncdfsf2+0x144> + bd10: 47f9 li a5,30 + bd12: 00800637 lui a2,0x800 + bd16: 410787b3 sub a5,a5,a6 + bd1a: 457d li a0,31 + bd1c: 8e59 or a2,a2,a4 + bd1e: 04f55163 bge a0,a5,bd60 <__truncdfsf2+0x148> + bd22: 5779 li a4,-2 + bd24: 41070733 sub a4,a4,a6 + bd28: 02000513 li a0,32 + bd2c: 00e65733 srl a4,a2,a4 + bd30: 00a78863 beq a5,a0,bd40 <__truncdfsf2+0x128> + bd34: ca268693 addi a3,a3,-862 + bd38: 00d616b3 sll a3,a2,a3 + bd3c: 00d8e8b3 or a7,a7,a3 + bd40: 011037b3 snez a5,a7 + bd44: 8fd9 or a5,a5,a4 + bd46: 0077f713 andi a4,a5,7 + bd4a: 4801 li a6,0 + bd4c: fb15 bnez a4,bc80 <__truncdfsf2+0x68> + bd4e: 00579713 slli a4,a5,0x5 + bd52: 4685 li a3,1 + bd54: f40748e3 bltz a4,bca4 <__truncdfsf2+0x8c> + bd58: 4681 li a3,0 + bd5a: b7a5 j bcc2 <__truncdfsf2+0xaa> + bd5c: 4681 li a3,0 + bd5e: b78d j bcc0 <__truncdfsf2+0xa8> + bd60: c8268693 addi a3,a3,-894 + bd64: 00d89733 sll a4,a7,a3 + bd68: 00e03733 snez a4,a4 + bd6c: 00d616b3 sll a3,a2,a3 + bd70: 00f8d8b3 srl a7,a7,a5 + bd74: 00d767b3 or a5,a4,a3 + bd78: 00f8e7b3 or a5,a7,a5 + bd7c: b7e9 j bd46 <__truncdfsf2+0x12e> + bd7e: 86c2 mv a3,a6 + bd80: b789 j bcc2 <__truncdfsf2+0xaa> + +0000bd82 <__trunctfdf2>: + bd82: 00c52803 lw a6,12(a0) + bd86: 4118 lw a4,0(a0) + bd88: 4154 lw a3,4(a0) + bd8a: 450c lw a1,8(a0) + bd8c: 6521 lui a0,0x8 + bd8e: fff50793 addi a5,a0,-1 # 7fff <_strtod_l+0x317> + bd92: 01085613 srli a2,a6,0x10 + bd96: 00359e13 slli t3,a1,0x3 + bd9a: 8e7d and a2,a2,a5 + bd9c: 01d75893 srli a7,a4,0x1d + bda0: 01d6d793 srli a5,a3,0x1d + bda4: 01081313 slli t1,a6,0x10 + bda8: 068e slli a3,a3,0x3 + bdaa: 1141 addi sp,sp,-16 + bdac: 01c7e7b3 or a5,a5,t3 + bdb0: 0116e6b3 or a3,a3,a7 + bdb4: 01035313 srli t1,t1,0x10 + bdb8: 00371e13 slli t3,a4,0x3 + bdbc: 00160893 addi a7,a2,1 # 800001 <_data_lma+0x7f3569> + bdc0: 1579 addi a0,a0,-2 + bdc2: 81f5 srli a1,a1,0x1d + bdc4: 030e slli t1,t1,0x3 + bdc6: c43e sw a5,8(sp) + bdc8: c236 sw a3,4(sp) + bdca: c072 sw t3,0(sp) + bdcc: 00a8f533 and a0,a7,a0 + bdd0: 01f85813 srli a6,a6,0x1f + bdd4: 0065e5b3 or a1,a1,t1 + bdd8: c905 beqz a0,be08 <__trunctfdf2+0x86> + bdda: 7771 lui a4,0xffffc + bddc: 40070713 addi a4,a4,1024 # ffffc400 <_eusrstack+0xdffec400> + bde0: 963a add a2,a2,a4 + bde2: 7fe00713 li a4,2046 + bde6: 04c75d63 bge a4,a2,be40 <__trunctfdf2+0xbe> + bdea: 7ff00613 li a2,2047 + bdee: 4701 li a4,0 + bdf0: 4781 li a5,0 + bdf2: 0732 slli a4,a4,0xc + bdf4: 0652 slli a2,a2,0x14 + bdf6: 8331 srli a4,a4,0xc + bdf8: 087e slli a6,a6,0x1f + bdfa: 8f51 or a4,a4,a2 + bdfc: 01076733 or a4,a4,a6 + be00: 853e mv a0,a5 + be02: 85ba mv a1,a4 + be04: 0141 addi sp,sp,16 + be06: 8082 ret + be08: 8fd5 or a5,a5,a3 + be0a: 8fcd or a5,a5,a1 + be0c: 01c7e7b3 or a5,a5,t3 + be10: e205 bnez a2,be30 <__trunctfdf2+0xae> + be12: cbf1 beqz a5,bee6 <__trunctfdf2+0x164> + be14: 4781 li a5,0 + be16: 4695 li a3,5 + be18: 0036d593 srli a1,a3,0x3 + be1c: 00979713 slli a4,a5,0x9 + be20: 01d79693 slli a3,a5,0x1d + be24: 00b6e7b3 or a5,a3,a1 + be28: 8331 srli a4,a4,0xc + be2a: 7ff67613 andi a2,a2,2047 + be2e: b7d1 j bdf2 <__trunctfdf2+0x70> + be30: dfcd beqz a5,bdea <__trunctfdf2+0x68> + be32: 4801 li a6,0 + be34: 7ff00613 li a2,2047 + be38: 00080737 lui a4,0x80 + be3c: 4781 li a5,0 + be3e: bf55 j bdf2 <__trunctfdf2+0x70> + be40: 0ac04663 bgtz a2,beec <__trunctfdf2+0x16a> + be44: fcc00793 li a5,-52 + be48: 0ef64f63 blt a2,a5,bf46 <__trunctfdf2+0x1c4> + be4c: 03d00793 li a5,61 + be50: 40c78633 sub a2,a5,a2 + be54: 40565793 srai a5,a2,0x5 + be58: 00080737 lui a4,0x80 + be5c: 8dd9 or a1,a1,a4 + be5e: 00279513 slli a0,a5,0x2 + be62: 870a mv a4,sp + be64: 4681 li a3,0 + be66: c62e sw a1,12(sp) + be68: 00a108b3 add a7,sp,a0 + be6c: 0711 addi a4,a4,4 + be6e: 8a7d andi a2,a2,31 + be70: 01c6e6b3 or a3,a3,t3 + be74: 01170963 beq a4,a7,be86 <__trunctfdf2+0x104> + be78: 00072e03 lw t3,0(a4) # 80000 <_data_lma+0x73568> + be7c: 0711 addi a4,a4,4 + be7e: 01c6e6b3 or a3,a3,t3 + be82: ff171be3 bne a4,a7,be78 <__trunctfdf2+0xf6> + be86: 470d li a4,3 + be88: 8f1d sub a4,a4,a5 + be8a: ca79 beqz a2,bf60 <__trunctfdf2+0x1de> + be8c: 01010893 addi a7,sp,16 + be90: 98aa add a7,a7,a0 + be92: ff08a883 lw a7,-16(a7) + be96: 02000e13 li t3,32 + be9a: 40ce0e33 sub t3,t3,a2 + be9e: 01c898b3 sll a7,a7,t3 + bea2: 0116e6b3 or a3,a3,a7 + bea6: cb75 beqz a4,bf9a <__trunctfdf2+0x218> + bea8: 070a slli a4,a4,0x2 + beaa: 950a add a0,a0,sp + beac: 00e10eb3 add t4,sp,a4 + beb0: 888a mv a7,sp + beb2: 410c lw a1,0(a0) + beb4: 00452303 lw t1,4(a0) + beb8: 0891 addi a7,a7,4 + beba: 00c5d5b3 srl a1,a1,a2 + bebe: 01c31333 sll t1,t1,t3 + bec2: 0065e5b3 or a1,a1,t1 + bec6: feb8ae23 sw a1,-4(a7) + beca: 0511 addi a0,a0,4 + becc: ff1e93e3 bne t4,a7,beb2 <__trunctfdf2+0x130> + bed0: 4591 li a1,4 + bed2: 40f587b3 sub a5,a1,a5 + bed6: 45b2 lw a1,12(sp) + bed8: 0808 addi a0,sp,16 + beda: 972a add a4,a4,a0 + bedc: 00c5d5b3 srl a1,a1,a2 + bee0: feb72823 sw a1,-16(a4) + bee4: a861 j bf7c <__trunctfdf2+0x1fa> + bee6: 4601 li a2,0 + bee8: 4701 li a4,0 + beea: b721 j bdf2 <__trunctfdf2+0x70> + beec: 00469713 slli a4,a3,0x4 + bef0: 00479513 slli a0,a5,0x4 + bef4: 01c76733 or a4,a4,t3 + bef8: 82f1 srli a3,a3,0x1c + befa: 83f1 srli a5,a5,0x1c + befc: 0592 slli a1,a1,0x4 + befe: 00e03733 snez a4,a4 + bf02: 8ec9 or a3,a3,a0 + bf04: 8fcd or a5,a5,a1 + bf06: 8ed9 or a3,a3,a4 + bf08: 0076f713 andi a4,a3,7 + bf0c: c711 beqz a4,bf18 <__trunctfdf2+0x196> + bf0e: 00f6f713 andi a4,a3,15 + bf12: 4591 li a1,4 + bf14: 02b71c63 bne a4,a1,bf4c <__trunctfdf2+0x1ca> + bf18: 00800737 lui a4,0x800 + bf1c: 8f7d and a4,a4,a5 + bf1e: ee070de3 beqz a4,be18 <__trunctfdf2+0x96> + bf22: 0605 addi a2,a2,1 + bf24: 7ff00713 li a4,2047 + bf28: ece601e3 beq a2,a4,bdea <__trunctfdf2+0x68> + bf2c: ff800737 lui a4,0xff800 + bf30: 177d addi a4,a4,-1 + bf32: 8f7d and a4,a4,a5 + bf34: 01d71793 slli a5,a4,0x1d + bf38: 828d srli a3,a3,0x3 + bf3a: 0726 slli a4,a4,0x9 + bf3c: 7ff67613 andi a2,a2,2047 + bf40: 8fd5 or a5,a5,a3 + bf42: 8331 srli a4,a4,0xc + bf44: b57d j bdf2 <__trunctfdf2+0x70> + bf46: 4685 li a3,1 + bf48: 4781 li a5,0 + bf4a: 4601 li a2,0 + bf4c: ffc6b713 sltiu a4,a3,-4 + bf50: 00174713 xori a4,a4,1 + bf54: 97ba add a5,a5,a4 + bf56: 00800737 lui a4,0x800 + bf5a: 0691 addi a3,a3,4 + bf5c: 8f7d and a4,a4,a5 + bf5e: b7c1 j bf1e <__trunctfdf2+0x19c> + bf60: 858a mv a1,sp + bf62: 00a588b3 add a7,a1,a0 + bf66: 0008a883 lw a7,0(a7) + bf6a: 0591 addi a1,a1,4 + bf6c: 0605 addi a2,a2,1 + bf6e: ff15ae23 sw a7,-4(a1) # 8000fffc <_eusrstack+0x5ffffffc> + bf72: fec758e3 bge a4,a2,bf62 <__trunctfdf2+0x1e0> + bf76: 4711 li a4,4 + bf78: 40f707b3 sub a5,a4,a5 + bf7c: 078a slli a5,a5,0x2 + bf7e: 978a add a5,a5,sp + bf80: 0818 addi a4,sp,16 + bf82: 0007a023 sw zero,0(a5) # 400000 <_data_lma+0x3f3568> + bf86: 0791 addi a5,a5,4 + bf88: fee79de3 bne a5,a4,bf82 <__trunctfdf2+0x200> + bf8c: 4702 lw a4,0(sp) + bf8e: 00d036b3 snez a3,a3 + bf92: 4792 lw a5,4(sp) + bf94: 8ed9 or a3,a3,a4 + bf96: 4601 li a2,0 + bf98: bf85 j bf08 <__trunctfdf2+0x186> + bf9a: 4785 li a5,1 + bf9c: 4701 li a4,0 + bf9e: bf2d j bed8 <__trunctfdf2+0x156> + +0000bfa0 <_close>: + bfa0: 05800793 li a5,88 + bfa4: 1fffe717 auipc a4,0x1fffe + bfa8: ccf72623 sw a5,-820(a4) # 20009c70 + bfac: 557d li a0,-1 + bfae: 8082 ret + +0000bfb0 <_fstat>: + bfb0: 05800793 li a5,88 + bfb4: 1fffe717 auipc a4,0x1fffe + bfb8: caf72e23 sw a5,-836(a4) # 20009c70 + bfbc: 557d li a0,-1 + bfbe: 8082 ret + +0000bfc0 <_getpid>: + bfc0: 05800793 li a5,88 + bfc4: 1fffe717 auipc a4,0x1fffe + bfc8: caf72623 sw a5,-852(a4) # 20009c70 + bfcc: 557d li a0,-1 + bfce: 8082 ret + +0000bfd0 <_isatty>: + bfd0: 05800793 li a5,88 + bfd4: 1fffe717 auipc a4,0x1fffe + bfd8: c8f72e23 sw a5,-868(a4) # 20009c70 + bfdc: 4501 li a0,0 + bfde: 8082 ret + +0000bfe0 <_kill>: + bfe0: 05800793 li a5,88 + bfe4: 1fffe717 auipc a4,0x1fffe + bfe8: c8f72623 sw a5,-884(a4) # 20009c70 + bfec: 557d li a0,-1 + bfee: 8082 ret + +0000bff0 <_lseek>: + bff0: 05800793 li a5,88 + bff4: 1fffe717 auipc a4,0x1fffe + bff8: c6f72e23 sw a5,-900(a4) # 20009c70 + bffc: 557d li a0,-1 + bffe: 8082 ret + +0000c000 <_read>: + c000: 05800793 li a5,88 + c004: 1fffe717 auipc a4,0x1fffe + c008: c6f72623 sw a5,-916(a4) # 20009c70 + c00c: 557d li a0,-1 + c00e: 8082 ret + +0000c010 <_exit>: + c010: a001 j c010 <_exit> + c012: 0000 unimp + c014: c484 sw s1,8(s1) + c016: 0000 unimp + c018: c48c sw a1,8(s1) + c01a: 0000 unimp + c01c: c494 sw a3,8(s1) + c01e: 0000 unimp + c020: c478 sw a4,76(s0) + c022: 0000 unimp + c024: c470 sw a2,76(s0) + c026: 0000 unimp + c028: c49c sw a5,8(s1) + c02a: 0000 unimp + c02c: c4a4 sw s1,72(s1) + c02e: 0000 unimp + c030: c220 sw s0,64(a2) + c032: 0000 unimp + c034: c4ac sw a1,72(s1) + c036: 0000 unimp + c038: c4b4 sw a3,72(s1) + c03a: 0000 unimp + c03c: c4bc sw a5,72(s1) + c03e: 0000 unimp + c040: c4c0 sw s0,12(s1) + c042: 0000 unimp + c044: 7325 lui t1,0xfffe9 + c046: 7325 lui t1,0xfffe9 + c048: 0000 unimp + c04a: 0000 unimp + c04c: 74737953 0x74737953 + c050: 6d65 lui s10,0x19 + c052: 3a6b6c43 fmadd.d fs8,fs6,ft6,ft7,unknown + c056: 6425 lui s0,0x9 + c058: 0a0d addi s4,s4,3 + c05a: 0000 unimp + c05c: 2e32 lhu a2,26(a2) + c05e: 2e34 lbu a3,26(a2) + c060: 0035 c.nop 13 + c062: 0000 unimp + c064: 636c6557 0x636c6557 + c068: 20656d6f jal s10,6226e <_data_lma+0x557d6> + c06c: 6f74 flw fa3,92(a4) + c06e: 5420 lw s0,104(s0) + c070: 6e65 lui t3,0x19 + c072: 746e6563 bltu t3,t1,c7bc + c076: 7420534f 0x7420534f + c07a: 6e69 lui t3,0x1a + c07c: 2879 jal c11a <_exit+0x10a> + c07e: 7325 lui t1,0xfffe9 + c080: 0d29 addi s10,s10,10 + c082: 000a c.slli zero,0x2 + c084: 6174 flw fa3,68(a0) + c086: 00316b73 csrrsi s6,fcsr,2 + c08a: 0000 unimp + c08c: 6174 flw fa3,68(a0) + c08e: 00326b73 csrrsi s6,fcsr,4 + c092: 0000 unimp + c094: 756f6873 csrrsi a6,0x756,30 + c098: 646c flw fa1,76(s0) + c09a: 6e20 flw fs0,88(a2) + c09c: 7220746f jal s0,137be <_data_lma+0x6d26> + c0a0: 6e75 lui t3,0x1d + c0a2: 6120 flw fs0,64(a0) + c0a4: 2074 lbu a3,6(s0) + c0a6: 6568 flw fa0,76(a0) + c0a8: 6572 flw fa0,28(sp) + c0aa: 0d21 addi s10,s10,8 + c0ac: 0000 unimp + c0ae: 0000 unimp + c0b0: 49232323 sw s2,1158(t1) # fffe9486 <_eusrstack+0xdffd9486> + c0b4: 6120 flw fs0,64(a0) + c0b6: 206d jal c160 <_exit+0x150> + c0b8: 6174 flw fa3,68(a0) + c0ba: 0d316b73 csrrsi s6,0xd3,2 + c0be: 0000 unimp + c0c0: 7270 flw fa2,100(a2) + c0c2: 6e69 lui t3,0x1a + c0c4: 0074 addi a3,sp,12 + c0c6: 0000 unimp + c0c8: 656c flw fa1,76(a0) + c0ca: 2074 lbu a3,6(s0) + c0cc: 2061 jal c154 <_exit+0x144> + c0ce: 203d jal c0fc <_exit+0xec> + c0d0: 3b31 jal bdec <__trunctfdf2+0x6a> + c0d2: 0000 unimp + c0d4: 2061 jal c15c <_exit+0x14c> + c0d6: 3d2a lhu a0,58(a0) + c0d8: 3220 lbu s0,3(a2) + c0da: 7270203b 0x7270203b + c0de: 6e69 lui t3,0x1a + c0e0: 2874 lbu a3,22(s0) + c0e2: 73657227 0x73657227 + c0e6: 273a lhu a4,10(a4) + c0e8: 202c lbu a1,2(s0) + c0ea: 2961 jal c582 <_exit+0x572> + c0ec: 0000003b 0x3b + c0f0: 0a44 addi s1,sp,276 + c0f2: 0000 unimp + c0f4: 0a62 slli s4,s4,0x18 + c0f6: 0000 unimp + c0f8: 0ad4 addi a3,sp,340 + c0fa: 0000 unimp + c0fc: 0b04 addi s1,sp,400 + c0fe: 0000 unimp + c100: 0b1e slli s6,s6,0x7 + c102: 0000 unimp + c104: 0d72 slli s10,s10,0x1c + c106: 0000 unimp + c108: 0d72 slli s10,s10,0x1c + c10a: 0000 unimp + c10c: 0b82 c.slli64 s7 + c10e: 0000 unimp + c110: 0d72 slli s10,s10,0x1c + c112: 0000 unimp + c114: 0d72 slli s10,s10,0x1c + c116: 0000 unimp + c118: 0bce slli s7,s7,0x13 + c11a: 0000 unimp + c11c: 0d72 slli s10,s10,0x1c + c11e: 0000 unimp + c120: 0bea slli s7,s7,0x1a + c122: 0000 unimp + c124: 0d72 slli s10,s10,0x1c + c126: 0000 unimp + c128: 0d72 slli s10,s10,0x1c + c12a: 0000 unimp + c12c: 0d72 slli s10,s10,0x1c + c12e: 0000 unimp + c130: 0c1e slli s8,s8,0x7 + c132: 0000 unimp + c134: 0c3a slli s8,s8,0xe + c136: 0000 unimp + c138: 0c56 slli s8,s8,0x15 + c13a: 0000 unimp + c13c: 0cd2 slli s9,s9,0x14 + c13e: 0000 unimp + c140: 0cee slli s9,s9,0x1b + c142: 0000 unimp + c144: 0d22 slli s10,s10,0x8 + c146: 0000 unimp + c148: 0d72 slli s10,s10,0x1c + c14a: 0000 unimp + c14c: 0d56 slli s10,s10,0x15 + c14e: 0000 unimp + c150: 127a slli tp,tp,0x3e + c152: 0000 unimp + c154: 1406 slli s0,s0,0x21 + c156: 0000 unimp + c158: 134c addi a1,sp,420 + c15a: 0000 unimp + c15c: 1236 slli tp,tp,0x2d + c15e: 0000 unimp + c160: 124e slli tp,tp,0x33 + c162: 0000 unimp + c164: 1390 addi a2,sp,480 + c166: 0000 unimp + c168: 125a slli tp,tp,0x36 + c16a: 0000 unimp + c16c: 13c8 addi a0,sp,484 + c16e: 0000 unimp + c170: 1412 slli s0,s0,0x24 + c172: 0000 unimp + c174: 13f2 slli t2,t2,0x3c + c176: 0000 unimp + c178: 20da lhu a4,4(s1) + c17a: 0000 unimp + c17c: 21e6 lhu s1,6(a1) + c17e: 0000 unimp + c180: 21e6 lhu s1,6(a1) + c182: 0000 unimp + c184: 21e6 lhu s1,6(a1) + c186: 0000 unimp + c188: 209c lbu a5,0(s1) + c18a: 0000 unimp + c18c: 208e lhu a1,0(s1) + c18e: 0000 unimp + c190: 21e6 lhu s1,6(a1) + c192: 0000 unimp + c194: 2202 lhu s0,0(a2) + c196: 0000 unimp + c198: 2082 lhu s0,0(s1) + c19a: 0000 unimp + c19c: 21e6 lhu s1,6(a1) + c19e: 0000 unimp + c1a0: 201a lhu a4,0(s0) + c1a2: 0000 unimp + c1a4: 1fca slli t6,t6,0x32 + c1a6: 0000 unimp + c1a8: 1ff0 addi a2,sp,1020 + c1aa: 0000 unimp + c1ac: 2028 lbu a0,2(s0) + c1ae: 0000 unimp + c1b0: 2036 lhu a3,2(s0) + c1b2: 0000 unimp + c1b4: 20aa lhu a0,2(s1) + c1b6: 0000 unimp + c1b8: 20c2 lhu s0,4(s1) + c1ba: 0000 unimp + c1bc: 21e6 lhu s1,6(a1) + c1be: 0000 unimp + c1c0: 219a lhu a4,0(a1) + c1c2: 0000 unimp + c1c4: 21ac lbu a1,2(a1) + c1c6: 0000 unimp + c1c8: 21be lhu a5,2(a1) + c1ca: 0000 unimp + c1cc: 21d0 lbu a2,4(a1) + c1ce: 0000 unimp + c1d0: 2166 lhu s1,6(a0) + c1d2: 0000 unimp + c1d4: 2180 lbu s0,0(a1) + c1d6: 0000 unimp + c1d8: 2056 lhu a3,4(s0) + c1da: 0000 unimp + c1dc: 203c lbu a5,2(s0) + c1de: 0000 unimp + c1e0: 206c lbu a1,6(s0) + c1e2: 0000 unimp + c1e4: 1b24 addi s1,sp,440 + c1e6: 0000 unimp + c1e8: 1e30 addi a2,sp,824 + c1ea: 0000 unimp + c1ec: 1e46 slli t3,t3,0x31 + c1ee: 0000 unimp + c1f0: 1e56 slli t3,t3,0x35 + c1f2: 0000 unimp + c1f4: 1e80 addi s0,sp,880 + c1f6: 0000 unimp + c1f8: 1ad0 addi a2,sp,372 + c1fa: 0000 unimp + c1fc: 00003f3f 20646162 0x2064616200003f3f + c204: 686c flw fa1,84(s0) + c206: 61620073 0x61620073 + c20a: 2064 lbu s1,6(s0) + c20c: 6c6c6163 bltu s8,t1,c8ce <__mprec_tens+0xe> + c210: 0000 unimp + c212: 0000 unimp + c214: 6c6c6163 bltu s8,t1,c8d6 <__mprec_tens+0x16> + c218: 6e69 lui t3,0x1a + c21a: 6f6e2067 0x6f6e2067 + c21e: 2d6e lhu a1,30(a0) + c220: 7566 flw fa0,120(sp) + c222: 636e flw ft6,216(sp) + c224: 6974 flw fa3,84(a0) + c226: 00006e6f jal t3,12226 <_data_lma+0x578e> + c22a: 0000 unimp + c22c: 6c6c6163 bltu s8,t1,c8ee <__mprec_tens+0x2e> + c230: 6f20 flw fs0,88(a4) + c232: 00006d6f jal s10,12232 <_data_lma+0x579a> + c236: 0000 unimp + c238: 6162 flw ft2,24(sp) + c23a: 2064 lbu s1,6(s0) + c23c: 20727473 csrrci s0,0x207,4 + c240: 0000706f j 13240 <_data_lma+0x67a8> + c244: 7974 flw fa3,116(a0) + c246: 6570 flw fa2,76(a0) + c248: 6d20 flw fs0,88(a0) + c24a: 7369 lui t1,0xffffa + c24c: 616d addi sp,sp,240 + c24e: 6374 flw fa3,68(a4) + c250: 0068 addi a0,sp,12 + c252: 0000 unimp + c254: 6964 flw fs1,84(a0) + c256: 2076 lhu a3,6(s0) + c258: 7962 flw fs2,56(sp) + c25a: 7a20 flw fs0,112(a2) + c25c: 7265 lui tp,0xffff9 + c25e: 6469006f j 9c8a4 <_data_lma+0x8fe0c> + c262: 6e65 lui t3,0x19 + c264: 2074 lbu a3,6(s0) + c266: 7865 lui a6,0xffff9 + c268: 6570 flw fa2,76(a0) + c26a: 64657463 bgeu a0,t1,c8b2 <__mprec_bigtens+0x1a> + c26e: 0000 unimp + c270: 656c flw fa1,76(a0) + c272: 676e flw fa4,216(sp) + c274: 6874 flw fa3,84(s0) + c276: 0000 unimp + c278: 6f6c flw fa1,92(a4) + c27a: 70756b6f jal s6,63180 <_data_lma+0x566e8> + c27e: 6920 flw fs0,80(a0) + c280: 206e lhu a1,6(s0) + c282: 6f6e flw ft10,216(sp) + c284: 2d6e lhu a1,30(a0) + c286: 006a626f jal tp,b228c <_data_lma+0xa57f4> + c28a: 0000 unimp + c28c: 6e75 lui t3,0x1d + c28e: 776f6e6b 0x776f6e6b + c292: 206e lhu a1,6(s0) + c294: 2520706f j 134e6 <_data_lma+0x6a4e> + c298: 0064 addi s1,sp,12 + c29a: 0000 unimp + c29c: 6170 flw fa2,68(a0) + c29e: 7372 flw ft6,60(sp) + c2a0: 2065 jal c348 <_exit+0x338> + c2a2: 7265 lui tp,0xffff9 + c2a4: 6f72 flw ft10,28(sp) + c2a6: 0072 c.slli zero,0x1c + c2a8: 2029 jal c2b2 <_exit+0x2a2> + c2aa: 7865 lui a6,0xffff9 + c2ac: 6570 flw fa2,76(a0) + c2ae: 64657463 bgeu a0,t1,c8f6 <__mprec_tens+0x36> + c2b2: 0000 unimp + c2b4: 74732043 0x74732043 + c2b8: 6361 lui t1,0x18 + c2ba: 6162006b 0x6162006b + c2be: 2064 lbu s1,6(s0) + c2c0: 7865 lui a6,0xffff9 + c2c2: 7270 flw fa2,100(a2) + c2c4: 0000 unimp + c2c6: 0000 unimp + c2c8: 2a2e2527 fsw ft2,682(t3) # 1d2aa <_data_lma+0x10812> + c2cc: 61202773 csrr a4,0x612 + c2d0: 726c flw fa1,100(a2) + c2d2: 6165 addi sp,sp,112 + c2d4: 7964 flw fs1,116(a0) + c2d6: 6420 flw fs0,72(s0) + c2d8: 6365 lui t1,0x19 + c2da: 616c flw fa1,68(a0) + c2dc: 6572 flw fa0,28(sp) + c2de: 0064 addi s1,sp,12 + c2e0: 5245 li tp,-15 + c2e2: 4f52 lw t5,20(sp) + c2e4: 3a52 lhu a2,52(a2) + c2e6: 0020 addi s0,sp,8 + c2e8: 2a2e2527 fsw ft2,682(t3) + c2ec: 6e202773 csrr a4,0x6e2 + c2f0: 6920746f jal s0,13982 <_data_lma+0x6eea> + c2f4: 706d c.lui zero,0xffffb + c2f6: 656c flw fa1,76(a0) + c2f8: 656d lui a0,0x1b + c2fa: 746e flw fs0,248(sp) + c2fc: 6465 lui s0,0x19 + c2fe: 0000 unimp + c300: 6f6e flw ft10,216(sp) + c302: 2074 lbu a3,6(s0) + c304: 6e69 lui t3,0x1a + c306: 6c20 flw fs0,88(s0) + c308: 00706f6f jal t5,12b0e <_data_lma+0x6076> + c30c: 6f6e flw ft10,216(sp) + c30e: 2074 lbu a3,6(s0) + c310: 6e69 lui t3,0x1a + c312: 6620 flw fs0,72(a2) + c314: 6e75 lui t3,0x1d + c316: 203b0063 beq s6,gp,c516 <_exit+0x506> + c31a: 7865 lui a6,0xffff9 + c31c: 6570 flw fa2,76(a0) + c31e: 64657463 bgeu a0,t1,c966 <__mprec_tens+0xa6> + c322: 0000 unimp + c324: 6162 flw ft2,24(sp) + c326: 2064 lbu s1,6(s0) + c328: 20727473 csrrci s0,0x207,4 + c32c: 696c flw fa1,84(a0) + c32e: 6574 flw fa3,76(a0) + c330: 6172 flw ft2,28(sp) + c332: 006c addi a1,sp,12 + c334: 2a2e2527 fsw ft2,682(t3) # 1d2aa <_data_lma+0x10812> + c338: 6e202773 csrr a4,0x6e2 + c33c: 6620746f jal s0,1399e <_data_lma+0x6f06> + c340: 646e756f jal a0,f3986 <_data_lma+0xe6eee> + c344: 0000 unimp + c346: 0000 unimp + c348: 736a flw ft6,184(sp) + c34a: 3e2d jal be84 <__trunctfdf2+0x102> + c34c: 7262 flw ft4,56(sp) + c34e: 3d3c206b 0x3d3c206b + c352: 6a20 flw fs0,80(a2) + c354: 733e2d73 csrrs s10,0x733,t3 + c358: 7a69 lui s4,0xffffa + c35a: 0065 c.nop 25 + c35c: 2e2e lhu a1,26(a2) + c35e: 6e65542f 0x6e65542f + c362: 746e6563 bltu t3,t1,caac <_data_lma+0x14> + c366: 545f534f 0x545f534f + c36a: 6e69 lui t3,0x1a + c36c: 2f79 jal cb0a <_data_lma+0x72> + c36e: 6f74 flw fa3,92(a4) + c370: 736a5f73 csrrwi t5,0x736,20 + c374: 736f742f 0x736f742f + c378: 6a5f 2e73 0063 0x632e736a5f + c37e: 0000 unimp + c380: 006d6f6f jal t5,e2386 <_data_lma+0xd58ee> + c384: 6a28 flw fa0,80(a2) + c386: 663e2d73 csrrs s10,0x663,t3 + c38a: 616c flw fa1,68(a0) + c38c: 26207367 0x26207367 + c390: 4620 lw s0,72(a2) + c392: 4e5f 454f 4558 0x4558454f4e5f + c398: 3d202943 0x3d202943 + c39c: 203d jal c3ca <_exit+0x3ba> + c39e: 0030 addi a2,sp,8 + c3a0: 7262 flw ft4,56(sp) + c3a2: 6165 addi sp,sp,112 + c3a4: 0000006b 0x6b + c3a8: 73616c63 bltu sp,s6,cae0 <_data_lma+0x48> + c3ac: 00000073 ecall + c3b0: 65736163 bltu t1,s7,c9f2 <_ctype_+0x5e> + c3b4: 0000 unimp + c3b6: 0000 unimp + c3b8: 63746163 bltu s0,s7,c9da <_ctype_+0x46> + c3bc: 0068 addi a0,sp,12 + c3be: 0000 unimp + c3c0: 736e6f63 bltu t3,s6,cafe <_data_lma+0x66> + c3c4: 0074 addi a3,sp,12 + c3c6: 0000 unimp + c3c8: 746e6f63 bltu t3,t1,cb26 <_data_lma+0x8e> + c3cc: 6e69 lui t3,0x1a + c3ce: 6575 lui a0,0x1d + c3d0: 0000 unimp + c3d2: 0000 unimp + c3d4: 6f64 flw fs1,92(a4) + c3d6: 0000 unimp + c3d8: 6564 flw fs1,76(a0) + c3da: 6166 flw ft2,88(sp) + c3dc: 6c75 lui s8,0x1d + c3de: 0074 addi a3,sp,12 + c3e0: 6c65 lui s8,0x19 + c3e2: 00006573 csrrsi a0,ustatus,0 + c3e6: 0000 unimp + c3e8: 6f66 flw ft10,88(sp) + c3ea: 0072 c.slli zero,0x1c + c3ec: 6966 flw fs2,88(sp) + c3ee: 616e flw ft2,216(sp) + c3f0: 6c6c flw fa1,92(s0) + c3f2: 0079 c.nop 30 + c3f4: 6166 flw ft2,88(sp) + c3f6: 736c flw fa1,100(a4) + c3f8: 0065 c.nop 25 + c3fa: 0000 unimp + c3fc: 6669 lui a2,0x1a + c3fe: 0000 unimp + c400: 6e69 lui t3,0x1a + c402: 0000 unimp + c404: 6e69 lui t3,0x1a + c406: 6e617473 csrrci s0,0x6e6,2 + c40a: 666f6563 bltu t5,t1,ca74 <_ctype_+0xe0> + c40e: 0000 unimp + c410: 656c flw fa1,76(a0) + c412: 0074 addi a3,sp,12 + c414: 656e flw fa0,216(sp) + c416: 65720077 0x65720077 + c41a: 7574 flw fa3,108(a0) + c41c: 6e72 flw ft8,28(sp) + c41e: 0000 unimp + c420: 74697773 csrrci a4,0x746,18 + c424: 00006863 bltu zero,zero,c434 <_exit+0x424> + c428: 7274 flw fa3,100(a2) + c42a: 0079 c.nop 30 + c42c: 6874 flw fa3,84(s0) + c42e: 7369 lui t1,0xffffa + c430: 0000 unimp + c432: 0000 unimp + c434: 6874 flw fa3,84(s0) + c436: 6f72 flw ft10,28(sp) + c438: 00000077 0x77 + c43c: 7274 flw fa3,100(a2) + c43e: 6575 lui a0,0x1d + c440: 0000 unimp + c442: 0000 unimp + c444: 7974 flw fa3,116(a0) + c446: 6570 flw fa2,76(a0) + c448: 0000666f jal a2,12448 <_data_lma+0x59b0> + c44c: 6176 flw ft2,92(sp) + c44e: 0072 c.slli zero,0x1c + c450: 6f76 flw ft10,92(sp) + c452: 6469 lui s0,0x1a + c454: 0000 unimp + c456: 0000 unimp + c458: 6c696877 0x6c696877 + c45c: 0065 c.nop 25 + c45e: 0000 unimp + c460: 68746977 0x68746977 + c464: 0000 unimp + c466: 0000 unimp + c468: 6979 lui s2,0x1e + c46a: 6c65 lui s8,0x19 + c46c: 0064 addi s1,sp,12 + c46e: 0000 unimp + c470: 756e flw fa0,248(sp) + c472: 6c6c flw fa1,92(s0) + c474: 0000 unimp + c476: 0000 unimp + c478: 6e75 lui t3,0x1d + c47a: 6564 flw fs1,76(a0) + c47c: 6966 flw fs2,88(sp) + c47e: 656e flw fa0,216(sp) + c480: 0064 addi s1,sp,12 + c482: 0000 unimp + c484: 656a626f jal tp,b2ada <_data_lma+0xa6042> + c488: 00007463 bgeu zero,zero,c490 <_exit+0x480> + c48c: 7270 flw fa2,100(a2) + c48e: 0000706f j 1348e <_data_lma+0x69f6> + c492: 0000 unimp + c494: 69727473 csrrci s0,0x697,4 + c498: 676e flw fa4,216(sp) + c49a: 0000 unimp + c49c: 756e flw fa0,248(sp) + c49e: 626d lui tp,0x1b + c4a0: 7265 lui tp,0xffff9 + c4a2: 0000 unimp + c4a4: 6f62 flw ft10,24(sp) + c4a6: 61656c6f jal s8,62abc <_data_lma+0x56024> + c4aa: 006e c.slli zero,0x1b + c4ac: 65646f63 bltu s0,s6,cb0a <_data_lma+0x72> + c4b0: 6572 flw fa0,28(sp) + c4b2: 0066 c.slli zero,0x19 + c4b4: 6e756663 bltu a0,t2,cba0 <_data_lma+0x108> + c4b8: 00000063 beqz zero,c4b8 <_exit+0x4a8> + c4bc: 7265 lui tp,0xffff9 + c4be: 0072 c.slli zero,0x1c + c4c0: 616e flw ft2,216(sp) + c4c2: 006e c.slli zero,0x1b + c4c4: 2e25 jal c7fc + c4c6: 3731 jal c3d2 <_exit+0x3c2> + c4c8: 00000067 jr zero # 0 <_sinit> + c4cc: 6725 lui a4,0x9 + c4ce: 0000 unimp + c4d0: 0000007b 0x7b + c4d4: 002c addi a1,sp,8 + c4d6: 0000 unimp + c4d8: 003a c.slli zero,0xe + c4da: 0000 unimp + c4dc: 007d c.nop 31 + c4de: 0000 unimp + c4e0: 0022 c.slli zero,0x8 + c4e2: 0000 unimp + c4e4: 6322 flw ft6,8(sp) + c4e6: 665f 6e75 5f63 0x5f636e75665f + c4ec: 7830 flw fa2,112(s0) + c4ee: 6c25 lui s8,0x9 + c4f0: 2278 lbu a4,6(a2) + c4f2: 0000 unimp + c4f4: 5250 lw a2,36(a2) + c4f6: 2540504f 0x2540504f + c4fa: 756c flw fa1,108(a0) + c4fc: 0000 unimp + c4fe: 0000 unimp + c500: 5456 lw s0,116(sp) + c502: 5059 c.li zero,-10 + c504: 2545 jal cba4 <_data_lma+0x10c> + c506: 0064 addi s1,sp,12 + c508: 6469 lui s0,0x1a + c50a: 656c flw fa1,76(a0) + c50c: 0000 unimp + c50e: 0000 unimp + c510: 8eaa mv t4,a0 + c512: ffff 0xffff + c514: 8d2e mv s10,a1 + c516: ffff 0xffff + c518: 8e3e mv t3,a5 + c51a: ffff 0xffff + c51c: 8e46 mv t3,a7 + c51e: ffff 0xffff + c520: 8e3e mv t3,a5 + c522: ffff 0xffff + c524: 8d5e mv s10,s7 + c526: ffff 0xffff + c528: 8e3e mv t3,a5 + c52a: ffff 0xffff + c52c: 8e46 mv t3,a7 + c52e: ffff 0xffff + c530: 8d2e mv s10,a1 + c532: ffff 0xffff + c534: 8d2e mv s10,a1 + c536: ffff 0xffff + c538: 8d5e mv s10,s7 + c53a: ffff 0xffff + c53c: 8e46 mv t3,a7 + c53e: ffff 0xffff + c540: 8ea0 0x8ea0 + c542: ffff 0xffff + c544: 8ea0 0x8ea0 + c546: ffff 0xffff + c548: 8ea0 0x8ea0 + c54a: ffff 0xffff + c54c: 8d5e mv s10,s7 + c54e: ffff 0xffff + c550: 95ba add a1,a1,a4 + c552: ffff 0xffff + c554: 94ac 0x94ac + c556: ffff 0xffff + c558: 94ac 0x94ac + c55a: ffff 0xffff + c55c: 94aa add s1,s1,a0 + c55e: ffff 0xffff + c560: 94b2 add s1,s1,a2 + c562: ffff 0xffff + c564: 94b2 add s1,s1,a2 + c566: ffff 0xffff + c568: 9478 0x9478 + c56a: ffff 0xffff + c56c: 94aa add s1,s1,a0 + c56e: ffff 0xffff + c570: 94b2 add s1,s1,a2 + c572: ffff 0xffff + c574: 9478 0x9478 + c576: ffff 0xffff + c578: 94b2 add s1,s1,a2 + c57a: ffff 0xffff + c57c: 94aa add s1,s1,a0 + c57e: ffff 0xffff + c580: 95a6 add a1,a1,s1 + c582: ffff 0xffff + c584: 95a6 add a1,a1,s1 + c586: ffff 0xffff + c588: 95a6 add a1,a1,s1 + c58a: ffff 0xffff + c58c: 9478 0x9478 + c58e: ffff 0xffff + +0000c590 <__clz_tab>: + c590: 0100 0202 0303 0303 0404 0404 0404 0404 ................ + c5a0: 0505 0505 0505 0505 0505 0505 0505 0505 ................ + c5b0: 0606 0606 0606 0606 0606 0606 0606 0606 ................ + c5c0: 0606 0606 0606 0606 0606 0606 0606 0606 ................ + c5d0: 0707 0707 0707 0707 0707 0707 0707 0707 ................ + c5e0: 0707 0707 0707 0707 0707 0707 0707 0707 ................ + c5f0: 0707 0707 0707 0707 0707 0707 0707 0707 ................ + c600: 0707 0707 0707 0707 0707 0707 0707 0707 ................ + c610: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c620: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c630: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c640: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c650: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c660: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c670: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c680: 0808 0808 0808 0808 0808 0808 0808 0808 ................ + c690: 202c 7566 636e 6974 6e6f 203a 0000 0000 , function: .... + c6a0: 7361 6573 7472 6f69 206e 2522 2273 6620 assertion "%s" f + c6b0: 6961 656c 3a64 6620 6c69 2065 2522 2273 ailed: file "%s" + c6c0: 202c 696c 656e 2520 2564 2573 0a73 0000 , line %d%s%s... + c6d0: 2d23 2b30 0020 0000 6c68 004c 6665 4567 #-0+ ...hlL.efgE + c6e0: 4746 0000 0000 0000 ffff ffff ffff 7fef FG.............. + c6f0: 4e49 0046 6e69 0066 414e 004e 0030 0000 INF.inf.NAN.0... + c700: 3130 3332 3534 3736 3938 4241 4443 4645 0123456789ABCDEF + c710: 0000 0000 3130 3332 3534 3736 3938 6261 ....0123456789ab + c720: 6463 6665 0000 0000 2565 646c 0000 0000 cdef....e%ld.... + c730: 0000 7fc0 b716 ffff b702 ffff b734 ffff ............4... + c740: b73a ffff b716 ffff 0000 0000 0000 3fe0 :..............? + c750: 0000 0000 0000 3ff0 0000 0000 0000 4000 .......?.......@ + c760: 0000 ffc0 ffff 41df 3595 94a0 ffff 3fdf .......A.5.....? + c770: e535 35af 0000 3fe0 3595 94a0 ffff 3fcf 5..5...?.5.....? + c780: 666e 0000 6e69 7469 0079 0000 6e61 0000 nf..inity...an.. + +0000c790 : + c790: 0035 0000 fbce ffff 03cb 0000 0001 0000 5............... + c7a0: 0000 0000 .... + +0000c7a4 : + c7a4: 0034 0000 fbce ffff 03cb 0000 0001 0000 4............... + c7b4: 0000 0000 .... + +0000c7b8 : + c7b8: 89bc 97d8 d2b2 3c9c a733 d5a8 f623 3949 .......<3...#.I9 + c7c8: a73d 44f4 0ffd 32a5 979d cf8c ba08 255b =..D...2......[% + c7d8: 6f43 64ac 0628 1168 0000 0000 0000 3ff8 Co.d(.h........? + c7e8: 4361 636f 87a7 3fd2 c8b3 8b60 8a28 3fc6 aCoc...?..`.(..? + c7f8: 79fb 509f 4413 3fd3 0000 0000 0000 4024 .y.P.D.?......$@ + c808: 0000 0000 0000 401c 0000 0000 0000 4014 .......@.......@ + c818: 6e49 6966 696e 7974 0000 0000 614e 004e Infinity....NaN. + +0000c828 <__sf_fake_stderr>: + ... + +0000c848 <__sf_fake_stdin>: + ... + +0000c868 <__sf_fake_stdout>: + ... + c888: 0043 0000 4f50 4953 0058 0000 002e 0000 C...POSIX....... + +0000c898 <__mprec_bigtens>: + c898: 8000 37e0 c379 4341 6e17 b505 b8b5 4693 ...7y.AC.n.....F + c8a8: f9f5 e93f 4f03 4d38 1d32 f930 7748 5a82 ..?..O8M2.0.Hw.Z + c8b8: bf3c 7f73 4fdd 7515 <.s..O.u + +0000c8c0 <__mprec_tens>: + c8c0: 0000 0000 0000 3ff0 0000 0000 0000 4024 .......?......$@ + c8d0: 0000 0000 0000 4059 0000 0000 4000 408f ......Y@.....@.@ + c8e0: 0000 0000 8800 40c3 0000 0000 6a00 40f8 .......@.....j.@ + c8f0: 0000 0000 8480 412e 0000 0000 12d0 4163 .......A......cA + c900: 0000 0000 d784 4197 0000 0000 cd65 41cd .......A....e..A + c910: 0000 2000 a05f 4202 0000 e800 4876 4237 ... _..B....vH7B + c920: 0000 a200 1a94 426d 0000 e540 309c 42a2 ......mB..@..0.B + c930: 0000 1e90 bcc4 42d6 0000 2634 6bf5 430c .......B..4&.k.C + c940: 8000 37e0 c379 4341 a000 85d8 3457 4376 ...7y.AC....W4vC + c950: c800 674e c16d 43ab 3d00 6091 58e4 43e1 ..Ngm..C.=.`.X.C + c960: 8c40 78b5 af1d 4415 ef50 d6e2 1ae4 444b @..x...DP.....KD + c970: d592 064d f0cf 4480 4af6 c7e1 2d02 44b5 ..M....D.J...-.D + c980: 9db4 79d9 7843 44ea ...yCx.D + +0000c988 : + c988: 0005 0000 0019 0000 007d 0000 ........}... + +0000c994 <_ctype_>: + c994: 2000 2020 2020 2020 2020 2828 2828 2028 . ((((( + c9a4: 2020 2020 2020 2020 2020 2020 2020 2020 + c9b4: 8820 1010 1010 1010 1010 1010 1010 1010 ............... + c9c4: 0410 0404 0404 0404 0404 1004 1010 1010 ................ + c9d4: 1010 4141 4141 4141 0101 0101 0101 0101 ..AAAAAA........ + c9e4: 0101 0101 0101 0101 0101 0101 1010 1010 ................ + c9f4: 1010 4242 4242 4242 0202 0202 0202 0202 ..BBBBBB........ + ca04: 0202 0202 0202 0202 0202 0202 1010 1010 ................ + ca14: 0020 0000 0000 0000 0000 0000 0000 0000 ............... + ... diff --git a/obj/JSInterpreter-TencentOS.map b/obj/JSInterpreter-TencentOS.map new file mode 100644 index 0000000..59d429c --- /dev/null +++ b/obj/JSInterpreter-TencentOS.map @@ -0,0 +1,4413 @@ +Archive member included to satisfy reference by file (symbol) + +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) + ./TencentOS_Tiny/kernel/core/tos_time.o (__divdi3) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_udivdi3.o) + ./TencentOS_Tiny/kernel/core/tos_stopwatch.o (__udivdi3) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__adddf3) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__divdf3) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(eqdf2.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__eqdf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(gedf2.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__gedf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(ledf2.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__ledf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__muldf3) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(subdf3.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__subdf3) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixdfsi.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__fixdfsi) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatsidf.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__floatsidf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatunsidf.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__floatunsidf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(save-restore.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__riscv_save_12) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clz.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) (__clz_tab) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clzsi2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) (__clzsi2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + ./TencentOS_Tiny/tos_js/tos_js.o (__assert_func) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) (fiprintf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) (_impure_ptr) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcmp.o) + ./TencentOS_Tiny/tos_js/tos_js.o (memcmp) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcpy.o) + ./TencentOS_Tiny/tos_js/tos_js.o (memcpy) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memmove.o) + ./TencentOS_Tiny/tos_js/tos_js.o (memmove) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memset.o) + ./TencentOS_Tiny/tos_js/tos_js.o (memset) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) (_vfprintf_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) (_printf_float) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) (_printf_common) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + (_scanf_float) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + ./User/main.o (printf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + ./User/main.o (putchar) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + ./User/main.o (puts) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-s_modf.o) + ./TencentOS_Tiny/tos_js/tos_js.o (modf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) (nanf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + ./TencentOS_Tiny/tos_js/tos_js.o (snprintf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + ./TencentOS_Tiny/tos_js/tos_js.o (sprintf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strlen.o) + ./TencentOS_Tiny/tos_js/tos_js.o (strlen) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncpy.o) + ./TencentOS_Tiny/kernel/core/tos_task.o (strncpy) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) (_strtod_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) (_strtol_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + ./TencentOS_Tiny/tos_js/tos_js.o (vsnprintf) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) (__swbuf_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) (__swsetup_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) (abort) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) (_dtoa_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) (_fflush_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) (__sinit) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) (__sfvwrite_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) (_fwalk) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (__gethex) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (__match) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) (__locale_ctype_ptr_l) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (__localeconv_l) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) (__smakebuf_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) (malloc) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) (__ascii_mbtowc) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memchr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) (memchr) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (_Balloc) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-callocr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) (_calloc_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) (_free_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) (_malloc_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) (_realloc_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) (_svfprintf_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) (_putc_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) (_sbrk_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) (raise) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) (_kill_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) (__sread) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strcmp.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) (strcmp) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncmp.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (strncmp) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) (__ascii_wctomb) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-writer.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) (_write_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) (_close_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-ctype_.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) (_ctype_) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) (_fstat_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) (_isatty_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) (_lseek_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) (__malloc_lock) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-msizer.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) (_malloc_usable_size_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) (_read_r) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) (errno) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unorddf2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) (__unorddf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixunsdfsi.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (__fixunsdfsi) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(lesf2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (__lesf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unordsf2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) (__unordsf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(extenddftf2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) (__extenddftf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(truncdfsf2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) (__truncdfsf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(trunctfdf2.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) (__trunctfdf2) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) (_close) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) (_fstat) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) (_getpid) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) (_isatty) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) (_kill) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) (_lseek) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) (_read) +c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(_exit.o) + c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) (_exit) + +Allocating common symbols +Common symbol size file + +task1_stk 0x2800 ./User/main.o +k_rdyq 0x58 ./TencentOS_Tiny/kernel/core/tos_global.o +DMAPTPRxDescToGet 0x4 ./Peripheral/src/ch32v30x_eth.o +errno 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) +DMARxDescToGet 0x4 ./Peripheral/src/ch32v30x_eth.o +k_idle_task_stk 0x200 ./TencentOS_Tiny/kernel/core/tos_global.o +DMATxDescToSet 0x4 ./Peripheral/src/ch32v30x_eth.o +k_mmheap_ctl 0xc84 ./TencentOS_Tiny/kernel/core/tos_global.o +task1 0x78 ./User/main.o +k_idle_task 0x78 ./TencentOS_Tiny/kernel/core/tos_global.o +task2 0x78 ./User/main.o +k_mmheap_default_pool + 0x3000 ./TencentOS_Tiny/kernel/core/tos_global.o +task2_stk 0x2800 ./User/main.o +js_mem 0x7d0 ./User/main.o +k_irq_stk 0x200 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o +DMAPTPTxDescToSet 0x4 ./Peripheral/src/ch32v30x_eth.o + +Discarded input sections + + .text 0x0000000000000000 0x0 ./User/ch32v30x_it.o + .data 0x0000000000000000 0x0 ./User/ch32v30x_it.o + .bss 0x0000000000000000 0x0 ./User/ch32v30x_it.o + .text 0x0000000000000000 0x0 ./User/main.o + .data 0x0000000000000000 0x0 ./User/main.o + .bss 0x0000000000000000 0x0 ./User/main.o + .text.GPIO_Toggle_INIT + 0x0000000000000000 0x3e ./User/main.o + .text 0x0000000000000000 0x0 ./User/system_ch32v30x.o + .data 0x0000000000000000 0x0 ./User/system_ch32v30x.o + .bss 0x0000000000000000 0x0 ./User/system_ch32v30x.o + .text.SystemCoreClockUpdate + 0x0000000000000000 0xb2 ./User/system_ch32v30x.o + .data.AHBPrescTable + 0x0000000000000000 0x10 ./User/system_ch32v30x.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/tos_js/tos_js.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/tos_js/tos_js.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_setgct + 0x0000000000000000 0x4 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_setmaxcss + 0x0000000000000000 0x4 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mktrue + 0x0000000000000000 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mkfalse + 0x0000000000000000 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mknull + 0x0000000000000000 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mknum + 0x0000000000000000 0x2 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mkobj + 0x0000000000000000 0x24 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_getnum + 0x0000000000000000 0x2 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_getbool + 0x0000000000000000 0x4 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_getstr + 0x0000000000000000 0x4c ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_type 0x0000000000000000 0x54 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_type + 0x0000000000000000 0x24 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_stats + 0x0000000000000000 0x14 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_chkargs + 0x0000000000000000 0x8a ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_dump 0x0000000000000000 0x122 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_dump.str1.4 + 0x0000000000000000 0x84 ./TencentOS_Tiny/tos_js/tos_js.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/pm/tos_pm.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .debug_str 0x0000000000000000 0xa9e ./TencentOS_Tiny/kernel/pm/tos_pm.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/pm/tos_pm.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .debug_str 0x0000000000000000 0xaa4 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/pm/tos_tickless.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_barrier.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .debug_str 0x0000000000000000 0xaa5 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_barrier.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.bin_heap_do_percolate_up + 0x0000000000000000 0x9a ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_create + 0x0000000000000000 0x22 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_destroy + 0x0000000000000000 0x32 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_create_dyn + 0x0000000000000000 0x4e ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_destroy_dyn + 0x0000000000000000 0x4a ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_flush + 0x0000000000000000 0x30 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_is_empty + 0x0000000000000000 0x2e ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_pop + 0x0000000000000000 0x110 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_is_full + 0x0000000000000000 0x32 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text.tos_bin_heap_push + 0x0000000000000000 0x76 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_info 0x0000000000000000 0x1a92 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_abbrev 0x0000000000000000 0x418 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_loc 0x0000000000000000 0x865 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_aranges + 0x0000000000000000 0x68 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_ranges 0x0000000000000000 0x100 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_line 0x0000000000000000 0xf35 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_str 0x0000000000000000 0x161f ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .debug_frame 0x0000000000000000 0x164 ./TencentOS_Tiny/kernel/core/tos_binary_heap.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_create_empty + 0x0000000000000000 0x2c ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_create_full + 0x0000000000000000 0x2c ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_destroy + 0x0000000000000000 0xc ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_set + 0x0000000000000000 0x30 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_reset + 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_is_set + 0x0000000000000000 0x26 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_is_reset + 0x0000000000000000 0x2e ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text.tos_bitmap_lsb + 0x0000000000000000 0x4c ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_info 0x0000000000000000 0x142e ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_abbrev 0x0000000000000000 0x2fa ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_loc 0x0000000000000000 0x3b4 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_aranges + 0x0000000000000000 0x58 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_ranges 0x0000000000000000 0x48 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_line 0x0000000000000000 0x8fe ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_str 0x0000000000000000 0x13b8 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .debug_frame 0x0000000000000000 0xb4 ./TencentOS_Tiny/kernel/core/tos_bitmap.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_create + 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_destroy + 0x0000000000000000 0x38 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_create_dyn + 0x0000000000000000 0x2c ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_destroy_dyn + 0x0000000000000000 0x38 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_push + 0x0000000000000000 0x2e ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_push_stream + 0x0000000000000000 0x4e ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_pop + 0x0000000000000000 0x24 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_pop_stream + 0x0000000000000000 0x5c ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_flush + 0x0000000000000000 0x22 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_is_empty + 0x0000000000000000 0x20 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text.tos_chr_fifo_is_full + 0x0000000000000000 0x20 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_info 0x0000000000000000 0x17ed ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_abbrev 0x0000000000000000 0x2ff ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_loc 0x0000000000000000 0x5e8 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_aranges + 0x0000000000000000 0x70 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_ranges 0x0000000000000000 0x60 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_line 0x0000000000000000 0xa5e ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_str 0x0000000000000000 0x15c6 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .debug_frame 0x0000000000000000 0x174 ./TencentOS_Tiny/kernel/core/tos_char_fifo.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_completion.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_completion.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_completion.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_completion.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_completion.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_completion.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_completion.o + .debug_str 0x0000000000000000 0xaa8 ./TencentOS_Tiny/kernel/core/tos_completion.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_completion.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .debug_str 0x0000000000000000 0xaac ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_event.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_event.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_event.o + .text.event_do_post + 0x0000000000000000 0xa2 ./TencentOS_Tiny/kernel/core/tos_event.o + .text.tos_event_create + 0x0000000000000000 0x26 ./TencentOS_Tiny/kernel/core/tos_event.o + .text.tos_event_destroy + 0x0000000000000000 0x56 ./TencentOS_Tiny/kernel/core/tos_event.o + .text.tos_event_pend + 0x0000000000000000 0x10a ./TencentOS_Tiny/kernel/core/tos_event.o + .text.tos_event_post + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_event.o + .text.tos_event_post_keep + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_info 0x0000000000000000 0x16c0 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_abbrev 0x0000000000000000 0x2f1 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_loc 0x0000000000000000 0x5a6 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_aranges + 0x0000000000000000 0x48 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_ranges 0x0000000000000000 0x78 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_line 0x0000000000000000 0xa02 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_str 0x0000000000000000 0x14b1 ./TencentOS_Tiny/kernel/core/tos_event.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_event.o + .debug_frame 0x0000000000000000 0xf0 ./TencentOS_Tiny/kernel/core/tos_event.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_global.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_global.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_global.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.mail_q_do_post + 0x0000000000000000 0xd2 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_create + 0x0000000000000000 0x38 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_destroy + 0x0000000000000000 0x7c ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_create_dyn + 0x0000000000000000 0x38 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_destroy_dyn + 0x0000000000000000 0x7c ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_flush + 0x0000000000000000 0x22 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_pend + 0x0000000000000000 0xe6 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_post + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text.tos_mail_q_post_all + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_info 0x0000000000000000 0x1b42 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_abbrev 0x0000000000000000 0x348 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_loc 0x0000000000000000 0x632 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_aranges + 0x0000000000000000 0x60 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_ranges 0x0000000000000000 0x80 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_line 0x0000000000000000 0xb54 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_str 0x0000000000000000 0x165d ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .debug_frame 0x0000000000000000 0x15c ./TencentOS_Tiny/kernel/core/tos_mail_queue.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .debug_str 0x0000000000000000 0xaab ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_message_queue.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text.tos_mmblk_pool_create + 0x0000000000000000 0x7a ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text.tos_mmblk_pool_destroy + 0x0000000000000000 0x2e ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text.tos_mmblk_pool_create_dyn + 0x0000000000000000 0x94 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text.tos_mmblk_pool_destroy_dyn + 0x0000000000000000 0x50 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text.tos_mmblk_alloc + 0x0000000000000000 0x50 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text.tos_mmblk_free + 0x0000000000000000 0x54 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_info 0x0000000000000000 0x156e ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_abbrev 0x0000000000000000 0x2ee ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_loc 0x0000000000000000 0x497 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_aranges + 0x0000000000000000 0x48 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_ranges 0x0000000000000000 0x68 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_line 0x0000000000000000 0xc14 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_str 0x0000000000000000 0x14a9 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .debug_frame 0x0000000000000000 0xe0 ./TencentOS_Tiny/kernel/core/tos_mmblk.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.remove_free_block + 0x0000000000000000 0x5e ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.adjust_request_size + 0x0000000000000000 0x28 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_remove + 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_merge_next + 0x0000000000000000 0x42 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_locate_free + 0x0000000000000000 0xd8 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_split + 0x0000000000000000 0x4a ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_prepare_used + 0x0000000000000000 0x64 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.mmheap_init + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_alloc + 0x0000000000000000 0x44 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_calloc + 0x0000000000000000 0x36 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_aligned_alloc + 0x0000000000000000 0xc4 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_free + 0x0000000000000000 0x70 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_realloc + 0x0000000000000000 0xee ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_pool_rmv + 0x0000000000000000 0xa6 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_pool_check + 0x0000000000000000 0x5c ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_check + 0x0000000000000000 0x66 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.tos_mutex_create + 0x0000000000000000 0x4a ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.tos_mutex_create_dyn + 0x0000000000000000 0x68 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.tos_mutex_destroy + 0x0000000000000000 0x80 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.tos_mutex_pend_timed + 0x0000000000000000 0x12a ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.tos_mutex_pend + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.tos_mutex_post + 0x0000000000000000 0xf8 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_pend.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_pend.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_highest_pending_task_get + 0x0000000000000000 0x8 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_object_init + 0x0000000000000000 0x6 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_object_deinit + 0x0000000000000000 0x6 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_is_nopending + 0x0000000000000000 0xc ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_state2errno + 0x0000000000000000 0x30 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_task_block + 0x0000000000000000 0x4e ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_wakeup_one + 0x0000000000000000 0x1e ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_wakeup + 0x0000000000000000 0x24 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .debug_str 0x0000000000000000 0xab1 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .debug_str 0x0000000000000000 0xab4 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.prio_q_mgr_entry_cmp + 0x0000000000000000 0xa ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_create + 0x0000000000000000 0x86 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_destroy + 0x0000000000000000 0x58 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_create_dyn + 0x0000000000000000 0x84 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_destroy_dyn + 0x0000000000000000 0x6c ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_flush + 0x0000000000000000 0x68 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_is_empty + 0x0000000000000000 0x2e ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_dequeue + 0x0000000000000000 0x118 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_is_full + 0x0000000000000000 0x32 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text.tos_prio_q_enqueue + 0x0000000000000000 0x10e ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .rodata.__FUNCTION__.6987 + 0x0000000000000000 0x1d ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .rodata.__FUNCTION__.6996 + 0x0000000000000000 0x1d ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .rodata.__FUNCTION__.7036 + 0x0000000000000000 0x13 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .rodata.tos_prio_q_dequeue.str1.4 + 0x0000000000000000 0x16 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_info 0x0000000000000000 0x22a7 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_abbrev 0x0000000000000000 0x447 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_loc 0x0000000000000000 0xc5a ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_aranges + 0x0000000000000000 0x68 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_ranges 0x0000000000000000 0x1b8 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_line 0x0000000000000000 0x111b ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_str 0x0000000000000000 0x18f6 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .debug_frame 0x0000000000000000 0x194 ./TencentOS_Tiny/kernel/core/tos_priority_queue.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_create + 0x0000000000000000 0x22 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_destroy + 0x0000000000000000 0x32 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_create_dyn + 0x0000000000000000 0x4a ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_destroy_dyn + 0x0000000000000000 0x4a ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_flush + 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_is_empty + 0x0000000000000000 0x2e ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_dequeue + 0x0000000000000000 0x84 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_is_full + 0x0000000000000000 0x32 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text.tos_ring_q_enqueue + 0x0000000000000000 0x8a ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_info 0x0000000000000000 0x17c3 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_abbrev 0x0000000000000000 0x323 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_loc 0x0000000000000000 0x511 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_aranges + 0x0000000000000000 0x60 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_ranges 0x0000000000000000 0xc8 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_line 0x0000000000000000 0xc29 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_str 0x0000000000000000 0x154d ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .debug_frame 0x0000000000000000 0x128 ./TencentOS_Tiny/kernel/core/tos_ring_queue.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_robin.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_robin.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_robin.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_robin.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_robin.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_robin.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_robin.o + .debug_str 0x0000000000000000 0xaa3 ./TencentOS_Tiny/kernel/core/tos_robin.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_robin.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_create + 0x0000000000000000 0x52 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_destroy + 0x0000000000000000 0x40 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_rpend_timed + 0x0000000000000000 0xf4 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_rpend + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_rpend_try + 0x0000000000000000 0x66 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_wpend_timed + 0x0000000000000000 0x100 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_wpend + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_wpend_try + 0x0000000000000000 0x52 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_rpost + 0x0000000000000000 0x58 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_wpost + 0x0000000000000000 0x50 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text.tos_rwlock_post + 0x0000000000000000 0x60 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_info 0x0000000000000000 0x18b0 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_abbrev 0x0000000000000000 0x2d0 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_loc 0x0000000000000000 0x536 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_aranges + 0x0000000000000000 0x70 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_ranges 0x0000000000000000 0x60 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_line 0x0000000000000000 0xd57 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_str 0x0000000000000000 0x1581 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .debug_frame 0x0000000000000000 0x1c4 ./TencentOS_Tiny/kernel/core/tos_rwlock.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sched.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sched.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sched.o + .text.readyqueue_is_prio_onlyone + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_sched.o + .text.readyqueue_first_task_get + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_sched.o + .text.readyqueue_move_head_to_tail + 0x0000000000000000 0x26 ./TencentOS_Tiny/kernel/core/tos_sched.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sem.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sem.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.sem_do_post + 0x0000000000000000 0x80 ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_create_max + 0x0000000000000000 0x36 ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_create + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_create_max_dyn + 0x0000000000000000 0x6e ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_create_dyn + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_destroy + 0x0000000000000000 0x64 ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_post + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_post_all + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_sem.o + .text.tos_sem_pend + 0x0000000000000000 0xb0 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_info 0x0000000000000000 0x1779 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_abbrev 0x0000000000000000 0x2f9 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_loc 0x0000000000000000 0x412 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_aranges + 0x0000000000000000 0x60 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_ranges 0x0000000000000000 0x50 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_line 0x0000000000000000 0x985 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_str 0x0000000000000000 0x1545 ./TencentOS_Tiny/kernel/core/tos_sem.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_sem.o + .debug_frame 0x0000000000000000 0x14c ./TencentOS_Tiny/kernel/core/tos_sem.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_create + 0x0000000000000000 0x16 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_destroy + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_countdown + 0x0000000000000000 0x38 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_countdown_ms + 0x0000000000000000 0x32 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_delay + 0x0000000000000000 0x42 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_delay_ms + 0x0000000000000000 0x20 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_is_expired + 0x0000000000000000 0x36 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_remain + 0x0000000000000000 0x44 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text.tos_stopwatch_remain_ms + 0x0000000000000000 0x5c ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_info 0x0000000000000000 0x1447 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_abbrev 0x0000000000000000 0x2f9 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_loc 0x0000000000000000 0x295 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_aranges + 0x0000000000000000 0x58 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_ranges 0x0000000000000000 0x48 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_line 0x0000000000000000 0x765 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_str 0x0000000000000000 0x1406 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .debug_frame 0x0000000000000000 0x120 ./TencentOS_Tiny/kernel/core/tos_stopwatch.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sys.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sys.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_sys.o + .text.tos_knl_sched_lock + 0x0000000000000000 0x62 ./TencentOS_Tiny/kernel/core/tos_sys.o + .text.tos_knl_sched_unlock + 0x0000000000000000 0x64 ./TencentOS_Tiny/kernel/core/tos_sys.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_task.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_task.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_walkthru.part.9 + 0x0000000000000000 0x4a ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_suspend + 0x0000000000000000 0x84 ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_resume + 0x0000000000000000 0x6a ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_delay_abort + 0x0000000000000000 0x94 ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_curr_task_get + 0x0000000000000000 0x3a ./TencentOS_Tiny/kernel/core/tos_task.o + .text.task_default_walker + 0x0000000000000000 0x14a ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_walkthru + 0x0000000000000000 0x1c ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_info_display + 0x0000000000000000 0x20 ./TencentOS_Tiny/kernel/core/tos_task.o + .rodata.task_default_walker.str1.4 + 0x0000000000000000 0xcb ./TencentOS_Tiny/kernel/core/tos_task.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_tick.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_tick.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_tick.o + .text.tick_next_expires_get + 0x0000000000000000 0x46 ./TencentOS_Tiny/kernel/core/tos_tick.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_time.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_time.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_time.o + .text.tos_systick_get + 0x0000000000000000 0x30 ./TencentOS_Tiny/kernel/core/tos_time.o + .text.tos_systick_set + 0x0000000000000000 0x30 ./TencentOS_Tiny/kernel/core/tos_time.o + .text.tos_tick2millisec + 0x0000000000000000 0x2 ./TencentOS_Tiny/kernel/core/tos_time.o + .text.tos_millisec2tick + 0x0000000000000000 0x4 ./TencentOS_Tiny/kernel/core/tos_time.o + .text.tos_sleep_ms + 0x0000000000000000 0x1a ./TencentOS_Tiny/kernel/core/tos_time.o + .text.tos_sleep_hmsm + 0x0000000000000000 0x78 ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_info 0x0000000000000000 0x13ab ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_abbrev 0x0000000000000000 0x354 ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_loc 0x0000000000000000 0x116 ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_aranges + 0x0000000000000000 0x48 ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_ranges 0x0000000000000000 0x50 ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_line 0x0000000000000000 0x5fe ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_str 0x0000000000000000 0x13ba ./TencentOS_Tiny/kernel/core/tos_time.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_time.o + .debug_frame 0x0000000000000000 0xac ./TencentOS_Tiny/kernel/core/tos_time.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_timer.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_timer.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/kernel/core/tos_timer.o + .debug_info 0x0000000000000000 0xee1 ./TencentOS_Tiny/kernel/core/tos_timer.o + .debug_abbrev 0x0000000000000000 0x1ea ./TencentOS_Tiny/kernel/core/tos_timer.o + .debug_aranges + 0x0000000000000000 0x18 ./TencentOS_Tiny/kernel/core/tos_timer.o + .debug_line 0x0000000000000000 0x344 ./TencentOS_Tiny/kernel/core/tos_timer.o + .debug_str 0x0000000000000000 0xaa3 ./TencentOS_Tiny/kernel/core/tos_timer.o + .comment 0x0000000000000000 0x34 ./TencentOS_Tiny/kernel/core/tos_timer.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .text.port_int_disable + 0x0000000000000000 0xc ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .text.port_int_enable + 0x0000000000000000 0xc ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .text.port_cpu_reset + 0x0000000000000000 0x10 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + .text 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .data 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .bss 0x0000000000000000 0x0 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .text.tos_cpu_int_disable + 0x0000000000000000 0x18 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .text.tos_cpu_int_enable + 0x0000000000000000 0x18 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .text 0x0000000000000000 0x0 ./Startup/startup_ch32v30x.o + .data 0x0000000000000000 0x0 ./Startup/startup_ch32v30x.o + .bss 0x0000000000000000 0x0 ./Startup/startup_ch32v30x.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_adc.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_adc.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_DeInit + 0x0000000000000000 0x5a ./Peripheral/src/ch32v30x_adc.o + .text.ADC_Init + 0x0000000000000000 0x56 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_StructInit + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_adc.o + .text.ADC_Cmd 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_DMACmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ITConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ResetCalibration + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetResetCalibrationStatus + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_StartCalibration + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetCalibrationStatus + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_SoftwareStartConvCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetSoftwareStartConvStatus + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_DiscModeChannelCountConfig + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_DiscModeCmd + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_adc.o + .text.ADC_RegularChannelConfig + 0x0000000000000000 0xb8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ExternalTrigConvCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetConversionValue + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetDualModeConversionValue + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_adc.o + .text.ADC_AutoInjectedConvCmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_InjectedDiscModeCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ExternalTrigInjectedConvConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ExternalTrigInjectedConvCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_SoftwareStartInjectedConvCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetSoftwareStartInjectedConvCmdStatus + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_InjectedChannelConfig + 0x0000000000000000 0x7a ./Peripheral/src/ch32v30x_adc.o + .text.ADC_InjectedSequencerLengthConfig + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_SetInjectedOffset + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetInjectedConversionValue + 0x0000000000000000 0x1c ./Peripheral/src/ch32v30x_adc.o + .text.ADC_AnalogWatchdogCmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_AnalogWatchdogThresholdsConfig + 0x0000000000000000 0x6 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_AnalogWatchdogSingleChannelConfig + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_adc.o + .text.ADC_TempSensorVrefintCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetFlagStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ClearFlag + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_adc.o + .text.ADC_GetITStatus + 0x0000000000000000 0x1c ./Peripheral/src/ch32v30x_adc.o + .text.ADC_ClearITPendingBit + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_adc.o + .text.TempSensor_Volt_To_Temper + 0x0000000000000000 0x2a ./Peripheral/src/ch32v30x_adc.o + .text.ADC_BufferCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_adc.o + .text.Get_CalibrationValue + 0x0000000000000000 0x144 ./Peripheral/src/ch32v30x_adc.o + .debug_info 0x0000000000000000 0x16f4 ./Peripheral/src/ch32v30x_adc.o + .debug_abbrev 0x0000000000000000 0x3a9 ./Peripheral/src/ch32v30x_adc.o + .debug_loc 0x0000000000000000 0xa67 ./Peripheral/src/ch32v30x_adc.o + .debug_aranges + 0x0000000000000000 0x150 ./Peripheral/src/ch32v30x_adc.o + .debug_ranges 0x0000000000000000 0x140 ./Peripheral/src/ch32v30x_adc.o + .debug_line 0x0000000000000000 0x1895 ./Peripheral/src/ch32v30x_adc.o + .debug_str 0x0000000000000000 0xc0e ./Peripheral/src/ch32v30x_adc.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_adc.o + .debug_frame 0x0000000000000000 0x2b4 ./Peripheral/src/ch32v30x_adc.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_bkp.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_bkp.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_DeInit + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_TamperPinLevelConfig + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_TamperPinCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_ITConfig + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_RTCOutputConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_SetRTCCalibrationValue + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_WriteBackupRegister + 0x0000000000000000 0x1c ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_ReadBackupRegister + 0x0000000000000000 0x1c ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_GetFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_ClearFlag + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_GetITStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_bkp.o + .text.BKP_ClearITPendingBit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_bkp.o + .debug_info 0x0000000000000000 0x10c6 ./Peripheral/src/ch32v30x_bkp.o + .debug_abbrev 0x0000000000000000 0x2cc ./Peripheral/src/ch32v30x_bkp.o + .debug_loc 0x0000000000000000 0xd8 ./Peripheral/src/ch32v30x_bkp.o + .debug_aranges + 0x0000000000000000 0x78 ./Peripheral/src/ch32v30x_bkp.o + .debug_ranges 0x0000000000000000 0x68 ./Peripheral/src/ch32v30x_bkp.o + .debug_line 0x0000000000000000 0x692 ./Peripheral/src/ch32v30x_bkp.o + .debug_str 0x0000000000000000 0xa9c ./Peripheral/src/ch32v30x_bkp.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_bkp.o + .debug_frame 0x0000000000000000 0xec ./Peripheral/src/ch32v30x_bkp.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_can.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_can.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_can.o + .text.CAN_DeInit + 0x0000000000000000 0x4c ./Peripheral/src/ch32v30x_can.o + .text.CAN_Init + 0x0000000000000000 0xe8 ./Peripheral/src/ch32v30x_can.o + .text.CAN_FilterInit + 0x0000000000000000 0xee ./Peripheral/src/ch32v30x_can.o + .text.CAN_StructInit + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_can.o + .text.CAN_SlaveStartBank + 0x0000000000000000 0x38 ./Peripheral/src/ch32v30x_can.o + .text.CAN_DBGFreeze + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_can.o + .text.CAN_TTComModeCmd + 0x0000000000000000 0x58 ./Peripheral/src/ch32v30x_can.o + .text.CAN_Transmit + 0x0000000000000000 0xbc ./Peripheral/src/ch32v30x_can.o + .text.CAN_TransmitStatus + 0x0000000000000000 0x62 ./Peripheral/src/ch32v30x_can.o + .text.CAN_CancelTransmit + 0x0000000000000000 0x2a ./Peripheral/src/ch32v30x_can.o + .text.CAN_Receive + 0x0000000000000000 0x8c ./Peripheral/src/ch32v30x_can.o + .text.CAN_FIFORelease + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_can.o + .text.CAN_MessagePending + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_can.o + .text.CAN_OperatingModeRequest + 0x0000000000000000 0x72 ./Peripheral/src/ch32v30x_can.o + .text.CAN_Sleep + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_can.o + .text.CAN_WakeUp + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_can.o + .text.CAN_GetLastErrorCode + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_can.o + .text.CAN_GetReceiveErrorCounter + 0x0000000000000000 0x6 ./Peripheral/src/ch32v30x_can.o + .text.CAN_GetLSBTransmitErrorCounter + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_can.o + .text.CAN_ITConfig + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_can.o + .text.CAN_GetFlagStatus + 0x0000000000000000 0x56 ./Peripheral/src/ch32v30x_can.o + .text.CAN_ClearFlag + 0x0000000000000000 0x40 ./Peripheral/src/ch32v30x_can.o + .text.CAN_GetITStatus + 0x0000000000000000 0xd0 ./Peripheral/src/ch32v30x_can.o + .text.CAN_ClearITPendingBit + 0x0000000000000000 0x94 ./Peripheral/src/ch32v30x_can.o + .debug_info 0x0000000000000000 0x180e ./Peripheral/src/ch32v30x_can.o + .debug_abbrev 0x0000000000000000 0x3eb ./Peripheral/src/ch32v30x_can.o + .debug_loc 0x0000000000000000 0x999 ./Peripheral/src/ch32v30x_can.o + .debug_aranges + 0x0000000000000000 0xd8 ./Peripheral/src/ch32v30x_can.o + .debug_ranges 0x0000000000000000 0xf8 ./Peripheral/src/ch32v30x_can.o + .debug_line 0x0000000000000000 0x1a55 ./Peripheral/src/ch32v30x_can.o + .debug_str 0x0000000000000000 0xbb2 ./Peripheral/src/ch32v30x_can.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_can.o + .debug_frame 0x0000000000000000 0x19c ./Peripheral/src/ch32v30x_can.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_crc.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_crc.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_crc.o + .text.CRC_ResetDR + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_crc.o + .text.CRC_CalcCRC + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_crc.o + .text.CRC_CalcBlockCRC + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_crc.o + .text.CRC_GetCRC + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_crc.o + .text.CRC_SetIDRegister + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_crc.o + .text.CRC_GetIDRegister + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_crc.o + .debug_info 0x0000000000000000 0xaba ./Peripheral/src/ch32v30x_crc.o + .debug_abbrev 0x0000000000000000 0x25f ./Peripheral/src/ch32v30x_crc.o + .debug_loc 0x0000000000000000 0x75 ./Peripheral/src/ch32v30x_crc.o + .debug_aranges + 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_crc.o + .debug_ranges 0x0000000000000000 0x38 ./Peripheral/src/ch32v30x_crc.o + .debug_line 0x0000000000000000 0x3ea ./Peripheral/src/ch32v30x_crc.o + .debug_str 0x0000000000000000 0x672 ./Peripheral/src/ch32v30x_crc.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_crc.o + .debug_frame 0x0000000000000000 0x70 ./Peripheral/src/ch32v30x_crc.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dac.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dac.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dac.o + .text.DAC_DeInit + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_dac.o + .text.DAC_Init + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_dac.o + .text.DAC_StructInit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_dac.o + .text.DAC_Cmd 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_dac.o + .text.DAC_DMACmd + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_dac.o + .text.DAC_SoftwareTriggerCmd + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_dac.o + .text.DAC_DualSoftwareTriggerCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_dac.o + .text.DAC_WaveGenerationCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_dac.o + .text.DAC_SetChannel1Data + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_dac.o + .text.DAC_SetChannel2Data + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_dac.o + .text.DAC_SetDualChannelData + 0x0000000000000000 0x1c ./Peripheral/src/ch32v30x_dac.o + .text.DAC_GetDataOutputValue + 0x0000000000000000 0x26 ./Peripheral/src/ch32v30x_dac.o + .debug_info 0x0000000000000000 0xdc4 ./Peripheral/src/ch32v30x_dac.o + .debug_abbrev 0x0000000000000000 0x2fe ./Peripheral/src/ch32v30x_dac.o + .debug_loc 0x0000000000000000 0x23b ./Peripheral/src/ch32v30x_dac.o + .debug_aranges + 0x0000000000000000 0x78 ./Peripheral/src/ch32v30x_dac.o + .debug_ranges 0x0000000000000000 0x68 ./Peripheral/src/ch32v30x_dac.o + .debug_line 0x0000000000000000 0x812 ./Peripheral/src/ch32v30x_dac.o + .debug_str 0x0000000000000000 0x7f6 ./Peripheral/src/ch32v30x_dac.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_dac.o + .debug_frame 0x0000000000000000 0xf4 ./Peripheral/src/ch32v30x_dac.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dbgmcu.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dbgmcu.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dbgmcu.o + .text.DBGMCU_GetREVID + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_dbgmcu.o + .text.DBGMCU_GetDEVID + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_info 0x0000000000000000 0x971 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_abbrev 0x0000000000000000 0x1d1 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_aranges + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_ranges 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_line 0x0000000000000000 0x285 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_str 0x0000000000000000 0x5bd ./Peripheral/src/ch32v30x_dbgmcu.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_frame 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_dbgmcu.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dma.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dma.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_DeInit + 0x0000000000000000 0x16c ./Peripheral/src/ch32v30x_dma.o + .text.DMA_Init + 0x0000000000000000 0x38 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_StructInit + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_dma.o + .text.DMA_Cmd 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_ITConfig + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_SetCurrDataCounter + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_GetCurrDataCounter + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_GetFlagStatus + 0x0000000000000000 0x32 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_ClearFlag + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_dma.o + .text.DMA_GetITStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_dma.o + .text.DMA_ClearITPendingBit + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_dma.o + .debug_info 0x0000000000000000 0xd1a ./Peripheral/src/ch32v30x_dma.o + .debug_abbrev 0x0000000000000000 0x2fd ./Peripheral/src/ch32v30x_dma.o + .debug_loc 0x0000000000000000 0x19a ./Peripheral/src/ch32v30x_dma.o + .debug_aranges + 0x0000000000000000 0x60 ./Peripheral/src/ch32v30x_dma.o + .debug_ranges 0x0000000000000000 0x50 ./Peripheral/src/ch32v30x_dma.o + .debug_line 0x0000000000000000 0x9f9 ./Peripheral/src/ch32v30x_dma.o + .debug_str 0x0000000000000000 0x7ea ./Peripheral/src/ch32v30x_dma.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_dma.o + .debug_frame 0x0000000000000000 0xd8 ./Peripheral/src/ch32v30x_dma.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dvp.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dvp.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_dvp.o + .text.DVP_INTCfg + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_dvp.o + .text.DVP_Mode + 0x0000000000000000 0x32 ./Peripheral/src/ch32v30x_dvp.o + .text.DVP_Cfg 0x0000000000000000 0x62 ./Peripheral/src/ch32v30x_dvp.o + .debug_info 0x0000000000000000 0xbcc ./Peripheral/src/ch32v30x_dvp.o + .debug_abbrev 0x0000000000000000 0x241 ./Peripheral/src/ch32v30x_dvp.o + .debug_loc 0x0000000000000000 0x74 ./Peripheral/src/ch32v30x_dvp.o + .debug_aranges + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_dvp.o + .debug_ranges 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_dvp.o + .debug_line 0x0000000000000000 0x45d ./Peripheral/src/ch32v30x_dvp.o + .debug_str 0x0000000000000000 0x733 ./Peripheral/src/ch32v30x_dvp.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_dvp.o + .debug_frame 0x0000000000000000 0x40 ./Peripheral/src/ch32v30x_dvp.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_eth.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_eth.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DeInit + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_StructInit + 0x0000000000000000 0xd8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_HandleTxPkt + 0x0000000000000000 0x7e ./Peripheral/src/ch32v30x_eth.o + .text.ETH_HandleRxPkt + 0x0000000000000000 0x96 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetRxPktSize + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DropRxPkt + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_eth.o + .text.ETH_ReadPHYRegister + 0x0000000000000000 0x58 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_WritePHYRegister + 0x0000000000000000 0x52 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_PHYLoopBackCmd + 0x0000000000000000 0x40 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACTransmissionCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACReceptionCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetFlowControlBusyStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_InitiatePauseControlFrame + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_BackPressureActivationCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetMACFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetMACITStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACITConfig + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACAddressConfig + 0x0000000000000000 0x32 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetMACAddress + 0x0000000000000000 0x32 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACAddressPerfectFilterCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACAddressFilterConfig + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MACAddressMaskBytesFilterConfig + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescChainInit + 0x0000000000000000 0x46 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescRingInit + 0x0000000000000000 0x44 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMATxDescFlagStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMATxDescCollisionCount + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetDMATxDescOwnBit + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescTransmitITConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescFrameSegmentConfig + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescChecksumInsertionConfig + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescCRCCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescEndOfRingCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescSecondAddressChainedCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescShortFramePaddingCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescTimeStampCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATxDescBufferSizeConfig + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMARxDescChainInit + 0x0000000000000000 0x50 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMARxDescRingInit + 0x0000000000000000 0x52 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMARxDescFlagStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetDMARxDescOwnBit + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMARxDescFrameLength + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMARxDescReceiveITConfig + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMARxDescEndOfRingCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMARxDescSecondAddressChainedCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMARxDescBufferSize + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SoftwareReset + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetSoftwareResetStatus + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetlinkStaus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMAFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMAClearFlag + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMAITStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMAClearITPendingBit + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetTransmitProcessState + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetReceiveProcessState + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_FlushTransmitFIFO + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_Start + 0x0000000000000000 0x40 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetFlushTransmitFIFOStatus + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMATransmissionCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMAReceptionCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMAITConfig + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetDMAOverflowStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetRxOverflowMissedFrameCounter + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetBufferUnavailableMissedFrameCounter + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetCurrentTxDescStartAddress + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetCurrentRxDescStartAddress + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetCurrentTxBufferAddress + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetCurrentRxBufferAddress + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_ResumeDMATransmission + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_ResumeDMAReception + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_ResetWakeUpFrameFilterRegisterPointer + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetWakeUpFrameFilterRegister + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GlobalUnicastWakeUpCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetPMTFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_WakeUpFrameDetectionCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MagicPacketDetectionCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_PowerDownCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MMCCounterFreezeCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MMCResetOnReadCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MMCCounterRolloverCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MMCCountersReset + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_MMCITConfig + 0x0000000000000000 0x5c ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetMMCITStatus + 0x0000000000000000 0x3a ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetMMCRegister + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_EnablePTPTimeStampAddend + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_EnablePTPTimeStampInterruptTrigger + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_EnablePTPTimeStampUpdate + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_InitializePTPTimeStamp + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_PTPUpdateMethodConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_PTPTimeStampCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetPTPFlagStatus + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetPTPSubSecondIncrement + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetPTPTimeStampUpdate + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetPTPTimeStampAddend + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_SetPTPTargetTime + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_eth.o + .text.ETH_GetPTPRegister + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMAPTPTxDescChainInit + 0x0000000000000000 0x64 ./Peripheral/src/ch32v30x_eth.o + .text.ETH_DMAPTPRxDescChainInit + 0x0000000000000000 0x6e ./Peripheral/src/ch32v30x_eth.o + .text.ETH_HandlePTPTxPkt + 0x0000000000000000 0xda ./Peripheral/src/ch32v30x_eth.o + .text.ETH_HandlePTPRxPkt + 0x0000000000000000 0xca ./Peripheral/src/ch32v30x_eth.o + .text.RGMII_TXC_Delay + 0x0000000000000000 0x26 ./Peripheral/src/ch32v30x_eth.o + .rodata.ETH_GetSoftwareResetStatus.str1.4 + 0x0000000000000000 0x15 ./Peripheral/src/ch32v30x_eth.o + .debug_info 0x0000000000000000 0x2718 ./Peripheral/src/ch32v30x_eth.o + .debug_abbrev 0x0000000000000000 0x48e ./Peripheral/src/ch32v30x_eth.o + .debug_loc 0x0000000000000000 0xf4f ./Peripheral/src/ch32v30x_eth.o + .debug_aranges + 0x0000000000000000 0x300 ./Peripheral/src/ch32v30x_eth.o + .debug_ranges 0x0000000000000000 0x368 ./Peripheral/src/ch32v30x_eth.o + .debug_line 0x0000000000000000 0x3182 ./Peripheral/src/ch32v30x_eth.o + .debug_str 0x0000000000000000 0x18fb ./Peripheral/src/ch32v30x_eth.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_eth.o + .debug_frame 0x0000000000000000 0x6b0 ./Peripheral/src/ch32v30x_eth.o + COMMON 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_eth.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_exti.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_exti.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_DeInit + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_Init + 0x0000000000000000 0x6a ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_StructInit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_GenerateSWInterrupt + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_GetFlagStatus + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_ClearFlag + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_GetITStatus + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_exti.o + .text.EXTI_ClearITPendingBit + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_exti.o + .debug_info 0x0000000000000000 0xc14 ./Peripheral/src/ch32v30x_exti.o + .debug_abbrev 0x0000000000000000 0x2da ./Peripheral/src/ch32v30x_exti.o + .debug_loc 0x0000000000000000 0x181 ./Peripheral/src/ch32v30x_exti.o + .debug_aranges + 0x0000000000000000 0x50 ./Peripheral/src/ch32v30x_exti.o + .debug_ranges 0x0000000000000000 0x40 ./Peripheral/src/ch32v30x_exti.o + .debug_line 0x0000000000000000 0x5fe ./Peripheral/src/ch32v30x_exti.o + .debug_str 0x0000000000000000 0x784 ./Peripheral/src/ch32v30x_exti.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_exti.o + .debug_frame 0x0000000000000000 0x90 ./Peripheral/src/ch32v30x_exti.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_flash.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_flash.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_Unlock + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_UnlockBank1 + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_Lock + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_LockBank1 + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_GetUserOptionByte + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_GetWriteProtectionOptionByte + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_GetReadOutProtectionStatus + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ITConfig + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_GetFlagStatus + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ClearFlag + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_GetStatus + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_GetBank1Status + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_WaitForLastOperation + 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ErasePage + 0x0000000000000000 0x4c ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_EraseAllPages + 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_EraseAllBank1Pages + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_EraseOptionBytes + 0x0000000000000000 0xe6 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ProgramWord + 0x0000000000000000 0x68 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ProgramHalfWord + 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ProgramOptionByteData + 0x0000000000000000 0x11a ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_EnableWriteProtection + 0x0000000000000000 0x106 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ReadOutProtection + 0x0000000000000000 0xf4 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_UserOptionByteConfig + 0x0000000000000000 0x108 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_WaitForLastBank1Operation + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_Unlock_Fast + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_Lock_Fast + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ErasePage_Fast + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_EraseBlock_32K_Fast + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_EraseBlock_64K_Fast + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_ProgramPage_Fast + 0x0000000000000000 0x64 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_Access_Clock_Cfg + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_flash.o + .text.FLASH_Enhance_Mode + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_flash.o + .debug_info 0x0000000000000000 0x137f ./Peripheral/src/ch32v30x_flash.o + .debug_abbrev 0x0000000000000000 0x43d ./Peripheral/src/ch32v30x_flash.o + .debug_loc 0x0000000000000000 0x7f2 ./Peripheral/src/ch32v30x_flash.o + .debug_aranges + 0x0000000000000000 0xf0 ./Peripheral/src/ch32v30x_flash.o + .debug_ranges 0x0000000000000000 0xe0 ./Peripheral/src/ch32v30x_flash.o + .debug_line 0x0000000000000000 0x1c70 ./Peripheral/src/ch32v30x_flash.o + .debug_str 0x0000000000000000 0xa6b ./Peripheral/src/ch32v30x_flash.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_flash.o + .debug_frame 0x0000000000000000 0x32c ./Peripheral/src/ch32v30x_flash.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_fsmc.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_fsmc.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NORSRAMDeInit + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NANDDeInit + 0x0000000000000000 0x26 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NORSRAMInit + 0x0000000000000000 0xba ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NANDInit + 0x0000000000000000 0x84 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NORSRAMStructInit + 0x0000000000000000 0x60 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NANDStructInit + 0x0000000000000000 0x36 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NORSRAMCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NANDCmd + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_NANDECCCmd + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_GetECC + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_ITConfig + 0x0000000000000000 0x26 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_GetFlagStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_ClearFlag + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_GetITStatus + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_fsmc.o + .text.FSMC_ClearITPendingBit + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_fsmc.o + .debug_info 0x0000000000000000 0x1054 ./Peripheral/src/ch32v30x_fsmc.o + .debug_abbrev 0x0000000000000000 0x2d9 ./Peripheral/src/ch32v30x_fsmc.o + .debug_loc 0x0000000000000000 0x454 ./Peripheral/src/ch32v30x_fsmc.o + .debug_aranges + 0x0000000000000000 0x90 ./Peripheral/src/ch32v30x_fsmc.o + .debug_ranges 0x0000000000000000 0x80 ./Peripheral/src/ch32v30x_fsmc.o + .debug_line 0x0000000000000000 0xe5a ./Peripheral/src/ch32v30x_fsmc.o + .debug_str 0x0000000000000000 0xabf ./Peripheral/src/ch32v30x_fsmc.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_fsmc.o + .debug_frame 0x0000000000000000 0x100 ./Peripheral/src/ch32v30x_fsmc.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_gpio.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_gpio.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_DeInit + 0x0000000000000000 0xa4 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_AFIODeInit + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_StructInit + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_ReadInputDataBit + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_ReadInputData + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_ReadOutputDataBit + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_ReadOutputData + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_SetBits + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_ResetBits + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_WriteBit + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_Write + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_PinLockConfig + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_EventOutputConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_EventOutputCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_PinRemapConfig + 0x0000000000000000 0xc4 ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_EXTILineConfig + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_gpio.o + .text.GPIO_ETH_MediaInterfaceConfig + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_gpio.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_i2c.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_i2c.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_DeInit + 0x0000000000000000 0x4c ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_Init + 0x0000000000000000 0x100 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_StructInit + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_Cmd 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_DMACmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_DMALastTransferCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GenerateSTART + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GenerateSTOP + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_AcknowledgeConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_OwnAddress2Config + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_DualAddressCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GeneralCallCmd + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_ITConfig + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_SendData + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_ReceiveData + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_Send7bitAddress + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_ReadRegister + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_SoftwareResetCmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_NACKPositionConfig + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_SMBusAlertConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_TransmitPEC + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_PECPositionConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_CalculatePEC + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GetPEC + 0x0000000000000000 0x6 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_ARPCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_StretchClockCmd + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_FastModeDutyCycleConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_CheckEvent + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GetLastEvent + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GetFlagStatus + 0x0000000000000000 0x32 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_ClearFlag + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_GetITStatus + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_i2c.o + .text.I2C_ClearITPendingBit + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_i2c.o + .debug_info 0x0000000000000000 0x1488 ./Peripheral/src/ch32v30x_i2c.o + .debug_abbrev 0x0000000000000000 0x3a7 ./Peripheral/src/ch32v30x_i2c.o + .debug_loc 0x0000000000000000 0x70d ./Peripheral/src/ch32v30x_i2c.o + .debug_aranges + 0x0000000000000000 0x110 ./Peripheral/src/ch32v30x_i2c.o + .debug_ranges 0x0000000000000000 0x100 ./Peripheral/src/ch32v30x_i2c.o + .debug_line 0x0000000000000000 0x1165 ./Peripheral/src/ch32v30x_i2c.o + .debug_str 0x0000000000000000 0xad7 ./Peripheral/src/ch32v30x_i2c.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_i2c.o + .debug_frame 0x0000000000000000 0x264 ./Peripheral/src/ch32v30x_i2c.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_iwdg.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_iwdg.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_iwdg.o + .text.IWDG_WriteAccessCmd + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_iwdg.o + .text.IWDG_SetPrescaler + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_iwdg.o + .text.IWDG_SetReload + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_iwdg.o + .text.IWDG_ReloadCounter + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_iwdg.o + .text.IWDG_Enable + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_iwdg.o + .text.IWDG_GetFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_iwdg.o + .debug_info 0x0000000000000000 0xabb ./Peripheral/src/ch32v30x_iwdg.o + .debug_abbrev 0x0000000000000000 0x282 ./Peripheral/src/ch32v30x_iwdg.o + .debug_loc 0x0000000000000000 0x68 ./Peripheral/src/ch32v30x_iwdg.o + .debug_aranges + 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_iwdg.o + .debug_ranges 0x0000000000000000 0x38 ./Peripheral/src/ch32v30x_iwdg.o + .debug_line 0x0000000000000000 0x3d9 ./Peripheral/src/ch32v30x_iwdg.o + .debug_str 0x0000000000000000 0x696 ./Peripheral/src/ch32v30x_iwdg.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_iwdg.o + .debug_frame 0x0000000000000000 0x70 ./Peripheral/src/ch32v30x_iwdg.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_misc.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_misc.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_misc.o + .text.NVIC_PriorityGroupConfig + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_misc.o + .text.NVIC_Init + 0x0000000000000000 0xaa ./Peripheral/src/ch32v30x_misc.o + .sbss.NVIC_Priority_Group + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_misc.o + .debug_info 0x0000000000000000 0xf74 ./Peripheral/src/ch32v30x_misc.o + .debug_abbrev 0x0000000000000000 0x2fb ./Peripheral/src/ch32v30x_misc.o + .debug_loc 0x0000000000000000 0xce ./Peripheral/src/ch32v30x_misc.o + .debug_aranges + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_misc.o + .debug_ranges 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_misc.o + .debug_line 0x0000000000000000 0x4f8 ./Peripheral/src/ch32v30x_misc.o + .debug_str 0x0000000000000000 0xcc2 ./Peripheral/src/ch32v30x_misc.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_misc.o + .debug_frame 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_misc.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_opa.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_opa.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_opa.o + .text.OPA_DeInit + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_opa.o + .text.OPA_Init + 0x0000000000000000 0x36 ./Peripheral/src/ch32v30x_opa.o + .text.OPA_StructInit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_opa.o + .text.OPA_Cmd 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_opa.o + .debug_info 0x0000000000000000 0xb2f ./Peripheral/src/ch32v30x_opa.o + .debug_abbrev 0x0000000000000000 0x252 ./Peripheral/src/ch32v30x_opa.o + .debug_loc 0x0000000000000000 0x56 ./Peripheral/src/ch32v30x_opa.o + .debug_aranges + 0x0000000000000000 0x38 ./Peripheral/src/ch32v30x_opa.o + .debug_ranges 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_opa.o + .debug_line 0x0000000000000000 0x486 ./Peripheral/src/ch32v30x_opa.o + .debug_str 0x0000000000000000 0x6ac ./Peripheral/src/ch32v30x_opa.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_opa.o + .debug_frame 0x0000000000000000 0x50 ./Peripheral/src/ch32v30x_opa.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_pwr.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_pwr.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_DeInit + 0x0000000000000000 0x2c ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_BackupAccessCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_PVDCmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_PVDLevelConfig + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_WakeUpPinCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_EnterSTOPMode + 0x0000000000000000 0x68 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_EnterSTANDBYMode + 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_GetFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_ClearFlag + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_EnterSTANDBYMode_RAM + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_EnterSTANDBYMode_RAM_LV + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_EnterSTANDBYMode_RAM_VBAT_EN + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_pwr.o + .text.PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_pwr.o + .debug_info 0x0000000000000000 0xf18 ./Peripheral/src/ch32v30x_pwr.o + .debug_abbrev 0x0000000000000000 0x351 ./Peripheral/src/ch32v30x_pwr.o + .debug_loc 0x0000000000000000 0x21a ./Peripheral/src/ch32v30x_pwr.o + .debug_aranges + 0x0000000000000000 0x80 ./Peripheral/src/ch32v30x_pwr.o + .debug_ranges 0x0000000000000000 0x88 ./Peripheral/src/ch32v30x_pwr.o + .debug_line 0x0000000000000000 0x92f ./Peripheral/src/ch32v30x_pwr.o + .debug_str 0x0000000000000000 0x82b ./Peripheral/src/ch32v30x_pwr.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_pwr.o + .debug_frame 0x0000000000000000 0xec ./Peripheral/src/ch32v30x_pwr.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rcc.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rcc.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_DeInit + 0x0000000000000000 0x52 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_HSEConfig + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_AdjustHSICalibrationValue + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_HSICmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PLLConfig + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PLLCmd + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_SYSCLKConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_GetSYSCLKSource + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_HCLKConfig + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PCLK1Config + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PCLK2Config + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ITConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ADCCLKConfig + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_LSEConfig + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_LSICmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_RTCCLKConfig + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_RTCCLKCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_AHBPeriphClockCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_APB1PeriphClockCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_APB2PeriphResetCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_APB1PeriphResetCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_BackupResetCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ClockSecuritySystemCmd + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_MCOConfig + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_GetFlagStatus + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_WaitForHSEStartUp + 0x0000000000000000 0x42 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ClearFlag + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_GetITStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ClearITPendingBit + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PREDIV1Config + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PREDIV2Config + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PLL2Config + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PLL2Cmd + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PLL3Config + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_PLL3Cmd + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_OTGFSCLKConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_I2S2CLKConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_I2S3CLKConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_AHBPeriphResetCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ADCCLKADJcmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_RNGCLKConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ETH1GCLKConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_ETH1G_125Mcmd + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_USBHSConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_USBHSPLLCLKConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_USBHSPLLCKREFCLKConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_USBHSPHYPLLALIVEcmd + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rcc.o + .text.RCC_USBCLK48MConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_rcc.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rng.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rng.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rng.o + .text.RNG_Cmd 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rng.o + .text.RNG_GetRandomNumber + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_rng.o + .text.RNG_ITConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rng.o + .text.RNG_GetFlagStatus + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rng.o + .text.RNG_ClearFlag + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_rng.o + .text.RNG_GetITStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rng.o + .text.RNG_ClearITPendingBit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rng.o + .debug_info 0x0000000000000000 0xb09 ./Peripheral/src/ch32v30x_rng.o + .debug_abbrev 0x0000000000000000 0x2c8 ./Peripheral/src/ch32v30x_rng.o + .debug_loc 0x0000000000000000 0xa8 ./Peripheral/src/ch32v30x_rng.o + .debug_aranges + 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_rng.o + .debug_ranges 0x0000000000000000 0x38 ./Peripheral/src/ch32v30x_rng.o + .debug_line 0x0000000000000000 0x453 ./Peripheral/src/ch32v30x_rng.o + .debug_str 0x0000000000000000 0x683 ./Peripheral/src/ch32v30x_rng.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_rng.o + .debug_frame 0x0000000000000000 0x8c ./Peripheral/src/ch32v30x_rng.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rtc.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rtc.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_ITConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_EnterConfigMode + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_ExitConfigMode + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_GetCounter + 0x0000000000000000 0x36 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_SetCounter + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_SetPrescaler + 0x0000000000000000 0x3e ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_SetAlarm + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_GetDivider + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_WaitForLastTask + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_WaitForSynchro + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_GetFlagStatus + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_ClearFlag + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_GetITStatus + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_rtc.o + .text.RTC_ClearITPendingBit + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_rtc.o + .debug_info 0x0000000000000000 0xd56 ./Peripheral/src/ch32v30x_rtc.o + .debug_abbrev 0x0000000000000000 0x2c0 ./Peripheral/src/ch32v30x_rtc.o + .debug_loc 0x0000000000000000 0x272 ./Peripheral/src/ch32v30x_rtc.o + .debug_aranges + 0x0000000000000000 0x80 ./Peripheral/src/ch32v30x_rtc.o + .debug_ranges 0x0000000000000000 0x70 ./Peripheral/src/ch32v30x_rtc.o + .debug_line 0x0000000000000000 0x7cf ./Peripheral/src/ch32v30x_rtc.o + .debug_str 0x0000000000000000 0x7e3 ./Peripheral/src/ch32v30x_rtc.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_rtc.o + .debug_frame 0x0000000000000000 0x12c ./Peripheral/src/ch32v30x_rtc.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_sdio.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_sdio.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_DeInit + 0x0000000000000000 0x30 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_Init + 0x0000000000000000 0x2a ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_StructInit + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_ClockCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_SetPowerState + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetPowerState + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_ITConfig + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_DMACmd + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_SendCommand + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_CmdStructInit + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetCommandResponse + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetResponse + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_DataConfig + 0x0000000000000000 0x26 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_DataStructInit + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetDataCounter + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_ReadData + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_WriteData + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetFIFOCount + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_StartSDIOReadWait + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_StopSDIOReadWait + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_SetSDIOReadWaitMode + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_SetSDIOOperation + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_SendSDIOSuspendCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_CommandCompletionCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_CEATAITCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_SendCEATACmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetFlagStatus + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_ClearFlag + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_GetITStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_sdio.o + .text.SDIO_ClearITPendingBit + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_sdio.o + .debug_info 0x0000000000000000 0x10d8 ./Peripheral/src/ch32v30x_sdio.o + .debug_abbrev 0x0000000000000000 0x385 ./Peripheral/src/ch32v30x_sdio.o + .debug_loc 0x0000000000000000 0x1bb ./Peripheral/src/ch32v30x_sdio.o + .debug_aranges + 0x0000000000000000 0xf8 ./Peripheral/src/ch32v30x_sdio.o + .debug_ranges 0x0000000000000000 0xe8 ./Peripheral/src/ch32v30x_sdio.o + .debug_line 0x0000000000000000 0xcc2 ./Peripheral/src/ch32v30x_sdio.o + .debug_str 0x0000000000000000 0xa55 ./Peripheral/src/ch32v30x_sdio.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_sdio.o + .debug_frame 0x0000000000000000 0x204 ./Peripheral/src/ch32v30x_sdio.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_spi.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_spi.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_DeInit + 0x0000000000000000 0x70 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_Init + 0x0000000000000000 0x3e ./Peripheral/src/ch32v30x_spi.o + .text.I2S_Init + 0x0000000000000000 0xc6 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_StructInit + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_spi.o + .text.I2S_StructInit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_Cmd 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_spi.o + .text.I2S_Cmd 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_ITConfig + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_DMACmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_SendData + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_ReceiveData + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_NSSInternalSoftwareConfig + 0x0000000000000000 0x24 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_SSOutputCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_DataSizeConfig + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_TransmitCRC + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_spi.o + .text.SPI_CalculateCRC + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_GetCRC + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_GetCRCPolynomial + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_BiDirectionalLineConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_GetFlagStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_ClearFlag + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_GetITStatus + 0x0000000000000000 0x28 ./Peripheral/src/ch32v30x_spi.o + .text.SPI_I2S_ClearITPendingBit + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_spi.o + .debug_info 0x0000000000000000 0x12d4 ./Peripheral/src/ch32v30x_spi.o + .debug_abbrev 0x0000000000000000 0x312 ./Peripheral/src/ch32v30x_spi.o + .debug_loc 0x0000000000000000 0x598 ./Peripheral/src/ch32v30x_spi.o + .debug_aranges + 0x0000000000000000 0xd0 ./Peripheral/src/ch32v30x_spi.o + .debug_ranges 0x0000000000000000 0xc0 ./Peripheral/src/ch32v30x_spi.o + .debug_line 0x0000000000000000 0xd58 ./Peripheral/src/ch32v30x_spi.o + .debug_str 0x0000000000000000 0xa86 ./Peripheral/src/ch32v30x_spi.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_spi.o + .debug_frame 0x0000000000000000 0x1a8 ./Peripheral/src/ch32v30x_spi.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_tim.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_tim.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_tim.o + .text.TI1_Config + 0x0000000000000000 0x82 ./Peripheral/src/ch32v30x_tim.o + .text.TI2_Config + 0x0000000000000000 0x9a ./Peripheral/src/ch32v30x_tim.o + .text.TIM_DeInit + 0x0000000000000000 0x138 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_TimeBaseInit + 0x0000000000000000 0xaa ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC1Init + 0x0000000000000000 0x82 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC2Init + 0x0000000000000000 0xae ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC3Init + 0x0000000000000000 0xac ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC4Init + 0x0000000000000000 0x88 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_BDTRConfig + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_TimeBaseStructInit + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OCStructInit + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ICStructInit + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_BDTRStructInit + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_tim.o + .text.TIM_Cmd 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_CtrlPWMOutputs + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ITConfig + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GenerateEvent + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_DMAConfig + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_DMACmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_InternalClockConfig + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ITRxExternalClockConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_TIxExternalClockConfig + 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ETRConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ETRClockMode1Config + 0x0000000000000000 0x2a ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ETRClockMode2Config + 0x0000000000000000 0x22 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_PrescalerConfig + 0x0000000000000000 0x6 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_CounterModeConfig + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectInputTrigger + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_EncoderInterfaceConfig + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ForcedOC1Config + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ForcedOC2Config + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ForcedOC3Config + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ForcedOC4Config + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ARRPreloadConfig + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectCOM + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectCCDMA + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_CCPreloadControl + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC1PreloadConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC2PreloadConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC3PreloadConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC4PreloadConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC1FastConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC2FastConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC3FastConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC4FastConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ClearOC1Ref + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ClearOC2Ref + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ClearOC3Ref + 0x0000000000000000 0x10 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ClearOC4Ref + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC1PolarityConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC1NPolarityConfig + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC2PolarityConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC2NPolarityConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC3PolarityConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC3NPolarityConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_OC4PolarityConfig + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_CCxCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_CCxNCmd + 0x0000000000000000 0x20 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectOCxM + 0x0000000000000000 0x4c ./Peripheral/src/ch32v30x_tim.o + .text.TIM_UpdateDisableConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_UpdateRequestConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectHallSensor + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectOnePulseMode + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectOutputTrigger + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectSlaveMode + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SelectMasterSlaveMode + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetCounter + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetAutoreload + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetCompare1 + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetCompare2 + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetCompare3 + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetCompare4 + 0x0000000000000000 0x6 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetIC1Prescaler + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetIC2Prescaler + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_tim.o + .text.TIM_PWMIConfig + 0x0000000000000000 0x92 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetIC3Prescaler + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetIC4Prescaler + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ICInit + 0x0000000000000000 0x1c0 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_SetClockDivision + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetCapture1 + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetCapture2 + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetCapture3 + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetCapture4 + 0x0000000000000000 0x6 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetCounter + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetPrescaler + 0x0000000000000000 0x4 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetFlagStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ClearFlag + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_tim.o + .text.TIM_GetITStatus + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_tim.o + .text.TIM_ClearITPendingBit + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_tim.o + .debug_info 0x0000000000000000 0x2a1d ./Peripheral/src/ch32v30x_tim.o + .debug_abbrev 0x0000000000000000 0x408 ./Peripheral/src/ch32v30x_tim.o + .debug_loc 0x0000000000000000 0x195e ./Peripheral/src/ch32v30x_tim.o + .debug_aranges + 0x0000000000000000 0x2d0 ./Peripheral/src/ch32v30x_tim.o + .debug_ranges 0x0000000000000000 0x2f0 ./Peripheral/src/ch32v30x_tim.o + .debug_line 0x0000000000000000 0x331e ./Peripheral/src/ch32v30x_tim.o + .debug_str 0x0000000000000000 0x1272 ./Peripheral/src/ch32v30x_tim.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_tim.o + .debug_frame 0x0000000000000000 0x614 ./Peripheral/src/ch32v30x_tim.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_usart.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_usart.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_usart.o + .text.USART_DeInit + 0x0000000000000000 0x112 ./Peripheral/src/ch32v30x_usart.o + .text.USART_StructInit + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_ClockInit + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_usart.o + .text.USART_ClockStructInit + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_usart.o + .text.USART_ITConfig + 0x0000000000000000 0x36 ./Peripheral/src/ch32v30x_usart.o + .text.USART_DMACmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_usart.o + .text.USART_SetAddress + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_usart.o + .text.USART_WakeUpConfig + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_usart.o + .text.USART_ReceiverWakeUpCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_LINBreakDetectLengthConfig + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_LINCmd + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_usart.o + .text.USART_ReceiveData + 0x0000000000000000 0x8 ./Peripheral/src/ch32v30x_usart.o + .text.USART_SendBreak + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_usart.o + .text.USART_SetGuardTime + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_usart.o + .text.USART_SetPrescaler + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_SmartCardCmd + 0x0000000000000000 0x1a ./Peripheral/src/ch32v30x_usart.o + .text.USART_SmartCardNACKCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_HalfDuplexCmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_OverSampling8Cmd + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_usart.o + .text.USART_OneBitMethodCmd + 0x0000000000000000 0x1e ./Peripheral/src/ch32v30x_usart.o + .text.USART_IrDAConfig + 0x0000000000000000 0x16 ./Peripheral/src/ch32v30x_usart.o + .text.USART_IrDACmd + 0x0000000000000000 0x18 ./Peripheral/src/ch32v30x_usart.o + .text.USART_ClearFlag + 0x0000000000000000 0xc ./Peripheral/src/ch32v30x_usart.o + .text.USART_GetITStatus + 0x0000000000000000 0x3c ./Peripheral/src/ch32v30x_usart.o + .text.USART_ClearITPendingBit + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_usart.o + .text 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_wwdg.o + .data 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_wwdg.o + .bss 0x0000000000000000 0x0 ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_DeInit + 0x0000000000000000 0x2e ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_SetPrescaler + 0x0000000000000000 0x14 ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_SetWindowValue + 0x0000000000000000 0x26 ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_EnableIT + 0x0000000000000000 0x12 ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_SetCounter + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_Enable + 0x0000000000000000 0xe ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_GetFlagStatus + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_wwdg.o + .text.WWDG_ClearFlag + 0x0000000000000000 0xa ./Peripheral/src/ch32v30x_wwdg.o + .debug_info 0x0000000000000000 0xb2f ./Peripheral/src/ch32v30x_wwdg.o + .debug_abbrev 0x0000000000000000 0x29d ./Peripheral/src/ch32v30x_wwdg.o + .debug_loc 0x0000000000000000 0xae ./Peripheral/src/ch32v30x_wwdg.o + .debug_aranges + 0x0000000000000000 0x58 ./Peripheral/src/ch32v30x_wwdg.o + .debug_ranges 0x0000000000000000 0x48 ./Peripheral/src/ch32v30x_wwdg.o + .debug_line 0x0000000000000000 0x4c1 ./Peripheral/src/ch32v30x_wwdg.o + .debug_str 0x0000000000000000 0x6a9 ./Peripheral/src/ch32v30x_wwdg.o + .comment 0x0000000000000000 0x34 ./Peripheral/src/ch32v30x_wwdg.o + .debug_frame 0x0000000000000000 0xa4 ./Peripheral/src/ch32v30x_wwdg.o + .text 0x0000000000000000 0x0 ./Debug/debug.o + .data 0x0000000000000000 0x0 ./Debug/debug.o + .bss 0x0000000000000000 0x0 ./Debug/debug.o + .text.Delay_Init + 0x0000000000000000 0x32 ./Debug/debug.o + .text.Delay_Us + 0x0000000000000000 0x32 ./Debug/debug.o + .text.Delay_Ms + 0x0000000000000000 0x32 ./Debug/debug.o + .sbss.p_ms 0x0000000000000000 0x2 ./Debug/debug.o + .sbss.p_us 0x0000000000000000 0x1 ./Debug/debug.o + .text 0x0000000000000000 0x0 ./Core/core_riscv.o + .data 0x0000000000000000 0x0 ./Core/core_riscv.o + .bss 0x0000000000000000 0x0 ./Core/core_riscv.o + .text.__get_FFLAGS + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_FFLAGS + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_FRM + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_FRM + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_FCSR + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_FCSR + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MSTATUS + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MSTATUS + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MISA + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MISA + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MIE + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MIE + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MTVEC + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MTVEC + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MSCRATCH + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MSCRATCH + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MEPC + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MEPC + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MCAUSE + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MCAUSE + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MTVAL + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__set_MTVAL + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MVENDORID + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MARCHID + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MIMPID + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_MHARTID + 0x0000000000000000 0x6 ./Core/core_riscv.o + .text.__get_SP + 0x0000000000000000 0x4 ./Core/core_riscv.o + .debug_info 0x0000000000000000 0x4bf ./Core/core_riscv.o + .debug_abbrev 0x0000000000000000 0x10d ./Core/core_riscv.o + .debug_aranges + 0x0000000000000000 0xf0 ./Core/core_riscv.o + .debug_ranges 0x0000000000000000 0xe0 ./Core/core_riscv.o + .debug_line 0x0000000000000000 0x5be ./Core/core_riscv.o + .debug_str 0x0000000000000000 0x2df ./Core/core_riscv.o + .comment 0x0000000000000000 0x34 ./Core/core_riscv.o + .debug_frame 0x0000000000000000 0x1c0 ./Core/core_riscv.o + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) + .text.__divdi3 + 0x0000000000000000 0x3d8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) + .eh_frame 0x0000000000000000 0x28 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_divdi3.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_udivdi3.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_udivdi3.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_udivdi3.o) + .eh_frame 0x0000000000000000 0x28 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_udivdi3.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(eqdf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(eqdf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(eqdf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(gedf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(gedf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(gedf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(ledf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(ledf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(ledf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(subdf3.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(subdf3.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(subdf3.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixdfsi.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixdfsi.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixdfsi.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatsidf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatsidf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatsidf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatunsidf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatunsidf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatunsidf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(save-restore.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(save-restore.o) + .eh_frame 0x0000000000000000 0xf8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(save-restore.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clz.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clz.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clz.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clzsi2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clzsi2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clzsi2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + .text.__assert + 0x0000000000000000 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + .text._fprintf_r + 0x0000000000000000 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcmp.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcmp.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcmp.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcpy.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcpy.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcpy.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memmove.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memmove.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memmove.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memset.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .text.__sprint_r + 0x0000000000000000 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .text.vfprintf + 0x0000000000000000 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + .text._printf_r + 0x0000000000000000 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + .text._putchar_r + 0x0000000000000000 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-s_modf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-s_modf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-s_modf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + .text._snprintf_r + 0x0000000000000000 0x6e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + .text._sprintf_r + 0x0000000000000000 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strlen.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strlen.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strlen.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncpy.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncpy.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncpy.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .text.strtod_l + 0x0000000000000000 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .text.strtof_l + 0x0000000000000000 0xfc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .text.strtof 0x0000000000000000 0x108 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata.strtof_l.cst4 + 0x0000000000000000 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata.strtof_l.cst8 + 0x0000000000000000 0x8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .text.strtol_l + 0x0000000000000000 0x1a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .text.strtol 0x0000000000000000 0x26 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + .text.__swbuf 0x0000000000000000 0x16 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + .text.fflush 0x0000000000000000 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__fp_lock + 0x0000000000000000 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__fp_unlock + 0x0000000000000000 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text._cleanup + 0x0000000000000000 0x12 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__sfp_lock_acquire + 0x0000000000000000 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__sfp_lock_release + 0x0000000000000000 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__sinit_lock_acquire + 0x0000000000000000 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__sinit_lock_release + 0x0000000000000000 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__fp_lock_all + 0x0000000000000000 0x1a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text.__fp_unlock_all + 0x0000000000000000 0x1a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) + .text.__sfvwrite_r + 0x0000000000000000 0x31a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) + .debug_frame 0x0000000000000000 0x60 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fvwrite.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + .text._fwalk 0x0000000000000000 0x62 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .text._setlocale_r + 0x0000000000000000 0x64 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .text.__locale_mb_cur_max + 0x0000000000000000 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .text.__locale_ctype_ptr + 0x0000000000000000 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .text.setlocale + 0x0000000000000000 0x16 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .sbss._PathLocale + 0x0000000000000000 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + .text.localeconv + 0x0000000000000000 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + .text.free 0x0000000000000000 0x14 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + .text._mbtowc_r + 0x0000000000000000 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memchr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memchr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memchr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .text._mprec_log10 + 0x0000000000000000 0x5e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .rodata.__mprec_tinytens + 0x0000000000000000 0x28 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .rodata._mprec_log10.cst8 + 0x0000000000000000 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-callocr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-callocr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-callocr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + .text.__ssprint_r + 0x0000000000000000 0x148 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + .text.putc 0x0000000000000000 0x16 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text._init_signal_r + 0x0000000000000000 0x3e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text._signal_r + 0x0000000000000000 0x48 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text.__sigtramp_r + 0x0000000000000000 0x5a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text.signal 0x0000000000000000 0x16 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text._init_signal + 0x0000000000000000 0x12 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text.__sigtramp + 0x0000000000000000 0x14 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + .text.__seofread + 0x0000000000000000 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + .text 0x0000000000000000 0x11e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strcmp.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strcmp.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strcmp.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncmp.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncmp.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncmp.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + .text._wctomb_r + 0x0000000000000000 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-writer.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-writer.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-writer.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-ctype_.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-ctype_.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-ctype_.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-msizer.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-msizer.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-msizer.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + .text.cleanup_glue + 0x0000000000000000 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + .text._reclaim_reent + 0x0000000000000000 0x10c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unorddf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unorddf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unorddf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixunsdfsi.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixunsdfsi.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixunsdfsi.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(lesf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(lesf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(lesf2.o) + .text.__lesf2 0x0000000000000000 0x8c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(lesf2.o) + .debug_frame 0x0000000000000000 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(lesf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unordsf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unordsf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unordsf2.o) + .text.__unordsf2 + 0x0000000000000000 0x3c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unordsf2.o) + .debug_frame 0x0000000000000000 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unordsf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(extenddftf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(extenddftf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(extenddftf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(truncdfsf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(truncdfsf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(truncdfsf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(trunctfdf2.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(trunctfdf2.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(trunctfdf2.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + .text 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(_exit.o) + .data 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(_exit.o) + .bss 0x0000000000000000 0x0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(_exit.o) + +Memory Configuration + +Name Origin Length Attributes +FLASH 0x0000000000000000 0x0000000000048000 xr +RAM 0x0000000020000000 0x0000000000010000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD ./User/ch32v30x_it.o +LOAD ./User/main.o +LOAD ./User/system_ch32v30x.o +LOAD ./TencentOS_Tiny/tos_js/tos_js.o +LOAD ./TencentOS_Tiny/kernel/pm/tos_pm.o +LOAD ./TencentOS_Tiny/kernel/pm/tos_tickless.o +LOAD ./TencentOS_Tiny/kernel/core/tos_barrier.o +LOAD ./TencentOS_Tiny/kernel/core/tos_binary_heap.o +LOAD ./TencentOS_Tiny/kernel/core/tos_bitmap.o +LOAD ./TencentOS_Tiny/kernel/core/tos_char_fifo.o +LOAD ./TencentOS_Tiny/kernel/core/tos_completion.o +LOAD ./TencentOS_Tiny/kernel/core/tos_countdownlatch.o +LOAD ./TencentOS_Tiny/kernel/core/tos_event.o +LOAD ./TencentOS_Tiny/kernel/core/tos_global.o +LOAD ./TencentOS_Tiny/kernel/core/tos_mail_queue.o +LOAD ./TencentOS_Tiny/kernel/core/tos_message_queue.o +LOAD ./TencentOS_Tiny/kernel/core/tos_mmblk.o +LOAD ./TencentOS_Tiny/kernel/core/tos_mmheap.o +LOAD ./TencentOS_Tiny/kernel/core/tos_mutex.o +LOAD ./TencentOS_Tiny/kernel/core/tos_pend.o +LOAD ./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o +LOAD ./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o +LOAD ./TencentOS_Tiny/kernel/core/tos_priority_queue.o +LOAD ./TencentOS_Tiny/kernel/core/tos_ring_queue.o +LOAD ./TencentOS_Tiny/kernel/core/tos_robin.o +LOAD ./TencentOS_Tiny/kernel/core/tos_rwlock.o +LOAD ./TencentOS_Tiny/kernel/core/tos_sched.o +LOAD ./TencentOS_Tiny/kernel/core/tos_sem.o +LOAD ./TencentOS_Tiny/kernel/core/tos_stopwatch.o +LOAD ./TencentOS_Tiny/kernel/core/tos_sys.o +LOAD ./TencentOS_Tiny/kernel/core/tos_task.o +LOAD ./TencentOS_Tiny/kernel/core/tos_tick.o +LOAD ./TencentOS_Tiny/kernel/core/tos_time.o +LOAD ./TencentOS_Tiny/kernel/core/tos_timer.o +LOAD ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o +LOAD ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o +LOAD ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o +LOAD ./Startup/startup_ch32v30x.o +LOAD ./Peripheral/src/ch32v30x_adc.o +LOAD ./Peripheral/src/ch32v30x_bkp.o +LOAD ./Peripheral/src/ch32v30x_can.o +LOAD ./Peripheral/src/ch32v30x_crc.o +LOAD ./Peripheral/src/ch32v30x_dac.o +LOAD ./Peripheral/src/ch32v30x_dbgmcu.o +LOAD ./Peripheral/src/ch32v30x_dma.o +LOAD ./Peripheral/src/ch32v30x_dvp.o +LOAD ./Peripheral/src/ch32v30x_eth.o +LOAD ./Peripheral/src/ch32v30x_exti.o +LOAD ./Peripheral/src/ch32v30x_flash.o +LOAD ./Peripheral/src/ch32v30x_fsmc.o +LOAD ./Peripheral/src/ch32v30x_gpio.o +LOAD ./Peripheral/src/ch32v30x_i2c.o +LOAD ./Peripheral/src/ch32v30x_iwdg.o +LOAD ./Peripheral/src/ch32v30x_misc.o +LOAD ./Peripheral/src/ch32v30x_opa.o +LOAD ./Peripheral/src/ch32v30x_pwr.o +LOAD ./Peripheral/src/ch32v30x_rcc.o +LOAD ./Peripheral/src/ch32v30x_rng.o +LOAD ./Peripheral/src/ch32v30x_rtc.o +LOAD ./Peripheral/src/ch32v30x_sdio.o +LOAD ./Peripheral/src/ch32v30x_spi.o +LOAD ./Peripheral/src/ch32v30x_tim.o +LOAD ./Peripheral/src/ch32v30x_usart.o +LOAD ./Peripheral/src/ch32v30x_wwdg.o +LOAD ./Debug/debug.o +LOAD ./Core/core_riscv.o +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libc_nano.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a +START GROUP +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libc_nano.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a +END GROUP +START GROUP +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libc_nano.a +LOAD c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a +END GROUP + 0x0000000000005000 __stack_size = 0x5000 + [!provide] PROVIDE (_stack_size = __stack_size) + +.init 0x0000000000000000 0x38 + 0x0000000000000000 _sinit = . + 0x0000000000000000 . = ALIGN (0x4) + *(SORT_NONE(.init)) + .init 0x0000000000000000 0x38 ./Startup/startup_ch32v30x.o + 0x0000000000000000 _start + 0x0000000000000038 . = ALIGN (0x4) + 0x0000000000000038 _einit = . + +.vector 0x0000000000000038 0x1c8 + *(.vector) + .vector 0x0000000000000038 0x1a0 ./Startup/startup_ch32v30x.o + 0x0000000000000200 . = ALIGN (0x40) + *fill* 0x00000000000001d8 0x28 + +.text 0x0000000000000200 0xc898 + 0x0000000000000200 . = ALIGN (0x4) + *(.text) + .text 0x0000000000000200 0x126 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + 0x0000000000000200 port_sched_start + 0x000000000000025c SW_handler + .text 0x0000000000000326 0x60 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(save-restore.o) + 0x0000000000000326 __riscv_save_12 + 0x000000000000032e __riscv_save_9 + 0x000000000000032e __riscv_save_11 + 0x000000000000032e __riscv_save_10 + 0x000000000000032e __riscv_save_8 + 0x000000000000033c __riscv_save_4 + 0x000000000000033c __riscv_save_6 + 0x000000000000033c __riscv_save_5 + 0x000000000000033c __riscv_save_7 + 0x0000000000000356 __riscv_save_3 + 0x0000000000000356 __riscv_save_2 + 0x0000000000000356 __riscv_save_1 + 0x0000000000000356 __riscv_save_0 + 0x0000000000000362 __riscv_restore_12 + 0x0000000000000366 __riscv_restore_11 + 0x0000000000000366 __riscv_restore_9 + 0x0000000000000366 __riscv_restore_10 + 0x0000000000000366 __riscv_restore_8 + 0x0000000000000370 __riscv_restore_5 + 0x0000000000000370 __riscv_restore_7 + 0x0000000000000370 __riscv_restore_6 + 0x0000000000000370 __riscv_restore_4 + 0x000000000000037a __riscv_restore_3 + 0x000000000000037a __riscv_restore_0 + 0x000000000000037a __riscv_restore_2 + 0x000000000000037a __riscv_restore_1 + .text 0x0000000000000386 0xa8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memset.o) + 0x0000000000000386 memset + *(.text.*) + .text.NMI_Handler + 0x000000000000042e 0x4 ./User/ch32v30x_it.o + 0x000000000000042e NMI_Handler + .text.HardFault_Handler + 0x0000000000000432 0x2 ./User/ch32v30x_it.o + 0x0000000000000432 HardFault_Handler + .text.task1_entry + 0x0000000000000434 0x1c ./User/main.o + 0x0000000000000434 task1_entry + .text.js_print + 0x0000000000000450 0x56 ./User/main.o + 0x0000000000000450 js_print + .text.task2_entry + 0x00000000000004a6 0x68 ./User/main.o + 0x00000000000004a6 task2_entry + .text.startup.main + 0x000000000000050e 0xac ./User/main.o + 0x000000000000050e main + .text.SystemInit + 0x00000000000005ba 0xfa ./User/system_ch32v30x.o + 0x00000000000005ba SystemInit + .text.vtype 0x00000000000006b4 0x16 ./TencentOS_Tiny/tos_js/tos_js.o + .text.is_err 0x00000000000006ca 0xe ./TencentOS_Tiny/tos_js/tos_js.o + .text.setlwm 0x00000000000006d8 0x30 ./TencentOS_Tiny/tos_js/tos_js.o + .text.cpy 0x0000000000000708 0x38 ./TencentOS_Tiny/tos_js/tos_js.o + .text.skiptonext + 0x0000000000000740 0x98 ./TencentOS_Tiny/tos_js/tos_js.o + .text.streq 0x00000000000007d8 0x1a ./TencentOS_Tiny/tos_js/tos_js.o + .text.unhex 0x00000000000007f2 0x3c ./TencentOS_Tiny/tos_js/tos_js.o + .text.esize 0x000000000000082e 0x28 ./TencentOS_Tiny/tos_js/tos_js.o + .text.is_err2.isra.2 + 0x0000000000000856 0x1a ./TencentOS_Tiny/tos_js/tos_js.o + .text.loadoff 0x0000000000000870 0x3e ./TencentOS_Tiny/tos_js/tos_js.o + .text.vstr 0x00000000000008ae 0x1c ./TencentOS_Tiny/tos_js/tos_js.o + .text.delscope + 0x00000000000008ca 0x16 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_truthy + 0x00000000000008e0 0x54 ./TencentOS_Tiny/tos_js/tos_js.o + .text.lkp 0x0000000000000934 0x4a ./TencentOS_Tiny/tos_js/tos_js.o + .text.resolveprop + 0x000000000000097e 0x36 ./TencentOS_Tiny/tos_js/tos_js.o + .text.parseident + 0x00000000000009b4 0x3c2 ./TencentOS_Tiny/tos_js/tos_js.o + .text.next.part.9 + 0x0000000000000d76 0x3e4 ./TencentOS_Tiny/tos_js/tos_js.o + .text.next 0x000000000000115a 0x16 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_unmark_entity + 0x0000000000001170 0x94 ./TencentOS_Tiny/tos_js/tos_js.o + .text.tostr 0x0000000000001204 0x218 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mkerr + 0x000000000000141c 0x64 ./TencentOS_Tiny/tos_js/tos_js.o + 0x000000000000141c js_mkerr + .text.mkentity + 0x0000000000001480 0x78 ./TencentOS_Tiny/tos_js/tos_js.o + .text.setprop 0x00000000000014f8 0x4c ./TencentOS_Tiny/tos_js/tos_js.o + .text.mkscope 0x0000000000001544 0x42 ./TencentOS_Tiny/tos_js/tos_js.o + .text.expect 0x0000000000001586 0x36 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mkstr + 0x00000000000015bc 0x18 ./TencentOS_Tiny/tos_js/tos_js.o + 0x00000000000015bc js_mkstr + .text.js_str 0x00000000000015d4 0x50 ./TencentOS_Tiny/tos_js/tos_js.o + 0x00000000000015d4 js_str + .text.js_str_literal + 0x0000000000001624 0x148 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_gc 0x000000000000176c 0x1ca ./TencentOS_Tiny/tos_js/tos_js.o + 0x000000000000176c js_gc + .text.js_create + 0x0000000000001936 0x4e ./TencentOS_Tiny/tos_js/tos_js.o + 0x0000000000001936 js_create + .text.js_mkundef + 0x0000000000001984 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + 0x0000000000001984 js_mkundef + .text.js_mkfun + 0x000000000000198c 0x6 ./TencentOS_Tiny/tos_js/tos_js.o + 0x000000000000198c js_mkfun + .text.js_glob 0x0000000000001992 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + 0x0000000000001992 js_glob + .text.js_set 0x000000000000199a 0x3e ./TencentOS_Tiny/tos_js/tos_js.o + 0x000000000000199a js_set + .text.js_eval 0x00000000000019d8 0x6e ./TencentOS_Tiny/tos_js/tos_js.o + 0x00000000000019d8 js_eval + .text.js_run 0x0000000000001a46 0xc ./TencentOS_Tiny/tos_js/tos_js.o + 0x0000000000001a46 js_run + .text.do_op 0x0000000000001a52 0x806 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_logical_and + 0x0000000000002258 0xc8 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_logical_or + 0x0000000000002320 0x70 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_ternary + 0x0000000000002390 0xb2 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_assignment + 0x0000000000002442 0x74 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_let 0x00000000000024b6 0x11e ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_stmt 0x00000000000025d4 0x448 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_block + 0x0000000000002a1c 0x94 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_block_or_stmt + 0x0000000000002ab0 0x3a ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_group + 0x0000000000002aea 0x32e ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_unary + 0x0000000000002e18 0x25a ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_mul_div_rem + 0x0000000000003072 0x78 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_plus_minus + 0x00000000000030ea 0x70 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_shifts + 0x000000000000315a 0x84 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_comparison + 0x00000000000031de 0x92 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_equality + 0x0000000000003270 0x76 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_bitwise_and + 0x00000000000032e6 0x68 ./TencentOS_Tiny/tos_js/tos_js.o + .text.js_bitwise_xor + 0x000000000000334e 0x68 ./TencentOS_Tiny/tos_js/tos_js.o + .text.do_assign_op + 0x00000000000033b6 0x76 ./TencentOS_Tiny/tos_js/tos_js.o + .text.blk_next + 0x000000000000342c 0xa ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_link_next + 0x0000000000003436 0x10 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.mmheap_ctl_init + 0x0000000000003446 0x58 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.generic_fls.part.0 + 0x000000000000349e 0x3c ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.mapping_insert + 0x00000000000034da 0x3c ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.blk_insert + 0x0000000000003516 0x62 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .text.tos_mmheap_pool_add + 0x0000000000003578 0x8e ./TencentOS_Tiny/kernel/core/tos_mmheap.o + 0x0000000000003578 tos_mmheap_pool_add + .text.mmheap_init_with_pool + 0x0000000000003606 0x1c ./TencentOS_Tiny/kernel/core/tos_mmheap.o + 0x0000000000003606 mmheap_init_with_pool + .text.mutex_old_owner_release + 0x0000000000003622 0x46 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .text.mutex_release + 0x0000000000003668 0x16 ./TencentOS_Tiny/kernel/core/tos_mutex.o + 0x0000000000003668 mutex_release + .text.pend_list_add + 0x000000000000367e 0x40 ./TencentOS_Tiny/kernel/core/tos_pend.o + .text.pend_highest_pending_prio_get + 0x00000000000036be 0x18 ./TencentOS_Tiny/kernel/core/tos_pend.o + 0x00000000000036be pend_highest_pending_prio_get + .text.pend_list_remove + 0x00000000000036d6 0x18 ./TencentOS_Tiny/kernel/core/tos_pend.o + 0x00000000000036d6 pend_list_remove + .text.pend_list_adjust + 0x00000000000036ee 0x16 ./TencentOS_Tiny/kernel/core/tos_pend.o + 0x00000000000036ee pend_list_adjust + .text.pend_task_wakeup + 0x0000000000003704 0x32 ./TencentOS_Tiny/kernel/core/tos_pend.o + 0x0000000000003704 pend_task_wakeup + .text.pend_wakeup_all + 0x0000000000003736 0x30 ./TencentOS_Tiny/kernel/core/tos_pend.o + 0x0000000000003736 pend_wakeup_all + .text.readyqueue_prio_mark + 0x0000000000003766 0x30 ./TencentOS_Tiny/kernel/core/tos_sched.o + .text.readyqueue_highest_ready_task_get + 0x0000000000003796 0x18 ./TencentOS_Tiny/kernel/core/tos_sched.o + 0x0000000000003796 readyqueue_highest_ready_task_get + .text.readyqueue_init + 0x00000000000037ae 0x26 ./TencentOS_Tiny/kernel/core/tos_sched.o + 0x00000000000037ae readyqueue_init + .text.readyqueue_add_head + 0x00000000000037d4 0x40 ./TencentOS_Tiny/kernel/core/tos_sched.o + 0x00000000000037d4 readyqueue_add_head + .text.readyqueue_add_tail + 0x0000000000003814 0x40 ./TencentOS_Tiny/kernel/core/tos_sched.o + 0x0000000000003814 readyqueue_add_tail + .text.readyqueue_add + 0x0000000000003854 0x22 ./TencentOS_Tiny/kernel/core/tos_sched.o + 0x0000000000003854 readyqueue_add + .text.readyqueue_remove + 0x0000000000003876 0x7c ./TencentOS_Tiny/kernel/core/tos_sched.o + 0x0000000000003876 readyqueue_remove + .text.knl_idle_entry + 0x00000000000038f2 0x2 ./TencentOS_Tiny/kernel/core/tos_sys.o + .text.tos_knl_irq_enter + 0x00000000000038f4 0x1e ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x00000000000038f4 tos_knl_irq_enter + .text.tos_knl_irq_leave + 0x0000000000003912 0x50 ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x0000000000003912 tos_knl_irq_leave + .text.tos_knl_start + 0x0000000000003962 0x2c ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x0000000000003962 tos_knl_start + .text.tos_knl_is_running + 0x000000000000398e 0xc ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x000000000000398e tos_knl_is_running + .text.knl_sched + 0x000000000000399a 0x42 ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x000000000000399a knl_sched + .text.knl_is_sched_locked + 0x00000000000039dc 0xa ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x00000000000039dc knl_is_sched_locked + .text.knl_is_inirq + 0x00000000000039e6 0xa ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x00000000000039e6 knl_is_inirq + .text.knl_is_idle + 0x00000000000039f0 0x10 ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x00000000000039f0 knl_is_idle + .text.knl_is_self + 0x0000000000003a00 0xe ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x0000000000003a00 knl_is_self + .text.knl_idle_init + 0x0000000000003a0e 0x30 ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x0000000000003a0e knl_idle_init + .text.tos_knl_init + 0x0000000000003a3e 0x24 ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x0000000000003a3e tos_knl_init + .text.tos_task_create + 0x0000000000003a62 0xee ./TencentOS_Tiny/kernel/core/tos_task.o + 0x0000000000003a62 tos_task_create + .text.tos_task_destroy + 0x0000000000003b50 0xde ./TencentOS_Tiny/kernel/core/tos_task.o + 0x0000000000003b50 tos_task_destroy + .text.task_exit + 0x0000000000003c2e 0xe ./TencentOS_Tiny/kernel/core/tos_task.o + .text.tos_task_yield + 0x0000000000003c3c 0x2a ./TencentOS_Tiny/kernel/core/tos_task.o + 0x0000000000003c3c tos_task_yield + .text.tos_task_prio_change + 0x0000000000003c66 0xc0 ./TencentOS_Tiny/kernel/core/tos_task.o + 0x0000000000003c66 tos_task_prio_change + .text.tos_task_delay + 0x0000000000003d26 0x5c ./TencentOS_Tiny/kernel/core/tos_task.o + 0x0000000000003d26 tos_task_delay + .text.tick_list_add + 0x0000000000003d82 0xca ./TencentOS_Tiny/kernel/core/tos_tick.o + 0x0000000000003d82 tick_list_add + .text.tick_list_remove + 0x0000000000003e4c 0x82 ./TencentOS_Tiny/kernel/core/tos_tick.o + 0x0000000000003e4c tick_list_remove + .text.tick_update + 0x0000000000003ece 0xa2 ./TencentOS_Tiny/kernel/core/tos_tick.o + 0x0000000000003ece tick_update + .text.tos_tick_handler + 0x0000000000003f70 0x16 ./TencentOS_Tiny/kernel/core/tos_tick.o + 0x0000000000003f70 tos_tick_handler + .text.port_cpsr_save + 0x0000000000003f86 0xc ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003f86 port_cpsr_save + .text.port_cpsr_restore + 0x0000000000003f92 0x6 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003f92 port_cpsr_restore + .text.sw_clearpend + 0x0000000000003f98 0xe ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003f98 sw_clearpend + .text.port_context_switch + 0x0000000000003fa6 0x10 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003fa6 port_context_switch + .text.port_irq_context_switch + 0x0000000000003fb6 0xc ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003fb6 port_irq_context_switch + .text.port_systick_config + 0x0000000000003fc2 0x24 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003fc2 port_systick_config + .text.port_systick_priority_set + 0x0000000000003fe6 0xe ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003fe6 port_systick_priority_set + .text.port_cpu_init + 0x0000000000003ff4 0x18 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x0000000000003ff4 port_cpu_init + .text.SysTick_Handler + 0x000000000000400c 0xac ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x000000000000400c SysTick_Handler + .text.tos_cpu_cpsr_save + 0x00000000000040b8 0xc ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x00000000000040b8 tos_cpu_cpsr_save + .text.tos_cpu_cpsr_restore + 0x00000000000040c4 0xc ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x00000000000040c4 tos_cpu_cpsr_restore + .text.cpu_context_switch + 0x00000000000040d0 0xc ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x00000000000040d0 cpu_context_switch + .text.cpu_irq_context_switch + 0x00000000000040dc 0xc ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x00000000000040dc cpu_irq_context_switch + .text.cpu_sched_start + 0x00000000000040e8 0x8 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x00000000000040e8 cpu_sched_start + .text.cpu_systick_init + 0x00000000000040f0 0x18 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x00000000000040f0 cpu_systick_init + .text.cpu_init + 0x0000000000004108 0x38 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x0000000000004108 cpu_init + .text.cpu_task_stk_init + 0x0000000000004140 0x5a ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x0000000000004140 cpu_task_stk_init + .text.tos_cpu_clz + 0x000000000000419a 0x40 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x000000000000419a tos_cpu_clz + .text.vector_handler + 0x00000000000041da 0xbe ./Startup/startup_ch32v30x.o + 0x00000000000041de Ecall_M_Mode_Handler + 0x00000000000041e0 Ecall_U_Mode_Handler + 0x00000000000041e2 Break_Point_Handler + 0x00000000000041e8 WWDG_IRQHandler + 0x00000000000041ea PVD_IRQHandler + 0x00000000000041ec TAMPER_IRQHandler + 0x00000000000041ee RTC_IRQHandler + 0x00000000000041f0 FLASH_IRQHandler + 0x00000000000041f2 RCC_IRQHandler + 0x00000000000041f4 EXTI0_IRQHandler + 0x00000000000041f6 EXTI1_IRQHandler + 0x00000000000041f8 EXTI2_IRQHandler + 0x00000000000041fa EXTI3_IRQHandler + 0x00000000000041fc EXTI4_IRQHandler + 0x00000000000041fe DMA1_Channel1_IRQHandler + 0x0000000000004200 DMA1_Channel2_IRQHandler + 0x0000000000004202 DMA1_Channel3_IRQHandler + 0x0000000000004204 DMA1_Channel4_IRQHandler + 0x0000000000004206 DMA1_Channel5_IRQHandler + 0x0000000000004208 DMA1_Channel6_IRQHandler + 0x000000000000420a DMA1_Channel7_IRQHandler + 0x000000000000420c ADC1_2_IRQHandler + 0x000000000000420e USB_HP_CAN1_TX_IRQHandler + 0x0000000000004210 USB_LP_CAN1_RX0_IRQHandler + 0x0000000000004212 CAN1_RX1_IRQHandler + 0x0000000000004214 CAN1_SCE_IRQHandler + 0x0000000000004216 EXTI9_5_IRQHandler + 0x0000000000004218 TIM1_BRK_IRQHandler + 0x000000000000421a TIM1_UP_IRQHandler + 0x000000000000421c TIM1_TRG_COM_IRQHandler + 0x000000000000421e TIM1_CC_IRQHandler + 0x0000000000004220 TIM2_IRQHandler + 0x0000000000004222 TIM3_IRQHandler + 0x0000000000004224 TIM4_IRQHandler + 0x0000000000004226 I2C1_EV_IRQHandler + 0x0000000000004228 I2C1_ER_IRQHandler + 0x000000000000422a I2C2_EV_IRQHandler + 0x000000000000422c I2C2_ER_IRQHandler + 0x000000000000422e SPI1_IRQHandler + 0x0000000000004230 SPI2_IRQHandler + 0x0000000000004232 USART1_IRQHandler + 0x0000000000004234 USART2_IRQHandler + 0x0000000000004236 USART3_IRQHandler + 0x0000000000004238 EXTI15_10_IRQHandler + 0x000000000000423a RTCAlarm_IRQHandler + 0x000000000000423c USBWakeUp_IRQHandler + 0x000000000000423e TIM8_BRK_IRQHandler + 0x0000000000004240 TIM8_UP_IRQHandler + 0x0000000000004242 TIM8_TRG_COM_IRQHandler + 0x0000000000004244 TIM8_CC_IRQHandler + 0x0000000000004246 RNG_IRQHandler + 0x0000000000004248 FSMC_IRQHandler + 0x000000000000424a SDIO_IRQHandler + 0x000000000000424c TIM5_IRQHandler + 0x000000000000424e SPI3_IRQHandler + 0x0000000000004250 UART4_IRQHandler + 0x0000000000004252 UART5_IRQHandler + 0x0000000000004254 TIM6_IRQHandler + 0x0000000000004256 TIM7_IRQHandler + 0x0000000000004258 DMA2_Channel1_IRQHandler + 0x000000000000425a DMA2_Channel2_IRQHandler + 0x000000000000425c DMA2_Channel3_IRQHandler + 0x000000000000425e DMA2_Channel4_IRQHandler + 0x0000000000004260 DMA2_Channel5_IRQHandler + 0x0000000000004262 ETH_IRQHandler + 0x0000000000004264 ETH_WKUP_IRQHandler + 0x0000000000004266 CAN2_TX_IRQHandler + 0x0000000000004268 CAN2_RX0_IRQHandler + 0x000000000000426a CAN2_RX1_IRQHandler + 0x000000000000426c CAN2_SCE_IRQHandler + 0x000000000000426e OTG_FS_IRQHandler + 0x0000000000004270 USBHSWakeup_IRQHandler + 0x0000000000004272 USBHS_IRQHandler + 0x0000000000004274 DVP_IRQHandler + 0x0000000000004276 UART6_IRQHandler + 0x0000000000004278 UART7_IRQHandler + 0x000000000000427a UART8_IRQHandler + 0x000000000000427c TIM9_BRK_IRQHandler + 0x000000000000427e TIM9_UP_IRQHandler + 0x0000000000004280 TIM9_TRG_COM_IRQHandler + 0x0000000000004282 TIM9_CC_IRQHandler + 0x0000000000004284 TIM10_BRK_IRQHandler + 0x0000000000004286 TIM10_UP_IRQHandler + 0x0000000000004288 TIM10_TRG_COM_IRQHandler + 0x000000000000428a TIM10_CC_IRQHandler + 0x000000000000428c DMA2_Channel6_IRQHandler + 0x000000000000428e DMA2_Channel7_IRQHandler + 0x0000000000004290 DMA2_Channel8_IRQHandler + 0x0000000000004292 DMA2_Channel9_IRQHandler + 0x0000000000004294 DMA2_Channel10_IRQHandler + 0x0000000000004296 DMA2_Channel11_IRQHandler + .text.handle_reset + 0x0000000000004298 0x8e ./Startup/startup_ch32v30x.o + 0x0000000000004298 handle_reset + .text.GPIO_Init + 0x0000000000004326 0xc0 ./Peripheral/src/ch32v30x_gpio.o + 0x0000000000004326 GPIO_Init + .text.RCC_GetClocksFreq + 0x00000000000043e6 0x106 ./Peripheral/src/ch32v30x_rcc.o + 0x00000000000043e6 RCC_GetClocksFreq + .text.RCC_APB2PeriphClockCmd + 0x00000000000044ec 0x1e ./Peripheral/src/ch32v30x_rcc.o + 0x00000000000044ec RCC_APB2PeriphClockCmd + .text.USART_Init + 0x000000000000450a 0xbc ./Peripheral/src/ch32v30x_usart.o + 0x000000000000450a USART_Init + .text.USART_Cmd + 0x00000000000045c6 0x16 ./Peripheral/src/ch32v30x_usart.o + 0x00000000000045c6 USART_Cmd + .text.USART_SendData + 0x00000000000045dc 0x8 ./Peripheral/src/ch32v30x_usart.o + 0x00000000000045dc USART_SendData + .text.USART_GetFlagStatus + 0x00000000000045e4 0xa ./Peripheral/src/ch32v30x_usart.o + 0x00000000000045e4 USART_GetFlagStatus + .text.USART_Printf_Init + 0x00000000000045ee 0x5a ./Debug/debug.o + 0x00000000000045ee USART_Printf_Init + .text._write 0x0000000000004648 0x3e ./Debug/debug.o + 0x0000000000004648 _write + .text._sbrk 0x0000000000004686 0x2a ./Debug/debug.o + 0x0000000000004686 _sbrk + .text.__udivdi3 + 0x00000000000046b0 0x398 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_udivdi3.o) + 0x00000000000046b0 __udivdi3 + .text.__adddf3 + 0x0000000000004a48 0x730 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) + 0x0000000000004a48 __adddf3 + .text.__divdf3 + 0x0000000000005178 0x5b4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + 0x0000000000005178 __divdf3 + .text.__eqdf2 0x000000000000572c 0x6a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(eqdf2.o) + 0x000000000000572c __nedf2 + 0x000000000000572c __eqdf2 + .text.__gedf2 0x0000000000005796 0xae c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(gedf2.o) + 0x0000000000005796 __gedf2 + 0x0000000000005796 __gtdf2 + .text.__ledf2 0x0000000000005844 0xb6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(ledf2.o) + 0x0000000000005844 __ledf2 + 0x0000000000005844 __ltdf2 + .text.__muldf3 + 0x00000000000058fa 0x4b8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + 0x00000000000058fa __muldf3 + .text.__subdf3 + 0x0000000000005db2 0x73a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(subdf3.o) + 0x0000000000005db2 __subdf3 + .text.__fixdfsi + 0x00000000000064ec 0x68 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixdfsi.o) + 0x00000000000064ec __fixdfsi + .text.__floatsidf + 0x0000000000006554 0x70 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatsidf.o) + 0x0000000000006554 __floatsidf + .text.__floatunsidf + 0x00000000000065c4 0x66 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatunsidf.o) + 0x00000000000065c4 __floatunsidf + .text.__clzsi2 + 0x000000000000662a 0x76 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clzsi2.o) + 0x000000000000662a __clzsi2 + .text.__assert_func + 0x00000000000066a0 0x3a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + 0x00000000000066a0 __assert_func + .text.fprintf 0x00000000000066da 0x26 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + 0x00000000000066da fiprintf + 0x00000000000066da fprintf + .text.memcmp 0x0000000000006700 0x26 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcmp.o) + 0x0000000000006700 memcmp + .text.memcpy 0x0000000000006726 0xb6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcpy.o) + 0x0000000000006726 memcpy + .text.memmove 0x00000000000067dc 0x4a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memmove.o) + 0x00000000000067dc memmove + .text.__sfputc_r + 0x0000000000006826 0x2a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .text.__sfputs_r + 0x0000000000006850 0x44 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + 0x0000000000006850 __sfputs_r + .text._vfprintf_r + 0x0000000000006894 0x29c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + 0x0000000000006894 _vfprintf_r + 0x0000000000006894 _vfiprintf_r + .text.__cvt 0x0000000000006b30 0xee c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + 0x0000000000006b30 __cvt + .text.__exponent + 0x0000000000006c1e 0x8c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + 0x0000000000006c1e __exponent + .text._printf_float + 0x0000000000006caa 0x4c4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + 0x0000000000006caa _printf_float + .text._printf_common + 0x000000000000716e 0x10c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000000716e _printf_common + .text._printf_i + 0x000000000000727a 0x2ac c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000000727a _printf_i + .text._scanf_float + 0x0000000000007526 0x476 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + 0x0000000000007526 _scanf_float + .text.printf 0x000000000000799c 0x42 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + 0x000000000000799c iprintf + 0x000000000000799c printf + .text.putchar 0x00000000000079de 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + 0x00000000000079de putchar + .text._puts_r 0x0000000000007a0a 0xe4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + 0x0000000000007a0a _puts_r + .text.puts 0x0000000000007aee 0xc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + 0x0000000000007aee puts + .text.modf 0x0000000000007afa 0xa8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-s_modf.o) + 0x0000000000007afa modf + .text.nanf 0x0000000000007ba2 0xc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + 0x0000000000007ba2 nanf + .text.snprintf + 0x0000000000007bae 0x70 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + 0x0000000000007bae sniprintf + 0x0000000000007bae snprintf + .text.sprintf 0x0000000000007c1e 0x46 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + 0x0000000000007c1e siprintf + 0x0000000000007c1e sprintf + .text.strlen 0x0000000000007c64 0x12 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strlen.o) + 0x0000000000007c64 strlen + .text.strncpy 0x0000000000007c76 0x24 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncpy.o) + 0x0000000000007c76 strncpy + .text.sulp 0x0000000000007c9a 0x4e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .text._strtod_l + 0x0000000000007ce8 0xc7e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + 0x0000000000007ce8 _strtod_l + .text._strtod_r + 0x0000000000008966 0x16 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + 0x0000000000008966 _strtod_r + .text.strtod 0x000000000000897c 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + 0x000000000000897c strtod + .text._strtol_l.isra.0 + 0x0000000000008998 0x144 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .text._strtol_r + 0x0000000000008adc 0x16 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + 0x0000000000008adc _strtol_r + .text._vsnprintf_r + 0x0000000000008af2 0x60 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + 0x0000000000008af2 _vsniprintf_r + 0x0000000000008af2 _vsnprintf_r + .text.vsnprintf + 0x0000000000008b52 0x12 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + 0x0000000000008b52 vsniprintf + 0x0000000000008b52 vsnprintf + .text.__swbuf_r + 0x0000000000008b64 0xc6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + 0x0000000000008b64 __swbuf_r + .text.__swsetup_r + 0x0000000000008c2a 0x112 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) + 0x0000000000008c2a __swsetup_r + .text.abort 0x0000000000008d3c 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) + 0x0000000000008d3c abort + .text.quorem 0x0000000000008d4c 0x13a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + .text._dtoa_r 0x0000000000008e86 0xc20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + 0x0000000000008e86 _dtoa_r + .text.__sflush_r + 0x0000000000009aa6 0x13e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + 0x0000000000009aa6 __sflush_r + .text._fflush_r + 0x0000000000009be4 0x66 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + 0x0000000000009be4 _fflush_r + .text.std 0x0000000000009c4a 0x6a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .text._cleanup_r + 0x0000000000009cb4 0xa c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x0000000000009cb4 _cleanup_r + .text.__sfmoreglue + 0x0000000000009cbe 0x48 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x0000000000009cbe __sfmoreglue + .text.__sinit 0x0000000000009d06 0x6c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x0000000000009d06 __sinit + .text.__sfp 0x0000000000009d72 0xa0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x0000000000009d72 __sfp + .text._fwalk_reent + 0x0000000000009e12 0x6c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + 0x0000000000009e12 _fwalk_reent + .text.rshift 0x0000000000009e7e 0x76 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + .text.__hexdig_fun + 0x0000000000009ef4 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + 0x0000000000009ef4 __hexdig_fun + .text.__gethex + 0x0000000000009f34 0x4ce c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + 0x0000000000009f34 __gethex + .text.L_shift 0x000000000000a402 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + .text.__match 0x000000000000a42e 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + 0x000000000000a42e __match + .text.__hexnan + 0x000000000000a45e 0x160 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + 0x000000000000a45e __hexnan + .text.__locale_ctype_ptr_l + 0x000000000000a5be 0x6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + 0x000000000000a5be __locale_ctype_ptr_l + .text.__localeconv_l + 0x000000000000a5c4 0x6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + 0x000000000000a5c4 __localeconv_l + .text._localeconv_r + 0x000000000000a5ca 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + 0x000000000000a5ca _localeconv_r + .text.__swhatbuf_r + 0x000000000000a5e2 0x5a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + 0x000000000000a5e2 __swhatbuf_r + .text.__smakebuf_r + 0x000000000000a63c 0xa2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + 0x000000000000a63c __smakebuf_r + .text.malloc 0x000000000000a6de 0xc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + 0x000000000000a6de malloc + .text.__ascii_mbtowc + 0x000000000000a6ea 0x3a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + 0x000000000000a6ea __ascii_mbtowc + .text.memchr 0x000000000000a724 0x1a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memchr.o) + 0x000000000000a724 memchr + .text._Balloc 0x000000000000a73e 0x8c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a73e _Balloc + .text._Bfree 0x000000000000a7ca 0x44 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a7ca _Bfree + .text.__multadd + 0x000000000000a80e 0x98 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a80e __multadd + .text.__s2b 0x000000000000a8a6 0xa6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a8a6 __s2b + .text.__hi0bits + 0x000000000000a94c 0x46 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a94c __hi0bits + .text.__lo0bits + 0x000000000000a992 0x6a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a992 __lo0bits + .text.__i2b 0x000000000000a9fc 0x1c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000a9fc __i2b + .text.__multiply + 0x000000000000aa18 0x144 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000aa18 __multiply + .text.__pow5mult + 0x000000000000ab5c 0xbe c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000ab5c __pow5mult + .text.__lshift + 0x000000000000ac1a 0xce c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000ac1a __lshift + .text.__mcmp 0x000000000000ace8 0x32 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000ace8 __mcmp + .text.__mdiff 0x000000000000ad1a 0xf2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000ad1a __mdiff + .text.__ulp 0x000000000000ae0c 0x46 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000ae0c __ulp + .text.__b2d 0x000000000000ae52 0xb4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000ae52 __b2d + .text.__d2b 0x000000000000af06 0xd4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000af06 __d2b + .text.__ratio 0x000000000000afda 0x74 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000afda __ratio + .text.__copybits + 0x000000000000b04e 0x36 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000b04e __copybits + .text.__any_on + 0x000000000000b084 0x46 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000b084 __any_on + .text._calloc_r + 0x000000000000b0ca 0x26 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-callocr.o) + 0x000000000000b0ca _calloc_r + .text._free_r 0x000000000000b0f0 0xa8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) + 0x000000000000b0f0 _free_r + .text._malloc_r + 0x000000000000b198 0xd4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + 0x000000000000b198 _malloc_r + .text._realloc_r + 0x000000000000b26c 0x58 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) + 0x000000000000b26c _realloc_r + .text.__ssputs_r + 0x000000000000b2c4 0xee c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + 0x000000000000b2c4 __ssputs_r + .text._svfprintf_r + 0x000000000000b3b2 0x27e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + 0x000000000000b3b2 _svfiprintf_r + 0x000000000000b3b2 _svfprintf_r + .text._putc_r 0x000000000000b630 0x86 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + 0x000000000000b630 _putc_r + .text._sbrk_r 0x000000000000b6b6 0x32 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) + 0x000000000000b6b6 _sbrk_r + .text._raise_r + 0x000000000000b6e8 0x62 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + 0x000000000000b6e8 _raise_r + .text.raise 0x000000000000b74a 0xc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + 0x000000000000b74a raise + .text._kill_r 0x000000000000b756 0x34 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + 0x000000000000b756 _kill_r + .text._getpid_r + 0x000000000000b78a 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + 0x000000000000b78a _getpid_r + .text.__sread 0x000000000000b78e 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + 0x000000000000b78e __sread + .text.__swrite + 0x000000000000b7be 0x4e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + 0x000000000000b7be __swrite + .text.__sseek 0x000000000000b80c 0x36 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + 0x000000000000b80c __sseek + .text.__sclose + 0x000000000000b842 0x6 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + 0x000000000000b842 __sclose + .text.strncmp 0x000000000000b848 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncmp.o) + 0x000000000000b848 strncmp + .text.__ascii_wctomb + 0x000000000000b874 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + 0x000000000000b874 __ascii_wctomb + .text._write_r + 0x000000000000b894 0x36 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-writer.o) + 0x000000000000b894 _write_r + .text._close_r + 0x000000000000b8ca 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) + 0x000000000000b8ca _close_r + .text._fstat_r + 0x000000000000b8fa 0x32 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) + 0x000000000000b8fa _fstat_r + .text._isatty_r + 0x000000000000b92c 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) + 0x000000000000b92c _isatty_r + .text._lseek_r + 0x000000000000b95c 0x34 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) + 0x000000000000b95c _lseek_r + .text.__malloc_lock + 0x000000000000b990 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + 0x000000000000b990 __malloc_lock + .text.__malloc_unlock + 0x000000000000b992 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + 0x000000000000b992 __malloc_unlock + .text._malloc_usable_size_r + 0x000000000000b994 0x14 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-msizer.o) + 0x000000000000b994 _malloc_usable_size_r + .text._read_r 0x000000000000b9a8 0x34 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) + 0x000000000000b9a8 _read_r + .text.__unorddf2 + 0x000000000000b9dc 0x3c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unorddf2.o) + 0x000000000000b9dc __unorddf2 + .text.__fixunsdfsi + 0x000000000000ba18 0x5c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixunsdfsi.o) + 0x000000000000ba18 __fixunsdfsi + .text.__extenddftf2 + 0x000000000000ba74 0x1a4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(extenddftf2.o) + 0x000000000000ba74 __extenddftf2 + .text.__truncdfsf2 + 0x000000000000bc18 0x16a c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(truncdfsf2.o) + 0x000000000000bc18 __truncdfsf2 + .text.__trunctfdf2 + 0x000000000000bd82 0x21e c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(trunctfdf2.o) + 0x000000000000bd82 __trunctfdf2 + .text._close 0x000000000000bfa0 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + 0x000000000000bfa0 _close + .text._fstat 0x000000000000bfb0 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + 0x000000000000bfb0 _fstat + .text._getpid 0x000000000000bfc0 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + 0x000000000000bfc0 _getpid + .text._isatty 0x000000000000bfd0 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + 0x000000000000bfd0 _isatty + .text._kill 0x000000000000bfe0 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + 0x000000000000bfe0 _kill + .text._lseek 0x000000000000bff0 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + 0x000000000000bff0 _lseek + .text._read 0x000000000000c000 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + 0x000000000000c000 _read + .text._exit 0x000000000000c010 0x2 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(_exit.o) + 0x000000000000c010 _exit + *(.rodata) + *fill* 0x000000000000c012 0x2 + .rodata 0x000000000000c014 0x30 ./TencentOS_Tiny/tos_js/tos_js.o + *(.rodata*) + .rodata.js_print.str1.4 + 0x000000000000c044 0x5 ./User/main.o + 0xd (size before relaxing) + *fill* 0x000000000000c049 0x3 + .rodata.main.str1.4 + 0x000000000000c04c 0x61 ./User/main.o + *fill* 0x000000000000c0ad 0x3 + .rodata.task1_entry.str1.4 + 0x000000000000c0b0 0xf ./User/main.o + *fill* 0x000000000000c0bf 0x1 + .rodata.task2_entry.str1.4 + 0x000000000000c0c0 0x2e ./User/main.o + *fill* 0x000000000000c0ee 0x2 + .rodata.parseident + 0x000000000000c0f0 0x60 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.tostr 0x000000000000c150 0x28 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.do_op 0x000000000000c178 0x84 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.do_op.str1.4 + 0x000000000000c1fc 0x9e ./TencentOS_Tiny/tos_js/tos_js.o + *fill* 0x000000000000c29a 0x2 + .rodata.expect.str1.4 + 0x000000000000c29c 0xc ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_group.str1.4 + 0x000000000000c2a8 0x1d ./TencentOS_Tiny/tos_js/tos_js.o + *fill* 0x000000000000c2c5 0x3 + .rodata.js_let.str1.4 + 0x000000000000c2c8 0x18 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_mkerr.str1.4 + 0x000000000000c2e0 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_stmt.str1.4 + 0x000000000000c2e8 0x3b ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_str.str1.4 + 0x000000000000c323 0x1 ./TencentOS_Tiny/tos_js/tos_js.o + *fill* 0x000000000000c323 0x1 + .rodata.js_str_literal.str1.4 + 0x000000000000c324 0x10 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.js_unary.str1.4 + 0x000000000000c334 0x11 ./TencentOS_Tiny/tos_js/tos_js.o + *fill* 0x000000000000c345 0x3 + .rodata.loadoff.str1.4 + 0x000000000000c348 0x36 ./TencentOS_Tiny/tos_js/tos_js.o + *fill* 0x000000000000c37e 0x2 + .rodata.mkentity.str1.4 + 0x000000000000c380 0x4 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.mkscope.str1.4 + 0x000000000000c384 0x1c ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.parseident.str1.4 + 0x000000000000c3a0 0xce ./TencentOS_Tiny/tos_js/tos_js.o + *fill* 0x000000000000c46e 0x2 + .rodata.str1.4 + 0x000000000000c470 0x54 ./TencentOS_Tiny/tos_js/tos_js.o + 0x60 (size before relaxing) + .rodata.tostr.str1.4 + 0x000000000000c4c4 0x44 ./TencentOS_Tiny/tos_js/tos_js.o + .rodata.knl_idle_init.str1.4 + 0x000000000000c508 0x5 ./TencentOS_Tiny/kernel/core/tos_sys.o + *fill* 0x000000000000c50d 0x3 + .rodata.__divdf3 + 0x000000000000c510 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + .rodata.__muldf3 + 0x000000000000c550 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + .rodata.__clz_tab + 0x000000000000c590 0x100 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clz.o) + 0x000000000000c590 __clz_tab + .rodata.__assert_func.str1.4 + 0x000000000000c690 0x3f c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + 0x43 (size before relaxing) + *fill* 0x000000000000c6cf 0x1 + .rodata._vfprintf_r.str1.4 + 0x000000000000c6d0 0x13 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + *fill* 0x000000000000c6e3 0x5 + .rodata._printf_float.cst8 + 0x000000000000c6e8 0x8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + .rodata._printf_float.str1.4 + 0x000000000000c6f0 0xe c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + 0x12 (size before relaxing) + *fill* 0x000000000000c6fe 0x2 + .rodata._printf_i.str1.4 + 0x000000000000c700 0x25 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + *fill* 0x000000000000c725 0x3 + .rodata._scanf_float.str1.4 + 0x000000000000c728 0x5 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + *fill* 0x000000000000c72d 0x3 + .rodata.nanf.cst4 + 0x000000000000c730 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + .rodata._strtod_l + 0x000000000000c734 0x14 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata._strtod_l.cst8 + 0x000000000000c748 0x38 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata._strtod_l.str1.4 + 0x000000000000c780 0xf c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + *fill* 0x000000000000c78f 0x1 + .rodata.fpi.3395 + 0x000000000000c790 0x14 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata.fpinan.3431 + 0x000000000000c7a4 0x14 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata.tinytens + 0x000000000000c7b8 0x28 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .rodata._dtoa_r.cst8 + 0x000000000000c7e0 0x38 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + 0x48 (size before relaxing) + .rodata._dtoa_r.str1.4 + 0x000000000000c818 0x10 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + 0x12 (size before relaxing) + .rodata.__sf_fake_stderr + 0x000000000000c828 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x000000000000c828 __sf_fake_stderr + .rodata.__sf_fake_stdin + 0x000000000000c848 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x000000000000c848 __sf_fake_stdin + .rodata.__sf_fake_stdout + 0x000000000000c868 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + 0x000000000000c868 __sf_fake_stdout + .rodata._setlocale_r.str1.4 + 0x000000000000c888 0xa c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + 0xd (size before relaxing) + *fill* 0x000000000000c892 0x2 + .rodata.str1.4 + 0x000000000000c894 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + 0x2 (size before relaxing) + .rodata.__mprec_bigtens + 0x000000000000c898 0x28 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000c898 __mprec_bigtens + .rodata.__mprec_tens + 0x000000000000c8c0 0xc8 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + 0x000000000000c8c0 __mprec_tens + .rodata.p05.3319 + 0x000000000000c988 0xc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .rodata._svfprintf_r.str1.4 + 0x000000000000c994 0x13 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + .rodata._ctype_ + 0x000000000000c994 0x101 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-ctype_.o) + 0x000000000000c994 _ctype_ + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + 0x000000000000ca98 . = ALIGN (0x4) + *fill* 0x000000000000ca95 0x3 + +.rela.dyn 0x000000000000ca98 0x0 + .rela.text.task2_entry + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.startup.main + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.sdata2.k_idle_task_stk_addr + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.mmheap_ctl_init + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.blk_insert + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.tos_mmheap_pool_add + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.readyqueue_prio_mark + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.readyqueue_highest_ready_task_get + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.readyqueue_init + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.readyqueue_add_head + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.readyqueue_add_tail + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.readyqueue_remove + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.knl_is_idle + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.knl_idle_init + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.tos_knl_init + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.sdata.k_irq_stk_top + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.init 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.vector 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text.handle_reset + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._sbrk + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.sdata.curbrk.5216 + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._vfprintf_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._svfprintf_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._sbrk_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._kill_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._write_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._close_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._fstat_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._isatty_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._lseek_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._read_r + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._close + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._fstat + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._getpid + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._isatty + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._kill + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._lseek + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + .rela.text._read + 0x000000000000ca98 0x0 ./User/ch32v30x_it.o + +.fini 0x000000000000ca98 0x0 + *(SORT_NONE(.fini)) + 0x000000000000ca98 . = ALIGN (0x4) + [!provide] PROVIDE (_etext = .) + [!provide] PROVIDE (_eitcm = .) + +.preinit_array 0x000000000000ca98 0x0 + [!provide] PROVIDE (__preinit_array_start = .) + *(.preinit_array) + [!provide] PROVIDE (__preinit_array_end = .) + +.init_array 0x000000000000ca98 0x0 + [!provide] PROVIDE (__init_array_start = .) + *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) + *(.init_array EXCLUDE_FILE(*crtend?.o *crtend.o *crtbegin?.o *crtbegin.o) .ctors) + [!provide] PROVIDE (__init_array_end = .) + +.fini_array 0x000000000000ca98 0x0 + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) + *(.fini_array EXCLUDE_FILE(*crtend?.o *crtend.o *crtbegin?.o *crtbegin.o) .dtors) + [!provide] PROVIDE (__fini_array_end = .) + +.ctors + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT_BY_NAME(.ctors.*)) + *(.ctors) + +.dtors + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT_BY_NAME(.dtors.*)) + *(.dtors) + +.dalign 0x0000000020000000 0x0 load address 0x000000000000ca98 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 PROVIDE (_data_vma = .) + +.dlalign 0x000000000000ca98 0x0 + 0x000000000000ca98 . = ALIGN (0x4) + 0x000000000000ca98 PROVIDE (_data_lma = .) + +.data 0x0000000020000000 0x230 load address 0x000000000000ca98 + *(.gnu.linkonce.r.*) + *(.data .data.*) + .data.APBAHBPrescTable + 0x0000000020000000 0x10 ./Peripheral/src/ch32v30x_rcc.o + .data.impure_data + 0x0000000020000010 0x60 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + .data.__global_locale + 0x0000000020000070 0x16c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + 0x0000000020000070 __global_locale + *(.gnu.linkonce.d.*) + 0x00000000200001e0 . = ALIGN (0x8) + *fill* 0x00000000200001dc 0x4 + 0x00000000200009e0 PROVIDE (__global_pointer$ = (. + 0x800)) + *(.sdata .sdata.*) + .sdata.SystemCoreClock + 0x00000000200001e0 0x4 ./User/system_ch32v30x.o + 0x00000000200001e0 SystemCoreClock + *fill* 0x00000000200001e4 0x4 + .sdata.k_cpu_tick_per_second + 0x00000000200001e8 0x8 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x00000000200001e8 k_cpu_tick_per_second + .sdata.k_stat_list + 0x00000000200001f0 0x8 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x00000000200001f0 k_stat_list + .sdata.k_tick_list + 0x00000000200001f8 0x8 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x00000000200001f8 k_tick_list + .sdata.k_irq_stk_top + 0x0000000020000200 0x4 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x0000000020000200 k_irq_stk_top + .sdata.ADCPrescTable + 0x0000000020000204 0x4 ./Peripheral/src/ch32v30x_rcc.o + .sdata.curbrk.5216 + 0x0000000020000208 0x4 ./Debug/debug.o + .sdata._impure_ptr + 0x000000002000020c 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + 0x000000002000020c _impure_ptr + *(.sdata2.*) + .sdata2.__func__.3873 + 0x0000000020000210 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + .sdata2.__func__.4194 + 0x0000000020000218 0x8 ./TencentOS_Tiny/tos_js/tos_js.o + .sdata2.k_idle_task_stk_addr + 0x0000000020000220 0x4 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000220 k_idle_task_stk_addr + .sdata2.k_idle_task_stk_size + 0x0000000020000224 0x4 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000224 k_idle_task_stk_size + .sdata2._global_impure_ptr + 0x0000000020000228 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-impure.o) + 0x0000000020000228 _global_impure_ptr + *(.gnu.linkonce.s.*) + 0x0000000020000230 . = ALIGN (0x8) + *fill* 0x000000002000022c 0x4 + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + 0x0000000020000230 . = ALIGN (0x4) + 0x0000000020000230 PROVIDE (_edata = .) + +.bss 0x0000000020000230 0x9a44 load address 0x000000000000ccc8 + 0x0000000020000230 . = ALIGN (0x4) + 0x0000000020000230 PROVIDE (_sbss = .) + *(.sbss*) + .sbss.k_cpu_cycle_per_tick + 0x0000000020000230 0x4 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000230 k_cpu_cycle_per_tick + .sbss.k_curr_task + 0x0000000020000234 0x4 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000234 k_curr_task + .sbss.k_irq_nest_cnt + 0x0000000020000238 0x1 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000238 k_irq_nest_cnt + *fill* 0x0000000020000239 0x3 + .sbss.k_knl_state + 0x000000002000023c 0x4 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x000000002000023c k_knl_state + .sbss.k_next_task + 0x0000000020000240 0x4 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000240 k_next_task + .sbss.k_sched_lock_nest_cnt + 0x0000000020000244 0x1 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000244 k_sched_lock_nest_cnt + *fill* 0x0000000020000245 0x3 + .sbss.k_tick_count + 0x0000000020000248 0x8 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020000248 k_tick_count + .sbss.__malloc_free_list + 0x0000000020000250 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + 0x0000000020000250 __malloc_free_list + .sbss.__malloc_sbrk_start + 0x0000000020000254 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + 0x0000000020000254 __malloc_sbrk_start + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + COMMON 0x0000000020000258 0x58c0 ./User/main.o + 0x0000000020000258 task1_stk + 0x0000000020002a58 task1 + 0x0000000020002ad0 task2 + 0x0000000020002b48 task2_stk + 0x0000000020005348 js_mem + COMMON 0x0000000020005b18 0x3f58 ./TencentOS_Tiny/kernel/core/tos_global.o + 0x0000000020005b18 k_rdyq + 0x0000000020005b70 k_idle_task_stk + 0x0000000020005d70 k_mmheap_ctl + 0x00000000200069f8 k_idle_task + 0x0000000020006a70 k_mmheap_default_pool + COMMON 0x0000000020009a70 0x200 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0x0000000020009a70 k_irq_stk + COMMON 0x0000000020009c70 0x4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + 0x0000000020009c70 errno + 0x0000000020009c74 . = ALIGN (0x4) + 0x0000000020009c74 PROVIDE (_ebss = .) + 0x0000000020009c74 PROVIDE (_end = _ebss) + [!provide] PROVIDE (end = .) + +.stack 0x000000002000b000 0x5000 + 0x000000002000b000 PROVIDE (_heap_end = .) + 0x000000002000b000 . = ALIGN (0x4) + [!provide] PROVIDE (_susrstack = .) + 0x0000000020010000 . = (. + __stack_size) + *fill* 0x000000002000b000 0x5000 + 0x0000000020010000 PROVIDE (_eusrstack = .) +OUTPUT(JSInterpreter-TencentOS.elf elf32-littleriscv) + +.debug_info 0x0000000000000000 0x1ea36 + .debug_info 0x0000000000000000 0x969 ./User/ch32v30x_it.o + .debug_info 0x0000000000000969 0x14f5 ./User/main.o + .debug_info 0x0000000000001e5e 0xb6a ./User/system_ch32v30x.o + .debug_info 0x00000000000029c8 0x7711 ./TencentOS_Tiny/tos_js/tos_js.o + .debug_info 0x000000000000a0d9 0xfcf ./TencentOS_Tiny/kernel/core/tos_global.o + .debug_info 0x000000000000b0a8 0x2f3c ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_info 0x000000000000dfe4 0x1a5d ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_info 0x000000000000fa41 0x1827 ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_info 0x0000000000011268 0x159f ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_info 0x0000000000012807 0x15e2 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_info 0x0000000000013de9 0x219d ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_info 0x0000000000015f86 0x13ef ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_info 0x0000000000017375 0x164b ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_info 0x00000000000189c0 0x26 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + .debug_info 0x00000000000189e6 0x16e6 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_info 0x000000000001a0cc 0x22 ./Startup/startup_ch32v30x.o + .debug_info 0x000000000001a0ee 0x109a ./Peripheral/src/ch32v30x_gpio.o + .debug_info 0x000000000001b188 0x1564 ./Peripheral/src/ch32v30x_rcc.o + .debug_info 0x000000000001c6ec 0x1427 ./Peripheral/src/ch32v30x_usart.o + .debug_info 0x000000000001db13 0xf23 ./Debug/debug.o + +.debug_abbrev 0x0000000000000000 0x40de + .debug_abbrev 0x0000000000000000 0x1cf ./User/ch32v30x_it.o + .debug_abbrev 0x00000000000001cf 0x359 ./User/main.o + .debug_abbrev 0x0000000000000528 0x2c0 ./User/system_ch32v30x.o + .debug_abbrev 0x00000000000007e8 0x715 ./TencentOS_Tiny/tos_js/tos_js.o + .debug_abbrev 0x0000000000000efd 0x1f9 ./TencentOS_Tiny/kernel/core/tos_global.o + .debug_abbrev 0x00000000000010f6 0x5a2 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_abbrev 0x0000000000001698 0x370 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_abbrev 0x0000000000001a08 0x3eb ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_abbrev 0x0000000000001df3 0x3a9 ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_abbrev 0x000000000000219c 0x3e1 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_abbrev 0x000000000000257d 0x4b1 ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_abbrev 0x0000000000002a2e 0x369 ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_abbrev 0x0000000000002d97 0x37f ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_abbrev 0x0000000000003116 0x14 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + .debug_abbrev 0x000000000000312a 0x33d ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_abbrev 0x0000000000003467 0x12 ./Startup/startup_ch32v30x.o + .debug_abbrev 0x0000000000003479 0x309 ./Peripheral/src/ch32v30x_gpio.o + .debug_abbrev 0x0000000000003782 0x351 ./Peripheral/src/ch32v30x_rcc.o + .debug_abbrev 0x0000000000003ad3 0x312 ./Peripheral/src/ch32v30x_usart.o + .debug_abbrev 0x0000000000003de5 0x2f9 ./Debug/debug.o + +.debug_aranges 0x0000000000000000 0xb18 + .debug_aranges + 0x0000000000000000 0x28 ./User/ch32v30x_it.o + .debug_aranges + 0x0000000000000028 0x40 ./User/main.o + .debug_aranges + 0x0000000000000068 0x28 ./User/system_ch32v30x.o + .debug_aranges + 0x0000000000000090 0x240 ./TencentOS_Tiny/tos_js/tos_js.o + .debug_aranges + 0x00000000000002d0 0x18 ./TencentOS_Tiny/kernel/core/tos_global.o + .debug_aranges + 0x00000000000002e8 0xd8 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_aranges + 0x00000000000003c0 0x58 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_aranges + 0x0000000000000418 0x80 ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_aranges + 0x0000000000000498 0x68 ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_aranges + 0x0000000000000500 0x88 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_aranges + 0x0000000000000588 0x88 ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_aranges + 0x0000000000000610 0x40 ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_aranges + 0x0000000000000650 0x70 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_aranges + 0x00000000000006c0 0x20 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + .debug_aranges + 0x00000000000006e0 0x70 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_aranges + 0x0000000000000750 0x30 ./Startup/startup_ch32v30x.o + .debug_aranges + 0x0000000000000780 0xa8 ./Peripheral/src/ch32v30x_gpio.o + .debug_aranges + 0x0000000000000828 0x1a8 ./Peripheral/src/ch32v30x_rcc.o + .debug_aranges + 0x00000000000009d0 0x100 ./Peripheral/src/ch32v30x_usart.o + .debug_aranges + 0x0000000000000ad0 0x48 ./Debug/debug.o + +.debug_ranges 0x0000000000000000 0x1e80 + .debug_ranges 0x0000000000000000 0x18 ./User/ch32v30x_it.o + .debug_ranges 0x0000000000000018 0x78 ./User/main.o + .debug_ranges 0x0000000000000090 0x38 ./User/system_ch32v30x.o + .debug_ranges 0x00000000000000c8 0xe30 ./TencentOS_Tiny/tos_js/tos_js.o + .debug_ranges 0x0000000000000ef8 0x4b8 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_ranges 0x00000000000013b0 0x150 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_ranges 0x0000000000001500 0xe8 ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_ranges 0x00000000000015e8 0xd8 ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_ranges 0x00000000000016c0 0xa8 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_ranges 0x0000000000001768 0x228 ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_ranges 0x0000000000001990 0x98 ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_ranges 0x0000000000001a28 0x60 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_ranges 0x0000000000001a88 0x78 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_ranges 0x0000000000001b00 0x28 ./Startup/startup_ch32v30x.o + .debug_ranges 0x0000000000001b28 0x98 ./Peripheral/src/ch32v30x_gpio.o + .debug_ranges 0x0000000000001bc0 0x198 ./Peripheral/src/ch32v30x_rcc.o + .debug_ranges 0x0000000000001d58 0xf0 ./Peripheral/src/ch32v30x_usart.o + .debug_ranges 0x0000000000001e48 0x38 ./Debug/debug.o + +.debug_line 0x0000000000000000 0x13f4f + .debug_line 0x0000000000000000 0x261 ./User/ch32v30x_it.o + .debug_line 0x0000000000000261 0x6e9 ./User/main.o + .debug_line 0x000000000000094a 0x755 ./User/system_ch32v30x.o + .debug_line 0x000000000000109f 0x6e1f ./TencentOS_Tiny/tos_js/tos_js.o + .debug_line 0x0000000000007ebe 0x372 ./TencentOS_Tiny/kernel/core/tos_global.o + .debug_line 0x0000000000008230 0x1e61 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_line 0x000000000000a091 0xd98 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_line 0x000000000000ae29 0x954 ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_line 0x000000000000b77d 0xa8d ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_line 0x000000000000c20a 0xa28 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_line 0x000000000000cc32 0x15b4 ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_line 0x000000000000e1e6 0x956 ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_line 0x000000000000eb3c 0x77f ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_line 0x000000000000f2bb 0x342 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + .debug_line 0x000000000000f5fd 0x8ea ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_line 0x000000000000fee7 0x352 ./Startup/startup_ch32v30x.o + .debug_line 0x0000000000010239 0xd6c ./Peripheral/src/ch32v30x_gpio.o + .debug_line 0x0000000000010fa5 0x1819 ./Peripheral/src/ch32v30x_rcc.o + .debug_line 0x00000000000127be 0x108b ./Peripheral/src/ch32v30x_usart.o + .debug_line 0x0000000000013849 0x706 ./Debug/debug.o + +.debug_str 0x0000000000000000 0x43d9 + .debug_str 0x0000000000000000 0x536 ./User/ch32v30x_it.o + 0x5ad (size before relaxing) + .debug_str 0x0000000000000536 0x703 ./User/main.o + 0xd20 (size before relaxing) + .debug_str 0x0000000000000c39 0xef ./User/system_ch32v30x.o + 0x6a7 (size before relaxing) + .debug_str 0x0000000000000d28 0xa6d ./TencentOS_Tiny/tos_js/tos_js.o + 0x111e (size before relaxing) + .debug_str 0x0000000000001795 0x2b ./TencentOS_Tiny/kernel/core/tos_global.o + 0xaa4 (size before relaxing) + .debug_str 0x00000000000017c0 0xce3 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + 0x17af (size before relaxing) + .debug_str 0x00000000000024a3 0x2f6 ./TencentOS_Tiny/kernel/core/tos_mutex.o + 0x15f8 (size before relaxing) + .debug_str 0x0000000000002799 0x186 ./TencentOS_Tiny/kernel/core/tos_pend.o + 0x1526 (size before relaxing) + .debug_str 0x000000000000291f 0x183 ./TencentOS_Tiny/kernel/core/tos_sched.o + 0xc84 (size before relaxing) + .debug_str 0x0000000000002aa2 0xde ./TencentOS_Tiny/kernel/core/tos_sys.o + 0x148b (size before relaxing) + .debug_str 0x0000000000002b80 0x22c ./TencentOS_Tiny/kernel/core/tos_task.o + 0x177e (size before relaxing) + .debug_str 0x0000000000002dac 0xdd ./TencentOS_Tiny/kernel/core/tos_tick.o + 0xc42 (size before relaxing) + .debug_str 0x0000000000002e89 0x733 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + 0x122e (size before relaxing) + .debug_str 0x00000000000035bc 0x3c ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + 0x6e (size before relaxing) + .debug_str 0x00000000000035f8 0xce ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + 0xcb3 (size before relaxing) + .debug_str 0x00000000000036c6 0x1e ./Startup/startup_ch32v30x.o + 0x5c (size before relaxing) + .debug_str 0x00000000000036e4 0x272 ./Peripheral/src/ch32v30x_gpio.o + 0x968 (size before relaxing) + .debug_str 0x0000000000003956 0x5e0 ./Peripheral/src/ch32v30x_rcc.o + 0xcb8 (size before relaxing) + .debug_str 0x0000000000003f36 0x428 ./Peripheral/src/ch32v30x_usart.o + 0xb0e (size before relaxing) + .debug_str 0x000000000000435e 0x7b ./Debug/debug.o + 0x8f6 (size before relaxing) + +.comment 0x0000000000000000 0x33 + .comment 0x0000000000000000 0x33 ./User/ch32v30x_it.o + 0x34 (size before relaxing) + .comment 0x0000000000000033 0x34 ./User/main.o + .comment 0x0000000000000033 0x34 ./User/system_ch32v30x.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/tos_js/tos_js.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_global.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_pend.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_sched.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_sys.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_task.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/kernel/core/tos_tick.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .comment 0x0000000000000033 0x34 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_gpio.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_rcc.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_usart.o + .comment 0x0000000000000033 0x34 ./Debug/debug.o + +.debug_frame 0x0000000000000000 0x3b98 + .debug_frame 0x0000000000000000 0x30 ./User/ch32v30x_it.o + .debug_frame 0x0000000000000030 0xb4 ./User/main.o + .debug_frame 0x00000000000000e4 0x3c ./User/system_ch32v30x.o + .debug_frame 0x0000000000000120 0xaec ./TencentOS_Tiny/tos_js/tos_js.o + .debug_frame 0x0000000000000c0c 0x324 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_frame 0x0000000000000f30 0x130 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_frame 0x0000000000001060 0x150 ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_frame 0x00000000000011b0 0xfc ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_frame 0x00000000000012ac 0x158 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_frame 0x0000000000001404 0x20c ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_frame 0x0000000000001610 0xc0 ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_frame 0x00000000000016d0 0x168 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_frame 0x0000000000001838 0x128 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_frame 0x0000000000001960 0x148 ./Peripheral/src/ch32v30x_gpio.o + .debug_frame 0x0000000000001aa8 0x344 ./Peripheral/src/ch32v30x_rcc.o + .debug_frame 0x0000000000001dec 0x204 ./Peripheral/src/ch32v30x_usart.o + .debug_frame 0x0000000000001ff0 0x9c ./Debug/debug.o + .debug_frame 0x000000000000208c 0x44 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(adddf3.o) + .debug_frame 0x00000000000020d0 0x50 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(divdf3.o) + .debug_frame 0x0000000000002120 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(eqdf2.o) + .debug_frame 0x0000000000002140 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(gedf2.o) + .debug_frame 0x0000000000002160 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(ledf2.o) + .debug_frame 0x0000000000002180 0x54 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(muldf3.o) + .debug_frame 0x00000000000021d4 0x44 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(subdf3.o) + .debug_frame 0x0000000000002218 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixdfsi.o) + .debug_frame 0x0000000000002238 0x38 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatsidf.o) + .debug_frame 0x0000000000002270 0x38 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(floatunsidf.o) + .debug_frame 0x00000000000022a8 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(_clzsi2.o) + .debug_frame 0x00000000000022c8 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-assert.o) + .debug_frame 0x0000000000002308 0x48 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fprintf.o) + .debug_frame 0x0000000000002350 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcmp.o) + .debug_frame 0x0000000000002370 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memcpy.o) + .debug_frame 0x0000000000002390 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memmove.o) + .debug_frame 0x00000000000023b0 0xd0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf.o) + .debug_frame 0x0000000000002480 0xbc c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_float.o) + .debug_frame 0x000000000000253c 0x8c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfprintf_i.o) + .debug_frame 0x00000000000025c8 0x60 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-vfscanf_float.o) + .debug_frame 0x0000000000002628 0x54 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-printf.o) + .debug_frame 0x000000000000267c 0x50 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putchar.o) + .debug_frame 0x00000000000026cc 0x54 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-puts.o) + .debug_frame 0x0000000000002720 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-s_modf.o) + .debug_frame 0x0000000000002750 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sf_nan.o) + .debug_frame 0x0000000000002770 0x60 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-snprintf.o) + .debug_frame 0x00000000000027d0 0x48 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sprintf.o) + .debug_frame 0x0000000000002818 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strlen.o) + .debug_frame 0x0000000000002838 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncpy.o) + .debug_frame 0x0000000000002858 0x154 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtod.o) + .debug_frame 0x00000000000029ac 0x70 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strtol.o) + .debug_frame 0x0000000000002a1c 0x48 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-vsnprintf.o) + .debug_frame 0x0000000000002a64 0x50 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wbuf.o) + .debug_frame 0x0000000000002ab4 0x3c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wsetup.o) + .debug_frame 0x0000000000002af0 0x28 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-abort.o) + .debug_frame 0x0000000000002b18 0x98 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-dtoa.o) + .debug_frame 0x0000000000002bb0 0x7c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fflush.o) + .debug_frame 0x0000000000002c2c 0x148 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-findfp.o) + .debug_frame 0x0000000000002d74 0x88 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fwalk.o) + .debug_frame 0x0000000000002dfc 0x84 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-gethex.o) + .debug_frame 0x0000000000002e80 0x80 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-gdtoa-hexnan.o) + .debug_frame 0x0000000000002f00 0x78 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-locale.o) + .debug_frame 0x0000000000002f78 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-localeconv.o) + .debug_frame 0x0000000000002fb8 0x64 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-makebuf.o) + .debug_frame 0x000000000000301c 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-malloc.o) + .debug_frame 0x000000000000304c 0x38 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mbtowc_r.o) + .debug_frame 0x0000000000003084 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-memchr.o) + .debug_frame 0x00000000000030a4 0x2e0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mprec.o) + .debug_frame 0x0000000000003384 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-callocr.o) + .debug_frame 0x00000000000033b4 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-freer.o) + .debug_frame 0x00000000000033f4 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-mallocr.o) + .debug_frame 0x0000000000003434 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-reallocr.o) + .debug_frame 0x0000000000003474 0xe0 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-svfprintf.o) + .debug_frame 0x0000000000003554 0x4c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-putc.o) + .debug_frame 0x00000000000035a0 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-sbrkr.o) + .debug_frame 0x00000000000035d0 0xec c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signal.o) + .debug_frame 0x00000000000036bc 0x40 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-signalr.o) + .debug_frame 0x00000000000036fc 0xa4 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-stdio.o) + .debug_frame 0x00000000000037a0 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-strncmp.o) + .debug_frame 0x00000000000037c0 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-wctomb_r.o) + .debug_frame 0x00000000000037f0 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-writer.o) + .debug_frame 0x0000000000003820 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-closer.o) + .debug_frame 0x0000000000003850 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-fstatr.o) + .debug_frame 0x0000000000003880 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-isattyr.o) + .debug_frame 0x00000000000038b0 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-lseekr.o) + .debug_frame 0x00000000000038e0 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-mlock.o) + .debug_frame 0x0000000000003910 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-nano-msizer.o) + .debug_frame 0x0000000000003930 0x30 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-readr.o) + .debug_frame 0x0000000000003960 0x70 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libg_nano.a(lib_a-reent.o) + .debug_frame 0x00000000000039d0 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(unorddf2.o) + .debug_frame 0x00000000000039f0 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(fixunsdfsi.o) + .debug_frame 0x0000000000003a10 0x3c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(extenddftf2.o) + .debug_frame 0x0000000000003a4c 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(truncdfsf2.o) + .debug_frame 0x0000000000003a6c 0x2c c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0\libgcc.a(trunctfdf2.o) + .debug_frame 0x0000000000003a98 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + .debug_frame 0x0000000000003ab8 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + .debug_frame 0x0000000000003ad8 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + .debug_frame 0x0000000000003af8 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + .debug_frame 0x0000000000003b18 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + .debug_frame 0x0000000000003b38 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + .debug_frame 0x0000000000003b58 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + .debug_frame 0x0000000000003b78 0x20 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(_exit.o) + +.debug_loc 0x0000000000000000 0x9093 + .debug_loc 0x0000000000000000 0xd3 ./User/main.o + .debug_loc 0x00000000000000d3 0xe5 ./User/system_ch32v30x.o + .debug_loc 0x00000000000001b8 0x4575 ./TencentOS_Tiny/tos_js/tos_js.o + .debug_loc 0x000000000000472d 0x15d5 ./TencentOS_Tiny/kernel/core/tos_mmheap.o + .debug_loc 0x0000000000005d02 0x3b4 ./TencentOS_Tiny/kernel/core/tos_mutex.o + .debug_loc 0x00000000000060b6 0x431 ./TencentOS_Tiny/kernel/core/tos_pend.o + .debug_loc 0x00000000000064e7 0x32d ./TencentOS_Tiny/kernel/core/tos_sched.o + .debug_loc 0x0000000000006814 0xf4 ./TencentOS_Tiny/kernel/core/tos_sys.o + .debug_loc 0x0000000000006908 0x782 ./TencentOS_Tiny/kernel/core/tos_task.o + .debug_loc 0x000000000000708a 0x3ab ./TencentOS_Tiny/kernel/core/tos_tick.o + .debug_loc 0x0000000000007435 0xb8 ./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o + .debug_loc 0x00000000000074ed 0x1b0 ./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + .debug_loc 0x000000000000769d 0x670 ./Peripheral/src/ch32v30x_gpio.o + .debug_loc 0x0000000000007d0d 0xa54 ./Peripheral/src/ch32v30x_rcc.o + .debug_loc 0x0000000000008761 0x7bb ./Peripheral/src/ch32v30x_usart.o + .debug_loc 0x0000000000008f1c 0x177 ./Debug/debug.o + +.stab 0x0000000000000000 0xb4 + .stab 0x0000000000000000 0x24 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) + .stab 0x0000000000000024 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(fstat.o) + 0x24 (size before relaxing) + .stab 0x000000000000003c 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(getpid.o) + 0x24 (size before relaxing) + .stab 0x0000000000000054 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(isatty.o) + 0x24 (size before relaxing) + .stab 0x000000000000006c 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(kill.o) + 0x24 (size before relaxing) + .stab 0x0000000000000084 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(lseek.o) + 0x24 (size before relaxing) + .stab 0x000000000000009c 0x18 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(read.o) + 0x24 (size before relaxing) + +.stabstr 0x0000000000000000 0x183 + .stabstr 0x0000000000000000 0x183 c:/users/a1885/program/mounriver/mounriver_studio/toolchain/risc-v embedded gcc/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib\libnosys.a(close.o) diff --git a/obj/Peripheral/src/ch32v30x_adc.d b/obj/Peripheral/src/ch32v30x_adc.d new file mode 100644 index 0000000..f203cae --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_adc.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_adc.o: ../Peripheral/src/ch32v30x_adc.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_adc.o b/obj/Peripheral/src/ch32v30x_adc.o new file mode 100644 index 0000000..ca1cd22 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_adc.o differ diff --git a/obj/Peripheral/src/ch32v30x_bkp.d b/obj/Peripheral/src/ch32v30x_bkp.d new file mode 100644 index 0000000..f902ab1 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_bkp.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_bkp.o: ../Peripheral/src/ch32v30x_bkp.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_bkp.o b/obj/Peripheral/src/ch32v30x_bkp.o new file mode 100644 index 0000000..108ff7e Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_bkp.o differ diff --git a/obj/Peripheral/src/ch32v30x_can.d b/obj/Peripheral/src/ch32v30x_can.d new file mode 100644 index 0000000..fecac9d --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_can.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_can.o: ../Peripheral/src/ch32v30x_can.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_can.o b/obj/Peripheral/src/ch32v30x_can.o new file mode 100644 index 0000000..f6e647a Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_can.o differ diff --git a/obj/Peripheral/src/ch32v30x_crc.d b/obj/Peripheral/src/ch32v30x_crc.d new file mode 100644 index 0000000..5e86490 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_crc.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_crc.o: ../Peripheral/src/ch32v30x_crc.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_crc.o b/obj/Peripheral/src/ch32v30x_crc.o new file mode 100644 index 0000000..2837ec0 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_crc.o differ diff --git a/obj/Peripheral/src/ch32v30x_dac.d b/obj/Peripheral/src/ch32v30x_dac.d new file mode 100644 index 0000000..e668d1c --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_dac.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_dac.o: ../Peripheral/src/ch32v30x_dac.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_dac.o b/obj/Peripheral/src/ch32v30x_dac.o new file mode 100644 index 0000000..4623e9f Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_dac.o differ diff --git a/obj/Peripheral/src/ch32v30x_dbgmcu.d b/obj/Peripheral/src/ch32v30x_dbgmcu.d new file mode 100644 index 0000000..49e84af --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_dbgmcu.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_dbgmcu.o: ../Peripheral/src/ch32v30x_dbgmcu.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_dbgmcu.o b/obj/Peripheral/src/ch32v30x_dbgmcu.o new file mode 100644 index 0000000..0e05251 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_dbgmcu.o differ diff --git a/obj/Peripheral/src/ch32v30x_dma.d b/obj/Peripheral/src/ch32v30x_dma.d new file mode 100644 index 0000000..17ef7af --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_dma.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_dma.o: ../Peripheral/src/ch32v30x_dma.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_dma.o b/obj/Peripheral/src/ch32v30x_dma.o new file mode 100644 index 0000000..c140ea4 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_dma.o differ diff --git a/obj/Peripheral/src/ch32v30x_dvp.d b/obj/Peripheral/src/ch32v30x_dvp.d new file mode 100644 index 0000000..bb91fe4 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_dvp.d @@ -0,0 +1,91 @@ +Peripheral/src/ch32v30x_dvp.o: ../Peripheral/src/ch32v30x_dvp.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dvp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dvp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_dvp.o b/obj/Peripheral/src/ch32v30x_dvp.o new file mode 100644 index 0000000..a1853ef Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_dvp.o differ diff --git a/obj/Peripheral/src/ch32v30x_eth.d b/obj/Peripheral/src/ch32v30x_eth.d new file mode 100644 index 0000000..2c56d44 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_eth.d @@ -0,0 +1,91 @@ +Peripheral/src/ch32v30x_eth.o: ../Peripheral/src/ch32v30x_eth.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_eth.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_eth.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_eth.o b/obj/Peripheral/src/ch32v30x_eth.o new file mode 100644 index 0000000..0853f14 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_eth.o differ diff --git a/obj/Peripheral/src/ch32v30x_exti.d b/obj/Peripheral/src/ch32v30x_exti.d new file mode 100644 index 0000000..d96d280 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_exti.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_exti.o: ../Peripheral/src/ch32v30x_exti.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_exti.o b/obj/Peripheral/src/ch32v30x_exti.o new file mode 100644 index 0000000..fa6d9c6 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_exti.o differ diff --git a/obj/Peripheral/src/ch32v30x_flash.d b/obj/Peripheral/src/ch32v30x_flash.d new file mode 100644 index 0000000..480bd72 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_flash.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_flash.o: ../Peripheral/src/ch32v30x_flash.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_flash.o b/obj/Peripheral/src/ch32v30x_flash.o new file mode 100644 index 0000000..83d00ba Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_flash.o differ diff --git a/obj/Peripheral/src/ch32v30x_fsmc.d b/obj/Peripheral/src/ch32v30x_fsmc.d new file mode 100644 index 0000000..1048113 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_fsmc.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_fsmc.o: ../Peripheral/src/ch32v30x_fsmc.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_fsmc.o b/obj/Peripheral/src/ch32v30x_fsmc.o new file mode 100644 index 0000000..96b0b9f Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_fsmc.o differ diff --git a/obj/Peripheral/src/ch32v30x_gpio.d b/obj/Peripheral/src/ch32v30x_gpio.d new file mode 100644 index 0000000..29a0d8c --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_gpio.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_gpio.o: ../Peripheral/src/ch32v30x_gpio.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_gpio.o b/obj/Peripheral/src/ch32v30x_gpio.o new file mode 100644 index 0000000..aaf84e7 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_gpio.o differ diff --git a/obj/Peripheral/src/ch32v30x_i2c.d b/obj/Peripheral/src/ch32v30x_i2c.d new file mode 100644 index 0000000..b84c34b --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_i2c.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_i2c.o: ../Peripheral/src/ch32v30x_i2c.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_i2c.o b/obj/Peripheral/src/ch32v30x_i2c.o new file mode 100644 index 0000000..505aaa7 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_i2c.o differ diff --git a/obj/Peripheral/src/ch32v30x_iwdg.d b/obj/Peripheral/src/ch32v30x_iwdg.d new file mode 100644 index 0000000..35cc456 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_iwdg.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_iwdg.o: ../Peripheral/src/ch32v30x_iwdg.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_iwdg.o b/obj/Peripheral/src/ch32v30x_iwdg.o new file mode 100644 index 0000000..8d0fd9e Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_iwdg.o differ diff --git a/obj/Peripheral/src/ch32v30x_misc.d b/obj/Peripheral/src/ch32v30x_misc.d new file mode 100644 index 0000000..e4fc969 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_misc.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_misc.o: ../Peripheral/src/ch32v30x_misc.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: diff --git a/obj/Peripheral/src/ch32v30x_misc.o b/obj/Peripheral/src/ch32v30x_misc.o new file mode 100644 index 0000000..4464d89 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_misc.o differ diff --git a/obj/Peripheral/src/ch32v30x_opa.d b/obj/Peripheral/src/ch32v30x_opa.d new file mode 100644 index 0000000..612a9dc --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_opa.d @@ -0,0 +1,91 @@ +Peripheral/src/ch32v30x_opa.o: ../Peripheral/src/ch32v30x_opa.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_opa.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_opa.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_opa.o b/obj/Peripheral/src/ch32v30x_opa.o new file mode 100644 index 0000000..66c09af Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_opa.o differ diff --git a/obj/Peripheral/src/ch32v30x_pwr.d b/obj/Peripheral/src/ch32v30x_pwr.d new file mode 100644 index 0000000..93022ca --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_pwr.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_pwr.o: ../Peripheral/src/ch32v30x_pwr.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_pwr.o b/obj/Peripheral/src/ch32v30x_pwr.o new file mode 100644 index 0000000..f9a38f0 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_pwr.o differ diff --git a/obj/Peripheral/src/ch32v30x_rcc.d b/obj/Peripheral/src/ch32v30x_rcc.d new file mode 100644 index 0000000..7177476 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_rcc.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_rcc.o: ../Peripheral/src/ch32v30x_rcc.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_rcc.o b/obj/Peripheral/src/ch32v30x_rcc.o new file mode 100644 index 0000000..6753d4e Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_rcc.o differ diff --git a/obj/Peripheral/src/ch32v30x_rng.d b/obj/Peripheral/src/ch32v30x_rng.d new file mode 100644 index 0000000..ebeefc9 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_rng.d @@ -0,0 +1,91 @@ +Peripheral/src/ch32v30x_rng.o: ../Peripheral/src/ch32v30x_rng.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rng.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rng.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_rng.o b/obj/Peripheral/src/ch32v30x_rng.o new file mode 100644 index 0000000..3b0040e Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_rng.o differ diff --git a/obj/Peripheral/src/ch32v30x_rtc.d b/obj/Peripheral/src/ch32v30x_rtc.d new file mode 100644 index 0000000..d24b05a --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_rtc.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_rtc.o: ../Peripheral/src/ch32v30x_rtc.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_rtc.o b/obj/Peripheral/src/ch32v30x_rtc.o new file mode 100644 index 0000000..106e6b6 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_rtc.o differ diff --git a/obj/Peripheral/src/ch32v30x_sdio.d b/obj/Peripheral/src/ch32v30x_sdio.d new file mode 100644 index 0000000..5bd15ed --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_sdio.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_sdio.o: ../Peripheral/src/ch32v30x_sdio.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_sdio.o b/obj/Peripheral/src/ch32v30x_sdio.o new file mode 100644 index 0000000..cff1a71 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_sdio.o differ diff --git a/obj/Peripheral/src/ch32v30x_spi.d b/obj/Peripheral/src/ch32v30x_spi.d new file mode 100644 index 0000000..e7f2c8d --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_spi.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_spi.o: ../Peripheral/src/ch32v30x_spi.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_spi.o b/obj/Peripheral/src/ch32v30x_spi.o new file mode 100644 index 0000000..132f372 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_spi.o differ diff --git a/obj/Peripheral/src/ch32v30x_tim.d b/obj/Peripheral/src/ch32v30x_tim.d new file mode 100644 index 0000000..66d53aa --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_tim.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_tim.o: ../Peripheral/src/ch32v30x_tim.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_tim.o b/obj/Peripheral/src/ch32v30x_tim.o new file mode 100644 index 0000000..25bf21f Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_tim.o differ diff --git a/obj/Peripheral/src/ch32v30x_usart.d b/obj/Peripheral/src/ch32v30x_usart.d new file mode 100644 index 0000000..5428828 --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_usart.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_usart.o: ../Peripheral/src/ch32v30x_usart.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_usart.o b/obj/Peripheral/src/ch32v30x_usart.o new file mode 100644 index 0000000..1957110 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_usart.o differ diff --git a/obj/Peripheral/src/ch32v30x_wwdg.d b/obj/Peripheral/src/ch32v30x_wwdg.d new file mode 100644 index 0000000..9a43f6e --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_wwdg.d @@ -0,0 +1,88 @@ +Peripheral/src/ch32v30x_wwdg.o: ../Peripheral/src/ch32v30x_wwdg.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/Peripheral/src/ch32v30x_wwdg.o b/obj/Peripheral/src/ch32v30x_wwdg.o new file mode 100644 index 0000000..c5a2b00 Binary files /dev/null and b/obj/Peripheral/src/ch32v30x_wwdg.o differ diff --git a/obj/Peripheral/src/subdir.mk b/obj/Peripheral/src/subdir.mk new file mode 100644 index 0000000..fb53831 --- /dev/null +++ b/obj/Peripheral/src/subdir.mk @@ -0,0 +1,95 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Peripheral/src/ch32v30x_adc.c \ +../Peripheral/src/ch32v30x_bkp.c \ +../Peripheral/src/ch32v30x_can.c \ +../Peripheral/src/ch32v30x_crc.c \ +../Peripheral/src/ch32v30x_dac.c \ +../Peripheral/src/ch32v30x_dbgmcu.c \ +../Peripheral/src/ch32v30x_dma.c \ +../Peripheral/src/ch32v30x_dvp.c \ +../Peripheral/src/ch32v30x_eth.c \ +../Peripheral/src/ch32v30x_exti.c \ +../Peripheral/src/ch32v30x_flash.c \ +../Peripheral/src/ch32v30x_fsmc.c \ +../Peripheral/src/ch32v30x_gpio.c \ +../Peripheral/src/ch32v30x_i2c.c \ +../Peripheral/src/ch32v30x_iwdg.c \ +../Peripheral/src/ch32v30x_misc.c \ +../Peripheral/src/ch32v30x_opa.c \ +../Peripheral/src/ch32v30x_pwr.c \ +../Peripheral/src/ch32v30x_rcc.c \ +../Peripheral/src/ch32v30x_rng.c \ +../Peripheral/src/ch32v30x_rtc.c \ +../Peripheral/src/ch32v30x_sdio.c \ +../Peripheral/src/ch32v30x_spi.c \ +../Peripheral/src/ch32v30x_tim.c \ +../Peripheral/src/ch32v30x_usart.c \ +../Peripheral/src/ch32v30x_wwdg.c + +OBJS += \ +./Peripheral/src/ch32v30x_adc.o \ +./Peripheral/src/ch32v30x_bkp.o \ +./Peripheral/src/ch32v30x_can.o \ +./Peripheral/src/ch32v30x_crc.o \ +./Peripheral/src/ch32v30x_dac.o \ +./Peripheral/src/ch32v30x_dbgmcu.o \ +./Peripheral/src/ch32v30x_dma.o \ +./Peripheral/src/ch32v30x_dvp.o \ +./Peripheral/src/ch32v30x_eth.o \ +./Peripheral/src/ch32v30x_exti.o \ +./Peripheral/src/ch32v30x_flash.o \ +./Peripheral/src/ch32v30x_fsmc.o \ +./Peripheral/src/ch32v30x_gpio.o \ +./Peripheral/src/ch32v30x_i2c.o \ +./Peripheral/src/ch32v30x_iwdg.o \ +./Peripheral/src/ch32v30x_misc.o \ +./Peripheral/src/ch32v30x_opa.o \ +./Peripheral/src/ch32v30x_pwr.o \ +./Peripheral/src/ch32v30x_rcc.o \ +./Peripheral/src/ch32v30x_rng.o \ +./Peripheral/src/ch32v30x_rtc.o \ +./Peripheral/src/ch32v30x_sdio.o \ +./Peripheral/src/ch32v30x_spi.o \ +./Peripheral/src/ch32v30x_tim.o \ +./Peripheral/src/ch32v30x_usart.o \ +./Peripheral/src/ch32v30x_wwdg.o + +C_DEPS += \ +./Peripheral/src/ch32v30x_adc.d \ +./Peripheral/src/ch32v30x_bkp.d \ +./Peripheral/src/ch32v30x_can.d \ +./Peripheral/src/ch32v30x_crc.d \ +./Peripheral/src/ch32v30x_dac.d \ +./Peripheral/src/ch32v30x_dbgmcu.d \ +./Peripheral/src/ch32v30x_dma.d \ +./Peripheral/src/ch32v30x_dvp.d \ +./Peripheral/src/ch32v30x_eth.d \ +./Peripheral/src/ch32v30x_exti.d \ +./Peripheral/src/ch32v30x_flash.d \ +./Peripheral/src/ch32v30x_fsmc.d \ +./Peripheral/src/ch32v30x_gpio.d \ +./Peripheral/src/ch32v30x_i2c.d \ +./Peripheral/src/ch32v30x_iwdg.d \ +./Peripheral/src/ch32v30x_misc.d \ +./Peripheral/src/ch32v30x_opa.d \ +./Peripheral/src/ch32v30x_pwr.d \ +./Peripheral/src/ch32v30x_rcc.d \ +./Peripheral/src/ch32v30x_rng.d \ +./Peripheral/src/ch32v30x_rtc.d \ +./Peripheral/src/ch32v30x_sdio.d \ +./Peripheral/src/ch32v30x_spi.d \ +./Peripheral/src/ch32v30x_tim.d \ +./Peripheral/src/ch32v30x_usart.d \ +./Peripheral/src/ch32v30x_wwdg.d + + +# Each subdirectory must supply rules for building sources it contributes +Peripheral/src/%.o: ../Peripheral/src/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/Startup/startup_ch32v30x.d b/obj/Startup/startup_ch32v30x.d new file mode 100644 index 0000000..cfcdb28 --- /dev/null +++ b/obj/Startup/startup_ch32v30x.d @@ -0,0 +1 @@ +Startup/startup_ch32v30x.o: ../Startup/startup_ch32v30x.S diff --git a/obj/Startup/startup_ch32v30x.o b/obj/Startup/startup_ch32v30x.o new file mode 100644 index 0000000..48fe839 Binary files /dev/null and b/obj/Startup/startup_ch32v30x.o differ diff --git a/obj/Startup/subdir.mk b/obj/Startup/subdir.mk new file mode 100644 index 0000000..353b416 --- /dev/null +++ b/obj/Startup/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_UPPER_SRCS += \ +../Startup/startup_ch32v30x.S + +OBJS += \ +./Startup/startup_ch32v30x.o + +S_UPPER_DEPS += \ +./Startup/startup_ch32v30x.d + + +# Each subdirectory must supply rules for building sources it contributes +Startup/%.o: ../Startup/%.S + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -x assembler-with-cpp -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Startup" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/TencentOS_Tiny/arch/risc-v/common/subdir.mk b/obj/TencentOS_Tiny/arch/risc-v/common/subdir.mk new file mode 100644 index 0000000..8b59e4b --- /dev/null +++ b/obj/TencentOS_Tiny/arch/risc-v/common/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../TencentOS_Tiny/arch/risc-v/common/tos_cpu.c + +OBJS += \ +./TencentOS_Tiny/arch/risc-v/common/tos_cpu.o + +C_DEPS += \ +./TencentOS_Tiny/arch/risc-v/common/tos_cpu.d + + +# Each subdirectory must supply rules for building sources it contributes +TencentOS_Tiny/arch/risc-v/common/%.o: ../TencentOS_Tiny/arch/risc-v/common/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/TencentOS_Tiny/arch/risc-v/common/tos_cpu.d b/obj/TencentOS_Tiny/arch/risc-v/common/tos_cpu.d new file mode 100644 index 0000000..c9c1c2e --- /dev/null +++ b/obj/TencentOS_Tiny/arch/risc-v/common/tos_cpu.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/arch/risc-v/common/tos_cpu.o: \ + ../TencentOS_Tiny/arch/risc-v/common/tos_cpu.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/arch/risc-v/common/tos_cpu.o b/obj/TencentOS_Tiny/arch/risc-v/common/tos_cpu.o new file mode 100644 index 0000000..65f89d9 Binary files /dev/null and b/obj/TencentOS_Tiny/arch/risc-v/common/tos_cpu.o differ diff --git a/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.d b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.d new file mode 100644 index 0000000..795af21 --- /dev/null +++ b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o: \ + ../TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o new file mode 100644 index 0000000..26901aa Binary files /dev/null and b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o differ diff --git a/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.d b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.d new file mode 100644 index 0000000..68abc9c --- /dev/null +++ b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.d @@ -0,0 +1,5 @@ +TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o: \ + ../TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.S \ + ../TencentOS_Tiny/arch/risc-v/rv32/gcc/port_config.h + +../TencentOS_Tiny/arch/risc-v/rv32/gcc/port_config.h: diff --git a/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o new file mode 100644 index 0000000..9d7fa2a Binary files /dev/null and b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o differ diff --git a/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/subdir.mk b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/subdir.mk new file mode 100644 index 0000000..2272295 --- /dev/null +++ b/obj/TencentOS_Tiny/arch/risc-v/rv32/gcc/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.c + +S_UPPER_SRCS += \ +../TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.S + +OBJS += \ +./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.o \ +./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.o + +S_UPPER_DEPS += \ +./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_s.d + +C_DEPS += \ +./TencentOS_Tiny/arch/risc-v/rv32/gcc/port_c.d + + +# Each subdirectory must supply rules for building sources it contributes +TencentOS_Tiny/arch/risc-v/rv32/gcc/%.o: ../TencentOS_Tiny/arch/risc-v/rv32/gcc/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ +TencentOS_Tiny/arch/risc-v/rv32/gcc/%.o: ../TencentOS_Tiny/arch/risc-v/rv32/gcc/%.S + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -x assembler-with-cpp -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Startup" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/TencentOS_Tiny/kernel/core/subdir.mk b/obj/TencentOS_Tiny/kernel/core/subdir.mk new file mode 100644 index 0000000..c913c40 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/subdir.mk @@ -0,0 +1,101 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../TencentOS_Tiny/kernel/core/tos_barrier.c \ +../TencentOS_Tiny/kernel/core/tos_binary_heap.c \ +../TencentOS_Tiny/kernel/core/tos_bitmap.c \ +../TencentOS_Tiny/kernel/core/tos_char_fifo.c \ +../TencentOS_Tiny/kernel/core/tos_completion.c \ +../TencentOS_Tiny/kernel/core/tos_countdownlatch.c \ +../TencentOS_Tiny/kernel/core/tos_event.c \ +../TencentOS_Tiny/kernel/core/tos_global.c \ +../TencentOS_Tiny/kernel/core/tos_mail_queue.c \ +../TencentOS_Tiny/kernel/core/tos_message_queue.c \ +../TencentOS_Tiny/kernel/core/tos_mmblk.c \ +../TencentOS_Tiny/kernel/core/tos_mmheap.c \ +../TencentOS_Tiny/kernel/core/tos_mutex.c \ +../TencentOS_Tiny/kernel/core/tos_pend.c \ +../TencentOS_Tiny/kernel/core/tos_priority_mail_queue.c \ +../TencentOS_Tiny/kernel/core/tos_priority_message_queue.c \ +../TencentOS_Tiny/kernel/core/tos_priority_queue.c \ +../TencentOS_Tiny/kernel/core/tos_ring_queue.c \ +../TencentOS_Tiny/kernel/core/tos_robin.c \ +../TencentOS_Tiny/kernel/core/tos_rwlock.c \ +../TencentOS_Tiny/kernel/core/tos_sched.c \ +../TencentOS_Tiny/kernel/core/tos_sem.c \ +../TencentOS_Tiny/kernel/core/tos_stopwatch.c \ +../TencentOS_Tiny/kernel/core/tos_sys.c \ +../TencentOS_Tiny/kernel/core/tos_task.c \ +../TencentOS_Tiny/kernel/core/tos_tick.c \ +../TencentOS_Tiny/kernel/core/tos_time.c \ +../TencentOS_Tiny/kernel/core/tos_timer.c + +OBJS += \ +./TencentOS_Tiny/kernel/core/tos_barrier.o \ +./TencentOS_Tiny/kernel/core/tos_binary_heap.o \ +./TencentOS_Tiny/kernel/core/tos_bitmap.o \ +./TencentOS_Tiny/kernel/core/tos_char_fifo.o \ +./TencentOS_Tiny/kernel/core/tos_completion.o \ +./TencentOS_Tiny/kernel/core/tos_countdownlatch.o \ +./TencentOS_Tiny/kernel/core/tos_event.o \ +./TencentOS_Tiny/kernel/core/tos_global.o \ +./TencentOS_Tiny/kernel/core/tos_mail_queue.o \ +./TencentOS_Tiny/kernel/core/tos_message_queue.o \ +./TencentOS_Tiny/kernel/core/tos_mmblk.o \ +./TencentOS_Tiny/kernel/core/tos_mmheap.o \ +./TencentOS_Tiny/kernel/core/tos_mutex.o \ +./TencentOS_Tiny/kernel/core/tos_pend.o \ +./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o \ +./TencentOS_Tiny/kernel/core/tos_priority_message_queue.o \ +./TencentOS_Tiny/kernel/core/tos_priority_queue.o \ +./TencentOS_Tiny/kernel/core/tos_ring_queue.o \ +./TencentOS_Tiny/kernel/core/tos_robin.o \ +./TencentOS_Tiny/kernel/core/tos_rwlock.o \ +./TencentOS_Tiny/kernel/core/tos_sched.o \ +./TencentOS_Tiny/kernel/core/tos_sem.o \ +./TencentOS_Tiny/kernel/core/tos_stopwatch.o \ +./TencentOS_Tiny/kernel/core/tos_sys.o \ +./TencentOS_Tiny/kernel/core/tos_task.o \ +./TencentOS_Tiny/kernel/core/tos_tick.o \ +./TencentOS_Tiny/kernel/core/tos_time.o \ +./TencentOS_Tiny/kernel/core/tos_timer.o + +C_DEPS += \ +./TencentOS_Tiny/kernel/core/tos_barrier.d \ +./TencentOS_Tiny/kernel/core/tos_binary_heap.d \ +./TencentOS_Tiny/kernel/core/tos_bitmap.d \ +./TencentOS_Tiny/kernel/core/tos_char_fifo.d \ +./TencentOS_Tiny/kernel/core/tos_completion.d \ +./TencentOS_Tiny/kernel/core/tos_countdownlatch.d \ +./TencentOS_Tiny/kernel/core/tos_event.d \ +./TencentOS_Tiny/kernel/core/tos_global.d \ +./TencentOS_Tiny/kernel/core/tos_mail_queue.d \ +./TencentOS_Tiny/kernel/core/tos_message_queue.d \ +./TencentOS_Tiny/kernel/core/tos_mmblk.d \ +./TencentOS_Tiny/kernel/core/tos_mmheap.d \ +./TencentOS_Tiny/kernel/core/tos_mutex.d \ +./TencentOS_Tiny/kernel/core/tos_pend.d \ +./TencentOS_Tiny/kernel/core/tos_priority_mail_queue.d \ +./TencentOS_Tiny/kernel/core/tos_priority_message_queue.d \ +./TencentOS_Tiny/kernel/core/tos_priority_queue.d \ +./TencentOS_Tiny/kernel/core/tos_ring_queue.d \ +./TencentOS_Tiny/kernel/core/tos_robin.d \ +./TencentOS_Tiny/kernel/core/tos_rwlock.d \ +./TencentOS_Tiny/kernel/core/tos_sched.d \ +./TencentOS_Tiny/kernel/core/tos_sem.d \ +./TencentOS_Tiny/kernel/core/tos_stopwatch.d \ +./TencentOS_Tiny/kernel/core/tos_sys.d \ +./TencentOS_Tiny/kernel/core/tos_task.d \ +./TencentOS_Tiny/kernel/core/tos_tick.d \ +./TencentOS_Tiny/kernel/core/tos_time.d \ +./TencentOS_Tiny/kernel/core/tos_timer.d + + +# Each subdirectory must supply rules for building sources it contributes +TencentOS_Tiny/kernel/core/%.o: ../TencentOS_Tiny/kernel/core/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/TencentOS_Tiny/kernel/core/tos_barrier.d b/obj/TencentOS_Tiny/kernel/core/tos_barrier.d new file mode 100644 index 0000000..59a8544 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_barrier.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_barrier.o: \ + ../TencentOS_Tiny/kernel/core/tos_barrier.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_barrier.o b/obj/TencentOS_Tiny/kernel/core/tos_barrier.o new file mode 100644 index 0000000..887021e Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_barrier.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_binary_heap.d b/obj/TencentOS_Tiny/kernel/core/tos_binary_heap.d new file mode 100644 index 0000000..94bc31d --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_binary_heap.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_binary_heap.o: \ + ../TencentOS_Tiny/kernel/core/tos_binary_heap.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_binary_heap.o b/obj/TencentOS_Tiny/kernel/core/tos_binary_heap.o new file mode 100644 index 0000000..7823859 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_binary_heap.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_bitmap.d b/obj/TencentOS_Tiny/kernel/core/tos_bitmap.d new file mode 100644 index 0000000..cd1b77a --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_bitmap.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_bitmap.o: \ + ../TencentOS_Tiny/kernel/core/tos_bitmap.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_bitmap.o b/obj/TencentOS_Tiny/kernel/core/tos_bitmap.o new file mode 100644 index 0000000..4841fda Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_bitmap.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_char_fifo.d b/obj/TencentOS_Tiny/kernel/core/tos_char_fifo.d new file mode 100644 index 0000000..d875da6 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_char_fifo.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_char_fifo.o: \ + ../TencentOS_Tiny/kernel/core/tos_char_fifo.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_char_fifo.o b/obj/TencentOS_Tiny/kernel/core/tos_char_fifo.o new file mode 100644 index 0000000..6179849 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_char_fifo.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_completion.d b/obj/TencentOS_Tiny/kernel/core/tos_completion.d new file mode 100644 index 0000000..aff13bb --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_completion.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_completion.o: \ + ../TencentOS_Tiny/kernel/core/tos_completion.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_completion.o b/obj/TencentOS_Tiny/kernel/core/tos_completion.o new file mode 100644 index 0000000..d753098 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_completion.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_countdownlatch.d b/obj/TencentOS_Tiny/kernel/core/tos_countdownlatch.d new file mode 100644 index 0000000..9cb84f6 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_countdownlatch.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_countdownlatch.o: \ + ../TencentOS_Tiny/kernel/core/tos_countdownlatch.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_countdownlatch.o b/obj/TencentOS_Tiny/kernel/core/tos_countdownlatch.o new file mode 100644 index 0000000..9caab6f Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_countdownlatch.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_event.d b/obj/TencentOS_Tiny/kernel/core/tos_event.d new file mode 100644 index 0000000..7091e4d --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_event.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_event.o: \ + ../TencentOS_Tiny/kernel/core/tos_event.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_event.o b/obj/TencentOS_Tiny/kernel/core/tos_event.o new file mode 100644 index 0000000..8080ff6 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_event.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_global.d b/obj/TencentOS_Tiny/kernel/core/tos_global.d new file mode 100644 index 0000000..f2adb78 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_global.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_global.o: \ + ../TencentOS_Tiny/kernel/core/tos_global.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_global.o b/obj/TencentOS_Tiny/kernel/core/tos_global.o new file mode 100644 index 0000000..31074ae Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_global.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mail_queue.d b/obj/TencentOS_Tiny/kernel/core/tos_mail_queue.d new file mode 100644 index 0000000..3161be5 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_mail_queue.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_mail_queue.o: \ + ../TencentOS_Tiny/kernel/core/tos_mail_queue.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mail_queue.o b/obj/TencentOS_Tiny/kernel/core/tos_mail_queue.o new file mode 100644 index 0000000..2e5d322 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_mail_queue.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_message_queue.d b/obj/TencentOS_Tiny/kernel/core/tos_message_queue.d new file mode 100644 index 0000000..def7f52 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_message_queue.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_message_queue.o: \ + ../TencentOS_Tiny/kernel/core/tos_message_queue.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_message_queue.o b/obj/TencentOS_Tiny/kernel/core/tos_message_queue.o new file mode 100644 index 0000000..e97c030 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_message_queue.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mmblk.d b/obj/TencentOS_Tiny/kernel/core/tos_mmblk.d new file mode 100644 index 0000000..509c405 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_mmblk.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_mmblk.o: \ + ../TencentOS_Tiny/kernel/core/tos_mmblk.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mmblk.o b/obj/TencentOS_Tiny/kernel/core/tos_mmblk.o new file mode 100644 index 0000000..23a4d79 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_mmblk.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mmheap.d b/obj/TencentOS_Tiny/kernel/core/tos_mmheap.d new file mode 100644 index 0000000..d1cd4b3 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_mmheap.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_mmheap.o: \ + ../TencentOS_Tiny/kernel/core/tos_mmheap.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mmheap.o b/obj/TencentOS_Tiny/kernel/core/tos_mmheap.o new file mode 100644 index 0000000..e74f79c Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_mmheap.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mutex.d b/obj/TencentOS_Tiny/kernel/core/tos_mutex.d new file mode 100644 index 0000000..49a1196 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_mutex.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_mutex.o: \ + ../TencentOS_Tiny/kernel/core/tos_mutex.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_mutex.o b/obj/TencentOS_Tiny/kernel/core/tos_mutex.o new file mode 100644 index 0000000..9e0df08 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_mutex.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_pend.d b/obj/TencentOS_Tiny/kernel/core/tos_pend.d new file mode 100644 index 0000000..a623f66 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_pend.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_pend.o: \ + ../TencentOS_Tiny/kernel/core/tos_pend.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_pend.o b/obj/TencentOS_Tiny/kernel/core/tos_pend.o new file mode 100644 index 0000000..86462c6 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_pend.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.d b/obj/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.d new file mode 100644 index 0000000..89c9c89 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o: \ + ../TencentOS_Tiny/kernel/core/tos_priority_mail_queue.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o b/obj/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o new file mode 100644 index 0000000..270cdd7 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_priority_mail_queue.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_priority_message_queue.d b/obj/TencentOS_Tiny/kernel/core/tos_priority_message_queue.d new file mode 100644 index 0000000..cf4d09f --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_priority_message_queue.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_priority_message_queue.o: \ + ../TencentOS_Tiny/kernel/core/tos_priority_message_queue.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_priority_message_queue.o b/obj/TencentOS_Tiny/kernel/core/tos_priority_message_queue.o new file mode 100644 index 0000000..b242067 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_priority_message_queue.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_priority_queue.d b/obj/TencentOS_Tiny/kernel/core/tos_priority_queue.d new file mode 100644 index 0000000..5bc82ca --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_priority_queue.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_priority_queue.o: \ + ../TencentOS_Tiny/kernel/core/tos_priority_queue.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_priority_queue.o b/obj/TencentOS_Tiny/kernel/core/tos_priority_queue.o new file mode 100644 index 0000000..34ea4a4 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_priority_queue.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_ring_queue.d b/obj/TencentOS_Tiny/kernel/core/tos_ring_queue.d new file mode 100644 index 0000000..57aa001 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_ring_queue.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_ring_queue.o: \ + ../TencentOS_Tiny/kernel/core/tos_ring_queue.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_ring_queue.o b/obj/TencentOS_Tiny/kernel/core/tos_ring_queue.o new file mode 100644 index 0000000..52ebe32 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_ring_queue.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_robin.d b/obj/TencentOS_Tiny/kernel/core/tos_robin.d new file mode 100644 index 0000000..589b82c --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_robin.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_robin.o: \ + ../TencentOS_Tiny/kernel/core/tos_robin.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_robin.o b/obj/TencentOS_Tiny/kernel/core/tos_robin.o new file mode 100644 index 0000000..2215d69 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_robin.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_rwlock.d b/obj/TencentOS_Tiny/kernel/core/tos_rwlock.d new file mode 100644 index 0000000..f871c2e --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_rwlock.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_rwlock.o: \ + ../TencentOS_Tiny/kernel/core/tos_rwlock.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_rwlock.o b/obj/TencentOS_Tiny/kernel/core/tos_rwlock.o new file mode 100644 index 0000000..4f9efcd Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_rwlock.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_sched.d b/obj/TencentOS_Tiny/kernel/core/tos_sched.d new file mode 100644 index 0000000..954d31d --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_sched.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_sched.o: \ + ../TencentOS_Tiny/kernel/core/tos_sched.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_sched.o b/obj/TencentOS_Tiny/kernel/core/tos_sched.o new file mode 100644 index 0000000..517cfc3 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_sched.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_sem.d b/obj/TencentOS_Tiny/kernel/core/tos_sem.d new file mode 100644 index 0000000..7dc6e39 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_sem.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_sem.o: \ + ../TencentOS_Tiny/kernel/core/tos_sem.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_sem.o b/obj/TencentOS_Tiny/kernel/core/tos_sem.o new file mode 100644 index 0000000..f51b763 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_sem.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_stopwatch.d b/obj/TencentOS_Tiny/kernel/core/tos_stopwatch.d new file mode 100644 index 0000000..4488498 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_stopwatch.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_stopwatch.o: \ + ../TencentOS_Tiny/kernel/core/tos_stopwatch.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_stopwatch.o b/obj/TencentOS_Tiny/kernel/core/tos_stopwatch.o new file mode 100644 index 0000000..a093f30 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_stopwatch.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_sys.d b/obj/TencentOS_Tiny/kernel/core/tos_sys.d new file mode 100644 index 0000000..80c1979 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_sys.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_sys.o: \ + ../TencentOS_Tiny/kernel/core/tos_sys.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_sys.o b/obj/TencentOS_Tiny/kernel/core/tos_sys.o new file mode 100644 index 0000000..32b5611 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_sys.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_task.d b/obj/TencentOS_Tiny/kernel/core/tos_task.d new file mode 100644 index 0000000..10a15a4 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_task.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_task.o: \ + ../TencentOS_Tiny/kernel/core/tos_task.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_task.o b/obj/TencentOS_Tiny/kernel/core/tos_task.o new file mode 100644 index 0000000..2a0a4aa Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_task.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_tick.d b/obj/TencentOS_Tiny/kernel/core/tos_tick.d new file mode 100644 index 0000000..cd7b488 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_tick.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_tick.o: \ + ../TencentOS_Tiny/kernel/core/tos_tick.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_tick.o b/obj/TencentOS_Tiny/kernel/core/tos_tick.o new file mode 100644 index 0000000..693c63e Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_tick.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_time.d b/obj/TencentOS_Tiny/kernel/core/tos_time.d new file mode 100644 index 0000000..8d20eee --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_time.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_time.o: \ + ../TencentOS_Tiny/kernel/core/tos_time.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_time.o b/obj/TencentOS_Tiny/kernel/core/tos_time.o new file mode 100644 index 0000000..32aedc3 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_time.o differ diff --git a/obj/TencentOS_Tiny/kernel/core/tos_timer.d b/obj/TencentOS_Tiny/kernel/core/tos_timer.d new file mode 100644 index 0000000..b62c0d8 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/core/tos_timer.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/core/tos_timer.o: \ + ../TencentOS_Tiny/kernel/core/tos_timer.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/core/tos_timer.o b/obj/TencentOS_Tiny/kernel/core/tos_timer.o new file mode 100644 index 0000000..f588d4c Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/core/tos_timer.o differ diff --git a/obj/TencentOS_Tiny/kernel/pm/subdir.mk b/obj/TencentOS_Tiny/kernel/pm/subdir.mk new file mode 100644 index 0000000..503b2f1 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/pm/subdir.mk @@ -0,0 +1,23 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../TencentOS_Tiny/kernel/pm/tos_pm.c \ +../TencentOS_Tiny/kernel/pm/tos_tickless.c + +OBJS += \ +./TencentOS_Tiny/kernel/pm/tos_pm.o \ +./TencentOS_Tiny/kernel/pm/tos_tickless.o + +C_DEPS += \ +./TencentOS_Tiny/kernel/pm/tos_pm.d \ +./TencentOS_Tiny/kernel/pm/tos_tickless.d + + +# Each subdirectory must supply rules for building sources it contributes +TencentOS_Tiny/kernel/pm/%.o: ../TencentOS_Tiny/kernel/pm/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/TencentOS_Tiny/kernel/pm/tos_pm.d b/obj/TencentOS_Tiny/kernel/pm/tos_pm.d new file mode 100644 index 0000000..945a507 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/pm/tos_pm.d @@ -0,0 +1,223 @@ +TencentOS_Tiny/kernel/pm/tos_pm.o: ../TencentOS_Tiny/kernel/pm/tos_pm.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/pm/tos_pm.o b/obj/TencentOS_Tiny/kernel/pm/tos_pm.o new file mode 100644 index 0000000..759a5b5 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/pm/tos_pm.o differ diff --git a/obj/TencentOS_Tiny/kernel/pm/tos_tickless.d b/obj/TencentOS_Tiny/kernel/pm/tos_tickless.d new file mode 100644 index 0000000..b170672 --- /dev/null +++ b/obj/TencentOS_Tiny/kernel/pm/tos_tickless.d @@ -0,0 +1,224 @@ +TencentOS_Tiny/kernel/pm/tos_tickless.o: \ + ../TencentOS_Tiny/kernel/pm/tos_tickless.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: diff --git a/obj/TencentOS_Tiny/kernel/pm/tos_tickless.o b/obj/TencentOS_Tiny/kernel/pm/tos_tickless.o new file mode 100644 index 0000000..a8a66e0 Binary files /dev/null and b/obj/TencentOS_Tiny/kernel/pm/tos_tickless.o differ diff --git a/obj/TencentOS_Tiny/tos_js/subdir.mk b/obj/TencentOS_Tiny/tos_js/subdir.mk new file mode 100644 index 0000000..d406cc9 --- /dev/null +++ b/obj/TencentOS_Tiny/tos_js/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../TencentOS_Tiny/tos_js/tos_js.c + +OBJS += \ +./TencentOS_Tiny/tos_js/tos_js.o + +C_DEPS += \ +./TencentOS_Tiny/tos_js/tos_js.d + + +# Each subdirectory must supply rules for building sources it contributes +TencentOS_Tiny/tos_js/%.o: ../TencentOS_Tiny/tos_js/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/TencentOS_Tiny/tos_js/tos_js.d b/obj/TencentOS_Tiny/tos_js/tos_js.d new file mode 100644 index 0000000..3e84021 --- /dev/null +++ b/obj/TencentOS_Tiny/tos_js/tos_js.d @@ -0,0 +1,4 @@ +TencentOS_Tiny/tos_js/tos_js.o: ../TencentOS_Tiny/tos_js/tos_js.c \ + ../TencentOS_Tiny/tos_js/tos_js.h + +../TencentOS_Tiny/tos_js/tos_js.h: diff --git a/obj/TencentOS_Tiny/tos_js/tos_js.o b/obj/TencentOS_Tiny/tos_js/tos_js.o new file mode 100644 index 0000000..354a52a Binary files /dev/null and b/obj/TencentOS_Tiny/tos_js/tos_js.o differ diff --git a/obj/User/ch32v30x_it.d b/obj/User/ch32v30x_it.d new file mode 100644 index 0000000..7f0187c --- /dev/null +++ b/obj/User/ch32v30x_it.d @@ -0,0 +1,90 @@ +User/ch32v30x_it.o: ../User/ch32v30x_it.c ../User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +../User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/User/ch32v30x_it.o b/obj/User/ch32v30x_it.o new file mode 100644 index 0000000..b55d817 Binary files /dev/null and b/obj/User/ch32v30x_it.o differ diff --git a/obj/User/main.d b/obj/User/main.d new file mode 100644 index 0000000..9b0267c --- /dev/null +++ b/obj/User/main.d @@ -0,0 +1,226 @@ +User/main.o: ../User/main.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js/tos_js.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_k.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_compiler.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_kerr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_def.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG/tos_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_default.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port_config.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_config_check.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ktypes.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu_types.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc/port.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_cpu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include/tos_fault.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_klib.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_list.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_slist.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_pend.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sys.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_bitmap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_ring_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_char_fifo.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_binary_heap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_mail_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_priority_message_queue.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_task.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_robin.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mutex.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sem.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_event.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_barrier.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_completion.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_countdownlatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_rwlock.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_timer.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_time.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_stopwatch.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmblk.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_mmheap.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_tick.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_sched.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_global.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include/tos_version.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js/tos_js.h: diff --git a/obj/User/main.o b/obj/User/main.o new file mode 100644 index 0000000..b8f3302 Binary files /dev/null and b/obj/User/main.o differ diff --git a/obj/User/subdir.mk b/obj/User/subdir.mk new file mode 100644 index 0000000..72e0393 --- /dev/null +++ b/obj/User/subdir.mk @@ -0,0 +1,26 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/ch32v30x_it.c \ +../User/main.c \ +../User/system_ch32v30x.c + +OBJS += \ +./User/ch32v30x_it.o \ +./User/main.o \ +./User/system_ch32v30x.o + +C_DEPS += \ +./User/ch32v30x_it.d \ +./User/main.d \ +./User/system_ch32v30x.d + + +# Each subdirectory must supply rules for building sources it contributes +User/%.o: ../User/%.c + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\common" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\arch\risc-v\rv32\gcc" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\core" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\hal" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm\include" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\kernel\pm" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\TOS_CONFIG" -I"C:\MRS_DATA\workspace\JSInterpreter-TencentOS\TencentOS_Tiny\tos_js" -I"C:\Users\a1885\scoop\apps\gcc\current\include" -std=gnu17 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + @ @ + diff --git a/obj/User/system_ch32v30x.d b/obj/User/system_ch32v30x.d new file mode 100644 index 0000000..43871cb --- /dev/null +++ b/obj/User/system_ch32v30x.d @@ -0,0 +1,88 @@ +User/system_ch32v30x.o: ../User/system_ch32v30x.c \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h \ + C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Core/core_riscv.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/system_ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_conf.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_adc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_bkp.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_can.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_crc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dac.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dbgmcu.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_dma.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_exti.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_flash.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_fsmc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_gpio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_i2c.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_iwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_pwr.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rcc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_rtc.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_sdio.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_spi.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_tim.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_usart.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_wwdg.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\User/ch32v30x_it.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Debug/debug.h: + +C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Peripheral\inc/ch32v30x_misc.h: diff --git a/obj/User/system_ch32v30x.o b/obj/User/system_ch32v30x.o new file mode 100644 index 0000000..60b8c6b Binary files /dev/null and b/obj/User/system_ch32v30x.o differ diff --git a/obj/makefile b/obj/makefile new file mode 100644 index 0000000..fd52fe5 --- /dev/null +++ b/obj/makefile @@ -0,0 +1,79 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include User/subdir.mk +-include TencentOS_Tiny/tos_js/subdir.mk +-include TencentOS_Tiny/kernel/pm/subdir.mk +-include TencentOS_Tiny/kernel/core/subdir.mk +-include TencentOS_Tiny/arch/risc-v/rv32/gcc/subdir.mk +-include TencentOS_Tiny/arch/risc-v/common/subdir.mk +-include Startup/subdir.mk +-include Peripheral/src/subdir.mk +-include Debug/subdir.mk +-include Core/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +SECONDARY_FLASH += \ +JSInterpreter-TencentOS.hex \ + +SECONDARY_LIST += \ +JSInterpreter-TencentOS.lst \ + +SECONDARY_SIZE += \ +JSInterpreter-TencentOS.siz \ + + +# Ŀ +all: JSInterpreter-TencentOS.elf secondary-outputs + +# ߵ +JSInterpreter-TencentOS.elf: $(OBJS) $(USER_OBJS) + @ @ riscv-none-embed-gcc -march=rv32imafcxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wunused -Wuninitialized -g -T "C:\MRS_DATA\workspace\JSInterpreter-TencentOS\Ld\Link.ld" -nostartfiles -Xlinker --gc-sections -Wl,-Map,"JSInterpreter-TencentOS.map" --specs=nano.specs -u _printf_float -u _scanf_float --specs=nosys.specs -o "JSInterpreter-TencentOS.elf" $(OBJS) $(USER_OBJS) $(LIBS) + @ @ +JSInterpreter-TencentOS.hex: JSInterpreter-TencentOS.elf + @ riscv-none-embed-objcopy -O ihex "JSInterpreter-TencentOS.elf" "JSInterpreter-TencentOS.hex" + @ @ +JSInterpreter-TencentOS.lst: JSInterpreter-TencentOS.elf + @ riscv-none-embed-objdump --all-headers --demangle --disassemble -M xw "JSInterpreter-TencentOS.elf" > "JSInterpreter-TencentOS.lst" + @ @ +JSInterpreter-TencentOS.siz: JSInterpreter-TencentOS.elf + @ riscv-none-embed-size --format=berkeley "JSInterpreter-TencentOS.elf" + @ @ +# Ŀ +clean: + -$(RM) $(ASM_UPPER_DEPS)$(OBJS)$(SECONDARY_FLASH)$(SECONDARY_LIST)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_DEPS)$(S_UPPER_DEPS)$(C_DEPS) JSInterpreter-TencentOS.elf + -@ +secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_LIST) $(SECONDARY_SIZE) + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/obj/objects.mk b/obj/objects.mk new file mode 100644 index 0000000..4d80ba0 --- /dev/null +++ b/obj/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/obj/sources.mk b/obj/sources.mk new file mode 100644 index 0000000..c78c655 --- /dev/null +++ b/obj/sources.mk @@ -0,0 +1,35 @@ +################################################################################ +# ԶɵļҪ༭ +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +ASM_UPPER_SRCS := +ASM_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +ASM_UPPER_DEPS := +OBJS := +SECONDARY_FLASH := +SECONDARY_LIST := +SECONDARY_SIZE := +ASM_DEPS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core \ +Debug \ +Peripheral/src \ +Startup \ +TencentOS_Tiny/arch/risc-v/common \ +TencentOS_Tiny/arch/risc-v/rv32/gcc \ +TencentOS_Tiny/kernel/core \ +TencentOS_Tiny/kernel/pm \ +TencentOS_Tiny/tos_js \ +User \ +